Display driver integrated circuit, display drive method, display apparatus, and electronic device

Abstract

The embodiments of the present application relate to the technical field of image processing, and relate to a display driver integrated circuit (IC), a display drive method, a display apparatus, and an electronic device. The IC comprises a power supply end and a plurality of output ends, wherein the power supply end is used for receiving a power supply voltage; and the plurality of output ends comprise a first output end and a second output end. The first output end is used for outputting a first display drive voltage within a first time period and outputting a second display drive voltage within a second time period, wherein the first display drive voltage is equal to the power supply voltage; and the second output end is used for maintaining the output of a third display drive voltage within the first time period, a first switching period and the second time period, wherein the first switching period lies between the first time period and the second time period, the second display drive voltage falls within a preset voltage range, and a maximum value of the preset voltage range is less than the third display drive voltage. In this way, the power consumption of a display driver IC can be reduced.

Description

Display driving chip, display driving method, display device and electronic equipment

[0001] The present application claims priority to the Chinese patent application No. 202411382628.2, filed on September 29, 2024, and entitled "Display driving chip, display driving method, display device and electronic equipment", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of image processing, and in particular to a display driving chip, a display driving method, a display device and an electronic equipment. BACKGROUND

[0003] A display screen includes a pixel circuit, which usually needs to be driven by a display driving chip (DDIC). About one fourth of the total machine power consumption is on the display driving chip side. As the user uses the total machine for a longer time, it is increasingly important to reduce the power consumption of the display driving chip. In an organic light-emitting diode (OLED) display screen, there is a red-green-blue-green (RGBG) pixel circuit. During the display driving chip driving the RGBG pixel circuit display process, the power consumption of the display driving chip is large. SUMMARY

[0004] Embodiments of the present application provide a display driving chip, a display driving method, a display device and an electronic equipment, which solve the problem of large power consumption of the display driving chip in the display driving chip driving the RGBG pixel circuit display process in the prior art.

[0005] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a display driving chip is provided, which includes a power supply end and a plurality of output ends. The power supply end is configured to receive a power supply voltage. The plurality of output ends includes a first output end and a second output end. The first output end is configured to output a first display driving voltage in a first time period and a second display driving voltage in a second time period, and the first display driving voltage is equal to the power supply voltage. The second output end is configured to output a third display driving voltage in the first time period, a first switching time period and the second time period, and the first switching time period is located between the first time period and the second time period. The second display driving voltage is located within a preset voltage interval, and the maximum value of the preset voltage interval is less than the third display driving voltage.

[0007] In the technical solution, the display driving chip can obtain multiple voltages according to the power supply voltage of the power supply terminal. The multiple voltages include voltages in a preset voltage range. The second display driving voltage is usually one of the multiple voltages in the preset voltage range. If the first display driving voltage and the second display driving voltage are both voltages obtained according to the power supply voltage, the values of the multiple voltages obtained according to the power supply voltage will be disturbed in the process of switching from the first display driving voltage to the second display driving voltage. In the technical solution, the voltage equal to the power supply voltage is used as the first display driving voltage. That is, the first display driving voltage can not be a voltage obtained according to the power supply voltage, but can be the power supply voltage itself. The values of the multiple voltages obtained according to the power supply voltage are less disturbed when the first output terminal outputs the dynamic voltage. The third display driving voltage output by the second output terminal can be a voltage obtained according to the power supply voltage, or can be the power supply voltage, and the third display driving voltage output by the second output terminal is not disturbed. Compared with the case where additional current is needed to stabilize the voltage of the second output terminal due to the disturbance, the technical solution does not need to additionally stabilize the voltage of the second output terminal, and can reduce power consumption. Compared with the case where the voltage of the second output terminal needs to be restored (re-established) due to the disturbance, the technical solution does not need to wait for the voltage of the second output terminal to be restored, and can improve the driving capability of the display driving chip and speed up the voltage output process. In addition, the technical solution does not need to reduce power consumption by using additional power consumption or circuit area, but reduces power consumption by outputting the power supply voltage, which can save circuit area and reduce power consumption to the greatest extent.

[0008] In a possible implementation of the first aspect, the multiple output terminals further include a third output terminal, the third output terminal being configured to output a fourth display driving voltage in a first time period and output the first display driving voltage in a second time period, the fourth display driving voltage being in the preset voltage range. The fourth display driving voltage output by the third output terminal in the first time period is different in size from the second display driving voltage output by the first output terminal in the second time period. In the possible implementation, if the first display driving voltage and the fourth display driving voltage are both voltages obtained according to the power supply voltage, the values of the multiple voltages obtained according to the power supply voltage will be disturbed in the process of switching from the first display driving voltage to the fourth display driving voltage. In the technical solution, the first display driving voltage can not be a voltage obtained according to the power supply voltage, but can be the power supply voltage itself. The values of the multiple voltages obtained according to the power supply voltage are less disturbed when the first output terminal outputs the dynamic voltage. The third display driving voltage output by the second output terminal is not disturbed. For the multiple output terminals, power consumption can be reduced and the voltage output process can be speeded up.

[0009] In a possible implementation manner of the first aspect, the first output terminal is specifically configured to output the first display driving voltage in the first time period, output the second display driving voltage in the second time period, output the first display driving voltage in the third time period, and output the second display driving voltage in the fourth time period. The second output terminal is specifically configured to output the third display driving voltage in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, and the fourth time period. The second switching time period is located between the second time period and the third time period, and the third switching time period is located between the third time period and the fourth time period. In the possible implementation manner, when the color display of the plurality of sub-pixels is driven in the third time period and the fourth time period, the first display driving voltage can not be a voltage obtained according to the power supply voltage, but can be the power supply voltage itself. When the dynamic voltage is output, the value of the plurality of voltages obtained according to the power supply voltage is less disturbed. For the case of driving the plurality of sub-pixels, the power consumption can be reduced, and the voltage output process can be accelerated.

[0010] In a possible implementation manner of the first aspect, the first output terminal is specifically configured to output the first display driving voltage in the first time period, output the second display driving voltage in the second time period, output the first display driving voltage in the third time period, and output the second display driving voltage in the fourth time period. The second output terminal is specifically configured to output the third display driving voltage in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, and the fourth time period. The second switching time period is located between the second time period and the third time period, and the third switching time period is located between the third time period and the fourth time period. In the possible implementation manner, when the color display of the plurality of sub-pixels is driven in the third time period and the fourth time period, the first display driving voltage can not be a voltage obtained according to the power supply voltage, but can be the power supply voltage itself. When the dynamic voltage is output, the value of the plurality of voltages obtained according to the power supply voltage is less disturbed. For the case of driving the plurality of sub-pixels, the power consumption can be reduced, and the voltage output process can be accelerated.

[0011] In a possible implementation of the first aspect, the chip further includes a first display channel circuit, a first display switch, and a first power switch. An output terminal of the first display channel circuit is coupled to a first terminal of the first display switch, and a second terminal of the first display switch is coupled to the first output terminal. The power terminal is coupled to a first terminal of the first power switch, and a second terminal of the first power switch is coupled to the first output terminal. In the possible implementation, the first display channel circuit is coupled to the first output terminal through the first display switch, and the power terminal is coupled to the first output terminal through the first power switch. The first output terminal can output a voltage provided by the first display channel circuit, or can output a power voltage received by the power terminal. When the first output terminal needs to output a voltage for driving a sub-pixel to emit light, the first display channel circuit can output the voltage to the first output terminal by turning on the first display switch and turning off the first power switch. When the first output terminal needs to output a voltage for driving a sub-pixel not to emit light, the power terminal can output the power voltage to the first output terminal by turning off the first display switch and turning on the first power switch. It can be seen that, when outputting a dynamic voltage, the first output terminal switches the voltage by turning on and off the first display switch and the first power switch, instead of switching the voltage inside the first display channel circuit. In this way, the voltage output by a display channel circuit adjacent to the first display channel circuit is less disturbed.

[0012] In a possible implementation of the first aspect, the chip further includes a plurality of display channel circuits, a plurality of display switches and a plurality of power switches. An output terminal of an mth display channel circuit is coupled with a first terminal of an mth display switch, and a second terminal of the mth display switch is coupled with an mth output terminal. A power terminal is coupled with a first terminal of an mth power switch, and a second terminal of the mth power switch is coupled with the mth output terminal. The mth display channel circuit is any one of the plurality of display channel circuits, the mth display switch is any one of the plurality of display switches, the mth power switch is any one of the plurality of power switches, and the mth output terminal is any one of the plurality of output terminals. In the possible implementation, the mth display channel circuit is coupled with the mth output terminal through the mth display switch, and the power terminal is coupled with the mth output terminal through the mth power switch. The mth output terminal can output a voltage provided by the mth display channel circuit or output a power voltage received by the power terminal. When the mth output terminal needs to output a voltage for driving a sub-pixel to emit light, the mth display channel circuit can output the voltage to the mth output terminal by turning on the mth display switch and turning off the mth power switch. When the mth output terminal needs to output a voltage for driving a sub-pixel not to emit light, the power terminal can output the power voltage to the output terminal by turning on the mth power switch and turning off the mth display switch. It can be seen that, when the mth output terminal outputs a dynamic voltage, the voltage is switched by turning on and turning off the mth display switch and the mth power switch, instead of being switched internally in the mth display channel circuit. In this way, the voltage output by a display channel circuit adjacent to the mth display channel circuit is less disturbed.

[0013] In a possible implementation of the first aspect, the chip further includes a plurality of drive enhancement circuits, and a kth drive enhancement circuit is coupled with a control terminal of a kth display switch. The kth drive enhancement circuit is any one of the plurality of drive enhancement circuits, and the kth display switch is any one of the plurality of display switches. In the possible implementation, an ideal waveform of a control waveform for controlling the display switch to turn on or turn off is a square wave, but the control waveform can be unstable in practice. The drive enhancement circuit can stabilize the control waveform of the display switch coupled therewith. By providing one drive enhancement circuit for each display switch, high-speed turning on and turning off of the plurality of display switches can be implemented.

[0014] In a possible implementation of the first aspect, the third display driving voltage is equal to the power voltage. In the possible implementation, the third display driving voltage can be provided by the power terminal, and the power consumption of the display channel circuit can be further reduced.

[0015] In a possible implementation of the first aspect, the power terminal is configured to connect to a power supply. In the above possible implementation, the power terminal is connected to the power supply, and a power supply voltage can be used as a voltage for driving the sub-pixel to not emit light through the power terminal. The power supply voltage has a strong power supply network and small path impedance, and can reduce additional power consumption caused by a dynamic voltage output by the display channel circuit.

[0016] In a second aspect, a display driving chip is provided. The display driving chip includes a power terminal, a first output terminal, a first display channel circuit, a first display switch, and a first power switch. The power terminal is configured to receive a power supply voltage. An output terminal of the first display channel circuit is coupled to a first terminal of the first display switch, and a second terminal of the first display switch is coupled to the first output terminal. The power terminal is coupled to a first terminal of the first power switch, and a second terminal of the first power switch is coupled to the first output terminal. In the above possible implementation, the first display channel circuit is coupled to the first output terminal through the first display switch, and the power terminal is coupled to the first output terminal through the first power switch. The first output terminal can output a voltage provided by the first display channel circuit, or can output the power supply voltage received by the power terminal. When the first output terminal needs to output a voltage for driving the sub-pixel to emit light, the first display channel circuit can output the voltage to the first output terminal by turning on the first display switch and turning off the first power switch. When the first output terminal needs to output a voltage for driving the sub-pixel to not emit light, the power terminal can output the power supply voltage to the first output terminal by turning off the first display switch and turning on the first power switch. It can be seen that, when the first output terminal outputs a dynamic voltage, the voltage is switched by turning on and off the first display switch and the first power switch, instead of being switched inside the first display channel circuit. Compared with a case where additional current is needed to stabilize the voltage due to interference, the technical solution does not need additional voltage stabilization, and can reduce power consumption. Compared with a case where the voltage needs to be restored (re-established) due to interference, the technical solution does not need to wait for the voltage to be restored, and can improve the driving capability of the display driving chip and speed up the voltage output process. Furthermore, the technical solution does not need to reduce power consumption by using additional power consumption or circuit area, but can reduce power consumption by outputting the power supply voltage, and can save circuit area and reduce power consumption to the greatest extent.

[0017] In a possible implementation of the second aspect, the chip further includes a plurality of output terminals, a plurality of display channel circuits, a plurality of display switches and a plurality of power switches. An output terminal of an mth display channel circuit is coupled with a first terminal of an mth display switch, a second terminal of the mth display switch is coupled with an mth output terminal. A power terminal is coupled with a first terminal of an mth power switch, a second terminal of the mth power switch is coupled with the mth output terminal. The mth display channel circuit is any one of the plurality of display channel circuits, the mth display switch is any one of the plurality of display switches, the mth power switch is any one of the plurality of power switches, and the mth output terminal is any one of the plurality of output terminals. In the possible implementation, the mth display channel circuit is coupled with the mth output terminal through the mth display switch, and the power terminal is coupled with the output terminal through the mth power switch. The mth output terminal can output a voltage provided by the mth display channel circuit, or output a power voltage received by the power terminal. When the mth output terminal needs to output a voltage for driving a sub-pixel to emit light, the mth display channel circuit can output the voltage to the mth output terminal by turning on the mth display switch and turning off the mth power switch. When the mth output terminal needs to output a voltage for driving a sub-pixel to not emit light, the power terminal can output the power voltage to the first output terminal by turning off the mth display switch and turning on the mth power switch. The power voltage of the power terminal can replace the voltage provided by the mth display channel circuit. It can be seen that, when the mth output terminal outputs a dynamic voltage, the voltage is switched by turning on and turning off the mth display switch and the mth power switch, instead of being switched internally in the mth display channel circuit. In this way, the voltage output by a display channel circuit adjacent to the mth display channel circuit is less disturbed.

[0018] In a possible implementation of the second aspect, the chip further includes a plurality of drive enhancement circuits, a kth drive enhancement circuit is coupled with a control terminal of a kth display switch, the kth drive enhancement circuit is any one of the plurality of drive enhancement circuits, and the kth display switch is any one of the plurality of display switches. In the possible implementation, an ideal waveform of a control waveform for controlling the display switch to turn on or turn off is a square wave, but the control waveform can be unstable in practice. The drive enhancement circuit can stabilize the control waveform of the display switch coupled therewith. By providing one drive enhancement circuit for each display switch, high-speed turning on and turning off of the plurality of display switches can be implemented.

[0019] In a possible implementation of the second aspect, the power terminal is configured to be connected with a power supply. In the possible implementation, the power terminal is connected with the power supply, and the power voltage can be used as the voltage for driving the sub-pixel to not emit light through the power terminal. The power voltage has a robust power supply network and a small path impedance, and can reduce additional power consumption caused by the display channel circuit outputting a dynamic voltage.

[0020] In a third aspect, a display driving method is provided. The display driving method is applied to a display driving chip. The display driving chip includes a power supply terminal and a plurality of output terminals. The power supply terminal is configured to receive a power supply voltage. The plurality of output terminals includes a first output terminal and a second output terminal. The method includes: outputting, by the first output terminal, a first display driving voltage in a first time period and a second display driving voltage in a second time period, the first display driving voltage being equal to the power supply voltage. Outputting, by the second output terminal, a third display driving voltage in the first time period, a first switching time period, and the second time period, the first switching time period being between the first time period and the second time period. The second display driving voltage is within a preset voltage range, and a maximum value of the preset voltage range is less than the third display driving voltage.

[0021] In a possible implementation of the third aspect, the method further includes: outputting, by a third output terminal, a fourth display driving voltage in the first time period and the first display driving voltage in the second time period, the fourth display driving voltage being within the preset voltage range. The fourth display driving voltage output by the third output terminal in the first time period is different from the second display driving voltage output by the first output terminal in the second time period.

[0022] In a possible implementation of the third aspect, outputting, by the first output terminal, the first display driving voltage in the first time period and the second display driving voltage in the second time period includes: outputting, by the first output terminal, the first display driving voltage in the first time period, the second display driving voltage in the second time period, the first display driving voltage in a third time period, and the second display driving voltage in a fourth time period. Outputting, by the second output terminal, the third display driving voltage in the first time period, the first switching time period, and the second time period includes: outputting, by the second output terminal, the third display driving voltage in the first time period, the first switching time period, the second time period, a second switching time period, the third time period, a third switching time period, and the fourth time period, the second switching time period being between the second time period and the third time period, and the third switching time period being between the third time period and the fourth time period.

[0023] In a possible implementation manner of the third aspect, the outputting, by the first output terminal, the first display driving voltage in the first time period and the second display driving voltage in the second time period comprises: outputting, by the first output terminal, the first display driving voltage in the first time period, the second display driving voltage in the second time period, the first display driving voltage in the third time period, the second display driving voltage in the fourth time period, the first display driving voltage in the nth time period, and the second display driving voltage in the (n+1)th time period, where n is an odd number greater than or equal to 5. The maintaining, by the second output terminal, the output of the third display driving voltage in the first time period, the first switching time period and the second time period comprises: maintaining, by the second output terminal, the output of the third display driving voltage in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, the fourth time period, the fourth switching time period, the nth time period, the nth switching time period and the (n+1)th time period, where the fourth switching time period is between the fourth time period and the nth time period, and the nth switching time period is between the nth time period and the (n+1)th time period.

[0024] In a possible implementation manner of the third aspect, the third display driving voltage is equal to the power supply voltage.

[0025] In a fourth aspect, a display device is provided. The display device comprises a display screen and the display driving chip provided in the first aspect or any possible implementation manner of the first aspect or the second aspect or any possible implementation manner of the second aspect. The display screen comprises a plurality of pixel channels. The jth pixel channel is coupled with the jth output terminal, the jth pixel channel is any one of the plurality of pixel channels, and the jth output terminal is any one of the plurality of output terminals of the display driving chip.

[0026] In a fifth aspect, an electronic device is provided. The electronic device comprises a circuit board and the display device provided in the fourth aspect, and the display driving chip in the display device is arranged on the circuit board.

[0027] In still another aspect of the present application, a computer readable storage medium is provided. The computer readable storage medium stores program codes which can be invoked by a processor to execute the method provided in the third aspect or any possible implementation manner of the third aspect.

[0028] In yet another aspect of the present application, a computer program product is provided. When the computer program product is run on a computer, the computer is caused to execute the method provided in the third aspect or any possible implementation manner of the third aspect.

[0029] It can be understood that any one of the display driving method, device, equipment, computer storage medium or computer program product provided above can apply the corresponding display driving chip provided above, and the beneficial effects achieved thereby can refer to the beneficial effects of the corresponding chip provided above, which will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0030] FIG. 1 is a schematic diagram of a first display device according to an embodiment of the present application;

[0031] FIG. 2 is a schematic diagram of a principle of driving a sub-pixel to emit light according to an embodiment of the present application;

[0032] FIG. 3 is a voltage waveform diagram of driving a sub-pixel to emit light according to an embodiment of the present application;

[0033] FIG. 4 is a voltage waveform diagram of driving a sub-pixel to emit light according to an embodiment of the present application;

[0034] FIG. 5 is a voltage waveform diagram of driving a sub-pixel to emit light according to an embodiment of the present application;

[0035] FIG. 6 is a schematic diagram of an electronic device according to an embodiment of the present application;

[0036] FIG. 7 is a schematic diagram of a second display device according to an embodiment of the present application;

[0037] FIG. 8 is a schematic diagram of a second display driving chip according to an embodiment of the present application;

[0038] FIG. 9 is a schematic diagram of a second display driving chip according to an embodiment of the present application;

[0039] FIG. 10 is a voltage waveform diagram of driving a sub-pixel to emit light according to an embodiment of the present application;

[0040] FIG. 11 is a voltage waveform diagram of driving a sub-pixel to emit light according to an embodiment of the present application;

[0041] FIG. 12 is a voltage waveform diagram of driving a sub-pixel to emit light according to an embodiment of the present application;

[0042] FIG. 13 is a schematic diagram of a display driving method according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used for the purpose of distinguishing the same type of features, and cannot be understood as indicating relative importance, quantity, order, etc.

[0044] The terms "exemplary" or "for example" and the like are used as illustrative examples, and not to imply a preference or a requirement. The term "exemplary" or "for example" and the like is used as illustrative examples, and not to imply a preference or a requirement.

[0045] The terms "coupled" and "connected," as used in the present application, are to be construed in a broad sense as having a direct or indirect connection between the elements connected, such as through electronic means, for example, through resistors, inductors, capacitors, or other electronic elements.

[0046] First, some basic concepts related to the embodiments of the present application are explained:

[0047] An organic light-emitting diode (OLED) display screen is a display technology that uses organic light-emitting materials as pixel light sources. Each pixel of the OLED display screen includes three sub-pixels of red (R), green (G), and blue (B). Each sub-pixel includes an OLED element. When current passes through, the OLED element emits light of the corresponding color. The brightness and color of each OLED element can be controlled individually. Each sub-pixel can also include a resistor-capacitance (RC) load. The OLED element has a certain delay in response to changes in voltage, and the RC load can slow down the rising and falling rates of the signal, making the voltage change curve of the OLED element more ideal. The RC load can also control the current of the OLED element, maintaining the consistency of the brightness and color of the OLED element. Therefore, the RC load can improve the stability of the display.

[0048] A red green blue green (RGBG) pixel circuit is a pixel circuit that uses an RGBG pixel arrangement. Each pixel includes one red sub-pixel, one blue sub-pixel, and two green sub-pixels. This can provide more color depth and finer color transitions. By adjusting the brightness combination of the four colors, countless colors can be generated, creating a rich visual effect.

[0049] A display driver IC (DDIC) is an integrated circuit chip specifically designed to control and drive a display screen. It is mainly used to convert the data to be displayed into an electrical signal to ensure that the image indicated by the data to be displayed can be clearly and accurately presented on the display screen.

[0050] In a possible implementation, as shown in FIG. 1, the first display device 1100A includes a first display screen 100A and a first display driving chip 200A (DDIC). For example, the first display screen 100A can be an OLED display screen.

[0051] The first display screen 100A can include a first pixel circuit 110A. The first pixel circuit 110A can include a plurality of channels, for example, a first channel 11A, a second channel 12A, a third channel 13A, a fourth channel 14A, and more channels not shown. Each channel in the plurality of channels can include a plurality of sub-pixels. Taking the first pixel circuit 110A as an RGBG pixel circuit for example, the first channel 11A can include at least four sub-pixels: B, R, B, R, the second channel 12A can include at least four sub-pixels: G, G, G, G, the third channel 13A can include at least four sub-pixels: R, B, R, B, and the fourth channel 14A can include at least four sub-pixels: G, G, G, G. One sub-pixel B, one sub-pixel R, and two sub-pixels G can be a pixel. For example, the first row of sub-pixels B in the first channel 11A, the first row of sub-pixels G in the second channel 12A, the first row of sub-pixels R in the third channel 13A, and the first row of sub-pixels G in the fourth channel 14A can be a pixel. The first display driving chip 200A can include a first power supply end, a plurality of output ends, a first gamma circuit 210A, and a plurality of driving channel circuits. The plurality of output ends can include a first output end, a second output end, a third output end, a fourth output end, and more output ends not shown. The plurality of driving channel circuits can include a first driving channel circuit 221A, a second driving channel circuit 222A, a third driving channel circuit 223A, a fourth driving channel circuit 224A, and more driving channel circuits not shown.

[0052] The first power supply end of the first display driving chip 200A and the plurality of driving channel circuits are coupled with the first gamma circuit 210A. The plurality of driving channel circuits of the first display driving chip 200A are coupled with the plurality of output ends one by one in a corresponding manner, and the specific corresponding manner can be referred to FIG. 1. The plurality of sub-pixels in each channel of the first pixel circuit 110A can be coupled to the same output end of the first display driving chip 200A, and the plurality of channels of the first pixel circuit 110A correspond to the plurality of output ends of the first display driving chip 200A one by one in a corresponding manner, and the specific corresponding manner can be referred to FIG. 1. For example, the first row of sub-pixels B in the first channel 11A, the second row of sub-pixels R in the first channel 11A, the third row of sub-pixels B in the first channel 11A, and the fourth row of sub-pixels R in the first channel 11A are all coupled to the first output end of the first display driving chip 200A. The first row of sub-pixels G in the second channel 12A, the second row of sub-pixels G in the second channel 12A, the third row of sub-pixels G in the second channel 12A, and the fourth row of sub-pixels G in the second channel 12A are all coupled to the second output end of the first display driving chip 200A. The sub-pixels in the same row in the plurality of channels of the first pixel circuit 110A can be coupled to the same clock signal line (not shown in FIG. 1). For example, the first row of sub-pixels B in the first channel 11A, the first row of sub-pixels G in the second channel 12A, the first row of sub-pixels R in the third channel 13A, and the first row of sub-pixels G in the fourth channel 14A can be coupled to the first clock signal line. The second row of sub-pixels R in the first channel 11A, the second row of sub-pixels G in the second channel 12A, the second row of sub-pixels B in the third channel 13A, and the second row of sub-pixels G in the fourth channel 14A can be coupled to the second clock signal line.

[0053] In an example, the first power terminal of the first display driving chip 200A is configured to connect to a power supply to receive a power voltage from the power supply. The first gamma circuit 210A receives the power voltage through the first power terminal, and converts the power voltage into a plurality of voltages with different magnitudes. For example, the plurality of voltages can be Vgmp’, Vdata1’, Vdata2’, …, Vdataq’, and Vgsp’ in descending order. The maximum voltage (e.g., Vgmp’) provided by the first gamma circuit 210A is less than the power voltage. The first gamma circuit 210A can output the plurality of voltages to each driving channel circuit. The driving channel circuit is configured to input the plurality of voltages and output a voltage obtained according to the plurality of voltages. Each driving channel circuit can provide one of the plurality of voltages to a corresponding channel through a corresponding output terminal. For example, the first gamma circuit 210A can output Vgmp’, Vdata1’, Vdata2’, …, Vdataq’, and Vgsp’ to the first driving channel circuit 221A. The first driving channel circuit 221A can obtain Vgmp according to Vgmp’, Vdata1 according to Vdata1’, Vdata2 according to Vdata2’, Vdataq according to Vdataq’, and Vgsp according to Vgsp’. The first driving channel circuit 221A can provide one of Vgmp, Vdata1, Vdata2, …, Vdataq, and Vgsp to a sub-pixel in the first channel 11A through the first output terminal. The maximum voltage (e.g., Vgmp) output by the driving channel circuit is less than the power voltage. When Vgmp is applied to the sub-pixel, the sub-pixel does not emit light. When Vdata1, Vdata2, …, Vdataq, and Vgsp are applied to the sub-pixel in turn, the brightness of the sub-pixel changes from small to large.

[0054] As shown in FIG. 2, the first driving channel circuit 221A can output Vgmp through the first output terminal in the first driving period, output Vdata in the second driving period, output Vgmp in the third driving period, and output Vdata in the fourth driving period. Wherein, Vdata is any one of Vdata1, Vdata2, …, Vdataq. The first channel 11A receives Vgmp in the first driving period, and under the cooperation of the clock signal line, the first row of sub-pixels B is applied with Vgmp, and the first row of sub-pixels B does not emit light. The first channel 11A receives Vdata in the second driving period, and under the cooperation of the clock signal line, the second row of sub-pixels R is applied with Vdata, and the second row of sub-pixels R emits light. The first channel 11A receives Vgmp in the third driving period, and under the cooperation of the clock signal line, the third row of sub-pixels B is applied with Vgmp, and the third row of sub-pixels B does not emit light. The first channel 11A receives Vdata in the fourth driving period, and under the cooperation of the clock signal line, the fourth row of sub-pixels R is applied with Vdata, and the fourth row of sub-pixels R emits light.

[0055] As shown in FIG. 3, the same as the principle shown in FIG. 2, when the voltage waveforms of the multiple output terminals are the voltage waveforms in FIG. 3, the second row of sub-pixels R of the first channel 11A emits light, the fourth row of sub-pixels R of the first channel 11A emits light, the first row of sub-pixels R of the third channel 13A emits light, the third row of sub-pixels R of the third channel 13A emits light, and the remaining sub-pixels do not emit light. At this time, the first display screen 100A is red.

[0056] As shown in FIG. 4, the same as the principle shown in FIG. 2, when the voltage waveforms of the multiple output terminals are the voltage waveforms in FIG. 4, the first row of sub-pixels B of the first channel 11A emits light, the third row of sub-pixels B of the first channel 11A emits light, the second row of sub-pixels B of the third channel 13A emits light, the fourth row of sub-pixels B of the third channel 13A emits light, and the remaining sub-pixels do not emit light. At this time, the first display screen 100A is blue.

[0057] As shown in FIG. 5, the same as the principle shown in FIG. 2, when the voltage waveforms of the multiple output terminals are the voltage waveforms in FIG. 5, the first row of sub-pixels G of the second channel 12A emits light, the third row of sub-pixels G of the second channel 12A emits light, the first row of sub-pixels G of the fourth channel 14A emits light, the third row of sub-pixels G of the fourth channel 14A emits light, and the remaining sub-pixels do not emit light. At this time, the first display screen 100A is green.

[0058] As shown in FIGS. 3-5, the output terminal can output dynamic voltage. Dynamic voltage refers to voltage of different magnitudes. The output terminal outputting dynamic voltage means that the output terminal does not always output voltage of the same magnitude, but outputs voltage of different magnitudes at different driving periods. The dynamic voltage is voltage of different magnitudes converted according to the data to be displayed, rather than voltage of different magnitudes caused by interference. For example, the first output terminal in FIG. 3 switches the output voltage from Vgmp to Vdata, or from Vdata to Vgmp. When the output terminal outputs dynamic voltage, the adjacent output terminal is supposed to output voltage of the same magnitude, but the voltage of the adjacent output terminal can be interfered. For example, when the first output terminal in FIG. 3 switches the output voltage from Vgmp to Vdata, or from Vdata to Vgmp, the Vgmp output by the adjacent second output terminal can be pulled down. The second output terminal is supposed to output Vgmp, but the actual voltage waveform has a dip.

[0059] The above interference is gamma disturbance caused by the first gamma circuit 210A. The first gamma circuit 210A outputs a plurality of voltages to the first drive channel circuit 221A as input voltages of the first drive channel circuit 221A, and outputs the plurality of voltages to the second drive channel circuit 222A as input voltages of the second drive channel circuit 222A. When the first drive channel circuit 221A outputs dynamic voltage, the first drive channel circuit 221A switches the voltage according to the plurality of voltages provided by the first gamma circuit 210A, which causes the voltage provided by the first gamma circuit 210A for the first drive channel circuit 221A to be interfered. When the voltage output by the first gamma circuit 210A is interfered, the input voltage of the second drive channel circuit 222A is also interfered, and thus the voltage output by the second drive channel circuit 222A is interfered.

[0060] When the voltage is interfered, a large current needs to be drawn through the power supply voltage for voltage stabilization, which causes large power consumption. In addition, the first gamma circuit 210A has a large number of wires, and the impedance and parasitic capacitance of the wires limit the driving capability of the first gamma circuit 210A, thereby limiting the driving capability of the drive channel circuit and the output voltage process. This slows down the process of voltage re-establishment (voltage recovery). In addition, if the gamma disturbance is to be reduced, the performance of the first gamma circuit 210A needs to be improved through additional power consumption or circuit area, which causes large power consumption and waste of circuit area. Therefore, the embodiment has the problems of conversion efficiency and thermal power consumption when outputting dynamic voltage, and the dynamic voltage picture has high power consumption, which cannot provide an optimal low-power solution.

[0061] In another possible implementation, the Vgmp described above can be provided by a low dropout regulator (LDO). However, the LDO has insufficient driving force, and when the LDO is disturbed, the voltage reestablishment process is particularly slow.

[0062] An electronic device is provided in an embodiment of the application. As shown in FIG. 6, the electronic device 1000B can include a circuit board (not shown in FIG. 6) and a second display apparatus 1100B. The second display apparatus 1100B can include a coupled second display screen 100B and a second display driving chip 200B. The second display driving chip 200B can be disposed on the circuit board.

[0063] As shown in FIG. 7, the second display screen 100B can include a second pixel circuit 110B. The second pixel circuit 110B can include a plurality of pixel channels, such as a first pixel channel 11B, a second pixel channel 12B, a third pixel channel 13B, a fourth pixel channel 14B, and more pixel channels not shown. Each of the plurality of pixel channels can include a plurality of sub-pixels. Taking the second pixel circuit 110B as an RGBG pixel circuit for example, the first pixel channel 11B can include at least four sub-pixels: B, R, B, R, the second pixel channel 12B can include at least four sub-pixels: G, G, G, G, the third pixel channel 13B can include at least four sub-pixels: R, B, R, B, and the fourth pixel channel 14B can include at least four sub-pixels: G, G, G, G. One sub-pixel B, one sub-pixel R, and two sub-pixels G can be taken as one pixel. For example, the first row of sub-pixels B in the first pixel channel 11B, the first row of sub-pixels G in the second pixel channel 12B, the first row of sub-pixels R in the third pixel channel 13B, and the first row of sub-pixels G in the fourth pixel channel 14B can be taken as one pixel.

[0064] The second display driving chip 200B can include a second power supply end, a plurality of output ends, a plurality of display switches, a plurality of power supply switches, a second gamma circuit 210B, and a plurality of display channel circuits. The plurality of output ends can include a first output end, a second output end, a third output end, a fourth output end, and more output ends not shown. The plurality of display switches can include a first display switch S1B, a second display switch S2B, a third display switch S3B, a fourth display switch S4B, and more display switches not shown. The plurality of power supply switches can include a first power supply switch K1B, a second power supply switch K2B, a third power supply switch K3B, a fourth power supply switch K4B, and more power supply switches not shown. The plurality of display channel circuits can include a first display channel circuit 221B, a second display channel circuit 222B, a third display channel circuit 223B, a fourth display channel circuit 224B, and more display channel circuits not shown.

[0065] The second power supply end of the second display driving chip 200B and the plurality of display channel circuits are coupled with the second gamma circuit 210B. The plurality of display channel circuits of the second display driving chip 200B are coupled with the first ends of the plurality of display switches one by one, and the second ends of the plurality of display switches are coupled with the plurality of output ends one by one. The second power supply end is coupled with the first ends of the plurality of power supply switches, and the second ends of the plurality of power supply switches are coupled with the plurality of output ends one by one. For example, the output end of the first display channel circuit 221B is coupled with the first end of the first display switch S1B, and the second end of the first display switch S1B is coupled with the first output end. The second power supply end is coupled with the first end of the first power supply switch K1B, and the second end of the first power supply switch K1B is coupled with the first output end. For another example, the output end of the mth display channel circuit is coupled with the first end of the mth display switch, and the second end of the mth display switch is coupled with the mth output end. The power supply end is coupled with the first end of the mth power supply switch, and the second end of the mth power supply switch is coupled with the mth output end. The mth display channel circuit is any one of the plurality of display channel circuits, the mth display switch is any one of the plurality of display switches, the mth power supply switch is any one of the plurality of power supply switches, and the mth output end is any one of the plurality of output ends.

[0066] The plurality of pixel channels of the second pixel circuit 110B are coupled with the plurality of output ends in the second display driving chip 200B one by one. For example, the jth pixel channel is coupled with the jth output end, the jth pixel channel is any one of the plurality of pixel channels, and the jth output end is any one of the plurality of output ends of the display driving chip. Alternatively, the plurality of sub-pixels in each pixel channel of the second pixel circuit 110B can be coupled to the same output end of the second display driving chip 200B, and the plurality of pixel channels of the second pixel circuit 110B are one by one corresponding to the plurality of output ends of the second display driving chip 200B. For example, the first row of sub-pixels B in the first pixel channel 11B, the second row of sub-pixels R in the first pixel channel 11B, the third row of sub-pixels B in the first pixel channel 11B, and the fourth row of sub-pixels R in the first pixel channel 11B are all coupled to the first output end of the second display driving chip 200B. The first row of sub-pixels G in the second pixel channel 12B, the second row of sub-pixels G in the second pixel channel 12B, the third row of sub-pixels G in the second pixel channel 12B, and the fourth row of sub-pixels G in the second pixel channel 12B are all coupled to the second output end of the second display driving chip 200B.

[0067] The sub-pixels in the same row in the plurality of pixel channels of the second pixel circuit 110B can be coupled to the same clock signal line (not shown in FIG. 7). For example, the sub-pixels B in the first row in the first pixel channel 11B, the sub-pixels G in the first row in the second pixel channel 12B, the sub-pixels R in the first row in the third pixel channel 13B, and the sub-pixels G in the first row in the fourth pixel channel 14B can be coupled to a third clock signal line. The sub-pixels R in the second row in the first pixel channel 11B, the sub-pixels G in the second row in the second pixel channel 12B, the sub-pixels B in the second row in the third pixel channel 13B, and the sub-pixels G in the second row in the fourth pixel channel 14B can be coupled to a fourth clock signal line.

[0068] In an example, possible implementations of the plurality of display channel circuits in the second display driving chip 200B and the second pixel circuit 110B are introduced next in connection with FIG. 8. FIG. 8 does not show the plurality of power switches.

[0069] The second power terminal of the second display driving chip 200B is configured to be connected to a power supply to receive a power supply voltage from the power supply. The second gamma circuit 210B receives the power supply voltage through the second power terminal and converts the power supply voltage into a plurality of voltages with different magnitudes. For example, the second gamma circuit 210B can include a plurality of resistors, and the plurality of voltages can be obtained by means of resistive voltage division, and the plurality of voltages can be Vgmp', Vdata1', Vdata2', …, Vdataq', Vgsp' in descending order of magnitude. Among them, the maximum voltage (such as Vgmp') provided by the second gamma circuit 210B is smaller than the power supply voltage. The second gamma circuit 210B can output the plurality of voltages to each display channel circuit.

[0070] The display channel circuit is configured to input the plurality of voltages and output a voltage obtained according to the plurality of voltages. Each display channel circuit can provide one of the plurality of voltages to the corresponding pixel channel through the corresponding output terminal when the corresponding display switch is turned on. For example, each display channel circuit can include a multiplexer (MUX) and a channel operational amplifier (CH-OP). The i-th input terminal of the multiplexer is coupled to the i-th voltage output terminal of the second gamma circuit 210B. The i-th input terminal of the multiplexer is any one of the plurality of input terminals of the multiplexer. The i-th voltage output terminal of the second gamma circuit 210B is any one of the plurality of voltage output terminals of the second gamma circuit 210B. The output terminal of the multiplexer is coupled to the first input terminal of the channel operational amplifier, and the second input terminal and the operational amplifier output terminal of the channel operational amplifier are both coupled to the first terminal of the first display switch S1B.

[0071] The first voltage output terminal of the second gamma circuit 210B can be configured to output Vgmp' to the first input terminal of the multiplexer of the first display channel circuit 221B, the second voltage output terminal of the second gamma circuit 210B can be configured to output Vdata1' to the second input terminal of the multiplexer of the first display channel circuit 221B, the third voltage output terminal of the second gamma circuit 210B can be configured to output Vdata2' to the third input terminal of the multiplexer of the first display channel circuit 221B,..., the (q+1)th voltage output terminal of the second gamma circuit 210B can be configured to output Vdataq' to the (q+1)th input terminal of the multiplexer of the first display channel circuit 221B, and the (q+2)th voltage output terminal of the second gamma circuit 210B can be configured to output Vgsp' to the (q+2)th input terminal of the multiplexer of the first display channel circuit 221B. The first display channel circuit 221B can obtain Vgmp according to Vgmp', Vdata1 according to Vdata1', Vdata2 according to Vdata2', Vdataq according to Vdataq', and Vgsp according to Vgsp'.

[0072] The first display channel can provide one of Vgmp, Vdata1, Vdata2,..., Vdataq, and Vgsp to the sub-pixel in the first pixel channel 11B through the first output terminal when the first display switch S1B is turned on and the first power switch K1B is turned off. The maximum voltage (e.g., Vgmp) output by the display channel circuit is less than the power supply voltage. The second power terminal can provide the power supply voltage to the first pixel channel 11B through the first output terminal when the first power switch K1B is turned on and the first display switch S1B is turned off. Each sub-pixel can include an RC load including a resistor R and a capacitor C, the first end of the resistor R is coupled to the first output terminal, the second end of the resistor R is coupled to the first end of the capacitor C, and the second end of the capacitor C is grounded.

[0073] In this embodiment, the display channel circuit is coupled to the output terminal through the display switch, and the second power terminal is coupled to the output terminal through the power switch. The output terminal can output the voltage of the display channel circuit, or output the power voltage received by the second power terminal. When the output terminal needs to output the voltage (e.g., Vdata) for driving the sub-pixel to emit light, the display channel circuit can output the voltage to the output terminal by turning on and off the display switch and the power switch. When the output terminal needs to output the voltage (e.g., Vgmp) for driving the sub-pixel not to emit light, the second power terminal can output the power voltage to the output terminal by turning on and off the display switch and the power switch. The power voltage is greater than Vgmp, and the power voltage can also drive the sub-pixel not to emit light, so the power voltage can replace Vgmp output by the display channel circuit. As can be seen, when the output terminal outputs the dynamic voltage, the voltage is switched by turning on and off the display switch and the power switch, instead of being switched according to the plurality of voltages provided by the second gamma circuit 210B. In this way, the voltage provided by the second gamma circuit 210B for the display channel circuit is less disturbed, and the voltage output by the display channel circuit adjacent to the display channel circuit is less disturbed. In this way, the voltage finally output by the output terminal is less disturbed.

[0074] In a possible implementation, as shown in FIG. 9, the plurality of display switches can be metal-oxide-semiconductor field-effect transistors (MOSFETs). The second display driving chip 200B further includes a plurality of driving buffer circuits, for example, a first driving buffer circuit 231B, a second driving buffer circuit 232B, a third driving buffer circuit 233B, and a fourth driving buffer circuit 234B. In some examples, the kth driving buffer circuit is coupled to the control terminal of the kth display switch. The kth driving buffer circuit is any one of the plurality of driving buffer circuits, and the kth display switch is any one of the plurality of display switches. For example, the first driving buffer circuit 231B is coupled to the control terminal of the first display switch S1B, the second driving buffer circuit 232B is coupled to the control terminal of the second display switch S2B, the third driving buffer circuit 233B is coupled to the control terminal of the third display switch S3B, and the fourth driving buffer circuit 234B is coupled to the control terminal of the fourth display switch S4B. Exemplarily, the driving buffer circuit is used to stabilize the control waveform of the display switch coupled thereto.

[0075] In this embodiment, the ideal waveform of the control waveform for controlling the display switch to turn on or turn off is a square wave, but in practice the control waveform can not be stable. The driving buffer circuit can stabilize the control waveform of the display switch coupled thereto. By providing one driving buffer circuit for each display switch, high-speed turning on and off of the plurality of display switches can be achieved.

[0076] In one possible implementation, the maximum voltage provided by the display channel circuit (e.g., Vgmp) can be replaced by the supply voltage at the second supply terminal.

[0077] In some examples, as shown in FIG. 10, the second display driving chip 200B is used to drive the second display screen 100B to display a red picture is taken as an example for description.

[0078] For example, in the first time period T1, the first power switch K1B is turned on, and the first display switch S1B is turned off (optionally, S1B is turned off first, and K1B is turned on later). In the second time period T2, the first display switch S1B is turned on, and the first power switch K1B is turned off. The first output terminal is configured to output a first display driving voltage in the first time period T1 and output a second display driving voltage in the second time period T2. The first display driving voltage is used to drive the sub-pixel to not emit light. For example, the first display driving voltage is equal to the supply voltage received by the second supply terminal. Optionally, the second supply terminal is configured to be connected to a power supply. The second supply terminal is configured to receive an analog supply voltage (AVDD). Since AVDD is greater than the maximum voltage (e.g., Vgmp) provided by the display channel circuit, AVDD can be used to drive the sub-pixel to not emit light, and AVDD can replace the maximum voltage Vgmp provided by the display channel circuit. In this implementation, the second supply terminal is connected to the power supply, and the supply voltage can be used as the voltage for driving the sub-pixel to not emit light through the second supply terminal. The supply voltage has a strong power supply network and a small path impedance, which can reduce the additional power consumption caused by the dynamic voltage output by the display channel circuit. Furthermore, the second display driving voltage is used to drive the sub-pixel to emit light. For example, the second display driving voltage is within a preset voltage interval. The maximum value of the preset voltage interval is less than the first display driving voltage. For example, the preset voltage interval is between Vgsp and Vgmp (the preset voltage interval does not include Vgsp and Vgmp). For example, Vgsp is 0.2V, AVDD is 8V, Vgmp = AVDD-Vgsp = 7.8V, and the preset voltage interval can be between 0.2V and 7.8V.

[0079] In the first time period T1, the first switching period Tz1, and the second time period T2, the second power switch K2B is turned on, and the second display switch S2B is turned off. The first switching period Tz1 is between the first time period T1 and the second time period T2. The second output terminal is configured to maintain output of a third display driving voltage in the first time period T1, the first switching period Tz1, and the second time period T2. The third display driving voltage is used to drive the sub-pixel to not emit light. For example, the third display driving voltage is equal to the supply voltage received by the second supply terminal. The maximum value of the preset voltage interval is also less than the third display driving voltage.

[0080] Alternatively, during the first time period T1, the first switching period Tz1 and the second time period T2, the second display switch S2B is turned on and the second power switch K2B is turned off. The second output end outputs the third display driving voltage during the first time period T1, the first switching period Tz1 and the second time period T2, which is equal to the maximum voltage (e.g., Vgmp) provided by the second display channel circuit 222B, that is, the third display driving voltage is less than the power voltage received by the second power supply end. The maximum value of the preset voltage interval is also less than the third display driving voltage.

[0081] Alternatively, during the first time period T1, the first switching period Tz1 and the second time period T2, the second display switch S2B is turned on and the second power switch K2B is turned off. The second output end outputs the third display driving voltage during the first time period T1, the first switching period Tz1 and the second time period T2, which is equal to the maximum voltage (e.g., Vgmp) provided by the second display channel circuit 222B, that is, the third display driving voltage is less than the power voltage received by the second power supply end. The maximum value of the preset voltage interval is also less than the third display driving voltage.

[0082] In the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3 and the fourth time period T4, the second power switch K2B is turned on, and the second display switch S2B is turned off. The second switching period Tz2 is located between the second time period T2 and the third time period T3, and the third switching period Tz3 is located between the third time period T3 and the fourth time period T4. The second output end is specifically configured to maintain the output of the third display driving voltage in the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3 and the fourth time period T4. Wherein, the third display driving voltage is equal to the power supply voltage (such as AVDD) received by the second power supply end. Alternatively, in the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3 and the fourth time period T4, the second display switch S2B is turned on, and the second power switch K2B is turned off. The third display driving voltage is equal to the maximum voltage (such as Vgmp) provided by the second display channel circuit 222B.

[0083] Exemplarily, in the first time period T1, the first power switch K1B is turned on, and the first display switch S1B is turned off (optionally, the S1B is turned off first, and then the K1B is turned on). In the second time period T2, the first display switch S1B is turned on, and the first power switch K1B is turned off. In the third time period T3, the first power switch K1B is turned on, and the first display switch S1B is turned off (optionally, the S1B is turned off first, and then the K1B is turned on). In the fourth time period T4, the first display switch S1B is turned on, and the first power switch K1B is turned off. In the nth time period Tn, the first power switch K1B is turned on, and the first display switch S1B is turned off (optionally, the S1B is turned off first, and then the K1B is turned on). In the (n+1)th time period Tn+1, the first display switch S1B is turned on, and the first power switch K1B is turned off. n is an odd number greater than or equal to 5. The first output end is configured to output the first display driving voltage in the first time period T1, output the second display driving voltage in the second time period T2, output the first display driving voltage in the third time period T3, output the second display driving voltage in the fourth time period T4, output the first display driving voltage in the nth time period Tn, and output the second display driving voltage in the (n+1)th time period Tn+1. The second display driving voltage output by the first output end in the first time period T1 can be Vdata12, the second display driving voltage output by the first output end in the fourth time period T4 can be Vdata14, and the second display driving voltage output by the first output end in the (n+1)th time period Tn+1 can be Vdata1(n+1). Vdata12, Vdata14, and Vdata1(n+1) are preset voltage values in a preset voltage range, for example, Vdata12, Vdata14, and Vdata1(n+1) are one of Vgmp, Vdata1, Vdata2, …, Vdataq, and Vgsp, respectively. Vdata12, Vdata14, and Vdata1(n+1) can be the same voltage value, or at least two of them can be different voltage values.

[0084] The second power switch K2B is turned on and the second display switch S2B is turned off in the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3, the fourth time period T4, the fourth switching period Tz4, the nth time period Tn, the nth switching period Tzn and the (n+1)th time period Tn+1. The second output end is configured to output a third display driving voltage in the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3, the fourth time period T4, the fourth switching period Tz4, the nth time period Tn, the nth switching period Tzn and the (n+1)th time period Tn+1. The third display driving voltage is equal to a power voltage (e.g., AVDD) received by the second power terminal. Alternatively, the second display switch S2B is turned on and the second power switch K2B is turned off in the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3, the fourth time period T4, the fourth switching period Tz4, the nth time period Tn, the nth switching period Tzn and the (n+1)th time period Tn+1. The third display driving voltage is equal to a maximum voltage (e.g., Vgmp) provided by the second display channel circuit 222B.

[0085] Alternatively, the first display channel circuit 221B outputs a maximum voltage (e.g., Vgmp) provided by the first display channel circuit 221B when the first display switch S1B is turned on and the first power switch K1B is turned on. In this embodiment, the first display channel circuit 221B continuously outputs the second display driving voltage, and the first display channel circuit 221B is in a static output mode. In this way, the first display channel circuit 221B can avoid interfering with the power voltage of the power terminal, and the design complexity of the first display channel circuit 221B can be reduced.

[0086] Exemplarily, in the first time period T1, the third display switch S3B is turned on, and the third power supply switch K3B is turned off. In the second time period T2, the third power supply switch K3B is turned on, and the third display switch S3B is turned off. In the third time period T3, the third display switch S3B is turned on, and the third power supply switch K3B is turned off. In the fourth time period T4, the third power supply switch K3B is turned on, and the third display switch S3B is turned off. In the nth time period Tn, the third display switch S3B is turned on, and the third power supply switch K3B is turned off. In the (n+1)th time period Tn+1, the third power supply switch K3B is turned on, and the third display switch S3B is turned off. n is an odd number greater than or equal to 5. The third output end is configured to output the fourth display driving voltage in the first time period T1, output the first display driving voltage in the second time period T2, output the fourth display driving voltage in the third time period T3, output the first display driving voltage in the fourth time period T4, output the fourth display driving voltage in the nth time period Tn, and output the first display driving voltage in the (n+1)th time period Tn+1. The fourth display driving voltage is within the preset voltage range. The fourth display driving voltage output by the third output end in the first time period T1 can be Vdata31, the fourth display driving voltage output by the third output end in the third time period T3 can be Vdata33, and the fourth display driving voltage output by the third output end in the nth time period Tn can be Vdata3n. Vdata31, Vdata33 and Vdata3n are preset voltage values in the preset voltage range, for example, Vdata31, Vdata33 and Vdata3n are one of Vgmp, Vdata1, Vdata2, …, Vdataq and Vgsp respectively. Vdata12, Vdata14, Vdata1(n+1), Vdata31, Vdata33 and Vdata3n can be the same voltage value, or at least two of them can be different voltage values.

[0087] In the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3, the fourth time period T4, the fourth switching period Tz4, the nth time period Tn, the nth switching period Tzn and the (n+1)th time period Tn+1, the fourth power switch K4B is turned on and the fourth display switch S4B is turned off. The fourth output end is configured to output the third display driving voltage in the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3, the fourth time period T4, the fourth switching period Tz4, the nth time period Tn, the nth switching period Tzn and the (n+1)th time period Tn+1. The third display driving voltage is equal to the power voltage (e.g., AVDD) received by the second power end. Alternatively, in the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3, the fourth time period T4, the fourth switching period Tz4, the nth time period Tn, the nth switching period Tzn and the (n+1)th time period Tn+1, the fourth display switch S4B is turned on and the fourth power switch K4B is turned off. The third display driving voltage is equal to the maximum voltage (e.g., Vgmp) provided by the fourth display channel circuit 224B.

[0088] In some other examples, the second display driving chip 200B can be configured to drive the second display screen 100B to display a blue picture. The voltage waveform diagrams of the plurality of output ends are shown in FIG. 11. The principle of the voltage waveform diagrams shown in FIG. 11 can refer to the description of the principle of the voltage waveform diagrams shown in FIG. 10, and the embodiments of the present application will not be described here. Exemplarily, Vdata11, Vdata13, Vdata1n, Vdata32, Vdata34 and Vdata3(n+1) are preset voltage values in a preset voltage interval, for example, Vdata11, Vdata13, Vdata1n, Vdata32, Vdata34 and Vdata3(n+1) are one of Vgmp, Vdata1, Vdata2, …, Vdataq and Vgsp respectively. Vdata11, Vdata13, Vdata1n, Vdata32, Vdata34 and Vdata3(n+1) can be the same voltage value, or at least two of them can be different voltage values.

[0089] In some examples, the second display driving chip 200B can be used to drive the second display screen 100B to display a green picture. The voltage waveform diagram of the plurality of output ends is shown in FIG. 12. The principle of the voltage waveform diagram shown in FIG. 12 can refer to the description of the principle of the voltage waveform diagram shown in FIG. 10, and the embodiments of the present application will not be described here. For example, Vdata21, Vdata23, Vdata2n, Vdata41, Vdata43, and Vdata4n are preset voltage values in a preset voltage interval, for example, Vdata21, Vdata23, Vdata2n, Vdata41, Vdata43, and Vdata4n are one of Vgmp, Vdata1, Vdata2, …, Vdataq, and Vgsp. Vdata21, Vdata23, Vdata2n, Vdata41, Vdata43, and Vdata4n can be the same voltage value, or at least two voltages can be different voltage values.

[0090] In this embodiment, in the case that the voltage output by the first output end is not a fixed size voltage, the voltage equal to the power voltage received by the second power supply end is used as the first display driving voltage. That is, the first display driving voltage and the second display driving voltage are from different sources. Compared with the embodiments shown in FIGS. 3-5, the power voltage at the second power supply end can be used instead of the maximum voltage provided by the display channel circuit. When the first output end outputs a dynamic voltage, it no longer switches the voltage according to the plurality of voltages provided by the second gamma circuit 210B. The interference on the voltage provided by the second gamma circuit 210B for the first display channel circuit 221B is alleviated, and the interference on the voltage output by the second display channel circuit 222B is alleviated. In this way, the interference on the voltage finally output by the second output end is alleviated. In this way, without voltage stabilization by large current drawn by the power voltage, power consumption can be reduced. Moreover, the problem of impedance and parasitic capacitance limiting the driving capability of the second gamma circuit 210B can be alleviated, thereby improving the driving capability of the second display driving chip 200B and speeding up the voltage output process. Moreover, without strengthening the performance of the second gamma circuit 210B by additional power consumption or circuit area to eliminate voltage interference, power consumption and circuit area waste can be reduced.

[0091] Based on the second display driving chip 200B provided in FIGS. 6-12, the embodiments of the present application further provide a display driving method applied to the second display driving chip 200B. As shown in FIG. 13, the method can at least include:

[0092] S100: output a first display driving voltage through the first output end in a first time period T1 and output a second display driving voltage in a second time period T2. For example, the first display driving voltage is equal to the power voltage received by the second power supply end.

[0093] S200: maintaining output of the third display driving voltage through the second output terminal in the first time period T1, the first switching time period Tz1 and the second time period T2. Exemplarily, the first switching time period Tz1 is located between the first time period T1 and the second time period T2. The second display driving voltage is located within the preset voltage interval, and a maximum value of the preset voltage interval is less than the third display driving voltage.

[0094] In a possible implementation, S100 can specifically include: outputting the first display driving voltage through the first output terminal in the first time period T1, outputting the second display driving voltage in the second time period T2, outputting the first display driving voltage in the third time period T3, and outputting the second display driving voltage in the fourth time period T4.

[0095] S200 can specifically include: maintaining output of the third display driving voltage through the second output terminal in the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3 and the fourth time period T4, and the second switching time period Tz2 is located between the second time period T2 and the third time period T3, and the third switching time period Tz3 is located between the third time period T3 and the fourth time period T4.

[0096] In a possible implementation, S100 can specifically include: outputting the first display driving voltage through the first output terminal in the first time period T1, outputting the second display driving voltage in the second time period T2, outputting the first display driving voltage in the third time period T3, outputting the second display driving voltage in the fourth time period T4, outputting the first display driving voltage in the nth time period Tn, and outputting the second display driving voltage in the (n+1)th time period Tn+1, where n is an odd number greater than or equal to 5.

[0097] S200 can specifically include: maintaining output of the third display driving voltage through the second output terminal in the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, the fourth time period T4, the fourth switching time period Tz4, the nth time period Tn, the nth switching time period Tzn and the (n+1)th time period Tn+1, and the fourth switching time period Tz4 is located between the fourth time period T4 and the nth time period Tn, and the nth switching time period Tzn is located between the nth time period Tn and the (n+1)th time period Tn+1.

[0098] In a possible implementation, the third display driving voltage is equal to a power supply voltage received by the power supply terminal.

[0099] It can be understood that the display driving method can be applied to the second display driving chip 200B. Since the effects of the chip have been described in detail in the foregoing chip embodiments, no further description is given here.

[0100] The embodiment of the present application further provides a computer readable storage medium, which stores program codes, and when the program codes are run on a device (for example, the device can be a single-chip microcomputer, a chip, a computer or a processor, etc.), the program codes can be called to execute one or more steps in the foregoing method embodiments.

[0101] Based on the understanding, the embodiment of the present application further provides a computer program product containing instructions, and the technical solution of the present application or the whole or part of the contribution to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes instructions to make a computer device (which can be a personal computer, a server or a network device, etc.) or a processor execute all or part of the steps of the method of each embodiment of the present application.

[0102] In several embodiments provided in the present application, it should be understood that the disclosed chip, device, equipment and method can be implemented by other ways. For example, the device embodiments described above are only schematic, for example, the division of the above modules is only a logical function division, and actual implementation can have another division manner, for example, a plurality of modules or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed modules can be indirect coupling or communication connection through some interfaces, devices or modules, and can be electrical, mechanical or other forms.

[0103] In addition, each functional module in each embodiment of the present application can be integrated in one device, or each module can be physically present alone, or two or more modules can be integrated in one device.

[0104] Finally, it should be noted that: the above description is only a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any change or replacement within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A display driving chip, characterized in that, The display driving chip comprises a power supply end and a plurality of output ends; the plurality of output ends comprise a first output end and a second output end; The power supply end is configured to receive a power supply voltage; The first output end is configured to output a first display driving voltage in a first time period and output a second display driving voltage in a second time period, and the first display driving voltage is equal to the power supply voltage; The second output end is configured to output a third display driving voltage in the first time period, a first switching time period and the second time period, and the first switching time period is located between the first time period and the second time period; The second display driving voltage is located within a preset voltage interval, and a maximum value of the preset voltage interval is less than the third display driving voltage.

2. The display driver chip of claim 1, wherein, The plurality of output ends further comprise a third output end; The third output end is configured to output a fourth display driving voltage in the first time period and output the first display driving voltage in the second time period, and the fourth display driving voltage is located within the preset voltage interval; The fourth display driving voltage output by the third output end in the first time period is different in size from the second display driving voltage output by the first output end in the second time period.

3. The display driving chip of claim 1 or 2, wherein The first output end is specifically configured to output the first display driving voltage in the first time period, output the second display driving voltage in the second time period, output the first display driving voltage in a third time period, and output the second display driving voltage in a fourth time period; The second output end is specifically configured to output the third display driving voltage in the first time period, the first switching time period, the second time period, a second switching time period, the third time period, a third switching time period and the fourth time period, and the second switching time period is located between the second time period and the third time period, and the third switching time period is located between the third time period and the fourth time period.

4. The display driving chip of claim 1 or 2, wherein The first output end is specifically configured to output the first display driving voltage in the first time period, output the second display driving voltage in the second time period, output the first display driving voltage in the third time period, output the second display driving voltage in the fourth time period, output the first display driving voltage in an n time period, and output the second display driving voltage in an n+1 time period, and n is an odd number greater than or equal to 5. The second output end is specifically configured to maintain output of the third display driving voltage in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, the fourth time period, the fourth switching time period, the nth time period, the nth switching time period and the (n+1)th time period.

5. The display driver chip according to any one of claims 1-4, wherein, The chip further comprises a first display channel circuit, a first display switch and a first power supply switch; an output end of the first display channel circuit is coupled with a first end of the first display switch, and a second end of the first display switch is coupled with the first output end; the power supply end is coupled with a first end of the first power supply switch, and a second end of the first power supply switch is coupled with the first output end.

6. The display driver chip of claim 5, wherein, The chip further comprises a plurality of display channel circuits, a plurality of display switches and a plurality of power supply switches; an output end of the mth display channel circuit is coupled with a first end of the mth display switch, and a second end of the mth display switch is coupled with an mth output end; the power supply end is coupled with a first end of the mth power supply switch, and a second end of the mth power supply switch is coupled with the mth output end; the mth display channel circuit is any one of the plurality of display channel circuits, the mth display switch is any one of the plurality of display switches, the mth power supply switch is any one of the plurality of power supply switches, and the mth output end is any one of the plurality of output ends.

7. The display driver chip of claim 6, wherein, The chip further comprises a plurality of drive enhancement circuits, a kth drive enhancement circuit is coupled with a control end of a kth display switch; the kth drive enhancement circuit is any one of the plurality of drive enhancement circuits, and the kth display switch is any one of the plurality of display switches.

8. The display driver chip according to any one of claims 1-7, wherein, The third display driving voltage is equal to the power supply voltage.

9. The display driver chip of any of claims 1-8, wherein, The power supply end is configured to be connected with a power supply.

10. A display driving chip, characterized in that, The display driving chip comprises a power supply end, a first output end, a first display channel circuit, a first display switch and a first power supply switch; the power supply end is configured to receive a power supply voltage; an output end of the first display channel circuit is coupled with a first end of the first display switch, and a second end of the first display switch is coupled with the first output end; the power supply end is coupled with a first end of the first power supply switch, and a second end of the first power supply switch is coupled with the first output end.

11. The display driver chip of claim 10, wherein, The chip further comprises a plurality of output ends, a plurality of display channel circuits, a plurality of display switches and a plurality of power supply switches; an output end of the mth display channel circuit is coupled with a first end of the mth display switch, and a second end of the mth display switch is coupled with an mth output end; the power supply end is coupled with a first end of the mth power supply switch, and a second end of the mth power supply switch is coupled with the mth output end; The mth display channel circuit is any one of the plurality of display channel circuits, the mth display switch is any one of the plurality of display switches, the mth power switch is any one of the plurality of power switches, and the mth output terminal is any one of the plurality of output terminals.

12. The display driver chip of claim 11, wherein, The chip further comprises a plurality of drive enhancement circuits, The kth drive enhancement circuit is coupled to the control terminal of the kth display switch, the kth drive enhancement circuit is any one of the plurality of drive enhancement circuits, and the kth display switch is any one of the plurality of display switches.

13. The display driver chip of any of claims 10-12, wherein, The power terminal is used to connect a power supply.

14. A display driving method, comprising: The display driving method is applied to a display driving chip, the display driving chip comprises a power terminal and a plurality of output terminals; the power terminal is used to receive a power voltage; the plurality of output terminals comprises a first output terminal and a second output terminal; the method comprises: outputting, through the first output terminal, a first display driving voltage in a first time period and a second display driving voltage in a second time period, the first display driving voltage being equal to the power voltage; maintaining, through the second output terminal, output of a third display driving voltage in the first time period, a first switching time period, and the second time period, the first switching time period being between the first time period and the second time period; wherein the second display driving voltage is within a preset voltage interval, and a maximum value of the preset voltage interval is less than the third display driving voltage.

15. The display driving method according to claim 14, wherein The plurality of output terminals further comprises a third output terminal, and the method further comprises: outputting, through the third output terminal, a fourth display driving voltage in the first time period and the first display driving voltage in the second time period, the fourth display driving voltage being within the preset voltage interval; The fourth display driving voltage output by the third output terminal in the first time period is different in size from the second display driving voltage output by the first output terminal in the second time period.

16. The display driving method of claim 14 or 15, wherein outputting, through the first output terminal, a first display driving voltage in a first time period and a second display driving voltage in a second time period, comprises: outputting, through the first output terminal, the first display driving voltage in the first time period, the second display driving voltage in the second time period, the first display driving voltage in a third time period, and the second display driving voltage in a fourth time period; maintaining, through the second output terminal, output of a third display driving voltage in the first time period, a first switching time period, and the second time period, comprises: maintaining, through the second output terminal, output of the third display driving voltage in the first time period, the first switching time period, the second time period, a second switching time period, the third time period, a third switching time period, and the fourth time period, the second switching time period being between the second time period and the third time period, and the third switching time period being between the third time period and the fourth time period.

17. The display driving method of claim 14 or 15, wherein the outputting, by the first output terminal, the first display driving voltage in the first time period and the second display driving voltage in the second time period comprises: outputting, by the first output terminal, the first display driving voltage in the first time period, the second display driving voltage in the second time period, the first display driving voltage in the third time period, the second display driving voltage in the fourth time period, the first display driving voltage in the nth time period, and the second display driving voltage in the nth+1 time period, n being an odd number greater than or equal to 5. The outputting, by the second output terminal, the third display driving voltage in the first time period, the first switching time period, and the second time period comprises: outputting, by the second output terminal, the third display driving voltage in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, the fourth time period, the fourth switching time period, the nth time period, the nth switching time period, and the nth+1 time period, the fourth switching time period being between the fourth time period and the nth time period, and the nth switching time period being between the nth time period and the nth+1 time period. The third display driving voltage is equal to the power supply voltage. The display device comprises a display screen and the display driving chip of any one of claims 1-13, and the display screen comprises a plurality of pixel channels. The jth pixel channel is coupled to the jth output terminal, the jth pixel channel being any one of the plurality of pixel channels, and the jth output terminal being any one of the plurality of output terminals of the display driving chip.

18. The display driving method according to any one of claims 14-17, wherein, The electronic device comprises a circuit board and the display device of claim 19, and the display driving chip in the display device is disposed on the circuit board.

19. A display device comprising: ​ ​ 20. An electronic device, comprising: ​

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