Power module packaging structure

Abstract

The present invention provides a power module packaging structure. The packaging structure comprises a substrate, a chip layer, a first clip, a second clip, leads, terminals, and a packaging layer, wherein the substrate comprises a metal layer, the metal layer comprises a first region, a second region, a first lead region, and a second lead region; the chip layer comprises first chips and second chips, and at least one first chip and second chip are respectively soldered to the first region and the second region; the first clip electrically connects the first chips to the second region and the first chips to the first lead region, respectively, and the first clip is provided with a first boss and a second boss; the second clip electrically connects the second chips to the second region and the second chips to the first lead region, respectively, and the second clip is provided with a third boss and a fourth boss; the leads are respectively electrically connected to the corresponding regions; the terminals are respectively electrically connected to the corresponding regions; and the packaging layer covers the exposed surfaces of all parts. By means of using a first chip and a second clip provided with bosses and through holes to interconnect a chip layer and a substrate, the present invention reduces the thermal-mechanical stress between the chip layer and the first clip, as well as between the chip layer and the second clip, thereby improving the reliability of the power module.

Description

Power module packaging structure TECHNICAL FIELD

[0001] The present application belongs to the technical field of power device packaging, and relates to a power module packaging structure. BACKGROUND

[0002] Power modules are core components in modern power electronic systems, which are widely used in traditional power electronic systems such as motor drives, frequency converters, power supplies, and are also widely used in new energy power production and power consumption fields such as photovoltaic, wind power, electric vehicles. At present, the lead bonding process is often used in the packaging process of insulated gate bipolar transistors (IGBT) power semiconductor devices to realize the electrical connection between chips and between chips and substrates. However, the bridge of bonding wires often brings problems such as large parasitic inductance, virtual welding, uneven current distribution on the surface of the chip, poor current carrying capacity, and reliability problems under the action of periodic thermal stress, which greatly limits the performance of IGBT power modules.

[0003] Therefore, it is urgent to find a power module packaging structure that can improve the current uniformity and reliability of the chip surface in the power module. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a power module packaging structure to solve the problem of uneven current distribution and poor reliability of the chip surface in the power module packaging structure in the prior art.

[0005] To achieve the above-mentioned purposes and other related purposes, the present application provides a power module packaging structure, comprising:

[0006] A substrate comprising an insulating and heat-conducting layer and a metal layer on the upper surface of the insulating and heat-conducting layer, the metal layer comprising a first area, a second area, a first lead area and a plurality of second lead areas;

[0007] A chip layer comprising a plurality of first chips and a plurality of second chips, at least one of the first chips and the second chips being welded to the first area, and at least one of the first chips and the second chips being welded to the second area;

[0008] A first clamping piece electrically connected to the first chip above the first area and the second area, and the first chip above the second area and the first lead area, respectively, the first clamping piece comprising at least one first boss and a second boss spaced apart from the first boss;

[0009] a second clip electrically connecting the second chip above the first area with the second area and the second chip above the second area with the first lead area, the second clip being provided with at least one third boss and a fourth boss spaced from the third boss;

[0010] a plurality of leads electrically connecting each of the second lead areas with a corresponding area of the back surface of the corresponding first chip;

[0011] a plurality of terminals electrically connected with the first area, the second area, the first lead area and each of the second lead areas, respectively;

[0012] a packaging layer covering exposed surfaces of the leads, the chip layer, the first clip and the second clip and the upper surface of the substrate.

[0013] Optionally, the first clip electrically connected with the first chip above the first area is symmetrically arranged with the first clip electrically connected with the first chip above the second area, and the second clip electrically connected with the second chip above the first area is symmetrically arranged with the second clip electrically connected with the second chip above the second area.

[0014] Optionally, the first chip and the second chip above the first area are symmetrically distributed with the first chip and the second chip above the second area.

[0015] Optionally, a plurality of the first bosses are spaced in the X direction in the first clip above the first chip, the first chip being electrically connected with the first clip regions on both sides of the first bosses in the X direction, the second boss being provided in the first clip between the first chip and the first clip region electrically connected with the second area and the first lead area, and the first boss and the second boss are further provided with a plurality of first through holes spaced in the Y direction and penetrating the first clip, the first through holes in the first boss dividing the first boss into multiple segments in the Y direction, and the first through holes in the second boss dividing the side wall of the second boss close to the first boss into multiple segments.

[0016] Optionally, the first through holes in each of the first bosses correspond to each other in the X direction, and the first through holes in the first boss and the second boss also correspond to each other in the X direction.

[0017] Optionally, a plurality of the third protrusions are arranged in the second clamping piece in the region directly above the second chip in the X direction, the second chip is electrically connected to the regions of the second clamping piece on both sides of the third protrusion in the X direction, the fourth protrusion is arranged in the second clamping piece between the region of the second clamping piece electrically connected to the first lead region and the second region and the second chip, and a plurality of second through holes are arranged in the third protrusion and the fourth protrusion in the Y direction and penetrate the second clamping piece, the second through holes in the third protrusion divide the third protrusion into multiple segments in the Y direction, and the second through holes in the fourth protrusion divide the side wall of the fourth protrusion close to the third protrusion into multiple segments.

[0018] Optionally, the second through holes in each of the third protrusions correspond to each other in the X direction, and the second through holes in the third protrusions and the fourth protrusions also correspond to each other in the X direction.

[0019] Optionally, a plurality of third through holes are arranged in an array on the mesa of the second protrusion and penetrate the first clamping piece, and a plurality of fourth through holes are arranged in an array on the mesa of the fourth protrusion and penetrate the second clamping piece.

[0020] Optionally, the terminals include a plurality of power terminals and a plurality of signal terminals, the power terminals include a direct current positive terminal electrically connected to the first region, a direct current negative terminal electrically connected to the first lead region, and an alternating current output terminal electrically connected to the second region.

[0021] Optionally, the signal terminals include upper bridge signal terminals and lower bridge signal terminals, the upper bridge signal terminals include an upper bridge first electrode sensing terminal, an upper bridge current sensing terminal, an upper bridge second electrode sensing terminal, an upper bridge gate terminal, an upper bridge negative temperature sensing terminal, and an upper bridge positive temperature sensing terminal, and the lower bridge signal terminals include a lower bridge first electrode sensing terminal, a lower bridge current sensing terminal, a lower bridge second electrode sensing terminal, a lower bridge gate terminal, a lower bridge negative temperature sensing terminal, and a lower bridge positive temperature sensing terminal.

[0022] Optionally, the upper bridge first electrode sensing terminal is electrically connected with the first region, the upper bridge current sensing terminal, the upper bridge second electrode sensing terminal, the upper bridge gate terminal, the upper bridge negative temperature sensing terminal and the upper bridge positive temperature sensing terminal are respectively electrically connected with different second lead regions, the second lead regions corresponding to the upper bridge current sensing terminal, the upper bridge second electrode sensing terminal, the upper bridge negative temperature sensing terminal and the upper bridge positive temperature sensing terminal are respectively electrically connected with the corresponding regions of the first chip back surface above the first region through the lead, and the second lead region corresponding to the upper bridge gate terminal is electrically connected with the gate of the first chip above the first region through the lead, the lower bridge first electrode sensing terminal is electrically connected with the second region, the lower bridge current sensing terminal, the lower bridge second electrode sensing terminal, the lower bridge gate terminal, the lower bridge negative temperature sensing terminal and the lower bridge positive temperature sensing terminal are respectively electrically connected with different second lead regions, the second lead regions corresponding to the lower bridge current sensing terminal, the lower bridge second electrode sensing terminal, the lower bridge negative temperature sensing terminal and the lower bridge positive temperature sensing terminal are respectively electrically connected with the corresponding regions of the first chip back surface above the second region through the lead, and the second lead region corresponding to the lower bridge gate terminal is electrically connected with the gate of the first chip above the second region through the lead.

[0023] Optionally, the upper bridge signal terminal, the alternating current output terminal and the lower bridge signal terminal are led out from the same side wall of the packaging layer, and the upper bridge signal terminal and the lower bridge signal terminal are symmetrically arranged about the alternating current output terminal.

[0024] Optionally, the direct current positive terminal and the direct current negative terminal are led out from the same side wall of the packaging layer, the alternating current output terminal is led out from the opposite side wall of the side wall from which the direct current positive terminal and the direct current negative terminal are led out, and the portions of the direct current positive terminal and the direct current negative terminal protruding from the side wall of the packaging layer are symmetrically distributed about the center line of the side wall of the packaging layer.

[0025] Optionally, the side walls of the first boss and the second boss are inclined.

[0026] Optionally, the first clamping piece is provided with a first opening penetrating the first clamping piece at both ends of the first clamping piece in the X direction, and the second clamping piece is provided with a second opening penetrating the second clamping piece at both ends of the second clamping piece in the X direction.

[0027] Optionally, the metal heat dissipation layer covering the lower surface of the insulating and heat conductive layer is further provided in the substrate, and the metal heat dissipation layer is insulated from the metal layer.

[0028] As described above, the power module packaging structure of the present application improves the uniformity of the chip layer surface current distribution by symmetrically distributing the first and second chips above the first and second regions, thereby enhancing the current carrying capacity of the power module; the layout of each chip in the chip layer is more flexible by using the first and second clamping pieces to interconnect the chip layer and the substrate, which reduces the length of the commutation loop in the power module and reduces the parasitic inductance inside the power module; by providing the first and second bosses, the first and third through holes in the first clamping piece, and the third and fourth bosses, the second and fourth through holes in the second clamping piece, and then filling the gaps between the through holes and the bosses and the chip layer with the packaging layer, the thermal mechanical stress between the first and second clamping pieces and the chip layer is reduced, at the same time, the engagement structure is formed between the packaging layer and the first and second clamping pieces, the bonding strength between the packaging layer and the first and second clamping pieces is enhanced, the delamination between the packaging layer and the first and second clamping pieces is avoided, the reliability of the power module is improved, and the power module has high industrial utilization value. BRIEF DESCRIPTION OF DRAWINGS

[0029] Fig. 1 shows a structural schematic diagram of the power module packaging structure of the present application.

[0030] Fig. 2 shows a top view of the power module packaging structure of the present application.

[0031] Fig. 3 shows a side view of the power module packaging structure of the present application.

[0032] Fig. 4 shows a structural schematic diagram of the first clamping piece of the power module packaging structure of the present application.

[0033] Fig. 5 shows a side view of the first clamping piece of the power module packaging structure of the present application.

[0034] Fig. 6 shows a structural schematic diagram of the second clamping piece of the power module packaging structure of the present application.

[0035] Fig. 7 shows a side view of the second clamping piece of the power module packaging structure of the present application.

[0036] BRIEF DESCRIPTION OF DRAWINGS 1 substrate 11 insulating and heat conducting layer 12 metal layer 13 first region 14 second region 15 first lead region 16 second lead region 2 chip layer 21 first chip 22 second chip 3 first clamp 31 first boss 32 second boss 33 first through hole 34 third through hole 4 second clamp 41 third boss 42 fourth boss 43 second through hole 44 fourth through hole 5 lead 6 terminal 61 power terminal 611 DC positive terminal 612 DC negative terminal 613 AC output terminal 62 signal terminal 63 upper bridge signal terminal 631 upper bridge first electrode sensing terminal 632 upper bridge current sensing terminal 633 upper bridge second electrode sensing terminal 634 upper bridge gate terminal 635 upper bridge negative temperature sensing terminal 636 upper bridge positive temperature sensing terminal 64 lower bridge signal terminal 641 lower bridge first electrode sensing terminal 642 lower bridge current sensing terminal 643Lower Bridge Second Electrode Sensing Terminal 644 Lower Bridge Gate Terminal 645 Lower Bridge Negative Temperature Sensing Terminal 646 Lower Bridge Positive Temperature Sensing Terminal 647 Packaging Layer DETAILED DESCRIPTION

[0037] Other advantages and benefits of the present application will become apparent to those skilled in the art upon consideration of the disclosure or can be learned by practice of the application. The present application can be realized and achieved by means other than as specifically described herein and constitute embodiments within the spirit and scope of the present application. Various modifications and changes can be made thereto without departing from the spirit and scope of the present application.

[0038] Referring to FIGS. 1-7, it is to be understood that the figures provided in this embodiment are merely schematic illustrations of the basic concept of the present application, and thus the figures show only the components related to the present application, rather than being drawn according to the number, shape and size of the components in actual implementation. The actual implementation of each component can be changed arbitrarily in terms of shape, number and ratio, and the layout of the components can be more complex.

[0039] The embodiment provides a power module packaging structure, as shown in Figures 1, 2 and 3, which are a structural schematic diagram of the power module packaging structure, a top view of the power module packaging structure and a side view of the power module packaging structure respectively, and the power module packaging structure comprises a substrate 1, a chip layer 2, a first clamping piece 3, a second clamping piece 4, a lead wire 5, a terminal 6 and a packaging layer 7, wherein the substrate 1 comprises an insulating and heat-conducting layer 11 and a metal layer 12 on the upper surface of the insulating and heat-conducting layer 11, the metal layer 12 comprises a first area 13, a second area 14, a first lead wire area 15 and a plurality of second lead wire areas 16; the chip layer 2 comprises a plurality of first chips 21 and a plurality of second chips 22, at least one first chip 21 and one second chip 22 are welded to the first area 13, and at least one first chip 21 and one second chip 22 are welded to the second area 14; the first clamping piece 3 is electrically connected to the first chip 21 above the first area 13 and the first chip 21 above the second area 14 and the second area 14 and the first lead wire area 15 respectively, at least one first boss 31 and a second boss 32 spaced from the first boss 31 are arranged in the first clamping piece 3; the second clamping piece 4 is electrically connected to the second chip 22 above the first area 13 and the second chip 22 above the second area 14 and the first lead wire area 15 respectively, at least one third boss 41 and a fourth boss 42 spaced from the third boss 41 are arranged in the second clamping piece 4; a plurality of lead wires 5 are electrically connected to each second lead wire area 16 and the corresponding area on the back of each first chip 21 corresponding to each second lead wire area 16 respectively; a plurality of terminals 6 are electrically connected to the first area 13, the second area 14, the first lead wire area 15 and each second lead wire area 16 respectively; and the packaging layer 7 covers the exposed surfaces of the lead wire 6, the chip layer 2, the first clamping piece 3 and the second clamping piece 4 and the upper surface of the substrate 1.

[0040] Specifically, the substrate 1 is used as a process platform for power device packaging, and the metal layer 12 on the upper surface of the substrate 1 also serves as an interconnection between corresponding chips in the power module; the size, thickness and shape of the substrate 1 can be selected according to actual conditions while ensuring the performance of the power module.

[0041] Specifically, the material of the insulating and heat-conducting layer 11 comprises aluminum oxide, aluminum nitride, silicon nitride or other suitable high-thermal-conductivity insulating materials.

[0042] Specifically, the shape, thickness and size of the insulating and heat-conducting layer 11 can be selected according to actual conditions while ensuring the performance of the power module.

[0043] Specifically, the material of the metal layer 12 comprises copper, gold, silver, aluminum or other suitable conductive materials. Preferably, a copper layer with high thermal conductivity and low resistivity is used as the metal layer 12.

[0044] Specifically, the first region 13, the second region 14, the first lead region 15 and the second lead region 16 are generally obtained by etching the first metal layer 12 formed on the surface of the first insulating and heat-conducting layer 11; the first region 13 is used for welding the first chip 21 and the second chip 22 in the upper bridge of the power module, the second region 14 is used for welding the first chip 21 and the second chip 22 in the lower bridge of the power module, and the first lead region 15 and the second lead region 16 are respectively used for welding the terminal 6 of the power module and the lead 5 of each device in the bonded interconnection power module.

[0045] Specifically, the thickness of the metal layer 12 can be selected according to actual conditions while ensuring the performance of the power module; the size and shape of the first region 13 can be selected according to actual conditions; the size and shape of the second region 14 can be selected according to actual conditions; the size and shape of the first lead region 15 can be selected according to actual conditions; the size, shape and number of the second lead region 16 can be selected according to actual conditions; and the arrangement of the first region 13, the second region 14, the first lead region 15 and the second lead region 16 on the surface of the first insulating and heat-conducting layer 11 can be selected according to actual conditions.

[0046] Specifically, the first chip 21 includes an IGBT chip, a MOS chip or other suitable power device chip; and the second chip 22 includes a diode chip or other suitable chip. Preferably, the first chip 21 is an IGBT chip, and the second chip 22 is a freewheeling diode chip.

[0047] Specifically, the size and shape of the first chip 21 are related to the manufacturing process, which is not limited here; and the size and shape of the second chip 22 are related to the related manufacturing process, which is not limited here.

[0048] Specifically, the first chip 21 and the second chip 22 are synchronously welded on the upper surfaces of the first region 13 and the second region 14, and welding the first chip 21 and the second chip 22 on the upper surfaces of the first region 13 and the second region 14 includes the following steps: synchronously forming a solder layer on the upper surfaces of the first region 13 and the second region 14; attaching the first chip 21 and the second chip 22 to the solder layer on the upper surfaces of the first region 13 and the second region 14, respectively, and the first chip 21 and the second chip 22 above the first region 13 and the second region 14 are symmetrically distributed; and welding the first chip 21 and the second chip 22 above the first region 13 and the second region 14 through the solder layer, so as to realize fixed electrical connection between the collector of the first chip 21 above the first region 13 and the first region 13, fixed electrical connection between the cathode of the second chip 22 above the first region 13 and the first region 13, fixed electrical connection between the collector of the first chip 21 above the second region 14 and the second region 14, and fixed electrical connection between the cathode of the second chip 22 above the second region 14 and the second region 14.

[0049] Specifically, the solder layer is usually a tin paste layer commonly used in the process of soldering power devices, which is obtained after the soldering process, and will not be described here; the method of mounting the first chip 21 and the second chip 22 includes manual mounting, mounting machine mounting or other suitable methods; the method of synchronously soldering the first chip 21 and the second chip 22 on the first area 13 and the second area 14 includes reflow soldering or other suitable soldering methods. Preferably, the mounting machine is used to mount the first chip 21 and the second chip 22, so as to improve the soldering precision of the chips and the symmetry of the chips soldered in the first area 13 and the second area 14.

[0050] As an example, the first chip 21 and the second chip 22 above the first area 13 are symmetrically distributed with the first chip 21 and the second chip 22 above the second area 14.

[0051] Specifically, by symmetrically distributing the first chip 21 and the second chip 22 above the first area 13 with the first chip 21 and the second chip 22 above the second area 14, the imbalance of current in the power module can be reduced, the current of individual chips can be prevented from being too large, and the bonding of the lead 5 and the soldering of the terminal 6 are facilitated.

[0052] Specifically, the distance between the first chip 21 and the second chip 22 can be selected according to actual conditions while ensuring the performance of the power module.

[0053] Specifically, the first chip 21 and the second chip 22 above the first area 13 are symmetrically distributed with the first chip 21 and the second chip 22 above the second area 14.

[0054] Specifically, the first solder layer is usually a tin paste layer commonly used in the process of soldering power devices, which is obtained after the soldering process, and will not be described here.

[0055] Specifically, as shown in FIG. 4 and FIG. 5, which are a structural schematic diagram of the first clamp 3 and a side view of the first clamp 3 respectively, the size and shape of the first clamp 3 can be selected according to actual conditions while ensuring the performance of the power module.

[0056] Specifically, the material of the first clamp 3 includes copper, gold, silver, aluminum, nickel, titanium, platinum or other suitable conductive materials. Preferably, a copper clamp with high thermal conductivity and low resistivity is used as the first clamp 3.

[0057] As an example, a plurality of first protrusions 31 are arranged in the first clamping piece 3 above the first chip 21 along the X direction, the first chip 21 is electrically connected with the regions of the first clamping piece 3 on both sides of the first protrusions 31 along the X direction, the second protrusion 32 is arranged in the first clamping piece 3 between the region of the first clamping piece 3 electrically connected with the second region 14 and the first lead region 15 and the first chip 21, and a plurality of first through holes 33 are arranged in the first protrusions 31 and the second protrusion 32 along the Y direction and penetrate the first clamping piece 3, the first through holes 33 in the first protrusions 31 divide the first protrusions 31 along the Y direction into multiple segments, and the first through holes 33 in the second protrusion 32 divide the side wall of the second protrusion 32 close to the first protrusions 31 into multiple segments.

[0058] Specifically, the side walls of the first protrusions 31 and the second protrusion 32 are inclined, the height, size and inclination degree of the side walls of the first protrusions 31 can be selected according to actual conditions under the condition of ensuring the performance of the power module, the number of the first protrusions 31 in the first clamping piece 3 can be selected according to actual conditions, the height, size and inclination degree of the side walls of the second protrusion 32 can be selected according to actual conditions, the distance between the adjacent two first protrusions 31 can be selected according to actual conditions, and the distance between the first protrusions 31 and the second protrusion 32 can be selected according to actual conditions. In the embodiment, three first protrusions 31 and one second protrusion 32 are arranged in the first clamping piece 3, the inclination degree, height and size in the Y direction of the side walls of the first protrusions 31 and the second protrusion 32 are the same, and the size of the first protrusions 31 in the X direction is smaller than the size of the second protrusion 32 in the X direction. The height here refers to the distance between the bottom surface of each protrusion and the top surface of the protrusion.

[0059] Specifically, by arranging the first protrusions 31 and the second protrusion 32 in the first clamping piece 3 and arranging a plurality of first through holes 33 in the side walls of the first protrusions 31 and the second protrusion 32 close to the first protrusions 31 along the Y direction, the thermal mechanical stress between the first clamping piece 3 and the first chip 21 can be reduced, the number of the first through holes 33 in the first protrusions 31 can be selected according to actual conditions under the condition of ensuring the performance of the power module, the distance between the first through holes 33 in the first protrusions 31 and the edge of the first clamping piece 3 in the Y direction can be selected according to actual conditions, the number of the first through holes 34 in the second protrusion 32 can be selected according to actual conditions, and the distance between the first through holes 33 in the second protrusion 32 and the edge of the first clamping piece 3 in the Y direction can be selected according to actual conditions. In the embodiment, five first through holes 33 are arranged in each first protrusion 31 along the Y direction, and five first through holes 33 are arranged on the side wall of the second protrusion 32 close to the first protrusions 31.

[0060] Specifically, in the X direction, the distance between two adjacent first through holes 33 in the first boss 31 is the same, and the cross-sectional shape of the first through hole 33 is a rounded rectangular shape; the distance between two adjacent first through holes 33 in the second boss 31 is the same, and the cross-sectional shape of the first through hole 33 is a rounded rectangular shape; the number of first through holes 33 in two adjacent first bosses 31 can be the same or different under the condition of ensuring the performance of the power module; the distance between two adjacent first through holes 33 in the first boss 31 can also be different; the distance between two adjacent first through holes 33 in the second boss 32 can also be different; the cross-sectional shape of the first through hole 33 in the first boss 31 can also not be a rounded rectangular shape; and the cross-sectional shape of the first through hole 33 in the second boss 32 can also not be a rounded rectangular shape. In the embodiment, the first through hole 33 in each first boss 31 corresponds to one in the X direction, and the first through hole 33 in the first boss 31 also corresponds to one in the X direction.

[0061] Specifically, the first clamping piece 3 is also provided with a first opening penetrating the first clamping piece 3 at both ends in the X direction, so that the two ends of the first clamping piece 3 in the X direction are divided into multiple sections in the Y direction, thereby reducing the thermal mechanical stress between the first clamping piece 3 and the chip layer 2. In the embodiment, two first openings are respectively arranged at both ends of the first clamping piece 3 in the X direction.

[0062] Specifically, the size and depth of the first opening can be selected according to actual conditions under the condition of ensuring the performance of the power module. The depth here refers to the size of the first opening in the X direction.

[0063] As an example, the mesa of the second boss 32 is provided with a plurality of third through holes 34 penetrating the first clamping piece 3 and arranged in an array.

[0064] Specifically, the third through hole 34 is arranged on the mesa of the second boss 32, so that the packaging layer 7 and the first clamping piece 3 are engaged with each other, the bonding strength between the first clamping piece 3 and the packaging layer 7 is enhanced, and delamination is avoided. The number of third through holes 34 in the second boss 32 can be selected according to actual conditions under the condition of ensuring the performance of the power module; the third through holes 34 in the second boss 32 can also not be arranged in an array; and the shape and size of the third through hole 34 can be selected according to actual conditions. Preferably, four circular third through holes 34 are arranged on the mesa of the second boss 32, which are symmetrically distributed about the center line of the second boss 32 in the X direction and the Y direction.

[0065] Specifically, the second welding layer is arranged between the second chip 22 and the second clip 4 above the first region 13 and the second region 14, and the two ends of the second clip 4 above the first region 13 are fixedly and electrically connected to the second chip 22 and the second region 14 through the second welding layer; the second welding layer is also arranged between the second chip 22 and the second clip 4 above the second region 14 and the first lead region 15, and the two ends of the second clip 4 above the first region 13 are fixedly and electrically connected to the second chip 22 and the first lead region 15 through the second welding layer.

[0066] Specifically, the second welding layer is usually a tin paste layer commonly used in the process of welding power devices, which is obtained after the soldering process, and will not be described here. In this embodiment, the first welding layer and the second welding layer are formed synchronously, and the electrical connection between the first clip 3, the first chip 21 and the second region 14 and the electrical connection between the second clip 4, the second chip 22 and the first lead region 15 are realized by synchronous soldering.

[0067] Specifically, as shown in FIGS. 6 and 7, which are a structural schematic view of the second clip 4 and a side view of the second clip 4 respectively, the size and shape of the second clip 4 can be selected according to actual conditions under the condition of ensuring the performance of the power module. In this embodiment, the size of the second clip 4 in the Y direction is smaller than the size of the first clip 3 in the Y direction, and the thickness and the size of the first clip 3 and the second clip 4 in the X direction are the same.

[0068] Specifically, the material of the second clip 4 includes copper, gold, silver, aluminum, nickel, titanium, platinum or other suitable conductive materials. Preferably, a copper clip with high thermal conductivity and low resistivity is used as the second clip 4.

[0069] For example, the first clip 3 electrically connected to the first chip 21 above the first region 13 is symmetrically arranged with the first clip 3 electrically connected to the first chip 21 above the second region 14, and the second clip 4 electrically connected to the second chip 22 above the first region 13 is symmetrically arranged with the second clip 4 electrically connected to the second chip 22 above the second region 14, so that the current distribution in the power module is more uniform.

[0070] As an example, a plurality of third protrusions 41 are arranged in the second clamping piece 4 in the region directly above the second chip 22 along the X direction, the second chip 22 is electrically connected with the regions of the second clamping piece 4 located on both sides of the third protrusions 41 along the X direction, a fourth protrusion 42 is arranged in the second clamping piece 4 between the region of the second clamping piece 4 electrically connected with the first lead region 15 and the second region 14 and the second chip 22, and a plurality of second through holes 43 are arranged in the third protrusions 41 and the fourth protrusion 42 along the Y direction and penetrate the second clamping piece 4, the second through holes 43 in the third protrusions 41 divide the third protrusions along the Y direction into multiple sections, and the second through holes 43 in the fourth protrusion 42 divide the side wall of the fourth protrusion 42 close to the third protrusions 41 into multiple sections.

[0071] Specifically, the side walls of the third protrusions 41 and the fourth protrusion 42 are inclined, the height, size and inclination degree of the side walls of the third protrusions 41 can be selected according to actual conditions under the condition of ensuring the performance of the power module, the number of the third protrusions 41 in the second clamping piece 4 can be selected according to actual conditions, the height, size and inclination degree of the side walls of the fourth protrusion 42 can be selected according to actual conditions, the distance between two adjacent third protrusions 41 can be selected according to actual conditions, and the distance between the third protrusions 41 and the fourth protrusion 42 can be selected according to actual conditions. In the embodiment, two third protrusions 41 and one fourth protrusion 42 are arranged in the second clamping piece 4, the inclination degree, height and size in the Y direction of the side walls of the third protrusions 41 and the fourth protrusion 42 are the same, and the size of the third protrusions 41 in the X direction is smaller than the size of the fourth protrusion 42 in the X direction. The height here refers to the distance between the bottom surface of each protrusion and the top surface of the protrusion.

[0072] Specifically, by arranging the third protrusions 41 and the fourth protrusion 42 in the second clamping piece 4 and arranging a plurality of second through holes 43 in the side walls of the third protrusions 41 and the fourth protrusion 42 close to the third protrusions 41 along the Y direction, the thermal mechanical stress between the second clamping piece 4 and the first chip 21 can be reduced, the number of the second through holes 43 in the third protrusions 41 can be selected according to actual conditions under the condition of ensuring the performance of the power module, the distance between the second through holes 43 in the third protrusions 41 and the edge of the second clamping piece 4 in the Y direction can be selected according to actual conditions, the number of the second through holes 43 in the fourth protrusion 42 can be selected according to actual conditions, and the distance between the second through holes 43 in the fourth protrusion 42 and the edge of the second clamping piece 4 in the Y direction can be selected according to actual conditions. In the embodiment, three second through holes 43 are arranged in each third protrusion 41 along the Y direction, and three second through holes 43 are arranged on the side wall of the fourth protrusion 42 close to the third protrusions 41.

[0073] Specifically, in the X direction, the distance between two adjacent second through holes 43 in the third boss 41 is the same, and the cross-sectional shape of the second through hole 43 is a rounded rectangular shape; the distance between two adjacent second through holes 43 in the fourth boss 42 is the same, and the cross-sectional shape of the second through hole 43 is a rounded rectangular shape; in the case of ensuring the performance of the power module, the number of second through holes 43 in two adjacent third bosses 41 can be the same or different; the distance between two adjacent second through holes 43 in the third boss 41 can also be different; the distance between two adjacent second through holes 43 in the fourth boss 42 can also be different; the cross-sectional shape of the second through hole 43 in the third boss 41 can also not be a rounded rectangular shape; and the cross-sectional shape of the second through hole 43 in the fourth boss 42 can also not be a rounded rectangular shape. In the embodiment, the second through hole 43 in each third boss 41 corresponds to one in the X direction, and the second through hole 43 in the third boss 41 also corresponds to one in the X direction.

[0074] Specifically, the second clamping piece 4 is also provided with a second opening penetrating the second clamping piece at both ends in the X direction, so that the two ends of the second clamping piece 4 in the X direction are divided into multiple sections in the Y direction, thereby reducing the thermal mechanical stress between the second clamping piece 4 and the chip layer 2. In the embodiment, two second openings are respectively arranged at both ends of the second clamping piece 4 in the X direction.

[0075] Specifically, in the case of ensuring the performance of the power module, the size and depth of the second opening can be selected according to actual conditions. Here, the depth refers to the size of the second opening in the X direction.

[0076] As an example, the mesa of the fourth boss 42 is provided with a plurality of fourth through holes 44 arranged in an array and penetrating the second clamping piece 4.

[0077] Specifically, the fourth through hole 44 is arranged on the mesa of the fourth boss 42, so that the packaging layer 7 and the second clamping piece 4 are engaged with each other, the bonding strength between the second clamping piece 4 and the packaging layer 7 is enhanced, and delamination is avoided. In the case of ensuring the performance of the power module, the number of fourth through holes 44 in the fourth boss 42 can be selected according to actual conditions; the fourth through holes 44 in the fourth boss 42 can also not be arranged in an array; and the shape and size of the fourth through hole 44 can be selected according to actual conditions. Preferably, four circular fourth through holes 44 are arranged on the mesa of the fourth boss 42, which are symmetrically distributed about the center line of the fourth boss 42 in the X direction and the Y direction.

[0078] Specifically, the lead 5 is used for interconnection between each chip and each region in the internal functional circuit of the power module, so as to lead the electrodes of the functional circuit to the second lead area 16.

[0079] Specifically, the material of the lead 5 includes copper, gold, silver, aluminum, nickel, or other suitable conductive materials.

[0080] Specifically, the shape of the lead wire 5 includes a linear shape, a strip shape, or other suitable shapes. Preferably, a linear conductive wire is used as the lead wire 5.

[0081] Specifically, the cross-sectional size, the cross-sectional shape, and the length of the lead wire 5 can be selected according to actual conditions while ensuring the performance of the power module, and the distance between two adjacent lead wires 5 can be selected according to actual conditions.

[0082] As an example, the terminal 6 includes a plurality of power terminals 61 and a plurality of signal terminals 62. The power terminals 61 include a direct current positive terminal 611 electrically connected to the first region, a direct current negative terminal 612 electrically connected to the first lead wire region 15, and an alternating current output terminal 613 electrically connected to the second region 14.

[0083] Specifically, the direct current positive terminal 611 and the direct current negative terminal 612 are respectively used to be electrically connected to the positive and negative poles of an external circuit to provide a voltage for the operation of the power module, and the alternating current output terminal 613 is used to convert the switching state of the first chip 21 into an alternating current output.

[0084] Specifically, the size, the shape, and the length of the portion protruding from the packaging layer 7 of the direct current positive terminal 611 can be selected according to actual conditions while ensuring the performance of the power module, the size, the shape, and the length of the portion protruding from the packaging layer 7 of the direct current negative terminal 612 can be selected according to actual conditions, and the size, the shape, and the length of the portion protruding from the packaging layer 7 of the alternating current output terminal 613 can be selected according to actual conditions.

[0085] Specifically, the material of the direct current positive terminal 611 includes copper, gold, silver, aluminum, nickel, titanium, platinum, or other suitable conductive materials, the material of the direct current negative terminal 612 includes copper, gold, silver, aluminum, nickel, titanium, platinum, or other suitable conductive materials, and the material of the alternating current terminal 613 includes copper, gold, silver, aluminum, nickel, titanium, platinum, or other suitable conductive materials.

[0086] Specifically, the direct current positive terminal 611 and the direct current negative terminal 612 are led out from the same side wall of the packaging layer 7, the alternating current output terminal 613 is led out from the opposite side wall of the side wall from which the direct current positive terminal 611 and the direct current negative terminal 612 are led out, and the portions of the direct current positive terminal 611 and the direct current negative terminal 612 protruding from the side wall of the packaging layer 7 are symmetrically distributed about the center line of the side wall of the packaging layer 7.

[0087] Specifically, the direct current positive terminal 611 and the direct current negative terminal 612 are led out from the same side wall of the packaging layer 7, and the distance between the direct current positive terminal 611 and the direct current negative terminal 612 can be selected according to actual conditions.

[0088] Specifically, the DC positive terminal 611 and the DC negative terminal 612 can be led out from different side walls of the packaging layer 7 according to actual needs, or the portions of the DC positive terminal 611 and the DC negative terminal 612 protruding from the side walls of the packaging layer 7 are not symmetrically distributed about the center line of the side walls of the packaging layer 7, under the condition of ensuring the performance of the power module.

[0089] As an example, the signal terminals 62 include an upper bridge signal terminal 63 and a lower bridge signal terminal 64, the upper bridge signal terminal 63 includes an upper bridge first electrode sensing terminal 631, an upper bridge current sensing terminal 632, an upper bridge second electrode sensing terminal 633, an upper bridge gate terminal 634, an upper bridge negative temperature sensing terminal 635, and an upper bridge positive temperature sensing terminal 636, and the lower bridge signal terminal 64 includes a lower bridge first electrode sensing terminal 641, a lower bridge current sensing terminal 642, a lower bridge second electrode sensing terminal 643, a lower bridge gate terminal 644, a lower bridge negative temperature sensing terminal 645, and a lower bridge positive temperature sensing terminal 646.

[0090] Specifically, the material of the signal terminals 62 includes copper, gold, silver, aluminum, nickel, titanium, platinum, or other suitable conductive materials; under the condition of ensuring the performance of the power module, the materials of the terminals of different signals can be different or the same; each signal terminal 62 can be led out from the same side wall of the packaging layer 7, or can be led out from different side walls of the packaging layer 7; among the signal terminals 62 led out from the same side wall of the packaging layer 7, the distance between adjacent two signal terminals 62 can be selected according to actual conditions, and can be the same or different.

[0091] Specifically, under the condition of ensuring the performance of the power module, the shape and size of each signal terminal 62 can be selected according to actual conditions; the length of the portion of each signal terminal 62 protruding from the packaging layer 7 can be selected according to actual conditions.

[0092] Specifically, one second lead area 16 corresponds to one signal terminal 62, and each signal terminal 62 is usually fixedly connected with its corresponding second lead area 16 by welding, and the welding process for fixedly connecting the signal terminal 62 with its corresponding second lead area 16 is a commonly used welding process, which will not be described here.

[0093] As an example, the upper bridge first electrode sensing terminal 631 is electrically connected with the first area 13, the upper bridge current sensing terminal 632, the upper bridge second electrode sensing terminal 633, the upper bridge gate terminal 634, the upper bridge negative temperature sensing terminal 635 and the upper bridge positive temperature sensing terminal 636 are respectively electrically connected with different second lead areas 16, the second lead areas 16 corresponding to the upper bridge current sensing terminal 632, the upper bridge second electrode sensing terminal 633, the upper bridge negative temperature sensing terminal 635 and the upper bridge positive temperature sensing terminal 636 are respectively electrically connected with the corresponding areas on the back of the first chip 21 above the first area 13 through the lead 5, the second lead area 16 corresponding to the upper bridge gate terminal 634 is electrically connected with the gate of the first chip 21 above the first area 13 through the lead 5, the lower bridge first electrode sensing terminal 641 is electrically connected with the second area 14, the lower bridge current sensing terminal 642, the lower bridge second electrode sensing terminal 643, the lower bridge gate terminal 644, the lower bridge negative temperature sensing terminal 645 and the lower bridge positive temperature sensing terminal 646 are respectively electrically connected with different second lead areas 16, the second lead areas 16 corresponding to the lower bridge current sensing terminal 642, the lower bridge second electrode sensing terminal 643, the lower bridge negative temperature sensing terminal 645 and the lower bridge positive temperature sensing terminal 646 are respectively electrically connected with the corresponding areas on the back of the first chip 21 above the second area 14 through the lead 5, the second lead area 16 corresponding to the lower bridge gate terminal 644 is electrically connected with the gate of the first chip 21 above the second area 14 through the lead 5.

[0094] Specifically, during the working process of the power module, the upper bridge first electrode sensing terminal 631 is used to detect the current of the first electrode of the first chip 21 in the upper bridge of the power module in real time, the upper bridge current sensing terminal 632 is used to detect the output current of the upper bridge of the power module in real time, the upper bridge second electrode sensing terminal 633 is used to detect the current of the second electrode of the first chip 21 in the upper bridge of the power module in real time, the upper bridge gate terminal 634 is used to input a control signal for controlling the gate of the first chip 21 in the upper bridge of the power module, so as to control the switch of the first chip 21 in the upper bridge, the upper bridge negative temperature sensing terminal 635 and the upper bridge positive temperature sensing terminal 636 are used to detect the working temperature of the first chip 21 in the upper bridge of the power module in real time, the lower bridge first electrode sensing terminal 641 is used to detect the current of the first electrode of the first chip 21 in the lower bridge of the power module in real time, the lower bridge current sensing terminal 642 is used to detect the output current of the lower bridge of the power module in real time, the lower bridge second electrode sensing terminal 643 is used to detect the current of the second electrode of the first chip 21 in the lower bridge of the power module in real time, the lower bridge gate terminal 644 is used to input a control signal for controlling the gate of the first chip 21 in the lower bridge, so as to control the switch of the first chip 21 in the lower bridge, and the lower bridge negative temperature sensing terminal 645 and the lower bridge positive temperature sensing terminal 646 are used to detect the working temperature of the first chip 21 in the lower bridge of the power module in real time.

[0095] Specifically, the temperature detection manner of the upper bridge negative temperature sensing terminal 635, the upper bridge positive temperature sensing terminal 636, the lower bridge negative temperature sensing terminal 645, and the lower bridge positive temperature sensing terminal 646 can be selected according to actual conditions. For example, the current of the first electrode of the first chip 21 in the upper bridge can be led to the upper bridge negative temperature sensing terminal 635 through the lead wire 5, and the temperature monitoring of the power module can be realized by externally connecting a temperature sensing diode.

[0096] For example, the upper bridge signal terminal 63, the alternating current output terminal 613, and the lower bridge signal terminal 64 are led out from the same side wall of the packaging layer 7, and the upper bridge signal terminal 63 and the lower bridge signal terminal 64 are symmetrically arranged about the alternating current output terminal 613. In this embodiment, the upper bridge first electrode sensing terminal 631, the upper bridge current sensing terminal 632, the upper bridge second electrode sensing terminal 633, the upper bridge gate terminal 634, the upper bridge negative temperature sensing terminal 635, and the upper bridge positive temperature sensing terminal 636 in the upper bridge signal terminal 63 are symmetrically arranged about the alternating current output terminal 613 with the lower bridge first electrode sensing terminal 641, the lower bridge current sensing terminal 642, the lower bridge second electrode sensing terminal 643, the lower bridge gate terminal 644, the lower bridge negative temperature sensing terminal 645, and the lower bridge positive temperature sensing terminal 646 in the lower bridge signal terminal.

[0097] Specifically, in the case of ensuring the performance of the power module, the terminals in the upper bridge signal terminal 63 and the terminals in the lower bridge signal terminal 64 can also be asymmetrically arranged.

[0098] Specifically, the packaging layer 7 is used to protect the components inside the power module, and the material of the packaging layer 7 includes epoxy resin, polyimide, polymaleimide triazine resin, polyphenyl ether, or polytetrafluoroethylene, or other suitable dielectric materials.

[0099] Specifically, the packaging layer 7 also covers the side wall of the upper substrate 3 and the substrate 1, and the side wall of the packaging layer 7 and the side wall of the substrate 1 are spaced apart by a predetermined distance to protect the components in the power module. In the case of ensuring the performance of the power module, the distance between the side wall of the packaging layer 7 and the side wall of the substrate 1 can be selected according to actual conditions.

[0100] Specifically, the lower surface of the insulating and heat conducting layer 12 is also provided with a metal heat dissipation layer, and the metal heat dissipation layer is insulated from the metal layer.

[0101] Specifically, by providing a metal heat dissipation layer on the back of the insulating and heat conducting layer 12, the heat dissipation capacity of the side of the insulating and heat conducting layer away from the metal layer can be improved, thereby improving the heat dissipation performance of the power module, and facilitating the welding of a heat dissipation structure for further improving the heat dissipation performance of the power module on the side of the substrate 1 away from the metal layer 12.

[0102] Specifically, the material of the metal heat dissipation layer includes copper, gold, silver, aluminum or other suitable conductive materials. Preferably, a copper layer with high thermal conductivity is used as the metal heat dissipation layer.

[0103] Specifically, the thickness of the metal heat dissipation layer can be selected according to actual conditions while ensuring the performance of the power module.

[0104] Specifically, by providing the first protrusion 31 and the second protrusion 32 on the first clamping piece 3, and the third protrusion 41 and the fourth protrusion 42 on the second clamping piece 4, the encapsulation layer 7 fills the gaps between the first protrusion 31, the second protrusion 32, the third protrusion 41 and the fourth protrusion 42 and the chip layer 2 and the substrate 1, reducing the thermal mechanical stress between the first clamping piece 3 and the second clamping piece 4 and the chip layer 2, avoiding false welding in the power module, and improving the reliability of the power module.

[0105] Specifically, by providing the first through hole 33 in the first protrusion 31 and the second protrusion 32, the second through hole 43 in the third protrusion 41 and the fourth protrusion 42, and the third through hole 34 in the second protrusion 32 and the fourth through hole 44 in the fourth protrusion 42, the encapsulation layer 7 fills the first through hole 33, the second through hole 43, the third through hole 34 and the fourth through hole 44, further reducing the thermal mechanical stress between the first clamping piece 3 and the second clamping piece 4 and the chip layer 2 and the substrate 1, and at the same time, the encapsulation layer 7 filling each through hole and each through hole interlock with each other, improving the bonding strength of the encapsulation layer 7 and the first clamping piece 3 and the second clamping piece 4, avoiding delamination between the encapsulation layer 7 and the first clamping piece 3 and the second clamping piece 4, improving the reliability of the power module, and the arrangement of each protrusion and each through hole has no effect on the current capacity of the power module.

[0106] Specifically, by making the first chip 21 and the second chip 22 in the first area 13 symmetrically distributed with the first chip 21 and the second chip 22 in the second area 14 respectively, and at the same time, making the first clamping piece 3 electrically connected to the first chip 21 above the first area 13 and the second area 14 symmetrically arranged with the first clamping piece 3 electrically connected to the first chip 21 above the second area 14 and the first lead area 15, and the second clamping piece 4 electrically connected to the second chip 22 above the first area 13 and the second area 14 symmetrically arranged with the second clamping piece 4 electrically connected to the second chip 22 above the second area 14 and the first lead area 15, the current uniformity of the chip layer surface is improved, the current carrying capacity of the power module is enhanced, and at the same time, due to the use of the first clamping piece 3 and the second clamping piece 4, the layout of each chip in the chip layer 2 is more flexible, the cross-sectional area of the interconnection structure between the chip layer 2 and the substrate 1 is increased, the length of the commutation loop in the power module is reduced, and the parasitic inductance inside the power module is reduced, thereby reducing the off voltage peak and switching oscillation, and improving the performance of the power module.

[0107] In summary, the power module packaging structure of the present application improves the packaging structure, and the first chip and the second chip above the first area and the second area are symmetrically distributed, which improves the current uniformity of the chip layer surface, enhances the current carrying capacity of the power module, and meanwhile, the first clamp and the second clamp are used to interconnect each area in the chip layer and the substrate, which makes the layout of each chip in the chip layer more flexible, increases the cross-sectional area of the interconnection structure between the chip layer and the substrate, reduces the length of the commutation loop in the power module, and reduces the parasitic inductance inside the power module; by arranging the first boss, the second boss, the first through hole and the third through hole in the first clamp, arranging the third boss, the fourth boss, the second through hole and the fourth through hole in the second clamp, and filling the gap between each through hole, each boss and the chip with the packaging layer, the thermal mechanical stress between the first clamp, the second clamp and the chip layer is reduced, the bonding strength between the packaging layer and the first clamp and the second clamp is improved, the delamination between the packaging layer and the first clamp and the second clamp is avoided, and the reliability of the power module is improved. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0108] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A power module package structure, characterized by, The application relates to a substrate, a chip layer, a first clamp, a second clamp, a plurality of leads, a plurality of terminals and a packaging layer. The substrate comprises an insulating and heat-conducting layer and a metal layer on the upper surface of the insulating and heat-conducting layer, wherein the metal layer comprises a first area, a second area, a first lead area and a plurality of second lead areas. The chip layer comprises a plurality of first chips and a plurality of second chips, at least one of the first chips and the second chips being welded to the first area, and at least one of the first chips and the second chips being welded to the second area. The first clamp is electrically connected to the first chip above the first area, the second area and the first chip above the second area and the first lead area respectively. The second clamp is electrically connected to the second chip above the first area, the second area and the first chip above the second area and the first lead area respectively. The plurality of leads are electrically connected to each of the second lead areas and the corresponding area of the back surface of the first chip. The plurality of terminals are electrically connected to the first area, the second area, the first lead area and each of the second lead areas respectively. The packaging layer covers the exposed surfaces of the leads, the chip layer, the first clamp and the second clamp and the upper surface of the substrate.

2. The power module package structure of claim 1, wherein: The first clamp electrically connected to the first chip above the first area is symmetrically arranged with the first clamp electrically connected to the first chip above the second area, and the second clamp electrically connected to the second chip above the first area is symmetrically arranged with the second clamp electrically connected to the second chip above the second area.

3. The power module package structure of claim 1, wherein: The first chip above the first area and the second chip above the first area are symmetrically distributed with the first chip above the second area and the second chip above the second area.

4. The power module package structure of claim 1, wherein: The plurality of first protrusions are arranged in the first clamp in the region directly above the first chip in the X direction, the first chip is electrically connected to the first clamp region on both sides of the first protrusion in the X direction, the second protrusion is arranged in the first clamp between the first chip and the first clamp region electrically connected to the second area and the first lead area, and the first protrusion and the second protrusion are further provided with a plurality of first through holes arranged in the Y direction and penetrating through the first clamp, the first through holes in the first protrusion divide the first protrusion into multiple segments in the Y direction, and the first through holes in the second protrusion divide the side wall of the second protrusion close to the first protrusion into multiple segments.

5. The power module package structure of claim 4, wherein: The first through holes in each of the first protrusions correspond to each other in the X direction, and the first through holes in the first protrusion and the second protrusion also correspond to each other in the X direction.

6. The power module package structure of claim 1, wherein: The third protrusions are arranged in the second clamping piece in the region directly above the second chip in the X direction, the second chip is electrically connected to the regions of the second clamping piece on both sides of the third protrusions in the X direction, the fourth protrusions are arranged in the second clamping piece between the regions of the second clamping piece electrically connected to the first lead region and the second region and the second chip, and the third protrusions and the fourth protrusions are further provided with second through holes arranged in the Y direction and penetrating the second clamping piece, the second through holes in the third protrusions divide the third protrusions into multiple segments in the Y direction, and the second through holes in the fourth protrusions divide the side walls of the fourth protrusions close to the third protrusions into multiple segments.

7. The power module package structure of claim 6, wherein: The second through holes in each of the third protrusions correspond to each other in the X direction, and the second through holes in the third protrusions and the fourth protrusions also correspond to each other in the X direction.

8. The power module package structure of claim 1, wherein: The mesa of the second protrusion is provided with third through holes arranged in an array and penetrating the first clamping piece, and the mesa of the fourth protrusion is provided with fourth through holes arranged in an array and penetrating the second clamping piece.

9. The power module package structure of claim 1, wherein: The terminal includes a plurality of power terminals and a plurality of signal terminals, the power terminals include a direct current positive electrode terminal electrically connected to the first region, a direct current negative electrode terminal electrically connected to the first lead region, and an alternating current output terminal electrically connected to the second region.

10. The power module package structure of claim 9, wherein: The signal terminals include upper bridge signal terminals and lower bridge signal terminals, the upper bridge signal terminals include an upper bridge first electrode sensing terminal, an upper bridge current sensing terminal, an upper bridge second electrode sensing terminal, an upper bridge gate terminal, an upper bridge negative temperature sensing terminal, and an upper bridge positive temperature sensing terminal, and the lower bridge signal terminals include a lower bridge first electrode sensing terminal, a lower bridge current sensing terminal, a lower bridge second electrode sensing terminal, a lower bridge gate terminal, a lower bridge negative temperature sensing terminal, and a lower bridge positive temperature sensing terminal.

11. The power module package structure of claim 10, wherein: The upper bridge first electrode sensing terminal is electrically connected with the first area, the upper bridge current sensing terminal, the upper bridge second electrode sensing terminal, the upper bridge gate terminal, the upper bridge negative temperature sensing terminal and the upper bridge positive temperature sensing terminal are respectively electrically connected with different second lead areas, the second lead areas corresponding to the upper bridge current sensing terminal, the upper bridge second electrode sensing terminal, the upper bridge negative temperature sensing terminal and the upper bridge positive temperature sensing terminal are respectively electrically connected with the corresponding areas of the first chip back surface above the first area through the lead, and the second lead area corresponding to the upper bridge gate terminal is electrically connected with the gate of the first chip above the first area through the lead.

12. The power module package structure of claim 10, wherein: The upper bridge signal terminal, the alternating current output terminal and the lower bridge signal terminal are led out from the same side wall of the packaging layer, and the upper bridge signal terminal and the lower bridge signal terminal are symmetrically arranged about the alternating current output terminal.

13. The power module package structure of claim 9, wherein: The direct current positive terminal and the direct current negative terminal are led out from the same side wall of the packaging layer, the alternating current output terminal is led out from the opposite side wall of the side wall of the packaging layer from which the direct current positive terminal and the direct current negative terminal are led out, and the part of the direct current positive terminal and the direct current negative terminal protruding from the side wall of the packaging layer is symmetrically distributed about the center line of the side wall of the packaging layer.

14. The power module package structure of claim 1, wherein: The side wall of the first boss and the second boss is inclined.

15. The power module package structure of claim 1, wherein: The first clamping piece is provided with a first opening penetrating the first clamping piece at both ends in the X direction, and the second clamping piece is provided with a second opening penetrating the second clamping piece at both ends in the X direction.

16. The power module package structure of claim 1, wherein: The metal heat dissipation layer covers the lower surface of the insulating and heat conducting layer, and the metal heat dissipation layer is insulated from the metal layer.

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