On-chip calibration source circuit for radio-frequency direct-sampling receiving chain, and chip

Abstract

Provided in the present application are an on-chip calibration source circuit for a radio-frequency direct-sampling receiving chain, and a chip. The on-chip calibration source circuit comprises a clock signal output circuit and a differential current signal output circuit, wherein an output end of the clock signal output circuit is connected to an input end of the differential current signal output circuit, and an output end of the differential current signal output circuit is movably connected to an input end of a digital variable gain amplifier; the clock signal output circuit is used for outputting a clock signal to the differential current signal output circuit; the differential current signal output circuit is used for generating a first calibration signal on the basis of an inputted clock signal, and outputting the first calibration signal to the digital variable gain amplifier, the first calibration signal being a differential current signal and used for performing error calibration on the digital variable gain amplifier; and the digital variable gain amplifier is used for outputting, on the basis of the first calibration signal, a second calibration signal to a time-interleaved analog-to-digital converter, the second calibration signal being used for performing error calibration on the time-interleaved analog-to-digital converter.

Description

On-chip calibration source circuit and chip for radio frequency direct sampling receive link

[0001] Cross-reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202411392390.1, filed September 30, 2024, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present application relates to the field of communication technology, in particular to an on-chip calibration source circuit and chip for a radio frequency direct sampling receive link. BACKGROUND

[0004] In recent years, with the rapid development of 5G communication, low-cost and high-performance radio frequency receive link has become a new research hotspot and has wide application prospects. Among them, the radio frequency direct sampling receive (Rx) link has gradually become the mainstream direction. Compared with the traditional frequency conversion reception scheme, the radio frequency receive link saves the mixing and many passive matching circuits, and has obvious advantages in cost and size, and has strong competitiveness.

[0005] A high-speed radio frequency direct sampling receive link is usually composed of a variable gain amplifier (DVGA) and a time-interleaved analog-to-digital converter (TI-ADC) in cascade. The DVGA receives a radio frequency signal and performs amplification, attenuation, filtering, etc. The TI-ADC samples and quantizes the analog signal output by the DVGA and converts it into a digital signal. The DVGA usually has a phase shift error, and the TI-ADC usually has a sub-channel gain (TI gain) mismatch, a sub-channel sampling time (TI skew) mismatch, and a sub-channel offset (TI offset) mismatch, etc. These errors affect the normal operation and performance of the radio frequency direct sampling receive link, so error calibration is needed.

[0006] In the related art, the commonly used calibration methods include off-chip calibration method and on-chip calibration method. The off-chip calibration method refers to injecting a required calibration signal (generally square wave or sine signal) from the outside to the radio frequency direct sampling receiving link, but the off-chip calibration method is poor in integration and inconvenient to operate, and needs complex test instruments and precise manual intervention. The on-chip calibration method generally needs to calibrate the TI-ADC and the DVGA through different paths respectively, and the calibration source generally uses voltage signal transmission, and the signal will be distorted in the transmission process, so an additional AC (Alternating Current) coupling capacitor is needed to avoid affecting the common mode operating point of the DVGA when calibrating the DVGA. SUMMARY

[0007] The present application provides a chip and an on-chip calibration source circuit for a radio frequency direct sampling receiving link.

[0008] The present application provides an on-chip calibration source circuit for a radio frequency direct sampling receiving link, the radio frequency direct sampling receiving link comprising a variable gain amplifier and a time-interleaved analog-to-digital converter, the on-chip calibration source circuit comprising: a clock signal output circuit and a differential current signal output circuit, an output end of the clock signal output circuit being connected to an input end of the differential current signal output circuit, an output end of the differential current signal output circuit being movably connected to an input end of the variable gain amplifier, and an output end of the variable gain amplifier being connected to an input end of the time-interleaved analog-to-digital converter; the clock signal output circuit is configured to output a clock signal to the differential current signal output circuit; the differential current signal output circuit is configured to generate a first calibration signal according to the input clock signal and output the first calibration signal to the variable gain amplifier, the first calibration signal being a differential current signal; the first calibration signal is used for error calibration of the variable gain amplifier; the variable gain amplifier is used for outputting a second calibration signal to the time-interleaved analog-to-digital converter according to the first calibration signal, the second calibration signal being a voltage signal; and the second calibration signal is used for error calibration of the time-interleaved analog-to-digital converter.

[0009] The present application provides a chip comprising a radio frequency direct sampling receiving link and an on-chip calibration source circuit, the radio frequency direct sampling receiving link comprising a variable gain amplifier and a time-interleaved analog-to-digital converter, and the on-chip calibration source circuit comprising the on-chip calibration source circuit described above.

[0010] The above embodiments and other aspects of the present application and implementation manners thereof are described in more detail in the description of drawings, specific embodiments and claims. BRIEF DESCRIPTION OF DRAWINGS

[0011] In the drawings of the embodiments of the present application:

[0012] Fig. 1 shows a working principle diagram of a time-interleaved analog-to-digital converter according to an embodiment of the present application.

[0013] Fig. 2 shows a block diagram of an on-chip calibration source circuit for a radio frequency direct-sampling receive chain according to an embodiment of the present application.

[0014] Fig. 3 shows a block diagram of a differential current driving circuit according to an embodiment of the present application.

[0015] Fig. 4 shows a circuit structure diagram of a differential current driving circuit according to an embodiment of the present application.

[0016] Fig. 5 shows a circuit structure diagram of a differential current signal output circuit according to an embodiment of the present application.

[0017] Fig. 6 shows a timing diagram of n groups of clock signals corresponding to n groups of differential current driving circuits according to an embodiment of the present application.

[0018] Fig. 7 shows a waveform diagram of signals output by n groups of differential current driving circuits being restored into voltage signals according to an embodiment of the present application.

[0019] Fig. 8 shows a block diagram of another on-chip calibration source circuit according to an embodiment of the present application.

[0020] Fig. 9 shows a block diagram of still another on-chip calibration source circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below with reference to the drawings.

[0022] The embodiments shown will be described in more detail in the following with reference to the drawings, but the embodiments shown can be embodied in various forms and the present disclosure should not be construed as being limited to the embodiments set forth below. Rather, the purpose of providing these embodiments is to make the present disclosure more thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0023] The accompanying drawings for the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification, which together with the detailed embodiments serve to explain the present disclosure, and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art from the detailed embodiments described below by reference to the drawings.

[0024] The present disclosure can be described with reference to plan views and / or sectional views by means of ideal schematic drawings of the present disclosure. Therefore, the example illustrations can be modified according to manufacturing techniques and / or tolerances.

[0025] In the case of no conflict, each embodiment of the present disclosure and each feature in the embodiments can be combined with each other.

[0026] The terminology used by the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used in the present disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in the present disclosure, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "includes" and / or "consisting of" when used in the present disclosure specifies the presence of stated features, integers, steps, operations, elements, and / or components but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] Unless otherwise defined, all terms used in the present disclosure, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly idealized or overly formal sense unless expressly so defined in the present disclosure.

[0028] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configuration formed based on a manufacturing process. Therefore, the regions exemplified in the drawings have a schematic property, and the shape of the regions shown in the drawings exemplifies a specific shape of the region of the element, but is not intended to be restrictive.

[0029] In the related art, a high-speed radio frequency direct sampling receiving link is usually composed of a variable gain amplifier (DVGA) and a time-interleaved analog-to-digital converter (TI-ADC) in cascade. The DVGA receives a radio frequency signal and performs processing such as amplification, attenuation, filtering, etc., and the TI-ADC samples and quantizes the analog signal output by the DVGA to convert it into a digital signal.

[0030] The analog-to-digital converter (ADC) of the high-speed radio frequency direct sampling receiving link usually adopts a TI-ADC to improve the working frequency. FIG. 1 shows a working principle diagram of a time-interleaved analog-to-digital converter according to an embodiment of the present application. As shown in FIG. 1, the TI-ADC uses M sub-ADCs with a sampling rate of Fs / M to alternately and in parallel sample with a fixed deviation phase of 360° / M, so that the total sampling rate can reach M times (M>1) of the sampling rate of the sub-ADC. Each analog-to-digital converter sequentially samples and quantizes the input signal and then outputs the signal through a multiplexer (MUX). However, due to the limitations of circuit design and the deviation of manufacturing process, there will be mismatches and non-identical performances among the M sub-ADCs, and the mismatches and non-identical performances will be more significant at high frequencies. Therefore, the TI-ADC usually has errors such as sub-channel gain mismatch, sub-channel sampling time mismatch, and sub-channel offset mismatch, which seriously affect the performance. The radio frequency broadband variable gain amplifier (DVGA) is generally composed of an adjustable attenuator (ATT) and a low noise amplifier (LNA). However, different phase shifts will be generated during each gain adjustment, and there will be phase shift errors. The existence of the above errors will affect the normal operation and performance of the radio frequency direct sampling receiving (Rx) link, so error calibration is needed.

[0031] In the related art, the commonly used calibration methods include an off-chip calibration method and an on-chip calibration method. The off-chip calibration method refers to injecting a required calibration signal (generally a square wave or a sine signal) from the outside to the radio frequency direct sampling receiving link. However, the off-chip calibration method has poor integration and is inconvenient to operate, and requires complex test instruments and precise manual intervention. The on-chip calibration method usually needs to calibrate the TI-ADC and the DVGA through different paths respectively, and the calibration source usually uses voltage signal transmission. However, distortion will occur in the signal during transmission, so an additional AC (Alternating Current) coupling capacitor is needed to avoid affecting the common-mode operating point of the DVGA when calibrating the DVGA.

[0032] Therefore, the present application provides an on-chip calibration source circuit and a chip for a radio frequency direct sampling receiving link, which aims to solve the above technical problems in the related art.

[0033] Figure 2 shows a block diagram of a calibration source circuit on chip for a radio frequency direct sampling receive chain according to an embodiment of the present application. As shown in Figure 2, the calibration source circuit on chip for error calibration of a radio frequency direct sampling receive chain according to an embodiment of the present application includes a clock signal output circuit 11 and a differential current signal output circuit 12, the output of the clock signal output circuit 11 is connected to the input of the differential current signal output circuit 12, the output of the differential current signal output circuit 12 is movably connected to the input of a variable gain amplifier 13, and the output of the variable gain amplifier 13 is connected to the input of a time-interleaved analog-to-digital converter 14.

[0034] The clock signal output circuit 11 is configured to output a clock signal to the differential current signal output circuit 12, the differential current signal output circuit 12 is configured to generate a first calibration signal according to the input clock signal and output the first calibration signal to the variable gain amplifier 13, the first calibration signal is a differential current signal, and the first calibration signal is used for error calibration of the variable gain amplifier 13. The variable gain amplifier 13 is configured to output a second calibration signal to the time-interleaved analog-to-digital converter 14 according to the first calibration signal, the second calibration signal is a voltage signal, and the second calibration signal is used for error calibration of the time-interleaved analog-to-digital converter 14.

[0035] In some embodiments, the output of the variable gain amplifier 13 is connected to the input of the time-interleaved analog-to-digital converter 14 through an input buffer 15 in the radio frequency direct sampling receive chain.

[0036] The calibration source circuit on chip according to an embodiment of the present application uses the differential current signal output circuit to generate a first calibration signal for calibration of the radio frequency direct sampling receive chain under the action of the clock signal output by the clock signal output circuit, the first calibration signal is a differential current signal, differential current signal transmission is adopted, the requirement for the signal transmission path is reduced, the quality of the signal transmission process can be effectively ensured, a high-quality calibration signal without distortion is obtained, no coupling capacitor needs to be arranged on the transmission path, the equivalent parasitic capacitance on the transmission path is small, and the influence on the radio frequency direct sampling receive chain is small. Since the variable gain amplifier is a resistive load and the time-interleaved analog-to-digital converter is a capacitive load, the two load characteristics are used to directly inject the first calibration signal at the input of the variable gain amplifier for error calibration of the variable gain amplifier, and then the first calibration signal is restored to a voltage signal by the variable gain amplifier and is input to the time-interleaved analog-to-digital converter for error calibration. That is, the first calibration signal output by the calibration source circuit on chip is directly injected at the input of the radio frequency direct sampling receive chain, and the error calibration of the variable gain amplifier and the time-interleaved analog-to-digital converter can be completed at one time without the need for additional other paths to calibrate the time-interleaved analog-to-digital converter.

[0037] In some embodiments, the clock signal output by the clock signal output circuit 11 is a differential clock signal, the clock signal includes a first clock signal and a second clock signal, the first clock signal and the second clock signal are mutually inverse square wave signals; the first calibration signal includes a first differential current signal and a second differential current signal.

[0038] In some embodiments, the differential current signal output circuit 12 includes at least one set of differential current driving circuits, and in some embodiments, the differential current driving circuit is a low-voltage differential signaling (LVDS) generating circuit.

[0039] FIG. 3 shows a composition block diagram of a differential current driving circuit provided by an embodiment of the present application, as shown in FIG. 3, each set of differential current driving circuit includes a first output circuit 121 and a second output circuit 122, the first output circuit 121 has a first output end, and the second output circuit 122 has a second output end. The first output circuit is configured to generate a first differential current signal according to the first clock signal and the second clock signal and output to the first output end, and the second output circuit is configured to generate a second differential current signal according to the first clock signal and the second clock signal and output to the second output end.

[0040] FIG. 4 shows a circuit structure schematic diagram of a differential current driving circuit provided by an embodiment of the present application, and in some embodiments, as shown in FIG. 4, the first output circuit 121 includes a first transistor T1 and a second transistor T2.

[0041] The control electrode of the first transistor T1 is connected to the output end of the clock signal output circuit 11 outputting the first clock signal clk_n; the first electrode of the first transistor T1 is connected to the first power supply end; and the second electrode of the first transistor T1 is connected to the first output end Voutn of the differential current signal output circuit. The control electrode of the second transistor T2 is connected to the output end of the clock signal output circuit 11 outputting the second clock signal clk_p; the first electrode of the second transistor T2 is connected to the second power supply end; and the second electrode of the second transistor T2 is connected to the first output end Voutn of the differential current signal output circuit.

[0042] In some embodiments, as shown in FIG. 4, the second output circuit 122 includes a third transistor T3 and a fourth transistor T4.

[0043] The control electrode of the third transistor T3 is connected to the output end of the clock signal output circuit 11 outputting the second clock signal clk_p; the first electrode of the third transistor T3 is connected to the first power supply end; and the second electrode of the third transistor T3 is connected to the second output end Voutp of the differential current signal output circuit. The control electrode of the fourth transistor T4 is connected to the output end of the clock signal output circuit 11 outputting the first clock signal clk_n; the first electrode of the fourth transistor T4 is connected to the second power supply end; and the second electrode of the fourth transistor T4 is connected to the second output end Voutp of the differential current signal output circuit.

[0044] In some embodiments, the first power supply end and the second power supply end are both current supply ends, and are used to generate current signals.

[0045] In some embodiments, the amplitude of the first calibration signal output by the on-chip calibration source circuit can be adjusted by adjusting the currents output by the first power supply end and the second power supply end of the differential current driving circuit, so as to meet the calibration requirement.

[0046] In some embodiments, as shown in FIG. 4, each set of differential current driving circuit further includes a common-mode feedback circuit 123; the common-mode feedback circuit includes an operational amplifier A, the output end of the operational amplifier A is connected to the first power supply end, the first input end Vref is a reference voltage end, the second input end Vcom is connected to the first output end Voutn and the second output end Voutp of the differential current signal output circuit through resistors, specifically, the second input end Vcom is connected to the first output end Voutn of the differential current signal output circuit through one resistor, and the second input end Vcom is connected to the second output end Voutp of the differential current signal output circuit through another resistor. Through the setting of the common-mode feedback circuit, a stable common-mode voltage can be provided for the output of the differential current signal output circuit.

[0047] In some embodiments, the differential current signal output circuit 12 includes multiple sets of differential current driving circuits, and the output end of the clock signal output circuit 11 is connected to one set of differential current driving circuits of the differential current signal output circuit 12 at each time of error calibration; the multiple sets of differential current driving circuits correspond to different frequencies of input clock signals, and the multiple sets of differential current driving circuits correspond to different sizes of output current signals. According to the calibration requirement, different differential current driving circuits can be selected to provide calibration signals, so as to output calibration signals with different amplitudes for calibration.

[0048] FIG. 5 shows a circuit structure schematic diagram of a differential current signal output circuit provided by an embodiment of the present application. In some embodiments, as shown in FIG. 5, the differential current signal output circuit 12 includes n (n is greater than or equal to 2) sets of differential current driving circuits, corresponding to n current supply ends, and the sizes of the currents output by the n current supply ends are I, 2I, 4I,..., 2n-1I, respectively.n I, each group of differential current driving circuit corresponds to a group of input clock signals, each group of clock signals includes clock signal clk_n and clock signal clk_p, clock signal clk_n and clock signal clk_p are differential clock signals, and are mutually inverse square wave signals. Wherein, the circuit structure of each group of differential current driving circuit can refer to the circuit structure of the differential current driving circuit shown in the above-mentioned figure 4.

[0049] The frequencies of the n groups of clock signals input corresponding to the n groups of differential current driving circuits are different, and the n groups of clock signals are denoted as clk1, clk2,..., clkn. Figure 6 shows the timing diagram of the n groups of clock signals corresponding to the n groups of differential current driving circuits in the embodiment of the present application. As shown in figure 6, the frequency of clk2 is 1 / 2 of clk1, the frequency of clk3 is 1 / 4 of clk1, and so on. The frequency of clkn is 1 / 2 of clk1. n-1 clk1 is the clock signal output by the clock signal output circuit, and clk2-clkn can be obtained by continuously dividing clk1 by 2 using a D flip-flop.

[0050] For the convenience of description, the transistors in each group of differential current driving circuits in figure 5 are replaced by switches for description. Clock signal clk_n and clock signal clk_p are used to control the on or off of the switches. It can be understood that when the switch corresponding to the control of clock signal clk_n is on, the switch corresponding to the control of clk_p is off. When the switch corresponding to the control of clock signal clk_n is off, the switch corresponding to the control of clk_p is on.

[0051] In some embodiments, the waveform of the voltage signal recovered after the differential current signal output by a group of differential current driving circuits passes through a variable gain amplifier is a square wave waveform, and the waveform of the voltage signal recovered after the signal output by n groups of differential current driving circuits passes through a variable gain amplifier is a stepped waveform, and the number of steps is n. Figure 7 shows the waveform diagram of the voltage signal recovered from the signal output by n groups of differential current driving circuits in the embodiment of the present application. As shown in figure 7, the waveform of the voltage signal recovered after the signal output by n groups of differential current driving circuits passes through a variable gain amplifier is a stepped waveform, and the number of steps is n. If n is large enough, the stepped waveform will tend to be a sinusoidal waveform.

[0052] In some embodiments, n groups of differential current driving circuits are used to form a differential current signal output circuit, and each group of differential current driving circuit corresponds to an output signal with different amplitude. A group of differential current driving circuit outputting the required calibration signal can be selected in turn to perform error calibration on the radio frequency direct sampling receiving link, so as to effectively provide the accuracy of calibration.

[0053] In the present application, "movable connection" means that the connection between the two can be disconnected when needed (for example, but not limited to, through impedance adjustment circuit 16 or a switch as described below).

[0054] Figure 8 shows a block diagram of another on-chip calibration source circuit provided by embodiments of the present application. In some embodiments, as shown in Figure 8, an impedance adjustment circuit 16 is further connected between the differential current signal output circuit 12 and the variable gain amplifier 13, and the impedance adjustment circuit 16 is used to adjust the impedance between the output end of the differential current signal output circuit 12 and the input end of the variable gain amplifier 13. The differential current signal output circuit 12 has two output ends, which are a first output end and a second output end, and the variable gain amplifier 13 has two input ends; the impedance adjustment circuit 16 includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to one output end of the differential current signal output circuit 12, and the other end of the first resistor R1 is movably connected to one input end of the variable gain amplifier 13; one end of the second resistor R2 is connected to the other output end of the differential current signal output circuit 12, and the other end of the second resistor R2 is movably connected to the other input end of the variable gain amplifier 13.

[0055] In some embodiments, as shown in Figure 8, the impedance adjustment circuit 16 further includes a third resistor R3, and the third resistor R3 is connected between the two output ends of the differential current signal output circuit 12; one end of the third resistor R3 is connected to one output end of the differential current signal output circuit 12, and the other end of the third resistor R3 is movably connected to the other output end of the differential current signal output circuit 12.

[0056] In some embodiments, "movable connection" includes connection through a switching element (switch). For example, as shown in Figure 8, the other end of the first resistor R1 is connected to one input end of the variable gain amplifier 13 through a switch S1, specifically, the other end of the first resistor R1 is connected to one end of the switch S1, and the other end of the switch S1 is connected to one input end of the variable gain amplifier 13. The other end of the second resistor R2 is connected to the other input end of the variable gain amplifier 13 through a switch S2, specifically, the other end of the second resistor R2 is connected to one end of the switch S2, and the other end of the switch S2 is connected to the other input end of the variable gain amplifier 13. The other end of the third resistor R3 is connected to the other output end of the differential current signal output circuit 12 through a switch S0, specifically, the other end of the third resistor R3 is connected to one end of the switch S0, and the other end of the switch S0 is connected to the other output end of the differential current signal output circuit 12.

[0057] In some embodiments, the first resistor R1, the second resistor R2, and the third resistor R3 can be fixed resistors or adjustable resistors.

[0058] In some embodiments, during calibration, the switches S1 and S2 are closed, so that the output end of the differential current signal output circuit 12 is in communication with the input end of the variable gain amplifier 13, while the switch S0 is open. During impedance adjustment, the switch S0 can be closed. After calibration is completed, the switches S1 and S2 are open, and the input end of the radio frequency direct sampling receiving chain, i.e. the input end of the variable gain amplifier 13, can normally input a radio frequency signal for normal operation.

[0059] In some embodiments, the signal source inputted to the input end of the variable gain amplifier 13 is different when the on-chip calibration source circuit is on and off, and the impedance is also different. When the on-chip calibration source circuit is working, the signal is generated by the on-chip calibration source circuit, and when the on-chip calibration source circuit is not working, the signal is an external radio frequency signal. Therefore, it is necessary to ensure good consistency of the phase in the two cases, so as to facilitate the subsequent phase calibration. During calibration, the impedance at the input end of the variable gain amplifier 13 can be adjusted through the impedance adjustment circuit 16, so as to improve the phase error calibration effect of the variable gain amplifier and the phase consistency when the calibration source is on and off.

[0060] In some embodiments, the clock signal output circuit 11 comprises a digital phase locked loop (DPLL) circuit.

[0061] FIG. 9 shows a block diagram of another on-chip calibration source circuit according to an embodiment of the present application. In some embodiments, as shown in FIG. 9, in order to enhance the driving capability and quality of the clock signal, a buffer circuit 17 and a duty corrector (DCC) circuit 18 are further connected between the clock signal output circuit 11 and the differential current signal output circuit 12; the buffer circuit 17 is configured to receive and store the clock signal outputted by the clock signal output circuit 11; the duty corrector circuit 18 is configured to receive the clock signal from the buffer circuit 17, adjust the duty cycle of the clock signal, and output the adjusted clock signal to the differential current signal output circuit 12.

[0062] In some embodiments, in order to strengthen the quality of the clock signal and ensure the stability of the clock signal, as shown in FIG. 9, a latch circuit 19 is further connected between the duty corrector circuit 18 and the differential current signal output circuit 11; the latch circuit 19 is configured to receive and buffer the adjusted clock signal from the duty corrector circuit 18, and output the adjusted clock signal to the differential current signal output circuit 12.

[0063] In some embodiments, the on-chip calibration source circuit further comprises a power supply module (not shown in the figure), which is configured to provide required operating voltage for all circuit modules and required current for the differential current signal output circuit 11, and the size of the current can be adjusted by changing the register configuration.

[0064] In some embodiments, the power supply module can include, but is not limited to, a low-dropout regulator (LDO), a current mirror, etc.

[0065] The embodiments of the present application also provide a chip, which comprises a radio frequency direct sampling receiving link and an on-chip calibration source circuit, the radio frequency direct sampling receiving link comprises a variable gain amplifier and a time-interleaved analog-to-digital converter, and the on-chip calibration source circuit comprises the on-chip calibration source circuit provided in the above embodiments.

[0066] The embodiments of the present application also provide a communication device comprising the chip described above.

[0067] In the above embodiments, the related description of the on-chip calibration source circuit can be referred to the specific description of the on-chip calibration source circuit in the above embodiments, and will not be repeated here.

[0068] The detailed description of the exemplary embodiments of the present application has been provided above by way of exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art without departing from the scope of the present application in view of the drawings and claims. Therefore, the proper scope of the present application will be determined according to the claims.

Claims

1. An on-chip calibration source circuit for a radio frequency direct-sampling receive chain, the radio frequency direct-sampling receive chain comprising a variable gain amplifier and a time-interleaved analog-to-digital converter, the on-chip calibration source circuit comprising: a clock signal output circuit and a differential current signal output circuit, an output end of the clock signal output circuit is connected to an input end of the differential current signal output circuit, and an output end of the differential current signal output circuit is movably connected to an input end of the variable gain amplifier, and an output end of the variable gain amplifier is connected to an input end of the time-interleaved analog-to-digital converter; the clock signal output circuit is configured to output a clock signal to the differential current signal output circuit; the differential current signal output circuit is configured to generate a first calibration signal according to the input clock signal and output the first calibration signal to the variable gain amplifier, and the first calibration signal is a differential current signal; the first calibration signal is used for error calibration of the variable gain amplifier; the variable gain amplifier is configured to output a second calibration signal to the time-interleaved analog-to-digital converter according to the first calibration signal, and the second calibration signal is a voltage signal; the second calibration signal is used for error calibration of the time-interleaved analog-to-digital converter.

2. The on-chip calibration source circuit of claim 1, wherein, the clock signal is a differential clock signal, and the clock signal includes a first clock signal and a second clock signal; and the first calibration signal includes a first differential current signal and a second differential current signal; the differential current signal output circuit includes at least one set of differential current driving circuits, and each set of the differential current driving circuits includes a first output circuit and a second output circuit; the first output circuit is configured to generate the first differential current signal according to the first clock signal and the second clock signal, and the second output circuit is configured to generate the second differential current signal according to the second clock signal and the first clock signal.

3. The on-chip calibration source circuit of claim 2, wherein, the first output circuit includes a first transistor and a second transistor; a control electrode of the first transistor is connected to an output end of the clock signal output circuit outputting the first clock signal; a first electrode of the first transistor is connected to a first power supply end; and a second electrode of the first transistor is connected to a first output end of the differential current signal output circuit; a control electrode of the second transistor is connected to an output end of the clock signal output circuit outputting the second clock signal; a first electrode of the second transistor is connected to a second power supply end; and a second electrode of the second transistor is connected to the first output end of the differential current signal output circuit.

4. The on-chip calibration source circuit of claim 2, wherein, the second output circuit includes a third transistor and a fourth transistor; a control electrode of the third transistor is connected to the output end of the clock signal output circuit outputting the second clock signal; a first electrode of the third transistor is connected to the first power supply end; and a second electrode of the third transistor is connected to a second output end of the differential current signal output circuit; a control electrode of the fourth transistor is connected to the output end of the clock signal output circuit outputting the first clock signal; a first electrode of the fourth transistor is connected to the second power supply end; and a second electrode of the fourth transistor is connected to the second output end of the differential current signal output circuit.

5. The on-chip calibration source circuit of claim 3 or 4, wherein, each set of the differential current driving circuits further includes a common-mode feedback circuit; The common mode feedback circuit comprises an operational amplifier, an output end of the operational amplifier is connected with a first power supply end, a first input end is a reference voltage end, and a second input end is connected with a first output end and a second input end of the differential current signal output circuit through a resistor.

6. The on-chip calibration source circuit of claim 2, wherein, The differential current signal output circuit comprises a plurality of groups of differential current driving circuits, and an output end of the clock signal output circuit is connected with one group of differential current driving circuits of the differential current signal output circuit at each time of error calibration. The plurality of groups of differential current driving circuits correspond to different frequencies of input clock signals, and the plurality of groups of differential current driving circuits correspond to different sizes of output current signals.

7. The on-chip calibration source circuit of claim 1, wherein, The differential current signal output circuit and the variable gain amplifier are further connected with an impedance adjusting circuit. The differential current signal output circuit has two output ends, and the variable gain amplifier has two input ends. The impedance adjusting circuit comprises a first resistor and a second resistor, one end of the first resistor is connected with one output end of the differential current signal output circuit, and the other end of the first resistor is movably connected with one input end of the variable gain amplifier; one end of the second resistor is connected with the other output end of the differential current signal output circuit, and the other end of the second resistor is movably connected with the other input end of the variable gain amplifier.

8. The on-chip calibration source circuit of claim 7, wherein, The impedance adjusting circuit further comprises a third resistor, and the third resistor is connected between the two output ends of the differential current signal output circuit. One end of the third resistor is connected with one output end of the differential current signal output circuit, and the other end of the third resistor is movably connected with the other output end of the differential current signal output circuit.

9. The on-chip calibration source circuit of claim 7 or 8, wherein, The movably connected comprises connection through a switch.

10. The on-chip calibration source circuit of claim 1, wherein, The clock signal output circuit comprises a digital lock loop phase circuit.

11. The on-chip calibration source circuit of claim 1, wherein, The clock signal output circuit and the differential current signal output circuit are further connected with a buffer circuit and a duty cycle correction circuit. The buffer circuit is configured to receive and store the clock signal output by the clock signal output circuit. The duty cycle correction circuit is configured to receive the clock signal from the buffer circuit, adjust the duty cycle of the clock signal, and output the adjusted clock signal to the differential current signal output circuit.

12. The on-chip calibration source circuit of claim 11, wherein, The duty cycle correction circuit and the differential current signal output circuit are further connected with a latch circuit. The latch circuit is configured to receive and buffer the adjusted clock signal from the duty cycle correction circuit, and output the adjusted clock signal to the differential current signal output circuit.

13. A chip comprising a radio frequency direct sampling receive chain and an on-chip calibration source circuit, the radio frequency direct sampling receive chain comprising a variable gain amplifier and a time-interleaved analog-to-digital converter, and the on-chip calibration source circuit comprising the on-chip calibration source circuit according to any one of claims 1-12.

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