Control device, optical system, and lithography apparatus

Abstract

The invention relates to a control device (100) for controlling a number N, where N ≥ 1, of actuators (200) for actuating N optical elements (310) of an optical system (300), comprising a control node (K2), which can be coupled to the actuator (200), for providing a control voltage (V2) for the actuator (200), and an amplifier (110), which is designed to receive a supply voltage (V1) provided at an input node (K1) and to provide an output voltage (V3) at an output node (K3), wherein the amplifier (110) has a plurality M, where M ≥ 2, of power sources (111, 112), comprising at least one controlled power source (112) and a hold capacitor (113) for maintaining the level of the provided output voltage (V3), wherein the controlled power source (112) comprises a transistor (114), the gate terminal of which can be controlled by an adjustable first control signal (S1), and an adjustable resistor (115) coupled to the transistor (114).

Description

[0001] Carl Zeiss SMT GmbH

[0002] 1

[0003] CONTROL DEVICE, OPTICAL SYSTEM AND LITHOGRAPHING SYSTEM

[0004] The present invention relates to a control device for controlling a number of actuators for actuating optical elements of an optical system, an optical system with such a control device and a lithography system with such an optical system.

[0005] The content of priority application DE 10 2024 209 184.7 is fully incorporated by reference.

[0006] Microlithography systems are known that incorporate actuated optical elements, such as microlens arrays or micromirror arrays. Microlithography is used to fabricate microstructured components, such as integrated circuits. The microlithography process is performed using a lithography system that includes an illumination system and a projection system.

[0007] Driven by the pursuit of ever smaller structures in the fabrication of integrated circuits, EUV lithography systems are currently being developed that use light with a wavelength in the range of 0.1 nm to 30 nm, particularly 13.5 nm. Since most materials absorb light of this wavelength, such EUV lithography systems must use reflective optics, i.e., mirrors, instead of the refracting optics, i.e., lenses, used previously.

[0008] The image of a mask (reticule) illuminated by the illumination system is projected by the projection system onto a substrate, such as a silicon wafer, coated with a photosensitive layer (photoresist) and positioned in the image plane of the projection system. This transfers the mask structure onto the photosensitive coating of the substrate. Actuable optical elements can improve the imaging of the mask onto the substrate. For example, wavefront errors during exposure, which lead to magnified and / or blurred images, can be compensated for.

[0009] For example, a MEMS actuator (MEMS; Microelectromechanical System) or a PMN actuator (PMN; Lead-Magnesium Niobate) can be used. A PMN actuator enables positioning in the sub-micrometer or sub-nanometer range. The actuator, Carl Zeiss SMT GmbH

[0010] 2. The actuator elements of which are stacked on top of each other generate a force upon application of a direct current voltage, causing a specific linear expansion. The position set by the direct current voltage (DC) can be negatively affected by external electromechanical crosstalk at the inherent resonance points of the actuator driven by the DC voltage. MEMS mirrors and actuators suitable for driving them are described, for example, in DE 10 2016 213 025 A1.

[0011] For controlling the actuator, a control device is used, which includes an amplifier, for example a class-A amplifier. Such a control device for controlling an actuator to actuate an optical element of an optical system is described, for example, in patent application DE 10 2023 206 070.

[0012] Furthermore, the applicant is internally aware of a control device for controlling at least one actuator for actuating an optical element of an optical system, which comprises an amplifier configured to receive a supplied voltage at an input node and to provide a drive voltage for the actuator at an output node, wherein the amplifier has a resistive voltage divider for adjusting the gain of the amplifier with a first resistor and a second resistor. The amplifier is, for example, a class-A amplifier with an operational amplifier controllable by a control voltage and a transistor. The center tap of the resistive voltage divider is connected via a feedback branch to the non-inverting input of the operational amplifier.The inverting input of the operational amplifier is connected to an input node of the control device to receive a control voltage.

[0013] Furthermore, patent application DE 102024206494.7 of the applicant discloses a control device for controlling a number of actuators for actuating optical elements of an optical system, which includes a control node that can be coupled to the actuator for providing a control voltage for the actuator, an amplifier configured to receive a supply voltage provided at an input node and to provide an output voltage at an output node, wherein the amplifier has a plurality of current sources comprising at least one charge-controlled current source and a holding capacitor for maintaining the level of the provided output voltage, and a connection between the Carl Zeiss SMT GmbH

[0014] 3

[0015] The output node and the drive node are coupled to a buffer configured to decouple the drive node from the output node and provide the drive voltage for the actuator based on the level of the output voltage of the holding capacitor. The current sources are designed to provide predictive charge packets to set a specific charge on the holding capacitor, representing the desired output voltage level. At least one of the current sources is configured as a charge-controlled current source, enabling the current sources to drive the amplifier's output voltage up and down predictably by charging and discharging the holding capacitor without loss. The amount of capacitor charge can be predicted by a control unit of the drive device, which can control both the amplitude of the current sources and their activation time.In this way, these two parameters, amplitude and time, provide two degrees of freedom that simultaneously reduce the effort required for the resolution of a digital-to-analog converter (DAC) necessary for controlling the amplifier and also ensure the high resolution required by the system.

[0016] However, increasing the amplifier's quiescent current can adversely cause a drift in the amplifier's output voltage and thus a drift in the drive voltage. This can increase the noise of the drive device.

[0017] Against this background, one object of the present invention is to improve the control of a number of actuators of an optical system.

[0018] According to a first aspect, a control device for controlling a number N, with N > 1, of actuators for actuating N optical elements of an optical system is proposed. The control device comprises: a control node that can be coupled to the actuator for providing a control voltage to the actuator, and an amplifier configured to receive a supply voltage provided at an input node and to provide an output voltage at an output node, wherein the amplifier has a plurality M, with M > 2, of current sources comprising at least one controlled current source and a holding capacitor for maintaining the level of the provided output voltage. Carl Zeiss SMT GmbH

[0019] 4 wherein the controlled current source comprises a transistor whose gate terminal can be controlled by an adjustable first control signal, and an adjustable resistor coupled to the transistor.

[0020] The present control device uses an amplifier with a holding capacitor, which is preferably a high-voltage capacitor, wherein the holding capacitor is charged by the M current sources. The current sources are suitable for setting a specific charge on the holding capacitor, which represents the desired level of the output voltage. The holding capacitor, preferably a high-voltage capacitor, ideally produces no noise and maintains the level of the output voltage provided by the amplifier.

[0021] The existing controlled current source is adjustable via two mechanisms: firstly, the transistor of the controlled current source is adjustable via the first control signal, and secondly, the adjustable resistor of the controllable current source is adjustable via the second control signal. These two mechanisms enable very precise charge control of the holding capacitor. In particular, the holding capacitor can be charged and discharged very precisely via these two mechanisms, and thus the charge stored by the holding capacitor can be very accurately adjusted.

[0022] The first control signal is in particular a voltage signal and is preferably suitable for fine-tuning the level of the output voltage and thus for fine-tuning the charge stored by the holding capacitor.

[0023] The second control signal is in particular a signal with a specific period and a specific duty cycle and is suitable for coarse adjustment of the charge stored by the holding capacitor and thus for coarse adjustment of the level of the output voltage.

[0024] The supply voltage is in particular a high voltage (or high voltage) and is, for example, in a range of 40 V to 200 V.

[0025] The actuator is, in particular, a MEMS actuator, a capacitive actuator, for example, a PMN actuator (PMN; lead magnesium niobate) or a PZT actuator (PZT; lead zirconate titanate) or a LiNbO3 actuator (lithium niobate). The actuator is specifically designed to actuate an optical element. Carl Zeiss SMT GmbH

[0026] 5 of the optical system to actuate. Examples of such an optical element include lenses, mirrors, and adaptive mirrors.

[0027] The optical system is preferably a projection optic of the lithography system or a projection exposure system. However, the optical system can also be an illumination system. The projection exposure system can be an EUV lithography system. EUV stands for "Extreme Ultraviolet" and refers to a wavelength of the working light between 0.1 nm and 30 nm. The projection exposure system can also be a DUV lithography system. DUV stands for "Deep Ultraviolet" and refers to a wavelength of the working light between 30 nm and 250 nm.

[0028] According to one embodiment, the control device comprises a buffer coupled between the output node and the control node. The buffer is configured to decouple the control node from the output node and to provide the control voltage for the actuator based on the level of the output voltage of the holding capacitor.

[0029] This decouples the holding capacitor from the drive node for controlling the actuator via the buffer. The buffer can also be called a buffer amplifier or buffer (buffer circuit or isolation circuit) and its primary function here is to decouple circuit components, primarily the drive node from the output node. The actuator is connected to the decoupled drive node, and the drive voltage is given in particular by V2 = V3 - VGS, where V2 is the drive voltage at the drive node, V3 is the output voltage at the output node of the amplifier, and VGS is the gate-source voltage of the buffer.

[0030] According to another embodiment, the holding capacitor is coupled between the amplifier's output node and ground. The amplifier's current sources are configured to maintain a specific charge on the holding capacitor, depending on the desired level of the drive voltage. As described above, at least one of the M current sources is a controlled current source, enabling the M current sources to drive the amplifier's output voltage up and down by charging and discharging the holding capacitor without loss. The specific charge on the holding capacitor represents the desired level of the output voltage to be provided by the amplifier. Carl Zeiss SMT GmbH

[0031] 6

[0032] According to another embodiment, the amplifier comprises a constant current source coupled between the input node and the output node, and a controlled current source coupled between the output node and ground. For example, M = 2. This embodiment is particularly simple from a control engineering perspective, since only a single current source is configured as the controlled current source.

[0033] According to another embodiment, the amplifier comprises a controlled current source coupled between the input node and the output node, and a controlled current source coupled between the output node and ground. For example, M = 2. In this embodiment, both current sources are designed as controlled current sources, thus enabling increased flexibility in charging the holding capacitor.

[0034] According to another embodiment, the buffer comprises a source-follower circuit with at least one transistor, in particular a field-effect transistor. The source-follower circuit can also be referred to as a source follower or common-drain amplifier. In this context, the source follower is used in particular for decoupling and as a voltage buffer. In the source follower, the gate terminal of the transistor serves as the signal input, the source terminal as the output, and the drain terminal as the common terminal. To increase the performance of the source follower, a resistor, in particular an adjustable resistor, or an adjustable current source is coupled to its output node, in this case the drive node. The adjustable current source has the advantage of requiring little chip area.

[0035] According to another embodiment, the source-follower circuit has a plurality of protection diodes coupled between the gate terminal of the transistor and the source terminal of the transistor.

[0036] According to another embodiment, the amplifier comprises at least three current sources, with M > 3. In this embodiment, three or more interconnected current sources are used to charge the holding capacitor.

[0037] According to another embodiment, the adjustable resistor is designed as a duty-cycle resistor. The duty-cycle resistor can be referred to in particular as a duty-cycle resistor. Carl Zeiss SMT GmbH

[0038] 7

[0039] According to another embodiment, the transistor is designed as an n-channel transistor whose source terminal is connected to the adjustable resistor.

[0040] According to another embodiment, the controlled current source is connected to the transistor and the adjustable resistor between the output node and ground.

[0041] According to another embodiment, the controlled current source includes a transistor whose gate terminal can be controlled by the adjustable first control signal. In this embodiment, the transistor is specifically designed as a high-voltage (HV) transistor. In alternative embodiments, the transistor can also be designed as a low-voltage (LV) transistor.

[0042] According to another embodiment, the controlled current source comprises the transistor whose gate terminal can be controlled by the adjustable first control signal, and another transistor. The second transistor is coupled between the control node and the first transistor.

[0043] According to a further embodiment, the control device comprises a control unit. The control unit is configured to control the transistor by means of the first control signal and to control the adjustable resistor by means of a second control signal (S2). The control unit provided allows for the control of the charging of the holding capacitor.

[0044] According to another embodiment, the control device is designed to maintain the output voltage of the amplifier at a predetermined level by controlling the transistor using the first control signal and by controlling the adjustable resistor using the second control signal.

[0045] According to a further embodiment, the control device is configured to achieve fine adjustment of the output voltage level by controlling the transistor with the first control signal and coarse adjustment of the output voltage level by controlling the adjustable resistor with the second control signal. Carl Zeiss SMT GmbH

[0046] 8

[0047] According to a further embodiment, the control device comprises a measuring circuit configured to provide a measuring voltage proportional to the output voltage. The control device is configured to provide the first control signal and the second control signal using the provided measuring voltage, a reference voltage, and a clock signal.

[0048] According to another embodiment, the measuring circuit is connected between the output node of the amplifier and the control device and comprises a capacitive voltage divider with a series connection of a first capacitor and a second capacitor. The center tap of the capacitive voltage divider is connected to the control device.

[0049] According to another embodiment, the measuring circuit comprises a capacitive voltage divider and a series connection of the holding capacitor and a second capacitor, wherein the center tap of the capacitive voltage divider is connected to the control device.

[0050] According to another embodiment, the measuring circuit comprises a capacitive voltage divider and a series connection of the actuator and a second capacitor, wherein the center tap of the capacitive voltage divider is connected to the control device.

[0051] The capacitive voltage divider, as a component of the measuring circuit for measuring a measurement voltage proportional to the output voltage, has the advantage that the use of high-impedance resistors can be eliminated. This advantageously reduces noise and the required electrical power and chip area. Furthermore, the capacitive voltage divider can be used in the feedback path for calibrating the period and pulse duration of the second drive signal or for testing purposes. Compared to conventional designs, this touch-triggered charging control tolerates higher DC currents in the amplifier and thus particularly facilitates the control of leakage currents.

[0052] According to a further embodiment, the control device comprises a comparator clocked by the clock signal, a control unit clocked by the clock signal, and a digital-to-analog converter clocked by the clock signal. The clocked comparator is configured to provide a digital comparison signal at the output side based on the measurement voltage received at the input and a second reference voltage. The clocked Carl Zeiss SMT GmbH

[0053] 9

[0054] The control unit is configured to provide the second control signal using the provided digital reference signal, such that it has a period determined by the clock signal and a duty cycle set according to the reference signal. Furthermore, the clocked control unit is configured to provide a digital counter signal representing a sequence of multiple provided digital reference signals. The clocked digital-to-analog converter is configured to provide the first control signal using the provided digital counter signal and a reference signal.

[0055] The period can also be called the period duration. The period duration is, in particular, the reciprocal of the frequency of the clock signal. The on-time can also be called the pulse duration. The second control signal is, for example, a PWM signal (PWM; pulse width modulation) with a pulse duration td and a period duration tclk.

[0056] In embodiments where the second control signal is configured as a signal with a specific period and pulse duration, the adjustable resistor can also be referred to as a duty-cycle resistor. Overall, the present control device thus provides duty-cycle charge control for the charging of the holding capacitor of the amplifier of the control device.

[0057] The present embodiment of the touch-triggered charging control for adjusting the charge of the holding capacitor has three degrees of freedom: the pulse duration td and the period tclk of the second control signal, and the first control signal. While the period tclk and the pulse duration td are used for coarse adjustment of the current, for example, from the picoampere range to the nanoampere range, the first control signal can be used for fine adjustment, in particular for leakage current compensation and for compensating for current deviations. The latter is particularly advantageous in harsh environmental conditions to shorten the calibration time and to be robust against drift and degradation effects.

[0058] According to a further embodiment, the control device is configured to control a plurality of actuators by means of a time-division multiplex signal determined by a time-division multiplexing scheme. Carl Zeiss SMT GmbH

[0059] 10

[0060] According to a second aspect, an optical system with a number of actuable optical elements is proposed, wherein each of the actuable optical elements of the number is assigned an actuator, wherein each actuator is assigned a control device for controlling the actuator according to the first aspect or according to one of the embodiments of the first aspect.

[0061] The optical system includes, in particular, a micromirror array and / or a microlens array with a multitude of independently actuable optical elements.

[0062] In embodiments, groups of actuators can be defined, wherein all actuators in a group are assigned the same control device.

[0063] According to one embodiment, the optical system is designed as an illumination optic or as a projection optic of a lithography system.

[0064] According to another embodiment, the optical system has a vacuum housing in which the actuable optical elements, the associated actuators and the control device are arranged.

[0065] According to a third aspect, a lithography system is proposed which has an optical system according to the second aspect or according to one of the embodiments of the second aspect.

[0066] The lithography system is, for example, an EUV lithography system whose working light lies in a wavelength range of 0.1 nm to 30 nm, or a DUV lithography system whose working light lies in a wavelength range of 30 nm to 250 nm.

[0067] The term "one" here should not necessarily be understood as restricting the number to exactly one element. Rather, it can also refer to multiple elements, such as two, three, or more. Similarly, every other counter used here should not be interpreted as restricting the number to the exact number stated. Instead, numerical deviations, both higher and lower, are possible unless otherwise specified.

[0068] Other possible implementations of the invention also include combinations of features or embodiments described previously or subsequently with regard to the exemplary embodiments, even if not explicitly mentioned. Carl Zeiss SMT GmbH

[0069] 11. The person skilled in the art may also add individual aspects as improvements or additions to the respective basic form of the invention.

[0070] Further advantageous embodiments and aspects of the invention are the subject of the dependent claims and the exemplary embodiments of the invention described below. The invention will be explained in more detail below with reference to preferred embodiments and the accompanying figures.

[0071] Fig. 1 shows a schematic meridional section of a projection exposure system for EUV projection lithography;

[0072] Fig. 2 shows a schematic representation of an embodiment of an optical system;

[0073] Fig. 3 shows a schematic block diagram of a first embodiment of a control device for controlling a number of actuators for actuating optical elements of an optical system;

[0074] Fig. 4 shows a schematic block diagram of a second embodiment of a control device for controlling a number of actuators for actuating optical elements of an optical system;

[0075] Fig. 5 shows a schematic block diagram of a third embodiment of a control device for controlling a number of actuators for actuating optical elements of an optical system;

[0076] Fig. 6 shows a schematic block diagram of a fourth embodiment of a control device for controlling a number of actuators for actuating optical elements of an optical system; and

[0077] Fig. 7 shows a schematic block diagram of a fifth embodiment of a control device for controlling a number of actuators for actuating optical elements of an optical system.

[0078] In the figures, identical or functionally equivalent elements have been labelled with the same reference symbols unless otherwise indicated. Furthermore, it should be noted that the representations in the figures are not necessarily to scale. Carl Zeiss SMT GmbH

[0079] 12

[0080] Fig. 1 shows an embodiment of a projection exposure system 1 (lithography system), in particular an EUV lithography system. One embodiment of the illumination system 2 of the projection exposure system 1 has, in addition to a light or radiation source 3, an illumination optic 4 for illuminating an object field 5 in an object plane 6. In an alternative embodiment, the light source 3 can also be provided as a separate module from the rest of the illumination system 2. In this case, the illumination system 2 does not include the light source 3.

[0081] A reticule 7 arranged in the object field 5 is exposed. The reticule 7 is held by a reticule holder 8. The reticule holder 8 can be moved, particularly in a scanning direction, via a reticule displacement drive 9.

[0082] Figure 1 illustrates a Cartesian coordinate system with an x-direction x, a y-direction y, and a z-direction z. The x-direction x runs perpendicular to the plane of the drawing. The y-direction y runs horizontally, and the z-direction z runs vertically. In Figure 1, the scan direction runs along the y-direction y. The z-direction z runs perpendicular to the object plane 6.

[0083] The projection exposure system 1 comprises a projection optic 10. The projection optic 10 serves to image the object field 5 onto an image field 11 in an image plane 12. The image plane 12 is parallel to the object plane 6. Alternatively, an angle other than 0° between the object plane 6 and the image plane 12 is also possible.

[0084] A structure on the reticulum 7 is imaged onto a photosensitive layer of a wafer 13 located in the image plane 12 within the image field 11. The wafer 13 is held by a wafer holder 14. The wafer holder 14 can be moved, particularly along the y-direction y, via a wafer transfer drive 15. The movement of the reticulum 7 via the reticulum transfer drive 9 and of the wafer 13 via the wafer transfer drive 15 can be synchronized.

[0085] Light source 3 is an EUV radiation source. Light source 3 emits, in particular, EUV radiation 16, which is also referred to below as useful radiation, illumination radiation, or illumination light. The useful radiation 16 has a wavelength in the range between 5 nm and 30 nm. Light source 3 can be a plasma source, for example, an LPP source (Laser Produced Plasma, with the assistance of Carl Zeiss SMT GmbH).

[0086] 13. Plasma generated by a laser) or a DPP source (Gas Discharged Produced Plasma). It could also be a synchrotron-based radiation source. Light source 3 could be a free-electron laser (FEL).

[0087] The illumination radiation 16 emanating from the light source 3 is focused by a collector 17. The collector 17 can be a collector with one or more ellipsoidal and / or hyperboloid reflective surfaces. The at least one reflective surface of the collector 17 can be illuminated by the illumination radiation 16 at grazing incidence (Gl), i.e., with angles of incidence greater than 45°, or at normal incidence (NI), i.e., with angles of incidence less than 45°. The collector 17 can be structured and / or coated to optimize its reflectivity for the useful radiation and to suppress stray light.

[0088] After the collector 17, the illumination radiation 16 propagates through an intermediate focus in an intermediate focal plane 18. The intermediate focal plane 18 can represent a separation between a radiation source module, comprising the light source 3 and the collector 17, and the illumination optics 4.

[0089] The illumination optics 4 comprise a deflecting mirror 19 and, downstream in the beam path, a first faceted mirror 20. The deflecting mirror 19 can be a planar deflecting mirror or, alternatively, a mirror with an effect that influences the beam shape beyond the mere deflection effect. Alternatively or additionally, the deflecting mirror 19 can be designed as a spectral filter that separates a useful wavelength of the illumination radiation 16 from stray light of a different wavelength. If the first faceted mirror 20 is arranged in a plane of the illumination optics 4 that is optically conjugate to the object plane 6 as the field plane, it is also referred to as a field faceted mirror. The first faceted mirror 20 comprises a plurality of individual first facets 21, which can also be referred to as field facets. Only a few of these first facets 21 are shown in Fig. 1 as examples.

[0090] The first facets 21 can be designed as macroscopic facets, in particular as rectangular facets or as facets with an arcuate or semicircular edge contour. The first facets 21 can be designed as planar facets or alternatively as convexly or concavely curved facets. Carl Zeiss SMT GmbH

[0091] 14

[0092] As is known, for example, from DE 10 2008 009 600 Al, the first facets 21 can themselves each be composed of a plurality of individual mirrors, in particular a plurality of micromirrors. The first facet mirror 20 can in particular be designed as a microelectromechanical system (MEMS system). For details, reference is made to DE 10 2008 009 600 Al.

[0093] Between the collector 17 and the deflecting mirror 19, the illumination radiation 16 runs horizontally, i.e. along the y-direction y.

[0094] In the beam path of the illumination optics 4, a second faceted mirror 22 is arranged downstream of the first faceted mirror 20. If the second faceted mirror 22 is arranged in a pupil plane of the illumination optics 4, it is also referred to as a pupil faceted mirror. The second faceted mirror 22 can also be arranged at a distance from a pupil plane of the illumination optics 4. In this case, the combination of the first faceted mirror 20 and the second faceted mirror 22 is also referred to as a specular reflector. Specular reflectors are known from US 2006 / 0132747 A1, EP 1 614 008 B1, and US 6,573,978.

[0095] The second facet mirror 22 comprises a plurality of second facets 23. In the case of a pupil facet mirror, the second facets 23 are also referred to as pupil facets.

[0096] The second facets 23 can also be macroscopic facets, which may, for example, have round, rectangular, or hexagonal edges, or alternatively, facets composed of micromirrors. Reference is also made to DE 10 2008 009 600 Al in this regard.

[0097] The second facets 23 can have planar or alternatively convex or concave curved reflective surfaces.

[0098] The illumination optics 4 thus form a double-faceted system. This basic principle is also known as a honeycomb condenser (EnglJ Fly's Eye Integrator).

[0099] It can be advantageous not to arrange the second faceted mirror 22 exactly in a plane that is optically conjugate to a pupil plane of the projection optics 10. In particular, the second faceted mirror 22 can be positioned relative to Carl Zeiss SMT GmbH

[0100] 15 of a pupil plane of the projection optics 10 may be arranged tilted, as is described for example in DE 10 2017 220 586 Al.

[0101] With the aid of the second faceted mirror 22, the individual first facets 21 are imaged into the object field 5. The second faceted mirror 22 is the last beam-shaping, or indeed the last, mirror for the illumination radiation 16 in the beam path before the object field 5.

[0102] In another embodiment of the illumination optics 4, not shown, a transmission optic can be arranged in the beam path between the second facet mirror 22 and the object field 5, which contributes in particular to imaging the first facets 21 into the object field 5. The transmission optic can have exactly one mirror, or alternatively two or more mirrors, which are arranged one behind the other in the beam path of the illumination optics 4. The transmission optic can in particular comprise one or two mirrors for normal incidence (Ni mirrors, normal incidence mirrors) and / or one or two mirrors for grazing incidence (GF mirrors, grazing incidence mirrors).

[0103] In the embodiment shown in Fig. 1, the lighting optics 4 has exactly three mirrors after the collector 17, namely the deflecting mirror 19, the first faceted mirror 20 and the second faceted mirror 22.

[0104] In a further embodiment of the lighting optics 4, the deflecting mirror 19 can also be omitted, so that the lighting optics 4 after the collector 17 can then have exactly two mirrors, namely the first faceted mirror 20 and the second faceted mirror 22.

[0105] The mapping of the first facets 21 by means of the second facets 23 or with the second facets 23 and a transmission optic into the object plane 6 is regularly only an approximate mapping.

[0106] The projection optics 10 comprise a plurality of mirrors Mi, which are numbered according to their arrangement in the beam path of the projection exposure system 1.

[0107] In the example shown in Fig. 1, the projection optics 10 comprise six mirrors M1 to M6. Alternatives with four, eight, ten, twelve, or any other number of mirrors Mi are also possible. The projection optics 10 is a double-obscured optic. The penultimate mirror M5 and the last mirror M6 each have a through-hole for the Carl Zeiss SMT GmbH

[0108] 16

[0109] Illumination radiation 16. The projection optics 10 has an image-side numerical aperture that is greater than 0.5 and that can also be greater than 0.6 and that can be, for example, 0.7 or 0.75.

[0110] The reflective surfaces of the mirrors Mi can be designed as freeform surfaces without an axis of rotational symmetry. Alternatively, the reflective surfaces of the mirrors Mi can be designed as aspherical surfaces with exactly one axis of rotational symmetry of the reflective surface shape. The mirrors Mi, like the mirrors of the illumination optics 4, can have highly reflective coatings for the illumination radiation 16. These coatings can be designed as multilayer coatings, in particular with alternating layers of molybdenum and silicon.

[0111] The projection optics 10 has a large object-image offset in the y-direction y between a y-coordinate of a center of the object field 5 and a y-coordinate of the center of the image field 11. This object-image offset in the y-direction y can be approximately as large as a z-distance between the object plane 6 and the image plane 12.

[0112] The projection optics 10 can be anamorphic. In particular, they have different image scales βx, βy in the x and y directions. The two image scales βx, βy of the projection optics 10 are preferably (βx, βy) = (+ / - 0.25, ± 0.125). A positive image scale β indicates an image without image inversion. A negative value for the image scale β indicates an image with image inversion.

[0113] The projection optics 10 thus lead to a reduction in the x-direction x, that is, in the direction perpendicular to the scan direction, in a ratio of 4'1.

[0114] The projection optics 10 lead to a reduction of 8H in the y-direction y, that is, in the scan direction.

[0115] Other magnification ratios are also possible. Magnification ratios with the same sign and absolute value in the x and y directions (x, y), for example with absolute values ​​of 0.125 or 0.25, are also possible.

[0116] The number of intermediate image planes in the x and y directions (x, y) in the beam path between the object field 5 and the image field 11 can be the same or, depending on the design of the projection optics 10, can differ. Carl Zeiss SMT GmbH

[0117] 17

[0118] Examples of projection optics with different numbers of such intermediate images in the x and y directions x, y are known from US 2018 / 0074303 Al.

[0119] Each of the second facets 23 is assigned to exactly one of the first facets 21 to form an illumination channel for illuminating the object field 5. This can result, in particular, in illumination according to Köhler's principle. The far field is divided into a multitude of object fields 5 with the help of the first facets 21. The first facets 21 generate a plurality of images of the intermediate focus on the second facets 23 assigned to each of them.

[0120] The first facets 21 are each superimposed on a corresponding second facet 23 to illuminate the object field 5 on the reticle 7. The illumination of the object field 5 is particularly homogeneous. It preferably exhibits a uniformity error of less than 2%. Field uniformity can be achieved by superimposing different illumination channels.

[0121] The illumination of the entrance pupil of the projection optics 10 can be geometrically defined by arranging the second facets 23. By selecting the illumination channels, in particular the subset of the second facets 23 that carry light, the intensity distribution in the entrance pupil of the projection optics 10 can be adjusted. This intensity distribution is also referred to as the illumination setting or illumination pupil filling.

[0122] Another preferred pupil uniformity in the area of ​​defined illuminated sections of an illumination pupil of the illumination optics 4 can be achieved by a redistribution of the illumination channels.

[0123] Further aspects and details of the illumination of the object field 5 and, in particular, the entrance pupil of the projection optics 10 are described below.

[0124] The projection optics 10 can, in particular, have a homocentric entrance pupil. This can be accessible. It can also be inaccessible.

[0125] The entrance pupil of the projection optics 10 cannot always be illuminated exactly by the second faceted mirror 22. When the projection optics 10 image the center of the second faceted mirror 22 telecentrically onto the wafer 13, the aperture rays often do not intersect at Carl Zeiss SMT GmbH

[0126] 18 a single point. However, a surface can be found in which the pairwise determined distance of the aperture rays is minimized. This surface represents the entrance pupil or a surface conjugate to it in position space. In particular, this surface exhibits a finite curvature.

[0127] The projection optics 10 may have different entrance pupil positions for the tangential and sagittal beam paths. In this case, an imaging element, in particular an optical component of the transmission optics, should be provided between the second faceted mirror 22 and the reticle 7. This optical element can accommodate the different positions of the tangential and sagittal entrance pupils.

[0128] In the arrangement of the components of the illumination optics 4 shown in Fig. 1, the second faceted mirror 22 is arranged in a plane conjugate to the entrance pupil of the projection optics 10. The first faceted mirror 20 is arranged tilted relative to the object plane 6. The first faceted mirror 20 is arranged tilted relative to an arrangement plane defined by the deflecting mirror 19. The first faceted mirror 20 is arranged tilted relative to an arrangement plane defined by the second faceted mirror 22.

[0129] Fig. 2 shows a schematic representation of an embodiment of an optical system 300 for a lithography system or projection exposure system 1, as shown, for example, in Fig. 1. Furthermore, the optical system 300 of Fig. 2 can also be used, for example, in a DUV lithography system.

[0130] The optical system 300 of Fig. 2 has a plurality of actuable optical elements 310. The optical system 300 is configured here as a micromirror array, wherein the optical elements 310 are micromirrors. Each micromirror 310 can be actuated by means of an associated actuator 200. For example, each micromirror 310 can be tilted about two axes and / or displaced in one, two, or three spatial axes by means of the associated actuator 200. For clarity, reference numerals are shown only for the top row of these elements.

[0131] The control device 100 controls the respective actuator 200, for example, with a control voltage V2 (see Figs. 3 to 7). This sets a position of the respective micromirror 310. The control device 100 is described in particular with reference to Figs. 3 to 7. Carl Zeiss SMT GmbH

[0132] 19

[0133] Figure 3 shows a schematic block diagram of a first embodiment of a control device 100 for controlling a number N, with N > 1, of actuators 200 for actuating N optical elements 310 of an optical system 300. Without loss of generality, N = 1 in Figure 3, and the control device 100 controls one actuator 200. In the embodiments shown in Figures 3 to 7, the actuator 200 is a capacitive actuator and is shown as a capacitive in Figures 3 to 7.

[0134] The control device 100 comprises an input node Kl for receiving the supply voltage VI and a control node K2 that can be coupled to the actuator 200 for providing the control voltage V2 for the actuator 200.

[0135] Furthermore, the control device 100 includes an amplifier 110, which is configured to receive the supply voltage VI provided at the input node Kl and to provide an output voltage V3 at an output node K3 of the amplifier 110.

[0136] As illustrated in Fig. 3, the amplifier 110 has a plurality M, with M > 2, of current sources 111, 112 comprising at least one controlled current source.

[0137] 112. In the embodiment of Fig. 3, the lower current source 112 coupled to ground GND is designed as a controlled current source 112.

[0138] Furthermore, amplifier 110 has a holding capacitor 113 to maintain the level of the provided output voltage V3. The holding capacitor

[0139] Capacitor 113 is coupled between the output node K3 of amplifier 110 and ground (GND). The current sources 111 and 112 of amplifier 110 are specifically configured to adjust the charge on the holding capacitor 113 according to a desired level of the drive voltage V2. Consequently, the two current sources 111 and 112 are capable of adjusting the charge on the holding capacitor 113 such that the desired drive voltage V2 is provided at the drive node K2 for the actuator 200.

[0140] As further shown in Fig. 3, a buffer 120 is provided between the output node K3 and the control node K2. The buffer 120 is configured to decouple the control node K2 from the output node K3 and to provide the control voltage V2 for the actuator 200 based on the level of the output voltage V3 of the holding capacitor 113. Carl Zeiss SMT GmbH

[0141] 20

[0142] As already explained above, at least one of the M current sources 111, 112 is configured as a controlled current source. As further explained above, the lower current source 112 in Fig. 3 is configured as a controlled current source. Accordingly, the upper current source 111, in particular, can be configured as a constant current source. The buffer 120 can also be referred to as a buffer amplifier or buffer and here has the function, in particular, of decoupling circuit sections, primarily the input node K2 from the output node K3.

[0143] The controlled current source 112 of Fig. 3 comprises a transistor 114 and an adjustable resistor 115 coupled to the transistor 114. The transistor 114 can be controlled via its gate terminal by an adjustable first control signal S1. The transistor 114 is preferably configured as an n-channel transistor whose source terminal is connected to the adjustable resistor 115. As shown in Fig. 3, the series circuit consisting of the transistor 114 and the adjustable resistor 115 is connected between the output node K3 and ground GND. The adjustable resistor 115 is, in particular, a duty-cycle resistor. The controlled current source 112 with the transistor 114 and the adjustable resistor 115 is thus connected between the input node K3 and ground GND.

[0144] In the embodiment shown in Fig. 3, the controlled current source 112 comprises the transistor 114. In some embodiments, the transistor 114 is a high-voltage (HV) transistor. In alternative embodiments, the transistor 114 is configured as a low-voltage (LV) transistor.

[0145] As further shown in Fig. 3, the control device 100 comprises a control unit 130. The control unit 130 is configured to control the transistor 114 by means of the first control signal S1 and to control the adjustable resistor 115 by means of a second control signal S2. In particular, the control unit 130 is configured to maintain the output voltage V3 of the amplifier 110 at a predetermined level by controlling the transistor 114 by means of the first control signal S1 and / or by controlling the adjustable resistor 115 by means of the second control signal S2.

[0146] In other words, it is a function of the control device 130 to maintain the output voltage V3 of the amplifier 110 at a predetermined level. For example, due to leakage currents or current changes during the operation of the optical system 300, the output voltage V3 may fluctuate. Carl Zeiss SMT GmbH

[0147] The output voltage V3 of amplifier 110 does not exactly maintain the predetermined level and fluctuates around it. To keep the output voltage V3 of amplifier 110 at the predetermined level, the control device has two different means: first, controlling transistor 114 by means of the first control signal S1, and second, controlling the adjustable resistor 115 by means of the second control signal S2. In applications, the control device 130 can select the first control signal S1, the second control signal S2, or a suitable combination of the first and second control signals S2 to set the predetermined level of the output voltage V3 of amplifier 110.

[0148] In particular, the control device 130 is configured to fine-tune the level of the output voltage V3 by controlling transistor 114 with the first control signal S1. Conversely, the control device 130 is also preferably configured to coarse-tune the level of the output voltage V3 by controlling the adjustable resistor 115 with the second control signal S2. In other words, the control device 130 provides fine-tuning of the output voltage V3 by controlling transistor 114 and coarse-tuning of the output voltage V3 by controlling the adjustable resistor 115.

[0149] Furthermore, the control device 100 of Fig. 3 comprises a measuring circuit 140, which is configured to provide a measuring voltage VDIV proportional to the output voltage V3. The control device 130 is specifically configured to provide the first control signal S1 and / or the second control signal S2 using the measuring voltage VDIV provided by the measuring circuit 140, a reference voltage VREF, a second reference voltage VREF2, and a clock signal CLK.

[0150] In the embodiment shown in Fig. 3, the measuring circuit 140 is connected between the output node K3 of the amplifier 110 and the control device 130. The measuring circuit 140 of Fig. 3 comprises a capacitive voltage divider Cl, C2, which includes a series connection of a first capacitor Cl and a second capacitor C2. The center tap of the capacitive voltage divider Cl, C2 is connected to the control device 130. The measuring voltage VDIV of the control device 130 is supplied via this center tap of the capacitive voltage divider Cl, C2. A switch 150 can be used to reset the measuring circuit 140. The measuring voltage is specified by Carl Zeiss SMT GmbH.

[0151] 22

[0152] VDIV is monitored by means of the control device 130. This feedback enables a finely controlled level of the output voltage V3 in clock frequency (CLK) intervals.

[0153] Fig. 4 shows a schematic block diagram of a second embodiment of a control device 100 for controlling a number of actuators 200 for actuating optical elements 310 of an optical system 300. The second embodiment according to Fig. 4 is based on the first embodiment according to Fig. 3 and differs only in the design of the controlled current source 112. The controlled current source 112 of Fig. 4 has, in addition to the transistor 114, another transistor 116. The additional transistor 116 is coupled between the control node K3 and the transistor 114.

[0154] In the embodiment of the controlled current source 112 with the two series-connected transistors 114 and 116, the transistor 114, controlled by the control device 130, can be configured as a low-voltage (LV) transistor, provided that the other transistor 116 is configured as a high-voltage (HV) transistor. The gate terminal of the other transistor 116 is connected to a supply voltage VDD. In alternative embodiments, the other transistor 116 can be configured as a low-voltage (LV) transistor.

[0155] Fig. 5 shows a schematic block diagram of a third embodiment of a control device 100 for controlling a number of actuators 200 for actuating optical elements 310 of an optical system 300. The third embodiment according to Fig. 5 is based on the second embodiment according to Fig. 4 and shows in particular a detailed design of the control device 130. The control device 130 of Fig. 5 comprises a comparator 131 clocked by a clock signal CLK2, a control unit 132 clocked by the clock signal CLK, and a digital-to-analog converter 133 (DAC) clocked by the clock signal CLK. As Fig. 5 shows, the comparator 131 can also be clocked by a derived clock signal CLK2, which is derived from the clock signal CLK by the control unit 132.

[0156] The clocked comparator 131 is configured to provide a digital comparison signal VCMP at its output, based on the input measurement voltage VDIV received by the measuring circuit 140 and a second reference voltage VREF2. In some embodiments, the reference voltage VREF2 can be ground. In alternative embodiments, the reference voltage VREF2 can correspond to a predetermined potential, e.g., 1 volt. Carl Zeiss SMT GmbH

[0157] 23

[0158] The clocked control unit 132 is configured to provide the second control signal S2 using the provided digital comparison signal VCMP, such that it has a period determined according to the clock signal CLK and a duty cycle (or pulse duration) set according to the comparison signal VCMP.

[0159] Furthermore, the clocked control unit 132 is configured to provide a digital counter signal ZS, representing a sequence of a plurality of provided digital counter signals VCMP, using the provided digital comparison signal VCMP. The digital counter signal ZS has, in particular, a relatively small bit width, for example, 8 or 10 bits. The clocked digital-to-analog converter 133 is configured to provide the first drive signal S1 using the provided digital counter signal ZS and a reference signal VREF. Specifically, the reference signals VREF at the inputs of the comparator 131 and the digital-to-analog converter 133 can differ.

[0160] Figure 6 shows a schematic block diagram of a fourth embodiment of a control device 100 for controlling a number of actuators 200 for actuating optical elements 310 of an optical system 300. The fourth embodiment according to Figure 6 differs from the third embodiment according to Figure 5 in the design of the measuring circuit 140. The measuring circuit 140 of Figure 6 also has a capacitive voltage divider. However, the capacitive voltage divider of the measuring circuit 140 according to Figure 6 is formed by a series connection of the holding capacitor 113 and a second capacitor C2. The series connection of the holding capacitor 113 and the second capacitor C2 is connected between the output node K3 of the amplifier 110 and ground GND.

[0161] Fig. 7 shows a schematic block diagram of a fifth embodiment of a control device 100 for controlling a number of actuators 200 for actuating optical elements 310 of an optical system 300. The fifth embodiment according to Fig. 7 differs from the embodiments of Figs. 5 and 6 in the design of the measuring circuit 140. The measuring circuit 140 according to Fig. 7 also includes a capacitive voltage divider. However, the capacitive voltage divider 200, C2 of the measuring circuit 140 according to Fig. 7 is formed by a series connection of the actuator 200 and a second capacitor C2. The center tap of the capacitive voltage divider consisting of the actuator 200 and the second capacitor C2 is connected to the control device 130. Carl Zeiss SMT GmbH

[0162] 24 connected, so that the measuring voltage VDIV can be supplied to the control device 130 via the path connected to the center tap.

[0163] Although the present invention has been described using exemplary embodiments, it can be modified in many ways.

[0164] Carl Zeiss SMT GmbH

[0165] 25

[0166] REFERENCE MARK LIST

[0167] 1 Projection exposure system

[0168] 2 B lighting system

[0169] 3 light source

[0170] 4 B lighting optics

[0171] 5 object field

[0172] 6 Object level

[0173] 7 reticles

[0174] 8 label holders

[0175] 9 Reticle displacement drive

[0176] 10 Projection optics

[0177] 11 Image field

[0178] 12 Image plane

[0179] 13 wafers

[0180] 14 wafer holders

[0181] 15 W wafer transfer drive

[0182] 16 B lighting beam

[0183] 17 Collector

[0184] 18 Intermediate focus plane

[0185] 19 deflecting mirrors

[0186] 20 first faceted mirror

[0187] 21 first facet

[0188] 22 second faceted mirror

[0189] 23 second facet

[0190] 100 Control device

[0191] 110 amplifiers

[0192] 111 Power source

[0193] 112 controlled power source

[0194] 113 Holding capacitor

[0195] 114 Transistor

[0196] 115 adjustable resistance (touch-controlled resistance)

[0197] 116 Transistor

[0198] 120 buffers

[0199] 130 Control device

[0200] 131 Comparator

[0201] 132 Control unit

[0202] 133 Digital-to-Analog Converters

[0203] 140 measuring circuit

[0204] 150 switches Carl Zeiss SMT GmbH

[0205] 26

[0206] 200 actuator

[0207] 300 optical system

[0208] 310 optical element

[0209] CLK clock signal

[0210] CLK2 derived clock signal

[0211] GND Ground

[0212] Kl Entrance Node

[0213] K2 control node

[0214] K3 Exit Node

[0215] 51 first control signal

[0216] 52 second control signal

[0217] VCMP digital comparison signal

[0218] VDD supply voltage

[0219] VDIV measuring voltage

[0220] VREF Reference Voltage

[0221] VREF2 second reference voltage

[0222] ZS counter reading signal

Claims

Carl Zeiss SMT GmbH 27 patent claims 1. Control device (100) for controlling a number N, with N > 1, of actuators (200) for actuating N optical elements (310) of an optical system (300), comprising: a control node (K2) coupling to the actuator (200) for providing a control voltage (V2) for the actuator (200), and an amplifier (110) configured to receive a supply voltage (V1) provided at an input node (K1) and to provide an output voltage (V3) at an output node (K3), wherein the amplifier (110) comprises a plurality M, with M > 2, of current sources (111, 112) comprising at least one controlled current source (112) and a holding capacitor (113) for maintaining the level of the provided output voltage (V3), wherein the controlled current source (112) comprises a transistor (114) whose gate terminal is connected by a adjustable first control signal (Sl) is controllable,and has an adjustable resistor (115) coupled to the transistor (114).

2. Control device according to claim 1, further comprising a buffer (120) coupled between the output node (K3) and the control node (K2), which is configured to decouple the control node (K2) from the output node (K3) and to provide the control voltage (V2) for the actuator (200) based on the level of the output voltage (V3) of the holding capacitor (113).

3. Control device according to claim 1 or 2, wherein the holding capacitor (113) is coupled between the output node (K3) of the amplifier (110) and ground (GND), wherein the current sources (111, 112) of the amplifier (110) are configured to set a charge on the holding capacitor (113) depending on a desired level of the control voltage (V2).

4. Control device according to one of claims 1 to 3, wherein the adjustable resistance (115) is designed as a push-button controlled resistance.

5. Control device according to one of claims 1 to 4, wherein the transistor (114) is designed as an n-channel transistor whose source terminal is connected to the adjustable resistor (115). Carl Zeiss SMT GmbH 28 6. Control device according to one of claims 1 to 5, wherein the controlled current source (112) is connected to the transistor (114) and the adjustable resistor (115) between the output node (K3) and ground (GND).

7. Control device according to one of claims 1 to 6, wherein the controlled current source (112) comprises the transistor (114) whose gate terminal can be controlled by the adjustable first control signal (Sl), wherein the transistor (114) is designed as an LV transistor or as an HV transistor.

8. Control device according to one of claims 1 to 7, wherein the controlled current source (112) comprises the transistor (114), whose gate terminal can be controlled by the adjustable first control signal (Sl), and a further transistor (116), wherein the further transistor (116) is coupled between the control node (K3) and the transistor (114).

9. Control device according to one of claims 1 to 8, wherein a control device (130) is provided which is configured to control the transistor (114) by means of the first control signal (S1) and to control the adjustable resistor (115) by means of a second control signal (S2).

10. Control device according to claim 9, wherein the control device (130) is configured to maintain the output voltage (V3) of the amplifier (110) at a predetermined level by controlling the transistor (114) by means of the first control signal (S1) and by controlling the adjustable resistor (115) by means of the second control signal (S2).

11. Control device according to claim 9 or 10, wherein the control device (130) is configured to perform a fine adjustment of the level of the output voltage (V3) by means of a control of the transistor (114) with the first control signal (S1) and a coarse adjustment of the level of the output voltage (V3) by means of a control of the adjustable resistor (115) with the second control signal (S2).

12. Control device according to one of claims 9 to 11, further comprising Carl Zeiss SMT GmbH 29 a measuring circuit (140) which is configured to provide a measuring voltage (VDIV) proportional to the output voltage (V3), wherein the control device (130) is configured to provide the first control signal (S1) and the second control signal (S2) using the provided measuring voltage (VDIV), a reference voltage (VREF), a second reference voltage (VREF2) and a clock signal (CLK).

13. Control device according to claim 12, wherein the measuring circuit (140) is connected between the output node (K3) of the amplifier (110) and the control device (130) and has a capacitive voltage divider (Cl, C2) comprising a series connection of a first capacitor (C 1) and a second capacitor (C2), wherein the center tap of the capacitive voltage divider (Cl, C2) is connected to the control device (130).

14. Control device according to claim 12, wherein the measuring circuit (140) comprising a capacitive voltage divider (113, C2) and a series connection of the holding capacitor (113) and a second capacitor (C2), wherein the center tap of the capacitive voltage divider (113, C2) is connected to the control device (130).

15. Control device according to claim 12, wherein the measuring circuit (140) comprising a capacitive voltage divider (200, C2) and a series connection of the actuator (200) and a second capacitor (C2), wherein the center tap of the capacitive voltage divider (200, C2) is connected to the control device (130).

16. Control device according to one of claims 12 to 15, wherein the control device (130) comprises a comparator (131) clocked by means of the clock signal (CLK2), a control unit (132) clocked by means of the clock signal (CLK), and a digital-to-analog converter (133) clocked by means of the clock signal (CLK), wherein the clocked comparator (131) is configured to provide a digital comparison signal (VCMP) at the output side based on the input-side received measurement voltage (VDIV) and a second reference voltage (VREF2), wherein the clocked control unit (132) is configured to provide the second control signal (S2) using the provided digital comparison signal (VCMP) such that it has a period determined according to the clock signal (CLK) and a duration determined according to the comparison signal (VCMP). Carl Zeiss SMT GmbH 30 has a set duty cycle, and to provide a digital counter signal (ZS) representing a sequence of a plurality of provided digital comparison signals (VCMP), wherein the clocked digital-to-analog converter (133) is configured to provide the first drive signal (Sl) using the provided digital counter signal (ZS) and a reference signal (VREF).

17. Optical system (300) with a number of actuable optical elements (310), wherein each of the actuable optical elements (310) is assigned an actuator (200), wherein each actuator (200) is assigned a control device (100) for controlling the actuator (200) according to one of claims 1 to 16.

18. Lithography system (1) with an optical system (300) according to claim 17.

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