Control circuit and switching power supply

Abstract

This control circuit 100 comprises a timer capacitor 120 impressed with a COMP timer voltage Vct indicating a waveform that starts to rise from a predetermined timer charging start lower limit voltage Vll and falls to the timer charging start lower limit voltage Vll after a predetermined time elapses. When the COMP timer voltage Vct starts to rise from the timer charging start lower limit voltage Vll, a switch element Q is turned on. When the COMP timer voltage Vct reaches the COMP voltage, the switch element Q is turned off. The on period of the switch element Q is controlled by adjusting the timer charging start lower limit voltage Vll.　According to the control circuit 100 of the present invention, it is possible to prevent the power factor of the switching power supply from decreasing and the total harmonic distortion (THD) from worsening.

Description

Control Circuit and Switching Power Supply Cross Reference

[0001] This application claims priority based on Japanese Patent Application No. 2024-165950 filed in Japan on September 25, 2024, and all the contents described in the application are incorporated herein by reference as they are.

[0002] The present invention relates to a control circuit and a switching power supply.

[0003] Conventionally, a switching power supply that constitutes a power factor correction circuit is known (see, for example, Patent Document 1).

[0004] As such a switching power supply, for example, the following switching power supply can be exemplified (switching power supply 9 according to the background art). The switching power supply 9 according to the background art includes a rectifier circuit 10, a DC conversion circuit 20 having a switch element Q, and a control circuit 900, and is a switching power supply that constitutes a power factor improvement circuit (PFC circuit) that performs current critical operation.

[0005] The rectifier circuit 10 has a bridge diode BD and filters NF1 and NF2. The DC conversion circuit 20 includes an inductor L3, a switch element Q, and a diode D1.

[0006] The control circuit 900 controls the switching operation of the switch element Q. As shown in FIG. 7, the control circuit 900 includes a feedback control unit 910, a timer capacitor 920, a comparator 930, and a timer capacitor charge / discharge current control unit 940.

[0007] The feedback control unit 910 outputs an error voltage (COMP voltage Vcomp) generated based on the difference between the feedback voltage VFB (output feedback signal) corresponding to the output voltage Vo of the switching power supply 9 and the reference voltage FB_ref of the error amplifier 912 to the comparator 930.

[0008] The timer capacitor 920 is connected on one end to the comparator 930 and the timer capacitor charge / discharge current control unit 940, and on the other end to ground potential. The timer capacitor 920 is subjected to a COMP timer voltage Vct (see the waveform of Vct in Figure 8), which exhibits a waveform that starts rising from the timer charge start lower limit voltage and then decreases to the timer charge start lower limit voltage after a predetermined time has elapsed. In the background technology, after the COMP timer voltage Vct rises from the timer charge start lower limit voltage, rapid charging is performed for a predetermined period (until time t12 in Figure 8(a)), and then normal charging is performed. Therefore, the COMP timer voltage Vct rises rapidly until time t12 and then rises slowly thereafter.

[0009] The timer capacitor charge / discharge current control unit 940 applies the COMP timer voltage Vct to the timer capacitor 920. It also receives a COMP timer reset signal from the comparator 930 and reduces the COMP timer voltage Vct to the lower limit voltage for timer charging, while simultaneously outputting a gate control signal Vg to turn off the switch element Q.

[0010] The comparator 930 compares the COMP timer voltage Vct with the COMP voltage Vcomp and outputs a COMP timer reset signal to the timer capacitor charge / discharge current control unit 940 when the COMP timer voltage Vct reaches the COMP voltage Vcomp (when the COMP voltage Vcomp and the COMP timer voltage Vct cross in Figure 8).

[0011] For example, under heavy load, the output voltage Vo of the switching power supply 9 does not rise easily, so the COMP voltage Vcomp also increases, as shown in Figure 8(a) (see COMP voltage Vcomp in Figure 8). Therefore, the COMP voltage Vcomp and the COMP timer voltage Vct intersect near the timer charging upper limit voltage Vmax of the COMP timer voltage Vct, and the switch element Q turns off. Consequently, the switch element Q is turned on from the time when it starts rising from the timer charging start lower limit voltage (timer reference voltage Vref) (time t11) until the timing when the COMP voltage Vcomp and the COMP timer voltage Vct intersect (time t13) (see gate voltage Vg in Figure 8(a)).

[0012] On the other hand, under light load conditions, as shown in Figure 8(b), the output voltage Vo of the switching power supply 9 tends to rise, so the COMP voltage Vcomp also becomes lower (see COMP voltage Vcomp in Figure 8(b)). Therefore, the COMP voltage Vcomp and the COMP timer voltage Vct intersect within a short period (time t15) from time t14 when the COMP timer voltage Vct begins to rise, and the switch element Q turns off. Consequently, the switch element Q is turned on from the time when the voltage starts to rise from the timer charging start lower limit voltage (timer reference voltage Vref) (time t14) until the timing when the COMP voltage Vcomp and the COMP timer voltage Vct intersect (time t15). Therefore, the on-period width (on-width) is shorter compared to the heavy load case (see gate voltage Vg in Figure 8(b)).

[0013] Thus, the control circuit 900 can control the on-period (on-width) of the switch element Q by controlling the on-off state of the switch element Q based on the error voltage (COMP voltage Vcomp) generated based on the difference between the feedback voltage VFB corresponding to the output voltage Vo of the switching power supply 9 and the reference voltage FB_ref of the error amplifier 912, thereby keeping the on-period (on-width) constant. Therefore, by making the capacitance of the capacitor C7 connected to the COMP terminal large enough so that it does not respond to the AC commercial cycle, the on-period (on-width) becomes almost constant within the AC commercial cycle, so that the input current flows in proportion to the input voltage, and the power factor can be improved.

[0014] U.S. Patent Application Publication No. 2011 / 110127

[0015] Incidentally, in power factor correction circuits, a filter is placed on the input side to smooth the switched current (see filter NF2 in Figure 6). However, the voltage waveform of the input voltage is easily distorted due to the influence of the filter's capacitors and inductors (for example, inductor L2, capacitors C2 and C3 in Figure 6), and consequently, distortion may occur in the current waveform of the input current. In particular, near the AC trough voltage (see the area enclosed by the dashed line A1 in Figure 4), the input current may not flow due to this distortion, resulting in a further decrease in the power factor and a worsening of the THD (Total Harmonic Distortion). This problem is more pronounced when the original input current is small, such as in the case of light load.

[0016] Furthermore, near the AC trough voltage, a negative switching current is generated due to resonant operation during switching, and this negative switching current is stored in the filter's capacitor, etc. In a power factor correction circuit, the charge stored in the filter's capacitor due to this negative switching current is used to cause current to flow back to the inductor. As a result, the input current decreases, and in this case as well, there is a problem that the power factor decreases and the THD deteriorates.

[0017] Here, we will explain THD (Total Harmonic Distortion). For example, even when a sine wave is input as the input current, switching noise and phase shift occur due to the influence of capacitors and inductors in the filter NF2, resulting in a distorted waveform. This distorted waveform is made up of a superposition of the fundamental wave, second harmonic, third harmonic, etc., and it is required to reduce the harmonic components from the second harmonic onwards in order to protect power equipment, etc. THD (Total Harmonic Distortion) is used as an index to show the degree of distortion of such input current. THD can be expressed by the following formula. Note I １ indicates the magnitude of the fundamental wave, I ２ , I ３ ...I ｎ This indicates the magnitude of the second harmonic, third harmonic, ... nth harmonic.

[0018] In this case, if the input current drops to zero near the AC trough voltage (i.e., if the period of zero input current continues for a predetermined time), the distortion from the original sine wave increases. Consequently, the harmonic components become larger, leading to a deterioration of THD.

[0019] The present invention was made to solve the above-mentioned problems, and aims to provide a control circuit that can prevent a decrease in the power factor of a switching power supply and a deterioration in THD (Total Harmonic Distortion). It also aims to provide a switching power supply equipped with such a control circuit.

[0020] The present invention relates to a control circuit for controlling a switch element of a switching power supply having a switch element, and comprises a timer capacitor to which a COMP timer voltage is applied, the voltage having a waveform that starts rising from a predetermined timer charging start lower limit voltage and decreases to the timer charging start lower limit voltage after a predetermined time has elapsed, the control circuit controls the on period of the switch element by turning on the switch element when the COMP timer voltage starts rising from the timer charging start lower limit voltage, and turning off the switch element when the COMP timer voltage reaches an error voltage generated based on the difference between a feedback voltage corresponding to the output voltage of the switching power supply and a reference voltage of an error amplifier, and the control circuit controls the on period of the switch element by adjusting the timer charging start lower limit voltage.

[0021] The switching power supply of the present invention is characterized by comprising a rectifier circuit having a filter circuit, a DC conversion circuit having a switch element, and a control circuit of the present invention that controls the switching operation of the switch element.

[0022] According to the control circuit and switching power supply of the present invention, the timer charging start lower limit voltage is adjusted based on the AC input voltage. Therefore, the on period can be extended in the vicinity of the AC trough voltage (see the area enclosed by the dashed line A1 in Figure 4), where there is a risk of the input current not flowing due to distortion, and the current flowing through the switching element can be increased. Consequently, since the input current in the vicinity of the AC trough voltage can be made relatively large, it is possible to prevent the input current from not flowing in the vicinity of the AC trough voltage, thereby preventing a decrease in the power factor and a deterioration of THD (Total Harmonic Distortion).

[0023] Furthermore, according to the control circuit and switching power supply of the present invention, the timer charging start lower limit voltage is adjusted based on the AC input voltage, so the ON period can be extended near the AC trough voltage, and the current flowing through the switching element can be increased. Therefore, even if a negative switching current flows due to resonant operation during switching, the ratio of the negative switching current to the current flowing through the switching element becomes relatively small. As a result, from this viewpoint as well, it is possible to prevent the input current from ceasing to flow near the AC trough voltage, and to prevent a decrease in the power factor and a deterioration of THD (Total Harmonic Distortion).

[0024] This is a circuit diagram showing a switching power supply 1 according to an embodiment. This is a block diagram showing the control circuit 100 according to an embodiment. This is a schematic diagram showing the relationship between the COMP voltage Vcomp, COMP timer voltage Vct, gate voltage Vg, and timer charge start lower limit voltage Vll of the switching power supply 1. These are graphs showing the input current Iin, the drain current ID of the switch element, the COMP timer voltage Vct, and the on period (on width) of the switch element Q in the example and comparative example. Figure 4(a) is a graph showing the input current Iin etc. in the example, and Figure 4(b) is a graph showing the input current Iin etc. in the comparative example. These are graphs showing the relationship between output power and THD in the comparative example and the example. Figure 5(a) is a graph showing the relationship between output power and THD when the AC input power supply is 100V, and Figure 5(b) is a graph showing the relationship between output power and THD when the AC input power supply is 240V. This is a circuit diagram showing a conventional switching power supply 9. This is a block diagram of a conventional control circuit 900. Reference numeral 960 indicates the timer reference voltage setting unit. This is a schematic diagram showing the relationship between the COMP voltage Vcomp, COMP timer voltage Vct, and gate voltage Vg of the switching power supply 9.

[0025] The control circuit and switching power supply of the present invention will be described below based on the embodiments shown in the figures. Note that the embodiments described below do not limit the invention as defined in the claims. Furthermore, not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the present invention.

[0026] [Embodiment] 1. Diagram 1 of the configuration of the switching power supply 1 according to the embodiment is a circuit diagram showing the switching power supply 1 according to the embodiment. As shown in Figure 1, the switching power supply 1 according to embodiment 1 comprises a rectifier circuit 10, a DC conversion circuit (power factor correction circuit) 20, a control circuit 100, and an output capacitor C4. The output capacitor C4 is arranged between the DC conversion circuit 20 and the output terminals (terminal Vo and terminal GND).

[0027] The switching power supply 1 according to this embodiment has a configuration substantially similar to the switching power supply 9 in the background art, but differs in that a control circuit 100 having a THD terminal is provided instead of the control circuit 900, a capacitor C8 connected to the THD terminal, and a line connecting the THD terminal to the upstream stage of the bridge diode BD, with resistors R8, R9, capacitor C11, diodes D2 and D3 provided on this line.

[0028] The rectifier circuit 10 converts AC power input from the commercial power input AC-IN into DC power. The rectifier circuit 10 comprises a bridge diode BD, a first filter NF1, and a second filter NF2.

[0029] A bridge diode (BD) converts the AC current of a commercial power input into a pulsating current, for example, by full-wave rectification.

[0030] The first filter NF1 is positioned between the commercial input power supply AC-IN and the bridge diode BD. The first filter NF1 consists of a capacitor C1 and a common-mode coil L1, with the capacitor C1 attenuating normal-mode noise and the common-mode coil L1 attenuating common-mode noise.

[0031] The second filter NF2 is positioned between the bridge diode BD and the DC conversion circuit 20. The second filter NF2 consists of capacitors C2 and C3 connected between the lines and an inductor L2 (normal mode coil) connected to the positive output terminal of the bridge diode BD, and attenuates normal mode noise. Capacitor C2 is positioned on the input side of inductor L2, and capacitor C3 is positioned on the output side of inductor L2.

[0032] The DC conversion circuit (power factor correction circuit) 20 includes an inductor L3 through which the current output from the rectifier circuit 10 flows, a switch element Q that changes the increase or decrease of the current flowing through the inductor L3, and a diode D1. The DC conversion circuit 20 is a current-critical type power factor correction circuit (PFC circuit) that suppresses harmonics to improve the power factor and converts the power output from the rectifier circuit 10 into DC power.

[0033] Inductor L3 has one end connected to the second filter NF2 of the rectifier circuit 10, and the other end connected to the drain terminal of the switch element Q and the anode electrode of the diode D1. Inductor L4 is positioned opposite inductor L3 and detects the inductor current of inductor L3. Inductor L4 is connected to the VDZC terminal of the control circuit 100.

[0034] The switching element Q is a MOSFET whose drain electrode is connected to the anode electrodes of inductor L3 and diode D1, whose source electrode is connected to ground potential via resistor R2, and whose gate electrode is connected to the gate drive terminal OUT of the control circuit 100. Note that the switching element Q is not limited to a MOSFET; other suitable switching elements such as IGBTs can be used.

[0035] Diode D1 has its anode electrode connected to the drain electrode of inductor L3 and switch element Q, and its cathode electrode connected to the output terminal Vo.

[0036] 2. Configuration of the Control Circuit 100 According to the Embodiment The control circuit 100 according to the embodiment is a control circuit that outputs a gate control signal Vg for controlling the switch element Q to the gate electrode of the switch element Q, and controls the switching of the switch element Q. The control circuit 100 has eight terminals: Vcc terminal, OUT terminal, GND terminal, VZDC terminal, FB terminal, COMP terminal, THD terminal, and OCL terminal.

[0037] The Vcc terminal is connected to an external power supply Vcc and receives the voltage from the external power supply Vcc. The OUT terminal (gate drive terminal) is connected to the gate electrode of the switch element Q and outputs a gate control signal Vg to the gate electrode to control the on / off state of the switch element Q. The GND terminal is connected to ground potential.

[0038] The VDZC terminal is connected via inductor L4 and resistor R1, and the detection result of the inductor current of inductor L3 is input.

[0039] The FB terminal is connected to capacitor C6 and resistors R5 and R6. The FB terminal is connected to the output terminal Vo of the switching power supply via resistors R4 and R5, and the voltage divided by resistors R4 and R5 and resistor R6 is input to the FB terminal.

[0040] The COMP terminal is the output terminal of error amplifier 112 (feedback error amplifier, see Fig. 2) connected to capacitor C7. The output of error amplifier 112 is an error voltage (COMP voltage Vcomp) generated based on the difference between the feedback voltage VFB corresponding to the output voltage Vo of switching power supply 1 and the reference voltage FB_ref of error amplifier 112. The on-width of switch element Q is determined using the voltage of the COMP terminal (COMP voltage Vcomp) to control the output voltage.

[0041] The THD terminal is connected to capacitor C8 and resistors R9, R7 (and capacitor C11 connected in parallel with resistor R9). The THD terminal is connected to the front stage (the rear stage of the first filter NF1) of bridge diode BD via diode D2 (or D3) and resistors R8, R9, and inputs an AC input detection signal.

[0042] The OCL terminal is connected to resistor R3 and capacitor C9, and is connected to the midpoint of the source electrode of switch element Q and resistor R2 via resistor R3. The OCL terminal monitors whether an overcurrent is flowing through switch element Q by monitoring the voltage determined by resistor R2.

[0043] Next, the internal configuration of control circuit 100 will be described. As shown in Fig. 2, control circuit 100 includes a feedback control unit 110, a timer capacitor 120, a comparator 130, a timer capacitor charge / discharge current control unit 140, an arithmetic unit 150, and a timer reference voltage setting unit 160.

[0044] The feedback control unit 110 has one end connected to the FB terminal and the other end connected to the COMP terminal, and includes an error amplifier 112 inside. A feedback voltage VFB (output feedback signal) corresponding to the output voltage Vo of the switching power supply 1 is input to the first input terminal (- terminal) of the error amplifier 112, and a reference voltage FB_ref is input to the second input terminal (+ terminal) of the error amplifier 112. Also, a COMP voltage Vcomp is output, which charges and discharges a capacitor C7 connected to the outside of the COMP terminal and is input to the first input terminal (- terminal) of the comparator 130.

[0045] One end of the timer capacitor 120 is connected to the second input terminal (+ terminal) of the comparator 130 and the timer capacitor charge / discharge current control unit 140, and the other end is connected to the arithmetic unit 150. A COMP timer voltage (refer to the waveform of the COMP timer voltage Vct in FIG. 3), which shows a waveform that starts rising from a predetermined timer charge start lower limit voltage and drops to the predetermined timer charge start lower limit voltage after a predetermined time has elapsed, is applied to the timer capacitor 120 by the timer capacitor charge / discharge current control unit 140. The timer capacitor 120 serves as a timer for setting the on period of the switch element Q.

[0046] The comparator 130 compares the COMP timer voltage Vct with the COMP voltage Vcomp and outputs a COMP timer reset signal to the timer capacitor charge / discharge current control unit 140 when the COMP timer voltage Vct reaches the COMP voltage Vcomp.

[0047] The timer capacitor charge / discharge current control unit 140 is connected to the comparator 130, timer capacitor 120, calculation unit 150, and timer reference voltage setting unit 160. It is also connected to the gate electrode of the switch element Q via the OUT terminal and outputs a gate control signal Vg to the gate electrode of the switch element Q. Although not shown in the diagram, it is also connected to the inductor L4 via the VZDC terminal and detects the timing when the inductor current becomes zero. Furthermore, it is connected to an external power supply Vcc via the Vcc terminal and the timer reference voltage setting unit 160, and the timer reference voltage Vref is supplied from the timer reference voltage setting unit 160.

[0048] Here, the timer charging start lower limit voltage is the bias voltage applied to the timer capacitor 120, and is adjusted according to the AC input detection signal generated based on the AC input voltage. The timer charging start lower limit voltage is the timer reference voltage Vref near the AC peak voltage, and a voltage lower than the timer reference voltage Vref near the AC trough voltage (see the waveform of Vll in Figure 3(d)).

[0049] The timer capacitor charge / discharge current control unit 140 controls the charging current and discharge current to the timer capacitor 120 such that the COMP timer voltage Vct starts rising from the timer charge start lower limit voltage and then drops back down to the timer charge start lower limit voltage when it reaches a predetermined timer charge upper limit voltage Vmax (see the waveform of Vct in Figure 3).

[0050] Furthermore, the timer capacitor charge / discharge current control unit 140 outputs a control signal Vg to turn on the switch element Q when a COMP timer set signal is input from the calculation unit 150, and outputs a signal to turn off the switch element when the COMP timer voltage Vct reaches the COMP voltage Vcomp.

[0051] The timer capacitor charge / discharge current control unit 140 charges the timer capacitor 120 with a constant current when the COMP timer voltage Vct is above a predetermined timer reference voltage Vref, and controls the charging current to the timer capacitor 120 to decrease in accordance with the decrease in the COMP timer voltage when the COMP timer voltage is below the timer reference voltage Vref. The timer capacitor charge / discharge current control unit 140 applies a predetermined bias voltage (timer reference voltage Vref) to the timer capacitor 120 and varies the applied voltage according to the AC input voltage.

[0052] The calculation unit 150 is connected to the line preceding the bridge diode BD via the THD terminal and receives an AC input detection signal. Based on the AC input detection signal, which detects the AC input voltage, the calculation unit 150 adjusts the timer charging start lower limit voltage of the timer capacitor 120 and outputs a COMP timer set signal to the timer capacitor charge / discharge current control unit 140.

[0053] The calculation unit 150 receives an AC input signal obtained by full-wave rectifying the AC input voltage, and the upper limit, amplitude, or offset of the timer charging start lower limit voltage are limited.

[0054] The timer reference voltage setting unit 160 is connected to an external power supply Vcc via the Vcc terminal, generates a timer reference voltage Vref, and supplies it to the timer capacitor charge / discharge current control unit 140.

[0055] 3. Operation of the Switching Power Supply 1 and Control Circuit 100 According to the Embodiment Next, the operation of the switching power supply 1 and control circuit 100 according to the embodiment will be described with reference to Figure 3. The COMP voltage used is the COMP voltage under normal conditions, which is a heavy load. Figure 3 is a schematic diagram showing the relationship between the COMP voltage Vcomp, COMP timer voltage Vct, gate voltage Vg, and timer charge start lower limit voltage Vll of the switching power supply 1.

[0056] (1) When the AC input voltage is relatively high near the AC peak voltage (for example, the region enclosed by the dashed line A2 in Figure 4), the calculation unit 150 sets the timer reference voltage Vref as the timer charging start lower limit voltage Vll, as shown in Figures 3(c) and 3(d). Then, at time t1 when the COMP timer set signal is received, the COMP timer voltage Vct starts rising from the timer reference voltage Vref. Also, the timer capacitor charge / discharge current control unit 140 outputs a gate control signal Vg to the gate electrode of the switch element Q, turning on the gate voltage Vg of the switch element Q (see Vg in Figure 3(c)). At time t2, the COMP timer voltage Vct intersects with the COMP voltage Vcomp near the timer charging upper limit voltage Vmax. At this timing, the gate voltage Vg of the switch element Q is turned off. Therefore, the ON period of the switch element Q is the period between time t1 and t2.

[0057] Furthermore, when the timer charging start lower limit voltage calculated by the calculation unit 150 exceeds a predetermined timer reference voltage Vref, the timer capacitor charge / discharge current control unit 140 sets the timer reference voltage Vref as the timer charging start lower limit voltage. Consequently, the waveform is the same as that shown in Figure 3(c).

[0058] (2) Near the midpoint between the AC peak voltage and the AC trough voltage When the AC input voltage is near the midpoint between the AC peak voltage and the AC trough voltage, the calculation unit 150 sets a predetermined voltage V4 as the timer charging start lower limit voltage, as shown in Figures 3(b) and 3(d). Voltage V4 is a voltage lower than the timer reference voltage Vref.

[0059] When the COMP timer set signal is received at time t3, the COMP timer voltage Vct starts rising from the timer charging start lower limit voltage (voltage V4). Also, the timer capacitor charge / discharge current control unit 140 outputs a signal to the gate electrode of the switch element Q to turn on the switch element Q, turning on the gate voltage Vg (see the waveform of Vg in Figure 3(b)). At time t4, when the COMP voltage Vcomp reaches the timer reference voltage Vref, the rate of increase (slope) of the COMP voltage increases. At time t5, the gate voltage Vg of the switch element Q is turned off at the timing when the COMP timer voltage Vct intersects with the COMP voltage Vcomp near the timer charging upper limit voltage Vmax. Note that the waveform from time t4 to time t5 is the same as the waveform from time t1 to time t2 in Figure 3(c).

[0060] Therefore, the ON period of the switch element Q is the period between time t3 and t5. The period from time t4 to time t5 is the same as the period from time t1 to time t2 near the AC peak voltage (Figure 3(c)), so the ON period (ON width) is longer than in the case near the AC peak voltage by the amount of the period from time t3 to time t4.

[0061] (3) When the AC input voltage is near the AC trough voltage, the calculation unit 150 sets a predetermined voltage V1 as the timer charging start lower limit voltage, as shown in Figures 3(a) and 3(d). Voltage V1 is lower than the timer reference voltage Vref and voltage V4.

[0062] At time t6, when the COMP timer set signal is received, the COMP timer voltage Vct begins to rise from the timer charging start lower limit voltage (voltage V1). The slope at this time is smaller than the slope between times t1 and t2 when the voltage is near the AC peak voltage. The timer capacitor charge / discharge current control unit 140 also outputs a signal to the gate electrode of the switch element Q to turn on the switch element Q, turning on the gate voltage Vg (see Vg in Figure 3(a)). At time t7, when the COMP voltage Vcomp reaches a predetermined voltage V2, the rate of increase (slope) of the COMP voltage is increased and it continues to rise (see time t7 in Figure 3(a)). The slope at this time is smaller than the slope of the COMP voltage between times t1 and t2 when the voltage is near the AC peak voltage, and larger than the slope of the COMP voltage between times t6 and t7. At time t8, when the COMP voltage Vcomp reaches a predetermined voltage V3, the rate of increase (slope) of the COMP voltage is further changed and it continues to rise. The slope at this time is smaller than the slope of the COMP voltage at times t1 to t2 when the voltage is near the AC peak, and larger than the slope of the COMP voltage at times t7 to t8. When the COMP voltage Vcomp reaches the timer reference voltage Vref at time t9, the rate of increase (slope) of the COMP voltage increases. The slope at this time is the same as the slope of the COMP voltage at times t1 to t2 when the voltage is near the AC peak. At time t10, the gate voltage Vg of the switch element Q is turned off at the timing when the COMP timer voltage Vct intersects with the COMP voltage Vcomp near the timer charge upper limit voltage Vmax. Note that the waveform at times t9 to t10 is the same as the waveform at times t1 to t2 in Figure 3(c).

[0063] Therefore, the ON period of the switch element Q is the period between time t6 and t10. The period from time t9 to time t10 is the same as the period from time t1 to time t2 near the AC peak voltage (Figure 3(c)), so the ON period (ON width) is longer from time t6 to t9 than in the case near the AC peak voltage.

[0064] Thus, the control circuit 100 and switching power supply 1 according to this embodiment have an ON width that increases as they approach the AC trough voltage, compared to the ON width near the AC peak voltage.

[0065] 4. Waveforms and THD of the Switching Power Supply According to the Embodiment Next, the THD of the switching power supply according to the embodiment will be described using the switching power supplies according to the comparative example and the embodiment. The switching power supply according to the comparative example has the same configuration as the switching power supply according to the background art. The switching power supply according to the embodiment has the same configuration as the switching power supply according to the embodiment.

[0066] Figure 4 is a graph showing the input current Iin, the drain current ID of the switch element, the COMP timer voltage Vct, and the ON period (ON width) of the switch element Q in the example and comparative example. Figure 4(a) is a graph showing the input current Iin, etc. in the example, and Figure 4(b) is a graph showing the input current Iin, etc. in the comparative example. In Figures 4(a) and 4(b), the area enclosed by the dashed line A2 corresponds to the region near the AC peak voltage, and the area enclosed by the dashed line A1 corresponds to the region near the AC trough voltage.

[0067] Here, for both the comparative example and the embodiment, the input current Iin, the drain current ID of the switch element, the COMP timer voltage Vct, and the on-period (on-width) of the switch element Q were calculated at predetermined time intervals by simulation when the AC input power supply was 240V and the output power Po = 140W, and the waveforms were obtained by plotting them.

[0068] (1) Comparative Example As shown in Figure 4(b), in the comparative example, the ON width is approximately constant. Also, the input current Iin, the drain current ID of the switch element, and the COMP timer voltage Vct repeatedly increase and decrease. Focusing on the vicinity of the AC trough voltage (the area enclosed by the dashed line A1), the amplitude of the drain current ID is considerably small. Furthermore, the input current Iin has a period of zero current value for a predetermined period, and since distortion has occurred from the sine wave, it can be seen that the THD has worsened (increased).

[0069] (2) Example As shown in Figure 4(a), in this example, the ON width is large near the AC trough voltage (see the waveform of "ON width" in Figure 4(b)). Focusing on the area near the AC trough voltage (the region enclosed by the dashed line A1), the amplitude of the drain current ID is larger compared to the comparative example. In addition, the input current Iin has almost no period where the current value is zero, and although there is some fluctuation, it has a waveform similar to a sine wave, indicating that the THD is improved (decreased).

[0070] Therefore, it was confirmed that THD is improved by increasing the ON width near the AC valley voltage, as in the example.

[0071] Next, we will explain the THD when the output power is changed in the comparative example and the example. Figure 5 is a graph showing the relationship between output power and THD in the comparative example and the example. Figure 5(a) is a graph showing the relationship between output power and THD when the AC input power is 100V, and Figure 5(b) is a graph showing the relationship between output power and THD when the AC input power is 240V.

[0072] Here, for comparative examples and examples where the AC input power supply is 100V and 240V, the THD was calculated by computer simulation for each predetermined output power between 50W and 200W, and plotted accordingly.

[0073] (1) When the AC input power supply is 100V (AC100V), as shown in Figure 5(a), in the comparative example, when the power Po was 50W, the THD was approximately 12.03%, when the power Po was 70W, the THD was approximately 10.1%, when the power Po was 90W, the THD was approximately 9.11%, when the power Po was 140W, the THD was approximately 7.68%, and when the power Po was 180W, the THD was approximately 7.72%.

[0074] In contrast, in the examples, the THD was approximately 6.48% when the power Po was 50W, approximately 6.09% when the power Po was 70W, approximately 5.96% when the power Po was 90W, approximately 5.79% when the power Po was 140W, and approximately 6.01% when the power Po was 180W.

[0075] Therefore, it was found that, with an AC input power supply of 100V, the THD of the embodiment was lower than that of the comparative example at all output power levels. Thus, it was found that the THD was significantly improved in the range from light load to heavy load.

[0076] (2) When the AC input power supply is 240V (AC240V), as shown in Figure 5(b), in the comparative example, when the power Po was 50W, the THD was approximately 20.38%, when the power Po was 70W, the THD was approximately 16.44%, when the power Po was 90W, the THD was approximately 14.63%, when the power Po was approximately 140W, the THD was approximately 14.00%, and when the power Po was 180W, the THD was approximately 13.64%.

[0077] In contrast, in the example, the THD was approximately 12.38% when the power Po was 50W, approximately 6.84% when the power Po was 70W, approximately 5.43% when the power Po was 90W, approximately 4.73% when the power Po was 140W, and approximately 5.21% when the power Po was 180W.

[0078] Therefore, it was found that even with an AC input power supply of 240V, the THD of the embodiment was lower than that of the comparative example at all output power levels. Thus, it was found that the THD was greatly improved in the range from light load to heavy load.

[0079] From this, it was confirmed that the embodiment showed improved THD compared to the comparative example in both the case of an AC input voltage of 100V and 240V. Therefore, it was found that the embodiment showed improved THD compared to the comparative example at all AC input voltages, regardless of the magnitude of the AC input voltage.

[0080] 5. Effects of the Control Circuit 100 and Switching Power Supply 1 According to the control circuit 100 and switching power supply 1 according to the embodiment, since the timer charging start lower limit voltage Vll is adjusted based on the AC input voltage, the ON period can be made longer in the vicinity of the AC trough voltage (see the area enclosed by the dashed line A1 in Figure 4), where there is a risk that the input current will stop flowing due to distortion, and the current flowing through the switch element Q can be made larger. Therefore, since the input current in the vicinity of the AC trough voltage can be made relatively large, it is possible to prevent the input current from stopping in the vicinity of the AC trough voltage, and it is possible to prevent a decrease in the power factor and a deterioration of THD (Total Harmonic Distortion).

[0081] Furthermore, according to the control circuit 100 and switching power supply 1 of the embodiment, the timer charging start lower limit voltage Vll is adjusted based on the AC input voltage, so the on period can be made longer near the AC trough voltage, and the current flowing through the switching element Q can be made larger. Therefore, even if a negative switching current flows due to the resonant operation during switching, the ratio of the negative switching current to the current flowing through the switching element Q becomes relatively small. As a result, in this respect as well, it is possible to prevent the input current from ceasing to flow near the AC trough voltage, and to prevent a decrease in the power factor and a deterioration of THD (Total Harmonic Distortion).

[0082] Furthermore, according to the control circuit 100 of the embodiment, the timer capacitor charge / discharge current control unit 140 controls the COMP voltage Vcomp by controlling the charging current and discharge current to the timer capacitor 120, and outputs a signal to raise the COMP timer voltage Vct from the timer charging start lower limit voltage and turn on the switch element Q when a COMP timer set signal is input from the calculation unit 150, and outputs a signal to turn off the switch element Q when the COMP timer voltage Vct reaches the COMP voltage Vcomp, and the calculation unit 150 adjusts the timer charging start lower limit voltage of the timer capacitor 120 based on the AC input voltage and outputs a COMP timer set signal to the timer capacitor charge / discharge current control unit 140, so that the timer charging start lower limit voltage of the timer capacitor 120 can be adjusted and the ON width of the switch element Q can be adjusted according to the AC input voltage. As a result, it is possible to prevent distortion near the AC trough voltage from becoming large, and in practice, it is possible to prevent a decrease in the power factor and a deterioration in THD (Total Harmonic Distortion).

[0083] Furthermore, according to the control circuit 100 of this embodiment, when the timer charging start lower limit voltage calculated by the calculation unit 150 exceeds a predetermined timer reference voltage Vref, the timer capacitor charge / discharge current control unit 140 sets the timer reference voltage Vref as the timer charging start lower limit voltage. In this case, near the AC peak voltage, the ON width of the switch element Q is set to the same ON width as in the conventional case, which prevents the current flowing through the switch element Q from becoming too large and prevents a decrease in power factor and deterioration of THD.

[0084] Furthermore, according to the control circuit 100 of the embodiment, the timer capacitor charge / discharge current control unit 140 controls the charging current to the timer capacitor 120 such that the charging speed to the timer capacitor 120 decreases as the COMP timer voltage Vct decreases in the region where the COMP timer voltage Vct is lower than the timer reference voltage Vref. As a result, the timer capacitor 120 is charged slowly near the AC trough voltage where the input current of the AC input voltage is small, and the ON width of the switch element Q can be increased. Consequently, even when the AC input current is small, it is possible to prevent the input current from dropping to near zero near the AC trough voltage and to prevent the distortion of the input current near the AC trough voltage from increasing.

[0085] Furthermore, in the control circuit 100 according to this embodiment, when the COMP timer voltage Vct exceeds a predetermined timer reference voltage Vref, the charging current for charging the timer capacitor 120 is a constant current value. Therefore, conventional power factor correction can be performed near the AC peak voltage, and the timer capacitor 120 can be controlled relatively easily.

[0086] Furthermore, according to the control circuit 100 of this embodiment, the calculation unit 150 performs calculation processing on the AC input detection signal obtained based on the AC input voltage to obtain the timer charging start lower limit voltage, so that the timer charging start lower limit voltage can be controlled in accordance with fluctuations in the AC input current. Accordingly, the ON width of the switch element can be adjusted to appropriately reflect fluctuations in the AC input current.

[0087] Furthermore, according to the control circuit 100 of the embodiment, the calculation unit 150 calculates the timer charging start lower limit voltage so that when the AC input voltage is in a trough, the timer charging start lower limit voltage falls below a predetermined timer reference voltage. This prevents the input current near the AC trough voltage, where distortion occurs, the power factor decreases, and THD tends to worsen, from becoming zero.

[0088] Although the present invention has been described above based on the embodiments described above, the present invention is not limited to the embodiments described above. It can be implemented in various forms without departing from the spirit of the invention, and for example, the following modifications are also possible.

[0089] (1) The positions, connections, number, circuit configuration, terminals, etc. described in the above embodiments (including each modified example; the same applies hereinafter) are illustrative examples and can be changed within the scope that does not impair the effects of the present invention.

[0090] (2) In the above embodiment, when the timer charging start lower limit voltage calculated by the calculation unit 150 exceeds a predetermined timer reference voltage, the timer capacitor charge / discharge current control unit 140 sets the timer reference voltage Vref as the timer charging start lower limit voltage. However, the present invention is not limited thereto. The charging current may be increased in accordance with the rise in the COMP timer voltage. In this case, power factor reduction prevention and THD improvement can be performed more appropriately even near the AC peak voltage.

[0091] (3) In the above embodiment, when the timer reference voltage Vref is exceeded, a COMP timer voltage Vct showing a monotonically increasing waveform is used, but the present invention is not limited thereto. Similar to the COMP timer voltage in the switching power supply 9 of the background art, a COMP timer voltage Vct showing a waveform in which rapid charging is performed in the first half and then normal charging is performed after a predetermined time may be used, or a COMP timer voltage Vct showing any other appropriate waveform may be used.

[0092] (4) In the above embodiment, the critical point of the input current was detected by detecting the inductor current of inductor L3 using inductor L4 which is positioned opposite inductor L3, but the present invention is not limited thereto. The critical point of the input current may also be detected by detecting the zero voltage point from the drain voltage of the switch element.

[0093] 1…Switching power supply, 10…Rectifier circuit, 20…Power conversion circuit (power factor correction circuit), 110, 910…Feedback control unit, 112, 912…Error amplifier, 120, 920…Timer capacitor, 130, 930…Comparator, 140, 940…Timer capacitor charge / discharge current control unit, 150…Calculation unit

Claims

1. A control circuit for controlling a switching element of a switching power supply having a switching element, comprising: a timer capacitor to which a COMP timer voltage is applied that exhibits a waveform that starts rising from a predetermined timer charging start lower limit voltage and decreases to the timer charging start lower limit voltage after a predetermined time has elapsed; the control circuit is characterized by turning on the switching element when the COMP timer voltage starts rising from the timer charging start lower limit voltage, turning off the switching element when the COMP timer voltage reaches an error voltage generated based on the difference between a feedback voltage corresponding to the output voltage of the switching power supply and a reference voltage of an error amplifier, and adjusting the timer charging start lower limit voltage to control the on period of the switching element.

2. The system further comprises a feedback control unit, a comparator, a timer capacitor charge / discharge current control unit, and a calculation unit, wherein the feedback control unit generates the error voltage based on the difference between the feedback voltage corresponding to the output voltage of the switching power supply and the reference voltage of the error amplifier, and outputs the error voltage to the first input terminal of the comparator, the timer capacitor is connected on one end to the second input terminal of the comparator and the timer capacitor charge / discharge current control unit, and on the other end to the calculation unit, the comparator compares the COMP timer voltage with the error voltage and outputs a COMP timer reset signal to the timer capacitor charge / discharge current control unit when the COMP timer voltage reaches the error voltage, the timer capacitor charge / discharge current control unit controls the COMP timer voltage by controlling the charging current and discharging current to the timer capacitor, and outputs a signal to turn on the switch element when a COMP timer set signal is input from the calculation unit, and outputs a signal to turn off the switch element when the COMP timer voltage reaches the error voltage. The control circuit according to claim 1, characterized in that the calculation unit calculates the timer charging start lower limit voltage of the timer capacitor based on the AC input voltage and outputs the COMP timer set signal to the timer capacitor charge / discharge current control unit.

3. The control circuit according to claim 2, characterized in that when the calculated value of the timer charging start lower limit voltage calculated by the calculation unit exceeds a predetermined timer reference voltage, the timer reference voltage is set to the timer charging start lower limit voltage.

4. The control circuit according to claim 2 or 3, characterized in that when the COMP timer voltage falls below a predetermined timer reference voltage, the timer capacitor charge / discharge current control unit reduces the charging current for charging the timer capacitor as the COMP timer voltage decreases.

5. The control circuit according to any one of 2 to 4, characterized in that the timer capacitor charge / discharge current control unit sets the charging current for charging the timer capacitor to a constant current value when the COMP timer voltage exceeds a predetermined timer reference voltage.

6. The control circuit according to any one of claims 2 to 4, characterized in that when the COMP timer voltage exceeds a predetermined timer reference voltage, the timer capacitor charge / discharge current control unit increases the charging current for charging the timer capacitor as the COMP timer voltage increases.

7. The control circuit according to any one of 2 to 6, characterized in that the calculation unit performs calculation processing on the AC input detection signal obtained based on the AC input voltage to obtain the timer charging start lower limit voltage.

8. The control circuit according to any one of 2 to 7, characterized in that the calculation unit calculates the timer charging start lower limit voltage such that when the AC input voltage is in a dip, the timer charging start lower limit voltage falls below a predetermined timer reference voltage.

9. A switching power supply comprising a rectifier circuit having a filter circuit, a DC conversion circuit having a switch element, and a control circuit according to any one of claims 1 to 8 for controlling the switching operation of the switch element.

10. The switching power supply according to claim 9, characterized in that the control circuit is connected to the preceding stage of the filter circuit in the rectifier circuit.

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