Etching method and plasma processing device

Abstract

In one exemplary embodiment, an etching method includes: (a) a step for providing a substrate on a substrate support in a chamber, the substrate including a first region and a second region, the first region including a first material which contains nitrogen and silicon, the second region including a second material which differs from the first material; (b) a step for exposing the substrate to a first processing gas which contains a hydrogen fluoride gas; and (c) a step for, after the step (b), exposing the substrate to plasma that has been generated from a second processing gas which contains an inert gas, the plasma containing ions of the inert gas.

Description

Etching method and plasma processing apparatus

[0001] Exemplary embodiments of this disclosure relate to etching methods and plasma processing apparatus.

[0002] Patent Document 1 discloses a method for selectively etching a silicon nitride film containing nitrogen and silicon. In this method, an etching gas is supplied into a processing chamber while the processing gas is exhausted, setting the pressure inside the processing chamber to 40.0 Pa or higher (300 mTorr or higher). Then, microwaves are introduced into the processing chamber through a dielectric window at the top of the processing chamber to generate plasma inside the processing chamber. The silicon nitride film is then selectively etched in a non-biased state, without applying RF (radio frequency) to the mounting stage on which the substrate is placed inside the processing chamber.

[0003] Japanese Patent Publication No. 2014-060413

[0004] This disclosure provides an etching method and a plasma processing apparatus for selectively etching regions containing nitrogen and silicon.

[0005] In one exemplary embodiment, the etching method includes the steps of (a) providing a substrate on a substrate support in a chamber, wherein the substrate comprises a first region and a second region, the first region comprising a first material comprising nitrogen and silicon, and the second region comprising a second material different from the first material; (b) exposing the substrate to a first treatment gas comprising hydrogen fluoride gas; and (c) after (b), exposing the substrate to a plasma generated from a second treatment gas comprising an inert gas, wherein the plasma comprises ions of the inert gas.

[0006] According to one exemplary embodiment, regions containing nitrogen and silicon can be selectively etched.

[0007] Figure 1 is a schematic diagram showing a plasma processing apparatus according to one exemplary embodiment. Figure 2 is a schematic diagram showing a plasma processing apparatus according to one exemplary embodiment. Figure 3 is a flowchart of an etching method according to one exemplary embodiment. Figure 4 is a cross-sectional view of an example substrate to which the method of Figure 3 may be applied. Figure 5 is a cross-sectional view showing one step of the etching method according to one exemplary embodiment. Figure 6 is a cross-sectional view showing one step of the etching method according to one exemplary embodiment. Figure 7 is a cross-sectional view showing one step of the etching method according to one exemplary embodiment. Figure 8 is a cross-sectional view showing one step of the etching method when an electrical bias is supplied to the upper electrode. Figure 9(a) is a partially enlarged view of another example substrate to which the method of Figure 3 may be applied before etching. Figure 9(b) is a partially enlarged view of another example substrate to which the method of Figure 3 may be applied after etching. Figure 10(a) is a partially enlarged view of another example substrate to which the method of Figure 3 may be applied before etching. Figure 10(b) is a partially enlarged view of another example substrate to which the method of Figure 3 may be applied after etching. Figure 11(a) is a partially enlarged view of a substrate before etching, representing yet another example to which the method of Figure 3 may be applied. Figure 11(b) is a partially enlarged view of a substrate after etching, representing yet another example to which the method of Figure 3 may be applied. Figure 12(a) is a partially enlarged view of a substrate before etching, representing yet another example to which the method of Figure 3 may be applied. Figure 12(b) is a partially enlarged view of a substrate after etching, representing yet another example to which the method of Figure 3 may be applied. Figure 13(a) is a partially enlarged view of a substrate before etching, representing yet another example to which the method of Figure 3 may be applied. Figure 13(b) is a partially enlarged view of a substrate after etching, representing yet another example to which the method of Figure 3 may be applied. Figure 14(a) is a partially enlarged view of a substrate before etching, representing yet another example to which the method of Figure 3 may be applied. Figure 14(b) is a partially enlarged view of a substrate after etching, representing yet another example to which the method of Figure 3 may be applied. Figure 15(a) is a partially enlarged view of a substrate before etching, representing yet another example to which the method of Figure 3 may be applied. Figure 15(b) is a magnified partial view of a substrate after etching, representing yet another example to which the method of Figure 3 may be applied. Figure 16(a) is a magnified partial view of a substrate before etching, representing yet another example to which the method of Figure 3 may be applied.Figure 16(b) is a partially enlarged view of a substrate after etching, representing yet another example to which the method of Figure 3 may be applied. Figure 17 is a flowchart of the etching method according to another exemplary embodiment. Figure 18 shows the results of the first experiment. Figure 19 shows the results of the second experiment.

[0008] Various exemplary embodiments will be described in detail below with reference to the drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals.

[0009] Figure 1 is a diagram illustrating an example configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support unit 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space, and at least one gas outlet for discharging gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20, which will be described later, and the gas outlet is connected to an exhaust system 40, which will be described later. The substrate support unit 11 is located in the plasma processing space and has a substrate support surface for supporting a substrate.

[0010] The plasma generation unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), ECR (Electron Cyclotron Resonance) plasma, helicon wave excited plasma (HWP), or surface wave plasma (SWP), etc. Various types of plasma generation units, including AC (Alternating Current) plasma generation units and DC (Direct Current) plasma generation units, may also be used. In one embodiment, the AC signal (AC power) used in the AC plasma generation unit has a frequency in the range of 100 kHz to 10 GHz. Therefore, the AC signal includes an RF (Radio Frequency) signal and a microwave signal. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0011] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various processes described herein. The control unit 2 may be configured to control the elements of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 is implemented, for example, by a computer 2a. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The functions realized by the processing unit 2a1 described herein may be implemented in a circuit or processing circuit, including a general-purpose processor, an application-specific processor, integrated circuits, ASICs (Application Specific Integrated Circuits), a CPU (Central Processing Unit), a conventional circuit, and / or a combination thereof, programmed to realize the described functions. The processor is considered to be a circuit or processing circuit, including transistors and other circuits. The processor may be a programmed processor that executes a program stored in the storage unit 2a2. This program may be pre-stored in the storage unit 2a2 or retrieved via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a, or it may be a communication line connected to the communication interface 2a3. The storage unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing device 1 via a communication line such as a LAN (Local Area Network).In this disclosure, circuits, units, and means are hardware programmed to perform or configured to perform the functions described. Such hardware may be any hardware described in this disclosure, or any hardware known to be programmed to perform or execute the functions described. If such hardware is a processor that is considered to be a type of circuit, such circuit, means, or unit is a combination of hardware and software used to constitute such hardware and / or processor.

[0012] The following describes an example configuration of a capacitively coupled plasma processing apparatus as an example of a plasma processing apparatus 1. Figure 2 is a diagram illustrating an example configuration of a capacitively coupled plasma processing apparatus.

[0013] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply system 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support unit 11 and a gas introduction unit. The gas introduction unit is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas introduction unit includes a shower head 13. The substrate support unit 11 is located inside the plasma processing chamber 10. The shower head 13 is located above the substrate support unit 11. In one embodiment, the shower head 13 constitutes at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the shower head 13, the side walls 10a of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 is grounded. The shower head 13 and the substrate support unit 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0014] The substrate support portion 11 includes a main body portion 111 and a ring assembly 112. The main body portion 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 in a plan view. The substrate W is placed on the central region 111a of the main body portion 111, and the ring assembly 112 is placed on the annular region 111b of the main body portion 111 so as to surround the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also called the substrate support surface for supporting the substrate W, and the annular region 111b is also called the ring support surface for supporting the ring assembly 112.

[0015] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is placed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic chuck electrode 1111b placed within the ceramic member 1111a. The electrostatic chuck electrode 1111b is also called a clamping electrode. In one embodiment, the electrostatic chuck electrode 1111b is electrically connected or coupled to a chuck power supply. The chuck power supply may be a DC power supply or an AC power supply. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Furthermore, other members surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have an annular region 111b. In this case, the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or it may be placed on both the electrostatic chuck 1111 and the annular insulating member. In addition, at least one bias electrode, which is electrically connected or coupled to the power supply 31 and / or power supply 32 described later, may be placed inside the ceramic member 1111a. In this case, at least one bias electrode functions as a lower electrode. Also, the conductive member of the base 1110 and the bias electrode inside the ceramic member 1111a may function as multiple lower electrodes. In one embodiment, the first voltage generation unit 32a, which functions as a voltage pulse generation unit described later, is electrically connected or coupled to the bias electrode inside the ceramic member 1111a, and the first RF generation unit 31a, described later, is electrically connected or coupled to the conductive member of the base 1110. Furthermore, the electrostatic chuck electrode 1111b may function as a lower electrode. Therefore, the substrate support portion 11 includes at least one lower electrode.

[0016] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one covering ring. The edge rings are formed of a conductive or insulating material, and the covering rings are formed of an insulating material.

[0017] The substrate support section 11 may also include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid such as brine or gas flows through the flow path 1110a. In one embodiment, the flow path 1110a is formed within the base 1110, and one or more heaters are arranged within the ceramic member 1111a of the electrostatic chuck 1111. The substrate support section 11 may also include a heat transfer gas supply section configured to supply heat transfer gas to the gap between the back surface of the substrate W and the central region 111a.

[0018] The showerhead 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas inlet ports 13c. The processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s through the plurality of gas inlet ports 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas introduction unit may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the side wall 10a.

[0019] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one processing gas to the shower head 13 from a corresponding gas source 21 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of at least one processing gas.

[0020] The power supply system 30 includes a power supply 31 that is electrically connected to or coupled to the plasma processing chamber 10. In one embodiment, the power supply 31 is electrically connected to or coupled to the plasma processing chamber 10 via at least one impedance matcher. The impedance matcher may be a mechanically controlled matcher or an electronically controlled matcher. The power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the power supply 31 can function as at least part of the plasma generation unit 12. In addition, by supplying a bias RF signal to at least one lower electrode, a bias potential is generated on the substrate W, and ionic components in the formed plasma can be drawn into the substrate W.

[0021] The power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is electrically connected or coupled to at least one lower electrode and / or at least one upper electrode and is configured to generate a source RF signal (source RF power) to generate plasma in the plasma processing space 10s. In one embodiment, the first RF generation unit 31a is electrically connected or coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matcher. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generation unit 31a may be configured to generate a plurality of source RF signals having different frequencies. One or more generated source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0022] The second RF generation unit 31b is electrically connected to or coupled to at least one lower electrode and is configured to generate a bias RF signal (bias RF power). In one embodiment, the second RF generation unit 31b is electrically connected to or coupled to at least one lower electrode via at least one impedance matcher. When the first RF generation unit 31a is electrically connected to or coupled to a lower electrode, the second RF generation unit 31b may be electrically connected to or coupled to the same lower electrode, or it may be electrically connected to or coupled to a different lower electrode. The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generation unit 31b may be configured to generate a plurality of bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0023] The power supply system 30 may also include a power supply 32 that is electrically connected to or coupled to the plasma processing chamber 10. The power supply 32 includes a first voltage generation unit 32a and a second voltage generation unit 32b. In one embodiment, the first voltage generation unit 32a is electrically connected to or coupled to at least one lower electrode and is configured to generate a first voltage signal. The generated first voltage signal is applied to at least one lower electrode. In one embodiment, the second voltage generation unit 32b is electrically connected to or coupled to at least one upper electrode and is configured to generate a second voltage signal. The generated second voltage signal is applied to at least one upper electrode.

[0024] In various embodiments, the first and / or second voltage signals may be pulsed. In this case, the first voltage generation unit 32a and / or the second voltage generation unit 32b function as voltage pulse generation units configured to generate a sequence of voltage pulses. Thus, the sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. In one embodiment, the sequence of voltage pulses has a plurality of cycles, each cycle including a burst of voltage pulses in a first period and a constant reference voltage in a second period. That is, in the sequence of voltage pulses, the burst of voltage pulses is repeated. The absolute value of the voltage level of the voltage pulse is greater than the absolute value of the voltage level of the reference voltage. The voltage pulse may have an arbitrary waveform having a rectangle, trapezoid, triangle, or a combination thereof, and the arbitrary waveform may change over time. The voltage pulse may have positive polarity or negative polarity. The sequence of voltage pulses may also include one or more positive voltage pulses and one or more negative voltage pulses within one cycle. The first and second voltage generation units 32a and 32b may be provided in addition to the power supply 31, and the first voltage generation unit 32a may be provided in place of the second RF generation unit 31b.

[0025] The exhaust system 40 may be connected to, for example, a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0026] Figure 3 is a flowchart of an etching method according to one exemplary embodiment. The etching method shown in Figure 3 (hereinafter referred to as "Method MT1") can be performed by the plasma processing apparatus 1 of the above embodiment. Method MT1 can be applied to the substrate W shown in Figure 4.

[0027] Figure 4 is a cross-sectional view of an example substrate to which the method of Figure 3 may be applied. As shown in Figure 4, in one embodiment, the substrate W1 includes a first region R1 and a second region R2. As shown in Figure 4, the first region R1 and the second region R2 may be arranged adjacent to each other. In this case, the surface positions of the first region R1 and the surface positions of the second region R2 may be at the same height. That is, the surface of the first region R1 and the surface of the second region R2 may be flush. A base layer may be provided below each of the first region R1 and the second region R2. In this embodiment, in the substrate W1, the first region R1 is the region to be etched, and the second region R2 is the region not to be etched.

[0028] The first region R1 contains the first material. The first material contains nitrogen and silicon. The first material is silicon nitride (SiN ｘ The material may include at least one material selected from the group consisting of silicon oxynitride (SiON) and silicon carbonitride (SiCN). x is a positive real number. In this embodiment, the first material is described as including silicon nitride.

[0029] The second region R2 includes a second material. The second material is different from the first material. The second material may include silicon, germanium, or a High-k material. The second material is silicon oxide (SiO ｘ The second material may include at least one material selected from the group consisting of polysilicon, amorphous silicon, silicon germanium (SiGe), germanium (Ge), and High-k materials. x is a positive real number. The second material may include, as a High-k material, tungsten carbide (WC), tungsten (W), tungsten monoxide (WO), titanium dioxide (TiO ２ ), titanium nitride (TiN), hafnium (Hf), hafnium monoxide (HfO), tantalum (Ta), tantalum nitride (TaN), and tantalum dioxide (TaO ２ The second material may include at least one material selected from the group consisting of ). The second material may contain carbon. The second material may be at least one carbon-containing material selected from the group consisting of photoresist (polymer) and amorphous carbon.

[0030] Hereinafter, regarding the method MT1, taking the case where the method MT1 is applied to the substrate W1 using the plasma processing apparatus 1 of the above embodiment as an example, it will be described with reference to FIGS. 3 to 7. FIGS. 5 to 7 are cross-sectional views showing one step of an etching method according to one exemplary embodiment. When the plasma processing apparatus 1 is used, the method MT1 can be executed in the plasma processing apparatus 1 by controlling each part of the plasma processing apparatus 1 by the control unit 2. In the method MT1, as shown in FIG. 2, the substrate W1 on the substrate support portion 11 disposed in the plasma processing chamber 10 is processed.

[0031] As shown in FIG. 3, the method MT1 may include steps ST1 to ST5. The steps ST1 to ST5 may be executed in order. The method MT1 may not include the step ST3 or may not include the step ST5.

[0032] (Step ST1) In the step ST1, the substrate W1 shown in FIG. 4 is provided on the substrate support portion 11 in the plasma processing chamber 10.

[0033] (Step ST2) In the step ST2, the substrate W1 is exposed to a first processing gas containing hydrogen fluoride (HF) gas. In the step ST2, plasma may not be generated from the first processing gas. The supply of the first processing gas may be stopped at the end of the step ST2. In the step ST2, as shown in FIG. 5, hydrogen fluoride molecules are adsorbed on the surface of the first region R1 to form an adsorption layer AB. The adsorption layer AB may contain hydrogen fluoride. The adsorption layer AB may be a layer formed by the reaction between hydrogen fluoride and the first region R1. When the first material contains silicon nitride, the adsorption layer AB may contain ammonium fluorosilicate formed by the reaction between silicon nitride and hydrogen fluoride. The hydrogen fluoride molecules may selectively adsorb on the surface of the first region R1 and may not adsorb on the surface of the second region R2. In this case, the adsorption layer AB is not formed on the surface of the second region R2. The thickness of the adsorption layer AB may increase with the passage of time and may saturate at a certain value.

[0034] The first processing gas includes, in addition to hydrogen fluoride gas, alcohols such as methanol (CH ３ OH) and acetic acid (CH３ It may contain at least one selected from the group consisting of carboxylic acids such as COOH). The first treatment gas is propanol (C ３ H ７ OH), butanol (C ４ H ９ OH), or pentanol (C ５ H １１ OH), etc. The first treatment gas may contain an alcohol. The first treatment gas is formic acid (HCOOH), propionic acid (C ２ H ５ COOH), or butyric acid (C ３ H ７ COOH), etc. The first treatment gas may further contain at least one inert gas selected from the group consisting of noble gases and nitrogen (N ２ ). The noble gas may contain at least one gas selected from the group consisting of argon (Ar) gas, helium (He) gas, xenon (Xe) gas, and neon (Ne) gas. Among the flow rates of all the gases contained in the first treatment gas, the flow rate of hydrogen fluoride gas may be the largest. The inert gas that may be contained in the first treatment gas may be the same as or different from the inert gas contained in the second treatment gas in step ST4. The first treatment gas may not contain a fluorine-containing gas other than hydrogen fluoride gas.

[0035] The duration of step ST2 may be 0.1 to 200 seconds, or may be 30 to 80 seconds.

[0036] In step ST2, the temperature of the substrate support portion 11 may be controlled within the range of 20°C to 100°C, or may be controlled within the range of 40°C to 70°C. The temperature of the substrate support portion 11 may be controlled to 60°C. In the range of 20°C to 100°C, hydrogen fluoride molecules are likely to adsorb to the first region R1 containing nitrogen and silicon. For example, hydrogen fluoride molecules are more likely to adsorb to silicon nitride than to other substances in the range of 20°C to 100°C. Other substances are, for example, silicon oxide, polysilicon, single crystal silicon, photoresist, etc.

[0037] In step ST2, the pressure inside the plasma processing chamber 10 may be 100 mT (13 Pa) or higher. Alternatively, the pressure inside the plasma processing chamber 10 may be 1000 mT (130 Pa) or lower. The pressure inside the plasma processing chamber 10 may be 300 mT (39 Pa) or higher, or 800 mT (104 Pa) or lower.

[0038] Step ST2 may be carried out as follows: The gas supply unit 20 supplies the first processing gas into the plasma processing chamber 10. The control unit 2 controls the gas supply unit 20 and the plasma generation unit 12 so that plasma is not generated.

[0039] (Step ST3) In step ST3, the internal space of the plasma processing chamber 10 is purged. Purging may be performed by supplying an inert gas into the plasma processing chamber 10, or by evacuating the internal space of the plasma processing chamber 10. Purging may be performed by supplying an inert gas and evacuating in combination. Step ST3 is not necessarily required.

[0040] (Step ST4) In step ST4, as shown in Figure 6, the substrate W1 is exposed to plasma PL generated from the second processing gas. The second processing gas may be different from the first processing gas in step ST2. The second processing gas may be a noble gas and nitrogen (N ２ The noble gas includes at least one inert gas selected from the group consisting of argon (Ar), helium (He), xenon (Xe), and neon (Ne). The flow rate of the inert gas may be the largest of all the flow rates of the gases included in the second processing gas. The second processing gas may also include a silicon-containing gas.

[0041] Plasma PL contains multiple ions IN of the inert gas. Plasma PL may further contain multiple radicals RD of the inert gas. For example, if the second processing gas contains argon gas, then multiple argon ions (Ar ＋ ) and multiple argon radicals may be generated.

[0042] In step ST4, an electrical bias may be supplied to the substrate support section 11. The electrical bias may be bias RF power. In this case, the level of the electrical bias is the power level (effective value) of the bias RF power. The level of the electrical bias may be 500W or less, 200W or less, or 100W or less.

[0043] The electrical bias may be a direct current (DC) voltage. The DC voltage may include voltage pulses. In this case, the level of the electrical bias is the absolute value of the voltage level of the voltage pulses. The level of the electrical bias may be 1 kV or less, 500 V or less, or 100 V or less.

[0044] The duration of process ST4 may be shorter than the duration of process ST2. The duration of process ST4 may be 1 / 3 or less of the duration of process ST2. The duration of process ST4 may be 0.1 to 100 seconds, or 0.1 to 20 seconds.

[0045] The temperature of the substrate support portion 11 in step ST4 may be controlled to be the same as the temperature of the substrate support portion 11 in step ST2. Alternatively, the temperature of the substrate support portion 11 in step ST4 may be controlled to be higher or lower than the temperature of the substrate support portion 11 in step ST2. In step ST4, the temperature of the substrate support portion 11 may be controlled to be in the range of 20°C to 200°C, or in the range of 50°C to 100°C.

[0046] The pressure inside the plasma processing chamber 10 in step ST4 may be lower than the pressure inside the plasma processing chamber 10 in step ST2. In step ST4, the pressure inside the plasma processing chamber 10 may be 10 mTorr (1.3 Pa) or higher. Alternatively, the pressure inside the plasma processing chamber 10 may be 100 mTorr (13 Pa) or lower.

[0047] Step ST4 may be carried out as follows: First, the gas supply unit 20 supplies the second processing gas into the plasma processing chamber 10. Next, the plasma generation unit 12 generates plasma PL from the second processing gas in the plasma processing chamber 10. The control unit 2 controls the gas supply unit 20 and the plasma generation unit 12 so that plasma PL is generated. The control unit 2 controls the power supply system 30 so that an electrical bias is supplied to the substrate support unit 11.

[0048] (Step ST5) Step ST5 is repeated, following steps ST2 to ST4. This increases the etching amount of the first region R1. In step ST5, control parameters such as the temperature of the substrate support 11, the pressure inside the plasma processing chamber 10, and the level of the electrical bias may be changed each time the process is repeated.

[0049] According to the etching method described above (Method MT1), in step ST2, hydrogen fluoride molecules contained in the first processing gas are selectively adsorbed onto the surface of the first region R1, forming an adsorption layer AB. In step ST4, the adsorption layer AB is removed by the energy of the ions IN of the inert gas, thereby etching the first region R1. Therefore, according to the etching method described above, regions containing nitrogen and silicon can be selectively etched.

[0050] In process ST4, etching of the first region R1 proceeds. The mechanism by which etching proceeds is presumed to be as follows, but is not limited to this: Ions IN or radicals RD in the plasma PL supply energy to the adsorption layer AB, causing the adsorption layer AB to volatilize.

[0051] In step ST4, an electrical bias may be supplied to the substrate support 11. In this case, as shown in Figure 6, the electrical bias causes multiple ions IN in the plasma PL to collide with the substrate W1. The collision energy of the multiple ions IN causes the adsorption layer AB formed on the surface of the first region R1 to volatilize. For example, if the adsorption layer AB contains ammonium fluorosilicate, the collision energy of the multiple ions IN causes the ammonium fluorosilicate to volatilize and the adsorption layer AB is removed. As a result, on the substrate W1, as shown in Figure 7, the position of the surface of the first region R1 may be lower than the position of the surface of the second region R2. That is, the first region R1 is selectively etched. In addition to the collision of multiple ions IN, multiple radicals RD may be supplied to the adsorption layer AB, and the energy of the multiple radicals RD may promote the removal of the adsorption layer AB.

[0052] In step ST2, the temperature of the substrate support portion 11 may be controlled to a range of 20°C to 100°C. In this case, within the range of 20°C to 100°C, hydrogen fluoride molecules exhibit a tendency to adsorb to the first region R1 containing nitrogen and silicon. This further promotes the reaction between the first material and hydrogen fluoride.

[0053] In step ST4 of method MT1, an electrical bias may be supplied to the upper electrode located above the substrate support portion 11 within the plasma processing chamber 10. Figure 8 is a cross-sectional view showing step ST4 when an electrical bias is supplied to the upper electrode. Figure 8 shows a shower head 13 located above the substrate W1. In the example of Figure 8, the case where the shower head 13 is the upper electrode will be explained. The upper electrode may be provided on the surface of the shower head 13 that faces the plasma processing space 10s.

[0054] In step ST4, etching of the first region R1 proceeds even when an electrical bias is supplied to the upper electrode. The mechanism by which etching proceeds is presumed to be as follows, but is not limited to this. As shown in Figure 8, the electrical bias causes multiple ions IN in the plasma PL to collide with the upper electrode (showerhead 13). At this time, material contained in the upper electrode may be released into the chamber. The material contained in the upper electrode is, for example, silicon. The released material deposits on the second region R2, forming a deposited layer DP.

[0055] The deposited layer DP may be formed by means other than the collision of ions IN with the upper electrode and the release of silicon. For example, if the second processing gas contains a silicon-containing gas, the silicon contained in the second processing gas will deposit on the second region R2, and the deposited layer DP will be formed. In this case, the deposited layer DP may be formed by chemical vapor deposition.

[0056] On the other hand, in the adsorption layer AB formed on the surface of the first region R1, the energy of the inert gas ions IN causes the volatilization of the adsorption layer AB and etching to proceed. Furthermore, etching may proceed due to the energy of multiple radicals RD, or by controlling the temperature of the substrate support portion 11.

[0057] Alternatively, even if plasma PL is not generated, etching of the first region R1 can proceed by supplying energy to the adsorption layer AB. When controlling the temperature of the substrate support 11, for example, the temperature of the substrate support 11 is controlled to be 120°C or higher. However, the etching rate may be lower compared to the case where etching is promoted by the collision energy of multiple ions IN. For example, the etching rate may be reduced to half the rate compared to the case where etching is promoted by the collision energy of multiple ions IN.

[0058] The second region R2 is protected by the deposited layer DP, thereby suppressing etching of the second region R2. This improves the etching selectivity ratio of the first region R1 to the second region R2. When an electrical bias is supplied to the upper electrode, the first region R1 can be selectively etched with a higher etching selectivity ratio compared to when an electrical bias is supplied to the substrate support portion 11.

[0059] In step ST4, electrical bias may be supplied only to the substrate support portion 11, or only to the upper electrode. Alternatively, electrical bias may be supplied to both the substrate support portion 11 and the upper electrode. In this case, the level of electrical bias supplied to the substrate support portion 11 and the level of electrical bias supplied to the upper electrode may be the same. Alternatively, the level of electrical bias supplied to the substrate support portion 11 may be higher or lower than the level of electrical bias supplied to the upper electrode.

[0060] In step ST4, plasma PL is not necessarily generated from the second processing gas. As mentioned above, etching can also proceed by controlling the temperature of the substrate support portion 11. In step ST4, instead of generating plasma PL, etching may proceed by controlling the temperature of the substrate support portion 11 to 120°C or higher.

[0061] Figures 9 and 10 are enlarged partial views of a substrate of another example to which the method of Figure 3 may be applied. As shown in Figures 9(a) and 10(a), the substrate W2 includes a first region R1 and a second region R2. The first region R1 is provided on the second region R2. The second region R2 includes a first portion R21, a second portion R22, and a third portion R23. The materials of the first portion R21, the second portion R22, and the third portion R23 may all be the same material or may be different materials. The first portion R21 and the third portion R23 are provided on the second portion R22. The second region R2 includes a recess RS. The recess RS is formed with the second portion R22 as its bottom surface RSa, extending upward from the second portion R22 and penetrating the third portion R23 and the first portion R21. In other words, the side surface RSb of the recess RS is formed continuously from the third portion R23 to the first portion R21. The recess RS may consist of a through hole RS1 in the first portion R21 and a through hole RS2 in the third portion R23. The diameter of the through hole RS2 may be smaller than the diameter of the through hole RS1. In this case, a part of the third portion R23 protrudes closer to the center of the recess RS than the first portion R21. The protruding portion R23a in the third portion R23 may constitute a part of the side surface RSb.

[0062] The first region R1 is provided on the second portion R22. The first region R1 is formed on the second portion R22 at the bottom surface RSa of the recess RS. Furthermore, the first region R1 is formed along the side surface RSb on the third portion R23 and the first portion R21. Furthermore, the first region R1 is formed on the upper surface R21a of the first portion R21.

[0063] Figure 9(b) is a partially enlarged view of the substrate W2 after etching when an electrical bias is supplied to the substrate support 11. Due to the electrical bias supplied to the substrate support 11, multiple ions IN in the plasma PL collide with the substrate W2. As a result, anisotropic etching is promoted, and the first region R1 formed on the upper surface R21a of the first portion R21, the protruding portion R23a of the third portion R23, and the bottom surface RSa can be etched. As a result, as shown in Figure 9(b), the upper surface R21a, the protruding portion R23a, and the bottom surface RSa may be exposed.

[0064] Figure 10(b) is a partially enlarged view of the substrate W2 after etching when an electrical bias is supplied to the upper electrode. When an electrical bias is supplied to the upper electrode, etching may proceed by the energy of multiple radicals RD or by controlling the temperature of the substrate support portion 11. As a result, isotropic etching is promoted, and the first region R1 formed on the upper surface R21a of the first portion R21, the side surface RSb of the recess RS, and the bottom surface RSa can be etched. As a result, as shown in Figure 10(b), the upper surface R21a, the side surface RSb, and the bottom surface RSa may be exposed.

[0065] When method MT1 is applied to substrate W2, etching of the first region R1 can be performed with a high etching selectivity ratio for the second portion R22 of the second region R2 at the bottom surface RSa of the recess RS.

[0066] Figures 11 to 14 are enlarged partial views of a substrate of yet another example to which the method of Figure 3 may be applied. The substrate W3 includes a first region R1 and a second region R2. The first region R1 is provided on the second region R2. The substrate W3 includes a first pattern in which the second region R2 includes a first portion R21 and a second portion R22, as shown in Figures 11(a) and 13(a). The substrate W3 includes a second pattern in which the second region R2 includes a first portion R21, a second portion R22 and a third portion R23, as shown in Figures 12(a) and 14(a). The first and second patterns are formed alternately, for example, in the in-plane direction of the substrate W3. The materials of the first portion R21, the second portion R22 and the third portion R23 may all be the same material or may be different materials. The first portion R21 may contain polysilicon. The second part R22 may contain silicon oxide. The third part R23 may contain single-crystal silicon.

[0067] As shown in Figures 11(a) and 13(a), in the first pattern, the first portion R21 is provided on the second portion R22. The second region R2 includes at least one recess RS. The recess RS is formed with the second portion R22 as its bottom surface RSa1, extending upward from the second portion R22 and penetrating the first portion R21. That is, the side surface RSb of the recess RS may be composed of the first portion R21.

[0068] The first region R1 is formed on the second portion R22 at the bottom surface RSa1 of the recess RS. Furthermore, the first region R1 is formed on the first portion R21 along the side surface RSb. Furthermore, the first region R1 is formed on the upper surface R21a of the first portion R21.

[0069] Figure 11(b) is a partially enlarged view of the first pattern on the substrate W3 after etching when an electrical bias is supplied to the substrate support 11. Due to the electrical bias supplied to the substrate support 11, multiple ions IN in the plasma PL collide with the substrate W3. As a result, anisotropic etching is promoted, and the first region R1 formed on the upper surface R21a and the bottom surface RSa1 of the first portion R21 can be etched. As a result, as shown in Figure 11(b), the upper surface R21a and the bottom surface RSa1 may be exposed.

[0070] Figure 13(b) is a magnified view of a portion of the substrate W3 after etching of the first pattern when an electrical bias is supplied to the upper electrode. When an electrical bias is supplied to the upper electrode, etching may proceed by the energy of multiple radicals RD or by controlling the temperature of the substrate support portion 11. As a result, isotropic etching is promoted, and the first region R1 formed on the upper surface R21a of the first portion R21, the side surface RSb of the recess RS, and the bottom surface RSa can be etched. As a result, as shown in Figure 13(b), the thickness of the first region R1 may become smaller than before etching. The bottom surface RSa1 may be exposed.

[0071] As shown in Figures 12(a) and 14(a), in the second pattern, the first portion R21 and the third portion R23 are provided on the second portion R22. The second region R2 includes at least one recess RS. The recess RS is formed with the third portion R23 as its bottom surface RSa2, extending upward from the third portion R23 and penetrating the first portion R21. That is, the side surface RSb of the recess RS may be composed of the first portion R21.

[0072] The first region R1 is formed on the third portion R23 at the bottom surface RSa2 of the recess RS. Furthermore, the first region R1 is formed on the first portion R21 along the side surface RSb. Furthermore, the first region R1 is formed on the upper surface R21a of the first portion R21.

[0073] Figure 12(b) is a partially enlarged view of the second pattern of the substrate W3 after etching when an electrical bias is supplied to the substrate support 11. Due to the electrical bias supplied to the substrate support 11, multiple ions IN in the plasma PL collide with the substrate W3. As a result, anisotropic etching is promoted, and the first region R1 formed on the upper surface R21a and the bottom surface RSa2 of the first portion R21 can be etched. As a result, as shown in Figure 12(b), the upper surface R21a and the bottom surface RSa2 may be exposed.

[0074] Figure 14(b) is a partially enlarged view of the second pattern of the substrate W3 after etching when an electrical bias is supplied to the upper electrode. When an electrical bias is supplied to the upper electrode, etching may proceed by the energy of multiple radicals RD or by controlling the temperature of the substrate support portion 11. As a result, isotropic etching is promoted, and the first region R1 formed on the upper surface R21a of the first portion R21, the side surface RSb of the recess RS, and the bottom surface RSa2 can be etched. As a result, the bottom surface RSa2 may be exposed, as shown in Figure 14(b). In addition, the thickness of the first region R1 formed on the upper surface R21a of the first portion R21 and the thickness of the first region R1 formed on the side surface RSb may become smaller than before etching.

[0075] When method MT1 is applied to substrate W3, in the first pattern, etching of the first region R1 can be performed with a high etching selectivity ratio for the second portion R22 of the second region R2 at the bottom surface RSa1 of the recess RS. Similarly, in the second pattern, etching of the first region R1 can be performed with a high etching selectivity ratio for the third portion R23 of the second region R2 at the bottom surface RSa2 of the recess RS.

[0076] Figures 15 and 16 are enlarged partial views of a substrate of yet another example to which the method of Figure 3 may be applied. As shown in Figures 15(a) and 16(a), the substrate W4 includes a first region R1 and a second region R2. The substrate W4 further includes a first base region UR1 and a second base region UR2. The first base region UR1 is provided on the second base region UR2. The first region R1 is provided on the first base region UR1. Furthermore, the second region R2, which includes an opening RH, is provided on the first region R1. That is, in the substrate W4, the second base region UR2, the first base region UR1, the first region R1, and the second region R2 are stacked in this order.

[0077] Figure 15(b) is a partially enlarged view of the substrate W4 after etching when an electrical bias is supplied to the substrate support 11. Due to the electrical bias supplied to the substrate support 11, multiple ions IN in the plasma PL collide with the substrate W4. This promotes anisotropic etching, and the first region R1 can be etched using the second region R2 as a mask. As a result, as shown in Figure 15(b), a recess R1a is formed in the first region R1. The recess R1a communicates with the opening RH of the second region R2. The recess R1a is a through hole and may reach the first base region UR1. In this case, the first base region UR1 may be exposed at the bottom surface of the recess R1a.

[0078] Figure 16(b) is a partially enlarged view of the substrate W4 after etching when an electrical bias is supplied to the upper electrode. When an electrical bias is supplied to the upper electrode, etching may proceed by the energy of multiple radicals RD or by controlling the temperature of the substrate support portion 11. This promotes isotropic etching, so that the first region R1 can be etched with the second region R2 as a mask. As a result, as shown in Figure 16(b), a recess R1a is formed in the first region R1. The recess R1a includes an undercut below the second region R2 which is the mask. Furthermore, the recess R1a is a non-through hole and does not need to reach the first substrate region UR1.

[0079] When method MT1 is applied to substrate W4, etching of the first region R1 can be performed with a high etching selectivity ratio for the second region R2.

[0080] Figure 17 is a flowchart of an etching method according to another exemplary embodiment. The etching method shown in Figure 17 (hereinafter referred to as "Method MT2") can be performed by the plasma processing apparatus 1 of the above embodiment. Method MT2 differs from Method MT1 only in that it includes a step ST6 instead of step ST4 in Method MT1. In step ST6, energy is supplied to the substrate W. In step ST6, the adsorption layer AB formed on the surface of the first region R1 is volatilized by the supply of energy to the substrate W. The supplied energy may include at least one selected from the group consisting of plasma containing ions generated in the plasma processing chamber 10, heat to heat the substrate W, electromagnetic waves irradiated onto the substrate W, and a gas cluster ion beam. The plasma containing ions generated in the plasma processing chamber 10 may be, for example, plasma PL generated from a second processing gas, similar to step ST4 in Method MT1. Plasma PL may include a plurality of ions IN of an inert gas. Alternatively, the plasma containing ions generated in the plasma processing chamber 10 may be plasma generated from a processing gas different from the second processing gas, and may contain ions other than those of the inert gas.

[0081] If the supplied energy is heat to heat the substrate W, the plasma processing apparatus 1 may include a heating source. If the supplied energy is electromagnetic waves, the plasma processing apparatus 1 may include an electromagnetic wave irradiation source. Electromagnetic waves are, for example, light or lasers. If the supplied energy is a gas cluster ion beam (hereinafter referred to as "GCIB"), the plasma processing apparatus 1 may include a GCIB irradiation source. The GCIB irradiation source ionizes clusters (groups) formed by the aggregation of multiple gas molecules, accelerates them as a beam, and irradiates the surface of the substrate W. The heating source, electromagnetic wave irradiation source, or GCIB irradiation source may be provided inside the plasma processing chamber 10.

[0082] The following describes various experiments conducted to evaluate Method MT1. The experiments described below are not intended to limit this disclosure.

[0083] (First Experiment) In the first experiment, a substrate was first placed on a substrate support in the chamber of the plasma processing apparatus (step ST1). The substrate includes a first region containing a first material and a second region containing a second material. The first material is SiN, and the second material is SiO ２ Next, without generating plasma, a first processing gas containing HF gas and Ar gas was supplied onto the substrate (step ST2). The duration of step ST2 was 240 seconds. Next, Ar gas was supplied into the chamber to purge the internal space of the chamber (step ST3). The duration of step ST3 was 30 seconds. Next, while supplying an electrical bias to the substrate support, plasma generated from the Ar gas was supplied to the substrate (step ST4). The duration of step ST4 was 10 seconds. Next, steps ST2 to ST4 were repeated so that the number of executions (cycles) of each step ST2 to ST4 was 10 (step ST5). The temperature of the substrate support during steps ST2 to ST5 was 60°C.

[0084] (Experiment 2) Experiment 2 was conducted in the same manner as Experiment 1, except that the second material was polysilicon.

[0085] (Third Experiment) The third experiment was conducted in the same manner as the first experiment, except that the second material was a photoresist.

[0086] (Fourth Experiment) The fourth experiment was conducted in the same manner as the first experiment, except that in step ST4, no electrical bias was supplied to the substrate support and an electrical bias was supplied to the upper electrode.

[0087] (Experiment 5) Experiment 5 was conducted in the same manner as Experiment 2, except that in step ST4, no electrical bias was supplied to the substrate support and an electrical bias was supplied to the upper electrode.

[0088] (Experiment 6) Experiment 6 was conducted in the same manner as Experiment 3, except that in step ST4, no electrical bias was supplied to the substrate support section, and an electrical bias was supplied to the upper electrode.

[0089] (Results of Experiment 1) In each of Experiments 1 to 6, the amount of etching in the first and second regions was measured. The results are shown in Figure 18. In Figure 18, EX1 to EX6 show the measurement results for Experiments 1 to 6, respectively. Polysilicon is denoted as Poly-Si, and photoresist is denoted as PR.

[0090] First, regarding the etching amount of SiN, the etching amount in the first experiment was approximately twice that of the fourth experiment. This is thought to be because the etching was accelerated by the collision energy of multiple ions due to the supply of an electrical bias to the substrate support. A similar trend was observed in the etching amount of photoresist. The etching amount in the third experiment was approximately three times that of the sixth experiment.

[0091] On the other hand, SiO ２ In terms of etching amount, the first experiment showed that the etching amount was extremely low compared to that of SiN. This is because the second material is SiO ２ In this case, it can be said that the etching of the second region progresses extremely slowly compared to the etching of the first region. Furthermore, in the fourth experiment, the etching amount was negative. This is thought to be because the Si released from the upper electrode deposited on the second region, and the amount of deposition exceeded the amount of etching. A similar trend is observed in the etching amount of polysilicon.

[0092] (Second Experimental Results) Based on the first experimental results in each of the first to sixth experiments, SiO ２ The etching selectivity ratios of SiN to polysilicon, polysilicon, and photoresist were calculated. The results are shown in Figure 19. In Figure 19, the etching selectivity ratio when an electrical bias is supplied to the substrate support is denoted as SL1, and the etching selectivity ratio when an electrical bias is supplied to the upper electrode is denoted as SL2. The etching selectivity ratios were calculated from the etching amounts shown in Figure 18.

[0093] When an electrical bias is supplied to the substrate support, SiO ２ The etching selectivity ratio of SiN to was approximately 14. On the other hand, when an electrical bias was supplied to the upper electrode, SiO ２ The etching selectivity ratio of SiN to was over 100. This is because in the fourth experiment, SiO ２ This is because the etching amount was negative. A similar trend was observed in the etching selectivity ratio of SiN to polysilicon. Therefore, it can be said that the first region can be selectively etched relative to the second region, whether an electrical bias is supplied to the substrate support or to the upper electrode.

[0094] Although various exemplary embodiments have been described above, the invention is not limited to the exemplary embodiments described above, and various additions, omissions, substitutions, and modifications may be made. Furthermore, it is possible to combine elements from different embodiments to form other embodiments.

[0095] Herein, various exemplary embodiments included in this disclosure are described in [E1] to [E20] below.

[0096] [E1] An etching method comprising: (a) a step of providing a substrate on a substrate support in a chamber, wherein the substrate comprises a first region and a second region, the first region comprising a first material comprising nitrogen and silicon, and the second region comprising a second material different from the first material; (b) a step of exposing the substrate to a first processing gas comprising hydrogen fluoride gas; and (c) a step of exposing the substrate, after (b), to a plasma generated from a second processing gas comprising an inert gas, wherein the plasma comprises ions of the inert gas.

[0097] [E2] The etching method according to [E1], wherein in (c), an electrical bias is supplied to the substrate support portion.

[0098] [E3] The etching method according to [E1] or [E2], wherein in (c), an electrical bias is supplied to the upper electrode located above the substrate support within the chamber.

[0099] [E4] The etching method according to [E3], wherein the upper electrode contains silicon.

[0100] [E5] The etching method according to any one of [E1] to [E4], wherein the second processing gas contains a silicon-containing gas.

[0101] [E6] (d) The etching method according to any one of [E1] to [E5], further comprising the step of repeating (b) and (c).

[0102] [E7] The etching method according to any one of [E1] to [E6], wherein the plasma further comprises radicals of the inert gas.

[0103] [E8] The etching method according to any one of [E1] to [E7], wherein in (b), the temperature of the substrate support is controlled to be in the range of 20°C to 100°C.

[0104] [E9] The etching method according to any one of [E1] to [E8], wherein the pressure in the chamber in (b) is greater than the pressure in the chamber in (c).

[0105] [E10] The etching method according to any one of [E1] to [E9], wherein the first processing gas further comprises an inert gas.

[0106] [E11] The etching method according to any one of [E1] to [E10], wherein the inert gas comprises at least one gas selected from the group consisting of noble gases and nitrogen gas.

[0107] [E12] The etching method according to [E11], wherein the noble gas comprises at least one gas selected from the group consisting of argon gas, helium gas, xenon gas, and neon gas.

[0108] [E13] The etching method according to any one of [E1] to [E12], wherein the first material comprises at least one material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0109] [E14] The etching method according to any one of [E1] to [E13], wherein the second material comprises at least one material selected from the group consisting of silicon oxide, polysilicon, amorphous silicon, silicon germanium, germanium, and High-k materials.

[0110] [E15] The etching method according to any one of [E1] to [E14], wherein the first region is provided on the second region.

[0111] [E16] The etching method according to [E15], wherein the second region includes a recess, and in (c), the first region provided on the bottom surface of the recess is etched.

[0112] [E17] The etching method according to any one of [E1] to [E16], wherein the second region has an opening and is provided on the first region.

[0113] [E18] (e) The etching method according to any one of [E1] to [E17], further comprising the step of purging the internal space of the chamber between (b) and (c).

[0114] [E19] Etching method comprising: (a) a step of providing a substrate on a substrate support in a chamber, wherein the substrate comprises a first region and a second region, the first region comprising a first material comprising nitrogen and silicon, and the second region comprising a second material different from the first material; (b) a step of exposing the substrate to a first processing gas comprising hydrogen fluoride gas; and (c) a step of supplying energy to the substrate, wherein in (c), the energy comprises at least one selected from the group consisting of a plasma containing ions generated in the chamber, heat for heating the substrate, electromagnetic waves irradiated onto the substrate, and a gas cluster ion beam.

[0115] [E20] A plasma processing apparatus comprising: a chamber; a substrate support for supporting a substrate within the chamber; a gas supply unit configured to supply a first processing gas and a second processing gas into the chamber, wherein the first processing gas includes hydrogen fluoride gas and the second processing gas includes an inert gas; a plasma generation unit configured to generate plasma from the second processing gas within the chamber, wherein the plasma includes ions of the inert gas; and a control unit, wherein the control unit is configured to control the gas supply unit and the plasma generation unit to perform an etching method, the etching method comprising: (b) a step of exposing the substrate to the first processing gas; and (c) a step of exposing the substrate to the plasma generated from the second processing gas after (b).

[0116] 1...Plasma processing apparatus, 2...Control unit, 10...Plasma processing chamber (chamber), 11...Substrate support unit, 12...Plasma generation unit, 20...Gas supply unit, IN...Ions, PL...Plasma, R1...First region, R2...Second region, W1, W2, W3, W4...Substrates.

Claims

1. An etching method comprising: (a) a step of providing a substrate on a substrate support portion in a chamber, wherein the substrate comprises a first region and a second region, the first region comprising a first material comprising nitrogen and silicon, and the second region comprising a second material different from the first material; (b) a step of exposing the substrate to a first processing gas comprising hydrogen fluoride gas; and (c) a step of exposing the substrate, after (b), to a plasma generated from a second processing gas comprising an inert gas, wherein the plasma comprises ions of the inert gas.

2. The etching method according to claim 1, wherein in (c) above, an electrical bias is supplied to the substrate support portion.

3. The etching method according to claim 1 or 2, wherein in (c) above, an electrical bias is supplied to the upper electrode positioned above the substrate support within the chamber.

4. The etching method according to claim 3, wherein the upper electrode contains silicon.

5. The etching method according to claim 1 or 2, wherein the second processing gas includes a silicon-containing gas.

6. (d) The etching method according to claim 1 or 2, further comprising the step of repeating (b) and (c).

7. The etching method according to claim 1 or 2, wherein the plasma further comprises radicals of the inert gas.

8. The etching method according to claim 1 or 2, wherein, in (b), the temperature of the substrate support portion is controlled to be in the range of 20°C to 100°C.

9. The etching method according to claim 1 or 2, wherein the pressure in the chamber in (b) is greater than the pressure in the chamber in (c).

10. The etching method according to claim 1 or 2, wherein the first processing gas further comprises an inert gas.

11. The etching method according to claim 1 or 2, wherein the inert gas comprises at least one gas selected from the group consisting of noble gases and nitrogen gas.

12. The etching method according to claim 11, wherein the noble gas comprises at least one gas selected from the group consisting of argon gas, helium gas, xenon gas, and neon gas.

13. The etching method according to claim 1 or 2, wherein the first material comprises at least one material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon carbonitride.

14. The etching method according to claim 1 or 2, wherein the second material comprises at least one material selected from the group consisting of silicon oxide, polysilicon, amorphous silicon, silicon germanium, germanium, and High-k materials.

15. The etching method according to claim 1 or 2, wherein the first region is provided on the second region.

16. The etching method according to claim 15, wherein the second region includes a recess, and in (c), the first region provided on the bottom surface of the recess is etched.

17. The etching method according to claim 1 or 2, wherein the second region has an opening and is provided on the first region.

18. (e) The etching method according to claim 1 or 2, further comprising the step of purging the internal space of the chamber between (b) and (c).

19. An etching method comprising: (a) a step of providing a substrate on a substrate support in a chamber, wherein the substrate comprises a first region and a second region, the first region comprising a first material comprising nitrogen and silicon, and the second region comprising a second material different from the first material; (b) a step of exposing the substrate to a first processing gas comprising hydrogen fluoride gas; and (c) a step of supplying energy to the substrate, wherein in (c), the energy comprises at least one selected from the group consisting of a plasma containing ions generated in the chamber, heat for heating the substrate, electromagnetic waves irradiated onto the substrate, and a gas cluster ion beam.

20. A plasma processing apparatus comprising: a chamber; a substrate support for supporting a substrate within the chamber; a gas supply unit configured to supply a first processing gas and a second processing gas into the chamber, wherein the first processing gas includes hydrogen fluoride gas and the second processing gas includes an inert gas; a plasma generation unit configured to generate plasma from the second processing gas within the chamber, wherein the plasma includes ions of the inert gas; and a control unit, wherein the control unit is configured to control the gas supply unit and the plasma generation unit to perform an etching method, the etching method comprising: (b) a step of exposing the substrate to the first processing gas; and (c) a step of exposing the substrate to the plasma generated from the second processing gas after (b).

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