Electronic device

Abstract

This electronic device includes: a substrate including a non-light-emitting region including a normal region and support regions surrounded by the normal region; a pixel-defining film in which openings overlapping light-emitting regions are defined; light-emitting elements each including a first electrode, a common layer disposed on the first electrode, and a second electrode disposed on the common layer; partition walls disposed on the pixel-defining film and overlapping the normal region; and spacers disposed on the pixel-defining film and overlapping the support regions, wherein each of the spacers is surrounded by the adjacent partition wall and spaced apart from the partition wall.

Description

electronic devices

[0001] The present invention relates to an electronic device, and more specifically, to an electronic device with improved display quality.

[0002] Generally, electronic devices that provide video to users, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions, include electronic devices for displaying video. The electronic device generates video and provides the generated video to the user through a display screen.

[0003] The electronic device includes a plurality of pixels for generating an image and a plurality of lines connected to the pixels. The pixels are driven by receiving driving signals through the lines.

[0004] Large-sized electronic devices, such as tablets and smart televisions, may experience differences in the driving voltage delivered to each pixel, requiring a design to compensate for this.

[0005] An electronic device according to one embodiment of the present invention comprises: a substrate including a non-luminous region comprising light-emitting regions and a normal region and a support region surrounded by the normal region, and a display region disposed between the light-emitting regions; an inter-insulating layer disposed on the substrate; a pixel defining film disposed on the inter-insulating layer and having openings defined that overlap with the light-emitting regions; light-emitting elements each comprising a first electrode disposed on the inter-insulating layer and overlapping with the openings, a common layer disposed on the first electrode, and a second electrode disposed on the common layer; a partition disposed on the pixel defining film and overlapping with the normal region; and spacers disposed on the pixel defining film and overlapping with the support regions, wherein each of the spacers is surrounded by an adjacent partition and spaced apart from the partition.

[0006] The height from the pixel defining film to the spacer may be characterized as being greater than the height from the pixel defining film to the partition wall.

[0007] The above spacers may be characterized by including a transparent organic material or a colored organic material having light-blocking properties.

[0008] Each of the above spacers may be characterized by including a first pattern disposed on the pixel definition film and a second pattern disposed on the first pattern.

[0009] The height of the pixel definition film overlapping with the spacers in the areas adjacent to the support regions may be characterized as being greater than the height of the pixel definition film overlapping with the partition wall.

[0010] The area in which the spacers are arranged within the display area may be characterized as being 1% to 10% of the total area of ​​the display area.

[0011] The above partition may be characterized by including a first insulating pattern disposed on the pixel definition film, a second insulating pattern disposed on the first insulating pattern, a third insulating pattern disposed on the second insulating pattern, a first partition pattern disposed on the third insulating pattern, and a second partition pattern disposed on the first partition pattern.

[0012] The first to third insulation patterns may comprise different materials, wherein the first insulation pattern comprises at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide, and the second insulation pattern and the third insulation pattern may comprise any one of silicon oxide, silicon oxynitride, and silicon nitride.

[0013] The first bulkhead pattern may be characterized by including aluminum, and the second bulkhead pattern may be characterized by including titanium.

[0014] The thickness of the first bulkhead pattern is greater than the thickness of the second bulkhead pattern, the width of the second bulkhead pattern is greater than the width of the first bulkhead pattern, and a portion of the lower surface of the second bulkhead pattern protrudes from the first bulkhead pattern and is exposed from the first bulkhead pattern to define a tip portion.

[0015] The second electrode is a single pattern commonly provided to the light-emitting elements, and the second electrode may be characterized by extending from the light-emitting regions to the non-light-emitting regions to cover a portion of the side of the first partition pattern and the lower surface of the second partition pattern.

[0016] It may further include a dummy pattern disposed between the second partition pattern and the second electrode, wherein the dummy pattern comprises the same material as the common layer.

[0017] It may be characterized by further including power lines that provide power to the light-emitting elements, overlap the display area, and are disposed between the insulating layer and the substrate.

[0018] The above non-luminous region may further include contact regions disposed within the normal region and spaced apart from the support regions, wherein the contact regions are defined with contact holes through which the inter-insulating layer and the pixel defining film penetrate to expose the power lines, and the first partition pattern may be characterized by contacting the power lines exposed by the contact holes.

[0019] In the above contact regions, at least one of the first to third insulating patterns may be characterized by covering the side of the inter-insulating layer defining the contact hole and the side of the pixel defining film.

[0020] The pixel definition film described above may be characterized by including a colored organic material having light-blocking properties.

[0021] The device may further include an encapsulation layer disposed on the pixel definition film and covering the light-emitting elements, wherein the encapsulation layer comprises inorganic layers and an organic layer disposed between the inorganic layers.

[0022] The above-mentioned light-emitting regions may be characterized by including a first-1 light-emitting region and a first-2 light-emitting region that provide light of a first color and are spaced apart along the first direction; a second light-emitting region that provides light of a second color different from the first color and is spaced diagonally apart from the first-1 and first-2 light-emitting regions; and a third light-emitting region that is spaced apart from the second light-emitting region along a second direction intersecting the first direction and provides light of a third color different from the first and second colors.

[0023] The above spacer may be characterized by being positioned between adjacent first to third light-emitting regions.

[0024] The above-mentioned first to third light-emitting regions may be characterized by having different shapes.

[0025] According to the present invention, as the second electrode is connected to the power line through a partition within the display area, a voltage drop phenomenon can be prevented, thereby providing a constant voltage to the pixels. In addition, as the connection between the second electrode and the power line is made within the display area, unnecessary space for connecting the second electrode and the second power line in the non-display area can be reduced.

[0026] In addition, by placing a spacer that supports the mask in the display area, the tip structure of the bulkhead can be stably maintained even after the process of using the mask.

[0027] FIG. 1a is a perspective view of an electronic device according to one embodiment of the present invention.

[0028] FIG. 1b is a block diagram of an electronic device according to one embodiment of the present invention.

[0029] FIG. 2 is a cross-sectional view of an electronic device according to one embodiment of the present invention.

[0030] FIG. 3 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0031] FIG. 4a is a block diagram of a display module according to one embodiment of the present invention.

[0032] Figure 4b is an equivalent circuit of any one of the pixels shown in Figure 4a.

[0033] FIG. 5a is a plan view of a pixel unit according to one embodiment of the present invention.

[0034] FIG. 5b is a simplified plan view illustrating a portion of a display area according to one embodiment of the present invention.

[0035] Figure 6 is a cross-sectional view taken along I-I' of Figure 5a.

[0036] Figure 7 is an enlarged cross-sectional view of the bulkhead shown in Figure 6.

[0037] Figure 8 is a cross-sectional view taken along II-II' of Figure 5a.

[0038] Figure 9 is a cross-sectional view taken along III-III' of Figure 5a.

[0039] FIG. 10 is a cross-sectional view of a support area of ​​an electronic device according to one embodiment of the present invention.

[0040] FIG. 11 is a cross-sectional view of a support area of ​​an electronic device according to one embodiment of the present invention.

[0041] FIG. 12 is an enlarged view of a display area according to one embodiment of the present invention.

[0042] Where in this specification an element (e.g., a layer) is described as being “on,” “connected to,” or “coupled to” another element or layer, said element or layer may be directly located on, directly connected to, or directly coupled to the other element or layer, or one or more interposed elements or layers may exist between them. On the other hand, where an element or layer is described as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no interposed elements or layers between them. Additionally, the term “connected” may include physical, electrical, and / or physical connections, regardless of the presence of interposed elements. In addition, if an element is described using expressions such as “in contact” or “contacted” with another element, this may mean that the element is in “electrical contact,” “physical contact,” “indirect contact,” or “direct contact” with the other element.

[0043] In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed / connected / joined on the other component, or that a third component may be placed between them.

[0044] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective description of the technical content. “And / or” includes all one or more combinations that the associated components may define. The phrase “at least one of” used in the specification and claims is used for the purposes of meaning and interpretation to mean “at least one selected from a group consisting of.” For example, “at least one A and B” may be interpreted as “A, B or A and B.” Additionally, the term “and / or” used in the specification and claims is used for the purposes of meaning and interpretation to mean all combinations of “and” and “or.” For example, “A and / or B” may be interpreted as “A, B or A and B.” “And” and “or” may be used in a conjunctive or disjunctive sense and may be interpreted as equivalent to “and / or.”

[0045] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0046] In this specification, spatially relative terms such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” and “side” (e.g., in the case of “sidewall”) may be used for descriptive purposes and are intended to describe the relationship that one element has with other element(s) as illustrated in the drawings. These spatially relative terms should be interpreted to include not only the directions illustrated in the drawings but also all various directions the device has during use, operation, and / or manufacturing.

[0047] For example, if the device depicted in the drawing is inverted, an element described as being located “below” or “under” another element or feature may then be placed “above.” Accordingly, the exemplary term “below” may include placement in both “above” and “below” directions.

[0048] Additionally, the device may be oriented in a different direction (e.g., rotated 90 degrees or other directions), and accordingly, spatially relative expressions used in this specification should also be interpreted in accordance with such direction.

[0049] Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0050] In this specification, the term “about” may include a range of, for example, ±20%, ±10%, or ±5% from the stated numerical values, unless specifically stated otherwise. In some contexts, the term may be used with respect to rounding, inherent limits of measurement, or standard tolerances recognized in the art. Where the term “about” is applied to dimensions, concentrations, or other measurable parameters, it may include minute deviations that a person of ordinary skill in the art would understand as being of no substantial significance in the context. The interpretation of “about” should be determined by taking into account standard experimental or clinical tolerances according to the field of application. A person of ordinary skill in the art will recognize that “about” allows for practical deviations that do not substantially alter the intended characteristics of the invention. Similarly, with respect to mechanical dimensions, “about” may include a range of deviations within industry-recognized tolerances that do not substantially affect the performance of the invention.

[0051] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit them. The singular forms “a,” “an,” and “the” used herein should be interpreted to include the plural forms unless the context clearly indicates otherwise. Additionally, terms used herein such as “comprises,” “comprising,” “includes,” and / or “including” are intended to indicate the presence of a specified feature, integer, step, action, element, component, and / or set thereof, and do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or sets thereof.

[0052] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0054] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0055] FIG. 1a is a perspective view of an electronic device according to an embodiment of the present invention. Referring to FIG. 1a, an electronic device (DD) according to an embodiment of the present invention may have long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2) intersecting the first direction (DR1). The corners of the electronic device (DD) connecting the long sides and the short sides may have a curved shape. The corners of the electronic device (DD) having a curved shape may be defined as round corners. The shape of such an electronic device (DD) may be defined as a round corner rectangle. However, this is merely an example of the shape of an electronic device (DD) and is not limited to a round corner rectangle.

[0056] Hereinafter, the direction that intersects substantially perpendicularly with the plane defined by the first direction (DR1) and the second direction (DR2) is defined as the third direction (DR3). Additionally, in this specification, the meaning of "when viewed on a plane" is defined as the state viewed from the third direction (DR3).

[0057] The front surface of the electronic device (DD) can be defined as a display surface (DS) and may have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated by the electronic device (DD) can be provided to the user through the display surface (DS).

[0058] The display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may display an image, and the non-display area (NDA) may not display an image. The non-display area (NDA) may surround the display area (DA) and define a border of an electronic device (DD) that is printed in a predetermined color.

[0059] The display area (DA) may have a rounded corner rectangle shape depending on the shape of the electronic device (DD). For example, the display area (DA) may include rectangular sides extending in a first direction (DR1) and a second direction (DR2), and rounded corners connecting the sides. Among the four sides, the sides extending in the first direction (DR1) may be defined as long sides, and among the four sides, the sides extending in the second direction (DR2) may be defined as short sides.

[0060] The electronic device (DD) can detect inputs applied from outside the electronic device (DD). For example, the electronic device (DD) can detect a first input by a touch pen (PEN) and a second input by touch (TC). The touch pen (PEN) can be defined as an input device.

[0061] The touch pen (PEN) may be an active pen that outputs a signal. The second input by touch (TC) may include various forms of external inputs, such as parts of the user's body, light, heat, or pressure.

[0062] The electronic device (DD) and the touch pen (PEN) can communicate bidirectionally. The electronic device (DD) can provide an uplink signal to the touch pen (PEN). For example, the uplink signal may include information such as panel information and protocol version, but is not specifically limited thereto.

[0063] The touch pen (PEN) can provide a downlink signal to the electronic device (DD). The downlink signal may include a synchronization signal or status information of the touch pen (PEN). For example, the downlink signal may include coordinate information of the touch pen (PEN), battery information of the touch pen (PEN), tilt information of the touch pen (PEN), and / or various information stored in the touch pen (PEN), but is not particularly limited thereto.

[0064] The electronic device (DD) can be used in large electronic devices such as televisions, monitors, or outdoor billboards. Additionally, the electronic device (DD) can be used in small and medium-sized electronic devices such as personal computers, laptop computers, personal digital terminals, car navigation systems, game consoles, smartphones, tablets, or cameras. However, these are presented merely as exemplary embodiments, and the electronic device (DD) can be used in other electronic devices without departing from the concept of the invention.

[0065] FIG. 1b illustrates a block diagram of an electronic device (DD) according to one embodiment. Referring to FIG. 1b, the electronic device (DD) outputs various information through a display module (DM) within an operating system. When the processor (110) executes an application stored in memory (120), the display module (DM) provides application information to the user through a display panel (DP).

[0066] The processor (110) obtains an external input through the input module (130) or the sensor module (161) and executes an application corresponding to the external input. For example, if a user selects a camera icon displayed on the display panel (DP), the processor (110) obtains user input through the input sensor (161-2) and activates the camera module (171). The processor (110) transmits image data corresponding to the captured image obtained through the camera module (171) to the display module (DM). The display module (DM) can display the image corresponding to the captured image through the display panel (DP).

[0067] As another example, when personal information authentication is performed in the display module (DM), the fingerprint sensor (161-1) acquires the input fingerprint information as input data. The processor (110) compares the input data acquired through the fingerprint sensor (161-1) with the authentication data stored in the memory (120) and executes an application based on the comparison result. The display module (DM) can display the executed information through the display panel (DP) according to the logic of the application.

[0068] As another example, when a music streaming icon displayed on a display module (DM) is selected, the processor (110) obtains user input through an input sensor (161-2) and activates a music streaming application stored in memory (120). When a music execution command is input from the music streaming application, the processor (110) activates an audio output module (163) to provide audio information corresponding to the music execution command to the user.

[0069] The operation of the electronic device (DD) has been briefly described above. The configuration of the electronic device (DD) will be described in detail below. Some of the configurations of the electronic device (DD) described below may be integrated and provided as a single configuration, and a single configuration may be separated into two or more configurations.

[0070] Referring to FIG. 1b, the electronic device (DD) can communicate with an external electronic device (102) through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device (DD) may include a processor (110), memory (120), an input module (130), a display module (DM), a power module (150), an internal module (160), and an external module (170). According to one embodiment, at least one of the above-described components may be omitted, or one or more other components may be added to the electronic device (DD). According to one embodiment, some of the above-described components (e.g., a sensor module (161), an antenna module (162), or an acoustic output module (163)) may be integrated into another component (e.g., a display module (DM)).

[0071] The processor (110) can execute software to control at least one other component (e.g., a hardware or software component) of an electronic device (DD) connected to the processor (110) and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (110) stores commands or data received from other components (e.g., an input module (130), a sensor module (161), or a communication module (173)) in a volatile memory (121), processes the commands or data stored in the volatile memory (121), and the resulting data can be stored in a non-volatile memory (122).

[0072] The processor (110) may include a main processor (111) and an auxiliary processor (112). The main processor (111) may include one or more of a central processing unit (111-1, CPU) or an application processor (AP). The main processor (111) may further include one or more of a graphic processing unit (111-2, GPU), a communication processor (CP), and an image signal processor (ISP). The main processor (111) may further include a neural processing unit (111-3, NPU). The neural processing unit is a processor specialized for processing artificial intelligence models, and the artificial intelligence model may be generated through machine learning. The artificial intelligence model may include a plurality of artificial neural network layers. An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially. At least two of the processing unit and processor described above may be implemented as a single integrated configuration (e.g., a single chip), or each may be implemented as an independent configuration (e.g., multiple chips).

[0073] The auxiliary processor (112) may include a controller (112-1). The controller (112-1) may include an interface conversion circuit and a timing control circuit. The controller (112-1) receives a video signal from the main processor (111), converts the data format of the video signal to match the interface specifications with the display module (DM), and outputs video data. The controller (112-1) may output various control signals required for driving the display module (DM).

[0074] The auxiliary processor (112) may further include a data conversion circuit (112-2), a gamma correction circuit (112-3), a rendering circuit (112-4), etc. The data conversion circuit (112-2) receives image data from the controller (112-1) and can compensate the image data so that the image is displayed at a desired brightness according to the characteristics of the electronic device (DD) or the user's settings, etc., or can convert the image data to reduce power consumption or compensate for afterimages, etc. The gamma correction circuit (112-3) can convert image data or gamma reference voltage, etc. so that the image displayed on the electronic device (DD) has desired gamma characteristics. The rendering circuit (112-4) receives image data from the controller (112-1) and can render the image data by considering the pixel arrangement of the display panel (DP) applied to the electronic device (DD). At least one of the data conversion circuit (112-2), gamma correction circuit (112-3), and rendering circuit (112-4) may be integrated into another component (e.g., main processor (111) or controller (112-1)). At least one of the data conversion circuit (112-2), gamma correction circuit (112-3), and rendering circuit (112-4) may also be integrated into the data driving unit (DDV) described later.

[0075] The memory (120) can store various data used by at least one component of the electronic device (DD) (e.g., a processor (110) or a sensor module (161)) and input or output data for related commands. The memory (120) may include at least one of a volatile memory (121) and a non-volatile memory (122).

[0076] The input module (130) can receive commands or data to be used for components of the electronic device (DD) (e.g., processor (110), sensor module (161) or sound output module (163)) from outside the electronic device (DD) (e.g., user or external electronic device (102)).

[0077] The input module (130) may include a first input module (131) into which commands or data are input from a user and a second input module (132) into which commands or data are input from an external electronic device (102). The first input module (131) may include a microphone, a mouse, a keyboard, a key (e.g., a button), or a pen (e.g., a passive pen or an active pen). The second input module (132) may support a specified protocol that can be connected to the external electronic device (102) via a wired or wireless connection. According to one embodiment, the second input module (132) may include a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface. The second input module (132) may include a connector that can be physically connected to the external electronic device (102), such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0078] The display module (DM) provides visual information to the user. The display module (DM) may include a display panel (DP), a scan driver (SDC), and a data driver (DDV). The display module (DM) may further include a window, a chassis, and a bracket for protecting the display panel (DP).

[0079] The display panel (DP) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of the display panel (DP) is not particularly limited. The display panel (DP) may be a rigid type, or a flexible type that is rollable or foldable. The display module (DM) may further include a supporter, a bracket, or a heat dissipation member that supports the display panel (DP).

[0080] The scan driver (SDC) can be mounted on the display panel (DP) as a driver chip. Additionally, the scan driver (SDC) can be integrated into the display panel (DP). For example, the scan driver (SDC) may include an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon) TFT Gate driver circuit, or an OSG (Oxide Semiconductor TFT Gate driver circuit) embedded in the display panel (DP). The scan driver (SDC) receives a control signal from the controller (112-1) and outputs scan signals to the display panel (DP) in response to the control signal.

[0081] The display panel (DP) may further include a light-emitting driver. The light-emitting driver outputs a light-emitting control signal to the display panel (DP) in response to a control signal received from the controller (112-1). The light-emitting driver may be formed separately from the scan driver (SDC) or may be integrated into the scan driver (SDC).

[0082] The data driver (DDV) receives a control signal from the controller (112-1), converts the image data into an analog voltage (e.g., data voltage) in response to the control signal, and then outputs the data voltages to the display panel (DP).

[0083] The data driver (DDV) may be integrated into other components (e.g., controller (112-1)). The functions of the interface conversion circuit and timing control circuit of the controller (112-1) described above may also be integrated into the data driver (DDV).

[0084] The display module (DM) may further include a light-emitting driver and a voltage generation circuit. The voltage generation circuit can output various voltages required to drive the display panel (DP).

[0085] The power module (150) supplies power to the components of the electronic device (DD). The power module (150) may include a battery that charges the power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power module (150) may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and the modules described below. The power module (150) may include a wireless power transmission and reception member electrically connected to the battery. The wireless power transmission and reception member may include a plurality of coil-shaped antenna radiators.

[0086] The electronic device (DD) may further include an internal module (160) and an external module (170). The internal module (160) may include a sensor module (161), an antenna module (162), and an acoustic output module (163). The external module (170) may include a camera module (171), a light module (172), and a communication module (173).

[0087] The sensor module (161) can detect input by the user's body or input by a pen of the first input module (131) and generate an electrical signal or data value corresponding to the input. The sensor module (161) may include at least one of a fingerprint sensor (161-1), an input sensor (161-2), and a digitizer (161-3).

[0088] The fingerprint sensor (161-1) can generate a data value corresponding to the user's fingerprint. The fingerprint sensor (161-1) may include either an optical or capacitive fingerprint sensor.

[0089] The input sensor (161-2) can generate a data value corresponding to coordinate information of input by the user's body or input by a pen. The input sensor (161-2) generates a data value of the amount of change in capacitance due to the input. The input sensor (161-2) can detect input by a passive pen or transmit and receive data with an active pen.

[0090] The input sensor (161-2) may measure biosignals such as blood pressure, water content, or body fat. For example, if a user contacts a part of their body with the sensor layer or sensing panel and does not move for a certain period of time, the input sensor (161-2) may detect biosignals based on changes in the electric field caused by the part of the body and output information desired by the user to the display module (DM).

[0091] The digitizer (161-3) can generate a data value corresponding to the coordinate information of the input by the pen. The digitizer (161-3) generates the amount of electromagnetic change caused by the input as a data value. The digitizer (161-3) can detect input by a passive pen or transmit and receive data with an active pen.

[0092] At least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be implemented as a sensor layer formed on a display panel (DP) through a continuous process. The fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be positioned on the upper side of the display panel (DP), and any one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3), such as the digitizer (161-3), may be positioned on the lower side of the display panel (DP).

[0093] At least two of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) can be formed to be integrated into a single sensing panel through the same process. When integrated into a single sensing panel, the sensing panel can be positioned between a display panel (DP) and a window positioned above the display panel (DP). According to one embodiment, the sensing panel may be positioned on the window, and the position of the sensing panel is not particularly limited.

[0094] At least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be embedded in the display panel (DP). That is, at least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be formed simultaneously through a process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel (DP).

[0095] Additionally, the sensor module (161) may generate an electrical signal or data value corresponding to an internal or external state of the electronic device (DD). The sensor module (161) may further include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0096] The antenna module (162) may include one or more antennas for transmitting a signal or power to the outside or receiving it from the outside. According to one embodiment, the communication module (173) may transmit a signal to an external electronic device or receive it from an external electronic device through an antenna suitable for a communication method. The antenna pattern of the antenna module (162) may be integrated into one component of the display module (DM) (e.g., a display panel (DP)) or an input sensor (161-2), etc.

[0097] The sound output module (163) is a device for outputting a sound signal to the outside of the electronic device (DD), and may include, for example, a speaker used for general purposes such as multimedia playback or recording playback, and a receiver used exclusively for telephone reception. According to one embodiment, the receiver may be formed integrally with or separately from the speaker. The sound output pattern of the sound output module (163) may be integrated with the display module (DM).

[0098] The camera module (171) can capture still images and video. According to one embodiment, the camera module (171) may include one or more lenses, image sensors, or image signal processors. The camera module (171) may further include an infrared camera capable of measuring the presence or absence of a user, the location of the user, the user's gaze, etc.

[0099] The light module (172) can provide light. The light module (172) may include a light-emitting diode or a xenon lamp. The light module (172) may operate in conjunction with the camera module (171) or operate independently.

[0100] The communication module (173) can support the establishment of a wired or wireless communication channel between an electronic device (DD) and an external electronic device (102), and the performance of communication through the established communication channel. The communication module (173) may include one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a GNSS (global navigation satellite system) communication module, and a wired communication module such as a LAN (local area network) communication module or a power line communication module. The communication module (173) can communicate with the external electronic device (102) through a short-range communication network such as Bluetooth, WiFi Direct, or IrDA (infrared data association), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., LAN or WAN). The various types of communication modules (173) described above may be implemented as a single chip or each as a separate chip.

[0101] The input module (130), sensor module (161), camera module (171), etc., can be used to control the operation of the display module (DM) in conjunction with the processor (110).

[0102] The processor (110) outputs commands or data to the display module (DM), sound output module (163), camera module (171), or light module (172) based on input data received from the input module (130). For example, the processor (110) may generate image data in response to input data applied via a mouse or active pen, and output it to the display module (DM), or generate command data in response to input data and output it to the camera module (171) or light module (172). If the processor (110) does not receive input data from the input module (130) for a certain period of time, it may switch the operating mode of the electronic device (DD) to a low-power mode or sleep mode to reduce the power consumed by the electronic device (DD).

[0103] The processor (110) outputs commands or data to the display module (DM), sound output module (163), camera module (171), or light module (172) based on the sensing data received from the sensor module (161). For example, the processor (110) can compare the authentication data authorized by the fingerprint sensor (161-1) with the authentication data stored in the memory (120) and then execute an application based on the comparison result. The processor (110) can execute commands or output corresponding image data to the display module (DM) based on the sensing data detected by the input sensor (161-2) or the digitizer (161-3). If the sensor module (161) includes a temperature sensor, the processor (110) receives temperature data regarding the temperature measured from the sensor module (161) and can further perform brightness correction, etc., on the image data based on the temperature data.

[0104] The processor (110) can receive measurement data regarding the presence or absence of a user, the location of the user, the user's gaze, etc. from the camera module (171). The processor (110) can further perform brightness correction on the image data based on the measurement data. For example, the processor (110), having determined the presence or absence of a user through input from the camera module (171), can output the image data with corrected brightness to the display module (DM) through the data conversion circuit (112-2) or the gamma correction circuit (112-3).

[0105] Some of the above components may be connected to each other via a communication method between peripheral devices, such as a bus, GPIO (general purpose input / output), SPI (serial peripheral interface), MIPI (mobile industry processor interface), or UPI (Ultra path interconnect) link, to exchange signals (e.g., commands or data) with each other. The processor (110) may communicate with the display module (DM) via an interface agreed upon with each other, and may, for example, use any of the communication methods described above, but is not limited to the communication methods described above.

[0106] The electronic device (DD) according to the various embodiments disclosed in this document may be of various forms. The electronic device (DD) may include, for example, at least one of a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device (DD) according to the embodiments of this document is not limited to the aforementioned devices.

[0107] FIG. 2 is a cross-sectional view of an electronic device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an exemplary cross-section of the electronic device shown in FIG. 1a. FIG. 2 illustrates an exemplary cross-section of the electronic device (DD) viewed from a second direction (DR2). FIG. 2 omits some of the components of the electronic device (DD) described in FIG. 1b.

[0108] Referring to FIG. 2, the electronic device (DD) may include a display panel (DP), an input sensor (ISP), an anti-reflective layer (RPL), a window (WIN), a panel protection film (PPF), and first and second adhesive layers (AL1, AL2). The input sensor (ISP) shown in FIG. 2 may have the same configuration as the input sensor (161-2) described in FIG. 1b.

[0109] A display panel (DP) according to one embodiment of the present invention may be a light-emitting display panel. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0110] The input sensor (ISP) may be placed on the display panel (DP). The input sensor (ISP) may include a plurality of sensing units (not shown) for sensing external input in a capacitive manner. The input sensor (ISP) may be manufactured directly on the display panel (DP) during the manufacture of the electronic device (DD). Therefore, the input sensor (ISP) according to one embodiment may be placed directly on the display panel (DP). However, not limited thereto, the input sensor (ISP) may be manufactured as a separate panel from the display panel (DP) and attached to the display panel (DP) by an adhesive layer.

[0111] The anti-reflective layer (RPL) can be placed on the input sensor (ISP). The anti-reflective layer (RPL) can be manufactured directly on the input sensor (ISP) during the manufacture of the electronic device (DD). However, it is not limited thereto, and the anti-reflective layer (RPL) can be manufactured as a separate panel and attached to the input sensor (ISP) by an adhesive layer.

[0112] The anti-reflective layer (RPL) can be defined as an external light anti-reflective film. The anti-reflective layer (RPL) can reduce the reflectivity of external light incident from the electronic device (DD) toward the display panel (DP). External light may not be visible to the user due to the anti-reflective layer (RPL).

[0113] When external light traveling toward the display panel (DP) is reflected from the display panel (DP) and provided back to an external user, the user may perceive the external light as if through a mirror. To prevent this phenomenon, for example, the anti-reflection layer (RPL) may include a plurality of color filters that display the same color as the pixels of the display panel (DP).

[0114] Color filters can filter external light to the same color as the pixels. In this case, external light may not be visible to the user. However, not limited thereto, the anti-reflective layer (RPL) may include a phase retarder and / or polarizer to reduce the reflectivity of external light.

[0115] The window (WIN) can be placed on the anti-reflective layer (RPL). The window (WIN) can protect the display panel (DP), input sensor (ISP), and anti-reflective layer (RPL) from external scratches and impacts.

[0116] A panel protection film (PPF) may be placed under a display panel (DP). The panel protection film (PPF) may protect the lower part of the display panel (DP). The panel protection film (PPF) may include a flexible plastic material such as polyethyleneterephthalate (PET).

[0117] A first adhesive layer (AL1) is placed between a display panel (DP) and a panel protection film (PPF), and the display panel (DP) and the panel protection film (PPF) can be bonded together by the first adhesive layer (AL1). A second adhesive layer (AL2) is placed between a window (WIN) and an anti-reflection layer (RPL), and the window (WIN) and the anti-reflection layer (RPL) can be bonded together by the second adhesive layer (AL2).

[0118] FIG. 3 is a cross-sectional view of a display panel according to an embodiment of the present invention. FIG. 3 is a diagram illustrating an exemplary cross-section of the display panel shown in FIG. 2. For example, FIG. 3 shows a cross-section of the display panel (DP) viewed from a second direction (DR2).

[0119] Referring to FIG. 3, the display panel (DP) may include a substrate (SUB), a circuit element layer (DP-CL) disposed on the substrate (SUB), a display element layer (DP-OLED) disposed on the circuit element layer (DP-CL), and a thin film encapsulation layer (TFE) disposed on the display element layer (DP-OLED).

[0120] The substrate (SUB) may include a display area (DA) and a non-display area (NDA) around the display area (DA). The substrate (SUB) may include glass or a flexible plastic material such as polyimide. A display element layer (DP-OLED) may be placed on the display area (DA).

[0121] Multiple pixels may be disposed in the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor disposed in the circuit element layer (DP-CL) and a light-emitting element disposed in the display element layer (DP-OLED) and connected to the transistor.

[0122] A thin film encapsulation layer (TFE) may be disposed on a circuit element layer (DP-CL) to cover a display element layer (DP-OLED). The thin film encapsulation layer (TFE) can protect pixels from moisture, oxygen, and external foreign substances. The thin film encapsulation layer (TFE) may include inorganic layers and an organic layer. The organic layer may be disposed between the inorganic layers and sealed from the inorganic layers to provide a flat surface. According to one embodiment, the organic layer may be disposed on the inorganic layers or omitted, and is not limited to any one embodiment.

[0123] FIG. 4a is a block diagram of a display module according to an embodiment of the present invention of the electronic device shown in FIG. 1a.

[0124] Referring to FIG. 4a, the electronic device (DD) and the display module (DM) may include a display panel (DP), a timing controller (TC), a scan driver (SDC), a data driver (DDV), a light emission driver (EDV), and a voltage generator (VG).

[0125] The display panel (DP) may include a plurality of scan lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm), a plurality of light-emitting lines (EML1~EMLm), a plurality of data lines (DL1~DLn), and a plurality of pixels (PX). m and n are natural numbers.

[0126] Pixels (PX) can be electrically connected to scanning lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm), light emission lines (EML1~EMLm), and data lines (DL1~DLn), respectively. Each pixel (PX) can be electrically connected to four corresponding scanning lines, one corresponding data line, and one corresponding light emission line.

[0127] The scan lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm) may include a plurality of initialization scan lines (GIL1~GILm), a plurality of compensation scan lines (GCL1~GCLm), a plurality of write scan lines (GWL1~GWLm), and a plurality of bias scan lines (GBL1~GBLm).

[0128] Each pixel (PX) can be connected to a corresponding one of the initialization scan lines (GIL1~GILm), a corresponding one of the compensation scan lines (GCL1~GCLm), a corresponding one of the write scan lines (GWL1~GWLm), and a corresponding one of the bias scan lines (GBL1~GBLm).

[0129] Scan lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm) are connected to a scan driver (SDC) and extend in a first direction (DR1) and can be arranged in a second direction (DR2). Light emission lines (EML1~EMLm) are connected to a light emission driver (EDV) and extend in a first direction (DR1) and can be arranged in a second direction (DR2). Data lines (DL1~DLn) are connected to a data driver (DDV) and extend in a second direction (DR2) and can be arranged in a first direction (DR1).

[0130] The scan driver (SDC), light-emitting driver (EDV), and data driver (DDV) can substantially be placed on the display panel (DP), and this configuration will be illustrated below in FIG. 8.

[0131] The timing controller (TC) can receive a video signal (RGB) and a control signal (CTRL). The timing controller (TC) can generate a video data signal (DAS) by converting the data format of the video signal (RGB) to match the interface specifications with the data driver (DDV). In response to the control signal (CTRL), the timing controller (TC) can output a scan control signal (SCS), a data control signal (DCS), and an emission control signal (ECS).

[0132] A voltage generator (VG) can generate voltages required for the operation of a display panel (DP). The voltage generator (VG) can generate a first driving voltage (ELVDD), a second driving voltage (ELVSS), a first initialization voltage (VINT), and a second initialization voltage (VAINT). The first driving voltage (ELVDD), the second driving voltage (ELVSS), the first initialization voltage (VINT), and the second initialization voltage (VAINT) can be applied to pixels (PX).

[0133] The scan driver (SDC) can receive a scan control signal (SCS) from the timing controller (TC). The scan driver (SDC) can output scan signals to scan lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm) in response to the scan control signal (SCS). The scan signals can be applied to pixels (PX) through the scan lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm).

[0134] The data driver (DDV) can receive a data control signal (DCS) and an image data signal (DAS) from the timing controller (TC). The data driver (DDV) can convert the image data signal (DAS) into data signals and output them. The data signals can be defined as analog voltages corresponding to the grayscale levels of the image data signal (DAS). The data signals can be applied to pixels (PX) through data lines (DL1 to DLn).

[0135] The light-emitting driver (EDV) can receive a light-emitting control signal (ECS) from the timing controller (TC). The light-emitting driver (EDV) can output light-emitting signals to the light-emitting lines (EML1 to EMLm) in response to the light-emitting control signal (ECS). The light-emitting signals can be applied to pixels (PX) through the light-emitting lines (EML1 to EMLm).

[0136] Pixels (PX) can receive data voltages in response to scanning signals. Pixels (PX) can display an image by emitting light of a brightness corresponding to the data voltages in response to light emission signals.

[0137] FIG. 4b is a diagram illustrating the equivalent circuit of any one of the pixels shown in FIG. 4a.

[0138] For example, FIG. 4b shows a pixel (PXij) connected to the j-th data line (DLj), the i-th scan lines (GWLi, GCLi, GILi, GBLi), and the i-th emission line (EMLi). i and j are natural numbers.

[0139] Referring to FIG. 4b, a pixel (PXij) may include a pixel circuit (PC) and a light-emitting element (OLED) connected to the pixel circuit (PC). The pixel circuit (PC) can drive the light-emitting element (OLED).

[0140] The pixel circuit (PC) may include a plurality of transistors (T1 to T8) and a capacitor (CST). The transistors (T1 to T8) and the capacitor (CST) can control the amount of current flowing to the light-emitting element (OLED). The light-emitting element (OLED) can generate light having a predetermined brightness according to the amount of current provided.

[0141] The i-th write scan line (GWLi) can receive the i-th write scan signal (GWi), and the i-th compensation scan line (GCLi) can receive the i-th compensation scan signal (GCi). The i-th initialization scan line (GILi) can receive the i-th initialization scan signal (GIi), and the i-th bias scan line (GBLi) can receive the i-th bias scan signal (GBi). The i-th emission line (EMLi) can receive the i-th emission signal (EMi).

[0142] The pixel (PXij) can be connected to the j-th data line (DLj), the i-th write scan line (GWLi), the i-th compensation scan line (GCLi), the i-th initialization scan line (GILi), the i-th bias scan line (GBLi), the i-th light emission line (EMLi), the first initialization line (VIL1), the second initialization line (VIL2), the bias line (VBL), and the first and second power lines (PL1, PL2).

[0143] The first initialization line (VIL1) can receive the first initialization voltage (VINT), and the second initialization line (VIL2) can receive the second initialization voltage (VAINT). The bias line (VBL) can receive the bias voltage (VBIAS). The first power line (PL1) can receive the first driving voltage (ELVDD), and the second power line (PL2) can receive the second driving voltage (ELVSS).

[0144] The transistors (T1 to T8) may each include a source electrode, a drain electrode, and a gate electrode. Hereinafter, for convenience in FIG. 4b, either the source electrode or the drain electrode is defined as the first electrode and the other as the second electrode. Additionally, the gate electrode is defined as the control electrode.

[0145] The transistors (T1 to T8) may include the first to eighth transistors (T1 to T8). The first, second, and fifth to eighth transistors (T1, T2, T5 to T8) may be PMOS transistors. The third and fourth transistors (T3, T4) may be NMOS transistors.

[0146] The first transistor (T1) can be defined as a driving transistor, and the second transistor (T2) can be defined as a switching transistor. The third transistor (T3) can be defined as a compensation transistor. The fourth transistor (T4) and the seventh transistor (T7) can be defined as initialization transistors. The fifth transistor (T5) and the sixth transistor (T6) can be defined as light emission control transistors. The eighth transistor (T8) can be defined as a bias transistor.

[0147] A light-emitting element (OLED) can be defined as an organic light-emitting element. The light-emitting element (OLED) may include a first electrode (AE) and a second electrode (CE). The first electrode (AE) may receive a first driving voltage (ELVDD) through the sixth, first, and fifth transistors (T6, T1, T5). The first driving voltage (ELVDD) may be applied to a pixel circuit (PC) through a first power line (PL1).

[0148] The second electrode (CE) can receive a second driving voltage (ELVSS) having a level lower than the first driving voltage (ELVDD). The second driving voltage (ELVSS) can be applied to the pixel circuit (PC) through the second power line (PL2).

[0149] The first transistor (T1) is positioned between the fifth transistor (T5) and the sixth transistor (T6) and can be connected to the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) can be connected to the first power line (PL1) through the fifth transistor (T5) and to the first electrode (AE) through the sixth transistor (T6).

[0150] The first transistor (T1) may include a first electrode connected to the first power line (PL1) through the fifth transistor (T5), a second electrode connected to the first electrode (AE) through the sixth transistor (T6), and a control electrode connected to the first node (N1).

[0151] The first electrode of the first transistor (T1) can be connected to the fifth transistor (T5), and the second electrode of the first transistor (T1) can be connected to the sixth transistor (T6). The first transistor (T1) can control the amount of current flowing to the light-emitting element (OLED) according to the voltage of the first node (N1) applied to the control electrode of the first transistor (T1).

[0152] The second transistor (T2) may be positioned between the first transistor (T1) and the j-th data line (DLj) and connected to the first transistor (T1) and the j-th data line (DLj). The second transistor (T2) may include a first electrode connected to the j-th data line (DLj), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the i-th write scan line (GWLi).

[0153] The second transistor (T2) can be turned on by the i-th write scan signal (GWi) applied through the i-th write scan line (GWLi) to electrically connect the j-th data line (DLj) and the first electrode of the first transistor (T1). The second transistor (T2) can perform a switching operation to provide the data voltage (VD) (corresponding to the aforementioned data signal) applied through the j-th data line (DLj) to the first electrode of the first transistor (T1).

[0154] The third transistor (T3) can be connected to the second electrode of the first transistor (T1) and the first node (N1). The third transistor (T3) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the first node (N1), and a control electrode connected to the i-th compensation scan line (GCLi).

[0155] The third transistor (T3) can be turned on by the i-th compensation scan signal (GCi) applied through the i-th compensation scan line (GCLi) to electrically connect the second electrode of the first transistor (T1) and the control electrode of the first transistor (T1). When the third transistor (T3) is turned on, the first transistor (T1) and the third transistor (T3) can be connected in the form of a diode.

[0156] The fourth transistor (T4) may be connected to the first node (N1). The fourth transistor (T4) may include a first electrode connected to the first node (N1), a second electrode connected to the first initialization line (VIL1), and a control electrode connected to the i-th initialization scan line (GILi). The fourth transistor (T4) may be turned on by the i-th initialization scan signal (GIi) applied through the i-th initialization scan line (GILi) to provide the first initialization voltage (VINT) applied through the first initialization line (VIL1) to the first node (N1).

[0157] The fifth transistor (T5) may include a first electrode connected to the first power line (PL1), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the i-th light-emitting line (EMLi).

[0158] The sixth transistor (T6) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the first electrode (AE), and a control electrode connected to the i-th light-emitting line (EMLi).

[0159] The fifth transistor (T5) and the sixth transistor (T6) can be turned on by the i-th light emission signal (EMi) applied through the i-th light emission line (EMLi). By turning on the fifth transistor (T5) and the sixth transistor (T6), a first driving voltage (ELVDD) is provided to the light-emitting element (OLED), and a driving current can flow through the light-emitting element (OLED). Thus, the light-emitting element (OLED) can emit light.

[0160] The seventh transistor (T7) may include a first electrode connected to the first electrode (AE), a second electrode connected to the second initialization line (VIL2), and a control electrode connected to the i-th bias scan line (GBLi). The seventh transistor (T7) may be turned on by the i-th bias scan signal (GBi) applied through the i-th bias scan line (GBLi) to provide the second initialization voltage (VAINT) received through the second initialization line (VIL2) to the first electrode (AE) of the light-emitting element (OLED).

[0161] In an embodiment of the present invention, the second initialization voltage (VAINT) may have a different level from the first initialization voltage (VINT), but is not limited thereto and may have the same level as the first initialization voltage (VINT).

[0162] The seventh transistor (T7) can improve the black expression capability of the pixel (PXij). When the seventh transistor (T7) is turned on, the parasitic capacitor (not shown) of the light-emitting element (OLED) can be discharged. Therefore, when black luminance is implemented, the light-emitting element (OLED) does not emit light due to the leakage current of the first transistor (T1), and accordingly, the black expression capability can be improved.

[0163] The capacitor (CST) may include a first electrode connected to the first power line (PL1) and a second electrode connected to the first node (N1). When the fifth transistor (T5) and the sixth transistor (T6) are turned on, the amount of current flowing through the first transistor (T1) can be determined according to the voltage stored in the capacitor (CST).

[0164] The eighth transistor (T8) may include a first electrode connected to the bias line (VBL), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the i-th bias scan line (GBLi).

[0165] The eighth transistor (T8) is turned on by the i-th bias scan signal (GBi) and can provide a bias voltage (VBIAS) applied through the bias line (VBL) to the first electrode of the first transistor (T1). However, the transistors included in the pixel (PXij) are not limited to this.

[0166] FIG. 5a is a plan view of a pixel unit according to an embodiment of the present invention. FIG. 5b is a plan view briefly illustrating a part of a display area according to an embodiment of the present invention.

[0167] Referring to FIG. 5a, in this embodiment, one pixel unit may include the pixels described in FIG. 4a and 4b. A plurality of pixel units may be provided and arranged along the first and second diagonal directions (CDR1, CDR2) within the display area (DA) described in FIG. 1a.

[0168] A pixel unit according to one embodiment may include first-1 to third pixels (PX-G1, PX-G2, PX-R, PX-B).

[0169] The first-1 pixel (PX-G1) can provide green light. The light generated from the first-1 pixel (PX-G1) can be provided to the display area (DA, see FIG. 1a) through the first-1 light-emitting region (PXA-G1). In this embodiment, the first-1 light-emitting region (PXA-G1) may be an octagonal shape extended along the second diagonal direction (CDR2).

[0170] The first-2 pixel (PX-G2) can provide green light similar to the first-1 pixel (PX-G1). The light generated from the first-2 pixel (PX-G2) can be provided to the display area (DA, see FIG. 1a) through the first-2 light-emitting region (PXA-G2). The first-2 light-emitting region (PXA-G2) can be spaced apart from the first-1 light-emitting region (PXA-G1) along the second direction (DR2). In this embodiment, the first-2 light-emitting region (PXA-G2) may be an octagonal shape extended along the first diagonal direction (CDR1).

[0171] The second pixel (PX-R) can provide red light. The light generated from the second pixel (PX-R) can be provided to the display area (DA, see FIG. 1a) through the second light-emitting region (PXA-R). The second light-emitting region (PXA-R) can be spaced apart from the third light-emitting region (PXA-B) along the first direction (DR1). The second light-emitting region (PXA-R) can be spaced apart from the first-1 light-emitting region (PXA-G1) along the second diagonal direction (CDR2) and spaced apart from the first-2 light-emitting region (PXA-G2) along the first diagonal direction (CDR1). In this embodiment, the second light-emitting region (PXA-R) may have a rhombus-shaped octagon.

[0172] The third pixel (PX-B) can provide blue light. The light generated from the third pixel (PX-B) can be provided to the display area (DA, see FIG. 1a) through the third light-emitting region (PXA-B). The third light-emitting region (PXA-B) may be spaced apart from the first-1 light-emitting region (PXA-G1) along the first diagonal direction (CDR1) and spaced apart from the first-2 light-emitting region (PXA-G2) along the second diagonal direction (CDR2). In this embodiment, the third light-emitting region (PXA-B) may have a rhombus-shaped octagon.

[0173] According to one embodiment, the area of ​​the second light-emitting region (PXA-R) may be larger than the area of ​​the first-1 and first-2 light-emitting regions (PXA-G1, PXA-G2) and smaller than the area of ​​the third light-emitting region (PXA-B).

[0174] In FIG. 5a, a dotted line surrounding each light-emitting region is shown, and the dotted line surrounding the first to third light-emitting regions (PXA-G1, PXA-G2, PXA-R, PXA-B) may correspond to the first electrode (anode) included in each of the first to third pixels (PX-G1, PX-G2, PX-R, PX-B).

[0175] The region between the first to third light-emitting regions (PXA-G1, PXA-G2, PXA-R, PXA-B) can be defined as a non-light-emitting region (NPXA).

[0176] A non-luminous region (NPXA) according to the present invention may include a normal region (A0), support regions (A1), and contact regions (A2). The support regions (A1) and contact regions (A2) may be surrounded by the normal region (A0). The support regions (A1) and contact regions (A2) may be adjacent to the corners of the luminous regions. The support regions (A1) and contact regions (A2) may be spaced apart from each other.

[0177] In this specification, the normal region (A0) may be defined as a region in which a partition (WA, see FIG. 6) is disposed on a pixel defining film (PDL, see FIG. 6).

[0178] The support regions (A1) can be defined as regions where a spacer (SP, see FIG. 8), described later, is placed. The spacer (SP) may be a structure that supports the mask (MS, see FIG. 8). A description regarding this will be provided later.

[0179] The contact regions (A2) can be defined as regions where the contact holes (CNT, see FIG. 9) defined in the insulating layers and the contact barrier (WA-C, see FIG. 9) come into contact. The second power line (PL2) described in FIG. 4a can be connected to the conductive pattern contained in the contact barrier (WA-C, see FIG. 9) through the contact holes (CNT, see FIG. 9).

[0180] According to the present invention, the second power line (PL2) described in FIG. 4a may be arranged to overlap with the display area (DA). The second power line (PL2) may include lines (P-1 to P-6) arranged along a first direction (DR1) and each extending along a second direction (DR2). Each of the lines (P-1 to P-6) may overlap with at least one contact area (A2) and a support area (A1). The number of contact areas (A2) and support areas (A1) that each of the lines (P-1 to P-6) overlaps may differ from one another. Each of the lines (P-1 to P-6) may be connected to at least one pixel through the contact area (A2). An explanation regarding this will be provided later.

[0181] FIG. 5b is a simplified plan view of the display area (DA).

[0182] Referring to FIG. 5b, a light-emitting region (PXA) included in a pixel unit may include first to third light-emitting regions (PXA-G1, PXA-G2, PXA-R, PXA-B), and a non-light-emitting region (NPXA) may include a normal region (A0), at least one support region (A1), and contact regions (A2).

[0183] A normal region (A0) occupies most of the non-emissive region (NPXA), and a support region (A1) may be positioned between the normal regions (A0). For example, one support region (A1) may be surrounded by emissive regions (PXA-G1, PXA-G2, PXA-R, PXA-B) included in one pixel unit. Contact regions (A2) may be positioned at the outer edge of the emissive regions (PXA-G1, PXA-G2, PXA-R, PXA-B). For example, each of the contact regions (A2) may be positioned adjacent to the outermost corner of the emissive regions (PXA-G1, PXA-G2, PXA-R, PXA-B). However, this is exemplary, and one pixel unit may include at least one support region (A1), and is not limited to any one embodiment. The spacer (SP, see FIG. 8) placed in the support area (A1) can be spaced apart from the adjacent bulkhead (WA, see FIG. 8). An explanation regarding this will be provided later.

[0184] FIG. 6 is a cross-sectional view taken along I-I' of FIG. 5a. FIG. 7 is an enlarged cross-sectional view of the bulkhead shown in FIG. 6. FIG. 8 is a cross-sectional view taken along II-II' of FIG. 5a. FIG. 9 is a cross-sectional view taken along III-III' of FIG. 5a.

[0185] FIG. 6 shows a cross-sectional view of the first pixel (PX-G1) illustrated in FIG. 5a. Referring to FIG. 6, a light-emitting element (OLED-G1) according to one embodiment may include a first electrode (AE-G1), a second electrode (CE), and a common layer (CL-G1). The common layer (CL-G1) may include a hole control layer, an electron control layer, and a light-emitting layer, etc.

[0186] A second electrode (CE) may be disposed on a first electrode (AE-G1), and a common layer (CL-G1) may be disposed between the first electrode (AE-G1) and the second electrode (CE). A light-emitting element (OLED-G1) according to one embodiment may further include a protective layer disposed on the second electrode (CE). The protective layer comprises an organic material and can prevent damage to components disposed beneath the protective layer during a subsequent process. According to one embodiment, the protective layer may be omitted.

[0187] The first, fourth, and sixth transistors (T1, T4, T6) and the light-emitting element (OLED-G1) may be disposed on a substrate (SUB). The display area (DA, see FIG. 1a) may include a first-1 light-emitting area (PXA-G1) and a non-light-emitting area (NPXA) adjacent to the first-1 light-emitting area (PXA-G1). FIG. 6 shows a barrier (WA) disposed in the normal area (A0) of the non-light-emitting area (NPXA).

[0188] The substrate (SUB) may include glass or a flexible plastic material such as polyimide. A circuit element layer (DP-CL), a display element layer (DP-OLED), a barrier (WA), and a thin film encapsulation layer (TFE) may be disposed on the substrate (SUB). The circuit element layer (DP-CL) may be disposed on the substrate (SUB). The circuit element layer (DP-CL) may include insulating layers. The display element layer (DP-OLED) may include a light-emitting element (OLED-G1) and a pixel defining film (PDL).

[0189] A barrier layer (BRL) can be disposed on a substrate (SUB). The barrier layer (BRL) can increase the bonding strength between the semiconductor pattern included in the transistors and the substrate (SUB). The barrier layer (BRL) may include an inorganic material.

[0190] A metal layer (BML) may be disposed on the barrier layer (BRL). The metal layer (BML) may be superimposed on the first transistor (T1). According to one embodiment, the metal layer (BML) may receive a positive voltage. When a positive voltage is applied to the metal layer (BML), the threshold voltage (Vth) value of the first transistor (T1) disposed on the metal layer (BML) may be maintained without changing.

[0191] The metal layer (BML) can block light incident on the first transistor (T1) from the bottom of the metal layer (BML). The metal layer (BML) may include a reflective metal. According to one embodiment, the metal layer (BML) may be omitted.

[0192] The buffer layer (BFL) is placed on the barrier layer (BRL) and can cover the metal layer (BML). The buffer layer (BFL) may include an inorganic material.

[0193] Semiconductor layers (S1, A1, Dr1) of the first transistor (T1) and semiconductor layers (S6, A6, Dr6) of the sixth transistor (T6) may be disposed on the buffer layer (BFL). The semiconductor layers (S1, A1, Dr1, S6, A6, Dr6) may include polysilicon. However, not limited thereto, the semiconductor layers (S1, A1, Dr1, S6, A6, Dr6) may include amorphous silicon.

[0194] The semiconductor layers (S1, A1, Dr1, S6, A6, Dr6) may be doped with an N-type dopant or a P-type dopant. The semiconductor layers (S1, A1, Dr1, S6, A6, Dr6) may include a high-doping region and a low-doping region. The conductivity of the high-doping region is greater than that of the low-doping region and may substantially serve as the source electrode and drain electrode of the first and sixth transistors (T1, T6). The low-doping region may substantially correspond to the active (or channel) of the first and sixth transistors (T1, T6).

[0195] The first source region (S1), the first channel region (A1), and the first drain region (Dr1) of the first transistor (T1) may be formed from semiconductor layers (S1, A1, Dr1). The sixth source region (S6), the sixth channel region (A6), and the sixth drain region (Dr6) of the sixth transistor (T6) may be formed from semiconductor layers (S6, A6, Dr6). The first channel region (A1) may be positioned between the first source region (S1) and the first drain region (Dr1). The sixth channel region (A6) may be positioned between the sixth source region (S6) and the sixth drain region (Dr6).

[0196] A first insulating layer (INS1) may be disposed on a buffer layer (BFL) to cover semiconductor layers (S1, A1, Dr1, S6, A6, Dr6). A first gate electrode (G1, or control electrode) of a first transistor (T1) and a sixth gate electrode (G6, or control electrode) of a sixth transistor (T6) may be disposed on the first insulating layer (INS1). When viewed in a planar view, the first gate electrode (G1) may overlap the first channel region (A1), and the sixth gate electrode (G6) may overlap the sixth channel region (A6).

[0197] Although not illustrated, the structure of the source region, channel region, drain region, and gate electrode of each of the second, fifth, and seventh transistors (T2, T5, T7) may be substantially the same as that of the first and sixth transistors (T1, T6).

[0198] A second insulating layer (INS2) may be disposed on a first insulating layer (INS1) to cover the first and sixth gate electrodes (G1, G6). A dummy electrode (DME) may be disposed on the second insulating layer (INS2). The dummy electrode (DME) is disposed on the first gate electrode (G1) and may overlap the first gate electrode (G1) when viewed in a planar view. The dummy electrode (DME) may form the aforementioned capacitor together with the first gate electrode (G1).

[0199] A third insulating layer (INS3) may be disposed on a second insulating layer (INS2) to cover a dummy electrode (DME). A semiconductor layer (S4, A4, Dr4) of a fourth transistor (T4) may be disposed on the third insulating layer (INS3). The semiconductor layer (S4, A4, Dr4) may include an oxide semiconductor formed of a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0200] The semiconductor layer (S4, A4, Dr4) may include multiple regions distinguished by whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, reduced region) may have greater conductivity than the region where it is not reduced (hereinafter, non-reduced region). The reduced region may substantially serve as the source electrode or drain electrode of the fourth transistor (T4). The non-reduced region may substantially correspond to the active (or channel) of the fourth transistor (T4).

[0201] The fourth source region (S4), the fourth channel region (A4), and the fourth drain region (Dr4) of the fourth transistor (T4) can be formed from semiconductor layers (S4, A4, Dr4). The fourth channel region (A4) can be positioned between the fourth source region (S4) and the fourth drain region (Dr4).

[0202] A fourth insulating layer (INS4) may be disposed on a third insulating layer (INS3) to cover the semiconductor layer (S4, A4, Dr4). A fourth gate electrode (G4) of a fourth transistor (T4) may be disposed on the fourth insulating layer (INS4). When viewed in a planar view, the fourth gate electrode (G4) may overlap with the fourth channel region (A4).

[0203] A fifth insulating layer (INS5) may be disposed on the fourth insulating layer (INS4) to cover the fourth gate electrode (G4). Although not illustrated, the structure of the source region, channel region, drain region, and gate electrode of the third transistor (T3) may be substantially the same as that of the fourth transistor (T4).

[0204] The barrier layer (BRL), buffer layer (BFL), and first to fifth insulating layers (INS1~INS5) may comprise inorganic materials. For example, the barrier layer (BRL), buffer layer (BFL), and first to fifth insulating layers (INS1~INS5) may comprise either silicon oxide or silicon nitride, or one of the barrier layer (BRL), buffer layer (BFL), and first to fifth insulating layers (INS1~INS5) may comprise a multilayer inorganic layer, and is not limited to any specific embodiment. The multilayer inorganic layer may have a structure in which layers comprising silicon nitride and silicon oxide are alternately stacked.

[0205] A connecting electrode (CNE) may be disposed between the sixth transistor (T6) and the light-emitting element (OLED-G1). The connecting electrode (CNE) may electrically connect the sixth transistor (T6) and the light-emitting element (OLED-G1). The connecting electrode (CNE) may include a first connecting electrode (CNE1) and a second connecting electrode (CNE2) disposed on the first connecting electrode (CNE1).

[0206] A first connecting electrode (CNE1) is disposed on a fifth insulating layer (INS5) and can be connected to a sixth drain region (Dr6) through a first contact hole (CE-2H1) defined in the first to fifth insulating layers (INS1~INS5). A sixth insulating layer can be disposed on the fifth insulating layer (INS5) to cover the first connecting electrode (CNE1).

[0207] The second connecting electrode (CNE2) may be disposed on the sixth insulating layer (INS6). The second connecting electrode (CNE2) may be connected to the first connecting electrode (CNE1) through a second contact hole (CE-3H2) defined in the sixth insulating layer (INS6).

[0208] According to the present embodiment, the second power line (PL2) is disposed on the sixth insulating layer (INS6) and can be covered by the seventh insulating layer (INS7, "intermediate insulating layer" of the claim).

[0209] A seventh insulating layer (INS7) may be disposed on a sixth insulating layer (INS6) to cover a second connecting electrode (CNE2). The sixth and seventh insulating layers (INS6, INS7) may include either an organic material or an inorganic material.

[0210] The lines (P-1 to P-6) of the second power line (PL2) described in FIG. 5a can be placed on the sixth insulating layer (INS6) and covered by the seventh insulating layer (INS7).

[0211] A pixel defining film (PDL) may be disposed on a seventh insulating layer (INS7). An opening (PDL-OP) that exposes at least a portion of the first electrode (AE-G1) may be defined in the pixel defining film (PDL). The opening (PDL-OP) may correspond to the light-emitting region described above. In this embodiment, the pixel defining film (PDL) may include an organic material having light-blocking properties. According to the present invention, the pixel defining film (PDL) may have a predetermined color. Within the display area (DA, see FIG. 1a), the normal region (A0) among the non-light-emitting regions (NPXA) is defined as the region where the pixel defining film (PDL) is disposed, and the light-emitting regions may be defined as regions that overlap with the openings (PDL-OP) defined in the pixel defining film (PDL).

[0212] The light-emitting element (OLED-G1) may include a first electrode (AE-G1), a common layer (CL-G1), and a second electrode (CE). The first electrode (AE-G1) is disposed on a seventh insulating layer (INS7, inter-layer insulating layer) and a portion of it may be exposed by an opening (PDL-OP).

[0213] A common layer (CL-G1) included in a light-emitting element (OLED-G1) may be disposed on the first electrode (AE-G1). The common layer (CL-G1) may include a hole control layer, an electron control layer, and a light-emitting layer, etc.

[0214] The second electrode (CE) may be disposed on the common layer (CL-G1). The second electrode (CE) may be an integral pattern disposed commonly among the light-emitting elements. According to one embodiment, the second electrode (CE) may comprise a silver-magnesium alloy (AgMg).

[0215] As illustrated in FIG. 7, the barrier (WA) can be disposed on the pixel defining film (PDL). More specifically, the barrier (WA) can be disposed entirely on the pixel defining film (PDL), excluding the support regions (A1) within the non-emissive region (NPXA).

[0216] A partition wall (WA) according to one embodiment may include a first insulation pattern (IN1), a second insulation pattern (IN2), a third insulation pattern (IN3), a first partition wall pattern (W1), and a second partition wall pattern (W2).

[0217] The first insulating pattern (IN1) may be placed directly on the pixel defining film (PDL). The first insulating pattern (IN1) may include an inorganic material. The second insulating pattern (IN2) may be placed on the first insulating pattern (IN1). The third insulating pattern (IN3) may be placed on the second insulating pattern (IN2). The first to third insulating patterns (IN1, IN2, IN3) may include different materials.

[0218] For example, the first insulation pattern (IN1) may include at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide. The second insulation pattern (IN2) and the third insulation pattern (IN3) may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0219] In this embodiment, the first insulation pattern (IN1) may be configured to disconnect the P-type hole injection layer among the layers included in the first common layer (CL-G1). Accordingly, the thickness of the first insulation pattern (IN1) may be thicker than the thickness of the P-type hole injection layer among the layers included in the first common layer (CL-G1).

[0220] According to one embodiment, the width of the second insulating pattern (IN2) in cross-section may be smaller than the widths of the first insulating pattern (IN1) and the third insulating pattern (IN3). The difference in width may be formed due to the difference in etching rates with respect to the etching solution of the first to third insulating patterns (IN1, IN2, IN3).

[0221] Common layers included in different pixels are separated from each other by a partition (WA) between them by first to third insulation patterns (IN1, IN2, IN3), and the separated common layers can come into contact with the sides of the first to third insulation patterns (IN1, IN2, IN3) and the upper surface of the third insulation pattern (IN3).

[0222] A first barrier pattern (W1) is placed on a third insulation pattern (IN3). The first barrier pattern (W1) may include a metal. For example, the first barrier pattern (W1) may include aluminum. As the first barrier pattern (W1) includes aluminum, the side (W1-S) of the first barrier pattern (W1) may be oxidized and not conductive. Therefore, the inner side (W1-I) of the side (W1-S) of the first barrier pattern (W1) may be defined as an insulating region.

[0223] A second bulkhead pattern (W2) may be placed on a first bulkhead pattern (W1). The second bulkhead pattern (W2) may include a metal different from that of the first bulkhead pattern (W1). For example, the second bulkhead pattern (W2) may include titanium.

[0224] According to the present embodiment, the thickness of the first partition pattern (W1) may be greater than the thickness of the second partition pattern (W2), and the width of the first partition pattern (W1) may be smaller than the width of the second partition pattern (W2). According to one embodiment, a portion of the second partition pattern (W2) may protrude from the first partition pattern (W1) and be exposed from the first partition pattern (W1). Thus, the lower surface (W2-B) of the second partition pattern (W2) may be exposed from the first partition pattern (W1). This may be formed due to the difference in etching rates with respect to the etching solution between the first partition pattern (W1) and the second partition pattern (W2). The first partition pattern (W1) and the second partition pattern (W2) may be defined as having a tip structure.

[0225] According to the present invention, a partition wall (WA) disposed in a normal region (A0) may be disposed spaced apart from a mask (MS) by a predetermined space (SS). Accordingly, in the normal region (A0), the mask (MS) is spaced apart from the partition wall (WA), and thus, damage is not applied during the process of using the mask (MS), thereby stably maintaining the tip structure of the partition wall (WA) disposed in the normal region (A0). The mask (MS) may be a fine metal mask used in the process of forming a common layer (CL-G1, see FIG. 6) before forming the second electrode (CE).

[0226] The second electrode (CE) can extend from the light-emitting regions to the non-light-emitting region (NPXA) to cover the partition (WA). The second electrode (CE) overlapping with the partition (WA) can come into contact with the side (W1-S) of the first partition pattern (W1), the lower surface (W2-B) of the second partition pattern (W2) exposed from the first partition pattern (W1), and the side (W2-S) of the second partition pattern (W2).

[0227] According to one embodiment, a dummy pattern (CL-P) may be disposed on the partition wall (WA). More specifically, a dummy pattern (CL-P) may be disposed between the upper surface of the second partition wall pattern (W2) and the second electrode (CE). The dummy pattern (CL-P) may be a portion that is disconnected by the partition wall (WA) during the process of forming the common layer (CL-G1, CL-G2).

[0228] As described above, since the inner side (W1-I) of the first partition pattern (W1) includes an oxidized and non-conductive insulating region, the second electrode (CE) covering the partition (WA) can be connected to other parts of the second electrode (CE) through the lower surface (W2-B) and the side surface (W2-S) of the second partition pattern (W2) exposed from the first partition pattern (W1).

[0229] According to one embodiment, the first thickness of the second electrode (CE) disposed on the common layer (CL-G1) may be greater than the second thickness of the second electrode (CE) covering the partition (WA). According to one embodiment, the second electrode (CE) may contact only a portion of the side (W1-S) of the first partition pattern (W1) and may be disconnected at the side (W1-S) of the first partition pattern (W1). The remaining portion of the second electrode (CE) may contact the side (W2-S) of the second partition pattern (W2) and the dummy pattern (CL-P). The second electrode (CE) disconnected on the partition (WA) may be electrically connected by the partition (WA) as it comes into contact with the partition (WA) containing a conductive material.

[0230] The thin film encapsulation layer (TFE) can be disposed on the light-emitting element (OLED-G1) to cover the light-emitting element (OLED-G1). The thin film encapsulation layer (TFE) can be disposed over the entire area of ​​the display area (DA). The thin film encapsulation layer (TFE) may include inorganic film layers and an organic layer disposed between the inorganic film layers, and is not limited to any one embodiment. Among the inorganic layers included in the thin film encapsulation layer (TFE), the lower inorganic layer is directly disposed on the second electrode (CE) and can cover the second electrode (CE) in a shape corresponding to the formation of the second electrode (CE).

[0231] FIG. 8 is a cross-sectional view taken along II-II' of FIG. 5a. FIG. 9 is a cross-sectional view taken along III-III' of FIG. 5a.

[0232] Referring to FIG. 8, according to the present embodiment, spacers (SP) may be disposed in the support regions (A1) among the non-emissive regions (NPXA, see FIG. 6). The spacers (SP) may be disposed on the pixel defining film (PDL).

[0233] A barrier (WA) may be disposed in the normal region (A0) of the non-emissive region (NPXA), and a spacer (SP) may be disposed in each of the support regions (A1). The barrier (WA) and the spacer (SP) may be disposed directly on the pixel defining film (PDL). The spacers (SP) according to the present invention may be surrounded by the barrier (WA) and spaced apart from the barrier (WA) by a predetermined distance. The barrier (WA) and the spacer (SP) may be covered by a second electrode (CE). An inorganic layer included in the thin film encapsulation layer (TFE) described in FIG. 6 may be disposed on the second electrode (CE) covering the barrier (WA) and the spacer (SP).

[0234] According to one embodiment, at least one spacer (SP) may overlap with the second power line (PL2). FIG. 8 illustrates, by way of example, overlapping with the sixth line (P-6) included in the second power line (PL2).

[0235] The spacer (SP) may include a transparent organic material such as polyimide. According to one embodiment, the spacer (SP) may include the same material as the pixel defining film (PDL). For example, the spacer (SP) and the pixel defining film (PDL) may include a colored organic material having light-blocking properties.

[0236] According to the present invention, the area in which spacers (SP) are arranged within a display area (DA, see FIG. 1a and FIG. 5) may be 1% to 10% of the total area of ​​the display area (DA, see FIG. 1a and FIG. 5).

[0237] According to the present invention, the first thickness (TH1) of the spacer (SP) may be greater than the second thickness (TH2) of the partition wall (WA). Accordingly, in a process using a mask (MS), the partition wall (WA) is spaced apart from the mask (MS) by a predetermined space (SS), and the mask (MS) can be supported by the spacer (SP). A process of forming common layers (CL-R, CL-B) can be carried out while the mask (MS) is supported by the spacer (SP). Therefore, when using the mask (MS), the mask (MS) and the partition wall (WA) are spaced apart in the normal region (A0), thereby allowing the tip structure of the partition wall (WA) to be maintained more stably.

[0238] Referring to FIG. 9, contact holes (CNT) that expose a second power line (PL2) may be defined in the contact areas (A2). FIG. 9 illustrates that a portion of the fourth line (P-4) among the lines (P-1 to P-6, see FIG. 5) crossing the display area (DA, see FIG. 5a) is exposed by the contact hole (CNT).

[0239] According to the present embodiment, the contact hole (CNT) may be formed by a first hole (C1) penetrating the seventh insulating layer (INS7) and a second hole (C2) that overlaps with the first hole (C1) and penetrates the pixel defining film (PDL). The width of the second hole (C2) may be greater than the width of the first hole (C1).

[0240] As the barrier (WA) is positioned inside the contact holes (CNT) in the contact regions (A2), the shape of the barrier (WA) in the contact regions (A2) may differ from the shape in the normal region (A0). For convenience of explanation, the barrier (WA) overlapping with the contact regions (A2) will be described as the contact barrier (WA-C).

[0241] The first to third insulating patterns (IN1-C, IN2-C, IN3-C) of the contact barrier (WA-C) can cover the side of the pixel defining film (PLD) defining the first hole (C1) and the side of the seventh insulating layer (IN7) defining the second hole (C2). The first to third insulating patterns (IN1-C, IN2-C, IN3-C) can expose the fourth line (P-4) together with the first hole (C1). However, this is not limited thereto, and the first insulating pattern (IN1-C) may be placed only on the pixel defining film (PDL) and spaced apart from the contact hole (CNT).

[0242] The first partition pattern (W1-C) is placed on the third insulation pattern (IN3-C) and the fourth line (P-4) and can come into contact with the fourth line (P-4). A second partition pattern (W2-C) is placed on the first partition pattern (W1-C), and a second electrode (CE) can be placed on the second partition pattern (W2-C).

[0243] According to the present invention, in a process using a mask (MS), the contact barrier (WA-C) can be spaced apart from the mask (MS) by a predetermined space (SS). Therefore, the contact barrier (WA-C) may not be damaged in the process using the mask (MS). Consequently, the contact structure between the contact barrier (WA-C) and the second power line (PL2) can be stably maintained.

[0244] According to the present invention, as a second electrode (CE) within a display area (DA, see FIG. 1a) is connected to a second power line (PL2) disposed in the display area (DA, see FIG. 5a) through a partition (WA), a voltage drop phenomenon can be prevented, thereby providing a constant voltage to the pixels. In addition, as the connection between the second electrode (CE) and the second power line (PL2) is made within the display area (DA, see FIG. 5a), unnecessary space for connecting the second electrode (CE) and the second power line (PL2) in a non-display area (NDA) can be reduced. Furthermore, pixel units with different resolutions can be driven individually.

[0245] FIG. 10 is a cross-sectional view of a support region of an electronic device according to an embodiment of the present invention. FIG. 11 is a cross-sectional view of a support region of an electronic device according to an embodiment of the present invention. Identical or similar reference numerals are assigned to configurations identical or similar to FIG. 6 to 9, and redundant descriptions are omitted.

[0246] Referring to FIG. 10, the pixel defining film (PDL-A) according to the present embodiment may be disposed on the seventh insulating layer (INS7). According to the present embodiment, the pixel defining film (PDL-A) in the region overlapping with the support regions (A1) and the region overlapping with the spacers (SP) may be larger than the height of the pixel defining film (PDL-A) overlapping with the partition wall (WA).

[0247] The pixel defining film (PDL-A) according to the present embodiment may include a first pattern (P1) disposed over the entire normal region (A0) and support regions (A1), and a second pattern (P2) disposed on the first pattern (P1) and overlapping with spacers (SP). The first pattern (P1) and the second pattern (P2) may be formed by a half-tone exposure process.

[0248] Therefore, the height of the spacer (SP-A) placed on the second pattern (P2) from the seventh insulating layer (INS7) may be greater than the height of the partition wall (WA). Thus, in a process using a mask (MS), the mask (MS) comes into contact only with the spacers (SP-A), so that damage to the partition wall (WA) may not be applied.

[0249] Referring to FIG. 11, a spacer (SP-B) placed in a support area (A1) may have a structure in which multiple organic layers are stacked. For example, the spacer (SP-B) may include a first pattern (SP1) and a second pattern (SP2). The first pattern (SP1) may be placed directly on a pixel defining film (PDL). The second pattern (SP2) may be placed directly on the first pattern (SP1). The first pattern (SP1) and the second pattern (SP2) may include either a transparent organic material or a colored organic material having light-blocking properties.

[0250] According to the present embodiment, the spacer (SP-B) may have a height greater than that of the partition wall (WA) as it includes multiple organic layers. Therefore, the height from the pixel definition film (PDL) to the spacer (SP-B) may be greater than the height of the partition wall (WA). Consequently, in a process using a mask (MS), the mask (MS) comes into contact only with the spacers (SP-B), so that damage to the partition wall (WA) may not be applied.

[0251] FIG. 12 is an enlarged view of a display area according to an embodiment of the present invention. Identical or similar reference numerals are assigned to configurations identical or similar to FIG. 5a through 9, and redundant descriptions are omitted.

[0252] Referring to FIG. 12, a pixel unit according to the present embodiment may include a light-emitting region (PXA-A) and a non-light-emitting region (NPXA). The light-emitting region (PXA-A) may include first-1 to third light-emitting regions (PXA-G1, PXA-G2, PXA-R, PXA-B) and may include a normal region (A0), support regions (A1), and contact regions (A2). The contact regions (A2) may be adjacent to the corners of the light-emitting regions. The support regions (A1) and the contact regions (A2) may be spaced apart from each other. The support region (A1) may be surrounded by the first-1 to third light-emitting regions (PXA-G1, PXA-G2, PXA-R, PXA-B).

[0253] According to the present embodiment, the shape of the first to third light-emitting regions (PXA-G1, PXA-G2, PXA-R, PXA-B) may be modified to increase the area of ​​the spacer (SP, see FIG. 8) placed in the support region (A1). According to the present embodiment, a recess region (RS) recessed inwardly into the light-emitting region may be defined at each corner of the first to third light-emitting regions (PXA-G1, PXA-G2, PXA-R, PXA-B) adjacent to the spacer (SP). The dotted line surrounding the first to third light-emitting regions (PXA-G1, PXA-G2, PXA-R, PXA-B) may correspond to the first electrode (AE, see FIG. 6) of the light-emitting element (OLED-G1, see FIG. 5a).

[0254] According to the present embodiment, by deforming the shape of the first to third light-emitting regions (PXA-G1, PXA-G2, PXA-R, PXA-B) within the display area (DA), an area for placing a spacer (SP) can be secured.

[0255] The above description is merely an example of the technical features of the present invention, and those skilled in the art may make various modifications and variations. Accordingly, the embodiments of the present invention described above may be implemented individually or in combination with one another.

[0256] Accordingly, the embodiments disclosed in this specification are intended to illustrate, not limit, the technical concept of the invention, and the scope of the technical concept of the invention is not limited by these embodiments. The scope of protection of the invention shall be interpreted by the claims set forth below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of the invention.

[0257] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0258] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

[0259] According to the present invention, since the second electrode is connected to the power line through a partition within the display area, a voltage drop phenomenon can be prevented, thereby providing a constant voltage to the pixels. Furthermore, since the connection between the second electrode and the power line is made within the display area, the invention provides an electronic device that reduces unnecessary space for connecting the second electrode and the second power line in a non-display area, thus offering high industrial applicability.

Claims

1. A substrate comprising a non-luminous region including luminous regions, a normal region, and a support region surrounded by the normal region, and a display region disposed between the luminous regions; An insulating layer disposed on the above substrate; A pixel defining film disposed on the insulating layer between the above and having openings defined that overlap with the light-emitting regions; Light-emitting elements comprising a first electrode disposed on an insulating layer between which each overlaps with the opening, a common layer disposed on the first electrode, and a second electrode disposed on the common layer; A partition disposed on the pixel definition film and overlapping with the normal region; and It includes spacers disposed on the pixel definition film and overlapping with the support regions, and Each of the above spacers is surrounded by the adjacent bulkhead and is an electronic device spaced apart from the bulkhead.

2. In Paragraph 1, The height from the pixel definition film to the spacer is An electronic device that is larger than the height from the pixel definition film to the partition wall.

3. In Paragraph 1, The above spacers are electronic devices comprising a transparent organic material or a colored organic material having light-blocking properties.

4. In Paragraph 1, Each of the above spacers is an electronic device comprising a first pattern disposed on the pixel defining film and a second pattern disposed on the first pattern.

5. In Paragraph 1, An electronic device in which the height of the pixel defining film overlapping with the spacers in the areas adjacent to the support regions is greater than the height of the pixel defining film overlapping with the partition wall.

6. In Paragraph 1, An electronic device in which the area in which the spacers are arranged within the display area is 1% to 10% of the total area of ​​the display area.

7. In Paragraph 1, The above partition is an electronic device comprising a first insulating pattern disposed on the pixel defining film, a second insulating pattern disposed on the first insulating pattern, a third insulating pattern disposed on the second insulating pattern, a first partition pattern disposed on the third insulating pattern, and a second partition pattern disposed on the first partition pattern.

8. In Paragraph 7, The above first to third insulation patterns comprise different materials, and The first insulation pattern above comprises at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide, and The above second insulation pattern and the above third insulation pattern are an electronic device comprising any one of silicon oxide, silicon oxynitride, and silicon nitride.

9. In Paragraph 7, The above first bulkhead pattern includes aluminum, and The above second partition pattern is an electronic device containing titanium.

10. In Paragraph 7, The thickness of the first bulkhead pattern is greater than the thickness of the second bulkhead pattern, and The width of the second bulkhead pattern is greater than the width of the first bulkhead pattern, and An electronic device in which a portion of the lower surface of the second bulkhead pattern protrudes from the first bulkhead pattern and is exposed from the first bulkhead pattern to define a tip portion.

11. In Paragraph 10, The second electrode is a single pattern commonly provided to the light-emitting elements, and The electronic device wherein the second electrode extends from the light-emitting regions to the non-light-emitting regions and covers a portion of the side of the first partition pattern and the lower surface of the second partition pattern.

12. In Paragraph 11, It further includes a dummy pattern disposed between the second partition pattern and the second electrode, and The above dummy pattern is an electronic device comprising the same material as the above common layer.

13. In Paragraph 12, An electronic device comprising power lines that provide power to the light-emitting elements, overlap the display area, and are further disposed between the insulating layer and the substrate.

14. In Paragraph 13, The above non-luminous region further includes contact regions disposed within the normal region and spaced apart from the support regions, and In the above contact regions, contact holes are defined through which the inter-insulating layer and the pixel defining film penetrate to expose the power lines, and The above first partition pattern is an electronic device that contacts the power line exposed by the contact hole.

15. In Paragraph 14, An electronic device in which, in the above contact regions, at least one of the first to third insulating patterns covers the side of the inter-insulating layer defining the contact hole and the side of the pixel defining film.

16. In Paragraph 1, The above pixel definition film is an electronic device comprising a colored organic material having light-blocking properties.

17. In Paragraph 1, It further includes an encapsulation layer disposed on the pixel definition film and covering the light-emitting elements, and The above-mentioned packaging layer comprises inorganic layers and an organic layer disposed between the inorganic layers, in an electronic device.

18. In Paragraph 1, The above-mentioned light-emitting regions are, An electronic device comprising: a first-1 light-emitting region and a first-2 light-emitting region spaced apart along a first direction for providing light of a first color; a second light-emitting region spaced diagonally apart from the first-1 and first-2 light-emitting regions for providing light of a second color different from the first color; and a third light-emitting region spaced apart from the second light-emitting region along a second direction intersecting the first direction for providing light of a third color different from the first and second colors.

19. In Paragraph 18, The above spacer is an electronic device disposed between adjacent first-1 to third light-emitting regions.

20. In Paragraph 18, The above-mentioned first-1 to third light-emitting regions are electronic devices having different shapes.

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