Forward error correction codes with extended error detection

Abstract

Methods and systems are described for receiving an input vector comprising a plurality of symbols, the plurality of symbols comprising redundancy symbols generated using a check matrix of a multi-error correction code (ECC) having an error capacity of t, wherein t is an integer greater than 1, generating a set of syndromes by applying the check matrix of a multi-error correction code (ECC) to the received input vector, generating an updated vector by correcting at least one symbol of the received input vector using the first subset of the set of syndromes, wherein a number of corrected symbols is less than t, updating a plurality of higher-order syndromes of the set of syndromes based on the updated vector and the check matrix, and detecting at least one unresolved error remains in the updated vector by determining one or more of the updated higher-order syndromes are non-zero.

Description

FORWARD ERROR CORRECTION CODES WITH EXTENDED ERROR DETECTIONCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 700,167, filed September 27, 2024, entitled “Decoding Forward Error Correction Codewords Using Combinatorial Logic Circuits Performing Finite Field Operations”, naming Amin Shokrollahi, which is hereby incorporated by reference in its entirety for all purposes.REFERENCES

[0002] The following references are herein incorporated by reference in their entirety for all purposes:

[0003] U.S. Patent No. 10,666,297, granted May 26, 2020, naming Amin Shokrollahi, entitled “Pipelined Forward Error Correction for Vector Signaling Code Channel”, hereinafter identified as [Shokrollahi],

[0004] U.S. Provisional Application No. 63 / 550,320, filed February 6, 2024, naming Jay arama Shenoy, entitled “Programmable Memory Fabric”, hereinafter identified as [Shenoy],

[0005] U.S. Provisional Application No. 63 / 559,144, filed February 28, 2024, naming Amin Shokrollahi, entitled “Dual In-Line Memory Module Error Correction Using Interleaved Error Correction Codes”.

[0006] U.S. Provisional Application No. 63 / 560,448, filed March 1, 2024, naming Amin Shokrollahi, entitled “Dual In-Line Memory Module Error Correction Using Interleaved Error Correction Codes”.

[0007] U.S. Provisional Application No. 63 / 561,692, filed March 5, 2024, naming Amin Shokrollahi, entitled “Dual In-Line Memory Module Error Correction Using Interleaved Error Correction Codes”.

[0008] U.S. Provisional Application No. 63 / 562,069, filed March 6, 2024, naming Amin Shokrollahi, entitled “Dual In-Line Memory Module Error Correction Using Interleaved Error Correction Codes”.

[0009] U.S. Provisional Application No. 63 / 574,817, filed April 4, 2024, naming Amin Shokrollahi, entitled “Dual In-Line Memory Module Error Correction Using Interleaved Error Correction Codes”.

[0010] U.S. Provisional Application No. 63 / 560,448, filed March 1, 2024, naming Amin Shokrollahi, entitled “Dual In-Line Memory Module Error Correction Using Interleaved Error Correction Codes”.

[0011] U.S. Provisional Application No. 63 / 648,161, filed May 15, 2024, naming Amin Shokrollahi, entitled “Dual In-Line Memory Module Error Correction Using Interleaved Error Correction Codes”, hereinafter [Shokrollahi II],

[0012] U.S. Provisional Application No. 63 / 662,820, filed June 21, 2024, naming Amin Shokrollahi, entitled “Dual In-Line Memory Module Error Correction Using Interleaved Error Correction Codes”.BACKGROUND

[0013] Data centers support business applications through e.g, data storage (management, backup, recovery), productivity applications, e-commerce transactions, online gaming, and machine leaming / artificial intelligence (Al) based applications. Data centers face multiple challenges when striving for improved performance and reduced total cost of ownership (TCO). Specifically, with cloud computing and artificial intelligence (Al) based applications, the demand for additional memory continues to increase. Three main issues act as roadblocks for data centers. The first is a three order of magnitude difference in latency between direct- attached dynamic random access memory (DRAM) and solid-state drives (SSDs). The second is the number of cores in multi-core processors that are outscaling the main memory channels, leaving processing cores absent memory bandwidth. The third is a growing problem of underutilized or stranded memory resources in accelerated computing with accelerators having their own direct attached memory.

[0014] Double Data Rate (DDR) memory is the predominant memory in personal computers (PCs), as well as server boards. Specifically, low-power DDR (LPDDR) is a type of DRAM that consumes less power and is targeted for mobile computers and devices such as mobile phones. LPDDR typically includes wider interfaces than its DDR4 and DDR5 counterparts, including interfaces of 16-bits and 32-bits, and accessing data in bursts of 16 or 32 transfers. Forward Error Correction (FEC) is a technique to improve data integrity stored in DRAMs both in link ECC applications (end to end ECC) as well as on-die ECC. Robust FEC codes are desired to reduce the probability of silent data corruption (SDC), with minimized increases in power consumption and latency.BRIEF DESCRIPTION

[0015] Methods and systems are described for receiving an input vector comprising a plurality of symbols, the plurality of symbols comprising redundancy symbols generated using a check matrix of a multi-error correction code (ECC) having an error capacity of / , wherein t is an integer greater than 1, generating a set of syndromes by applying the check matrix of a multierror correction code (ECC) to the received input vector, generating an updated vector by correcting at least one symbol of the received input vector using the first subset of the set of syndromes, wherein a number of corrected symbols is less than / , updating a plurality of higher- order syndromes of the set of syndromes based on the updated vector and the check matrix, and detecting at least one unresolved error remains in the updated vector by determining one or more of the updated higher-order syndromes are non-zero.BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 is a block diagram of a system employing forward error correction (FEC), in accordance with some embodiments.

[0017] FIG. 2 is a block diagram for computing syndromes from a received input vector according to a check matrix of a FEC code, in accordance with some embodiments.

[0018] FIGs. 3-5 are block diagrams illustrating various error case selection logic circuits, in accordance with some embodiments.

[0019] FIG. 6 is a block diagram of error value solving logic, in accordance with some embodiments.

[0020] FIG. 7 is a block diagram for error position solving logic, in accordance with some embodiments .

[0021] FIG. 8 is an algorithm implementable using combinatorial logic to solve a quadratic equation, in accordance with some embodiments.

[0022] FIG. 9 is an algorithm implementable using combinatorial logic to solve a cubic equation, in accordance with some embodiments.

[0023] FIG. 10 is an algorithm implementable using combinatorial logic to solve a quartic equation, in accordance with some embodiments.

[0024] FIG. 11 A is a block diagram of an error locator polynomial root-finding circuit implemented using multiple parallel evaluation circuits, in accordance with some embodiments.

[0025] FIG. 1 IB is a block diagram of an instance of a parallel evaluation circuit, in accordance with some embodiments.

[0026] FIG. 12 is a block diagram of an error value solving circuit, in accordance with some embodiments.

[0027] FIG. 13 is a block diagram illustrating pipelined stages of a FEC combinatorial logic circuit, in accordance with some embodiments.

[0028] FIG. 14 is a block diagram illustrating alternative pipelined stages of a FEC combinatorial logic circuit, in accordance with some embodiments.

[0029] FIGs. 15-17 illustrate various scenarios in a a single symbol correction, multi-symbol detection schemed for reduced probability of silent data corruption, in accordance with some embodiments.

[0030] FIG. 18 is a block diagram of a memory controller interacting with a low-power DDR (LPDDR) memory die having enhanced ECC capabilities, in accordance with some embodiments.

[0031] FIG. 19 is a flowchart of a method, in accordance with some embodiments.DETAILED DESCRIPTION

[0032] Described below are low-latency codes that encode and decode FEC blocks using combinatorial logic. Specifically, operations are performed in Galois Field 256 “GF(256)” utilizing combinatorial logic circuits to perform syndrome computation, error case selection, calculation of coefficients of the error locator polynomial, and root finding for quadratic, cubic, and quartic equations to solve for error positions. Alternative embodiments utilize parallel evaluation circuits to evaluate the error locator polynomial at every symbol position index to identify the roots. Using combinatorial logic circuits and parallel circuits, the latency due to error correction is significantly reduced, especially in the error position finding portion of the algorithm. It should be noted that the principles described herein may be adaptable to accommodate finite fields of other sizes as well, as well as codewords having various lengths.Combinatorial Logic in GF(2n)

[0033] Multiplication and division may both be performed using combinatorial logic circuits, specifically those tailored to perform operations in the finite field. One way to derive multiplication is by means of the Frobenius companion matrix of f(x). If f(x) = fo +fix + ... + fn-ix^+x”, then the Frobenius Companion matrix of f(x) is defined as:

[0034] Where In-i is the (n - 1) x (n - 1) identity matrix. The significance of the companion matrix lies in the following:7 are polynomials over GF(2n), then

[0035] is the vector of coefficients of the product h(x) ... g(x) mod f(x). With this the combinatorial circuits for multiplication inOne example for GF(32) is given below:

[0036] In the example of GF(32), represented by the irreducible polynomial f(x) = x5+x3+l, the Frobenius companion matrix is:

[0037] To obtain the combinatorial logic circuits for the multiplication of elements (xO, ..., x4) and (yO, ..., y4), the following vector is computed:

[0038] Therefore, where

[0039] In the above, addition is to be understood as the XOR operation and multiplication is understood as the logical AND operation.

[0040] The same principles above may be applied to perform operations in GF(256), which would correspond to eight-bit symbols. Suppose that GF(256) is represented by the irreducible polynomial f(x) = x8 +x7 +x5 +x+l with Frobenius companion matrix:

[0041] From the same principle above, the following formulas (or circuits) for the entries of

[0042] To perform division operations utilizing combinatorial logics, some embodiments multiple by the binary reciprocal of a non-zero element. Circuits for determining the binary reciprocal of a non-zero element are described below. The multiplicative structure of the finite field suggests that the matrix associated with the inverse of an element (xo, ...xn.i) is the matrix:

[0043] To calculate the inverse, the adjoint of the matrix is used which is equal to the inverse up to the determinant which is xov xi . . . v xn-i, the logical OR of the variables xo, . . . , xn-i . As such, it is 1 unless all the Xi are zero, in which case the reciprocal element doesn’t exist. Once the adjoint is computed, we multiply the vector (1, 0, . . . , 0) with its transpose from the left to obtain formulas for the reciprocal of the element (xo, . . . , xn-i). In other words, the reciprocal equals the first column of the adjoint matrix. The inverse (zo, . . . , zn-i) of a non-zero element (xo, . . . , xn-i) are given below for both GF(32) as well as GF (256).

[0044] In the same manner, formulas for the inverse (zo, ...,Z7) of (xo, ...,X7) may be determined. For brevity, the formula for only zo is given below.

[0045] While the above formulas may appear complex, particularly for division, they are readily implementable as efficient combinatorial logic circuits. Moreover, many algorithms described herein utilize few division operations. It is also noted that the above formulas may be further optimized, and that the formulas given above should not be considered limiting. In some embodiments, combinatorial logic circuits for computing square and cubes of an element are given below over GF (256).

[0046]

[0047]

[0048] In the following description, encoding and decoding of FEC-blocks of data are described that utilize multiplication, division, squaring, and cubic operations for calculatingsyndromes of a code, selecting an error case, calculating the error polynomials from the syndromes, and finding error positions that correspond to the roots of the error polynomial. In some embodiments, the roots are calculated using root-finding combinatorial logic, while alternative embodiments employ parallel evaluation circuits to determine the roots of the error locator polynomial. The combinatorial logic circuits may be created via register transfer level (RTL) code, or other synthesis tools.Encoding

[0049] Described below are low-latency codes that encode and decode FEC blocks using combinatorial logic, as opposed to generalized Reed Solomon (RS) codes that rely on Berlekamp-Massey for finding the error locator polynomial, the Chien search for finding the roots of the error locator polynomial, and extensive lookup tables for finding the error locations. The FEC codes herein utilize the following check matrix:

[0050] Where a, is the element of the field corresponding to the vector representation equal to the binary representation of the integer z that represents a symbol position index. Using the above check matrix yields an error-locator polynomial in which the roots correspond directly to the symbol position index(es) that contain the errors. In the above description, the symbols of the (n,k) FEC codes are 8-bit bytes, and thus the check matrix used above is over Galois Field 256 (GF(256)). Combinatorial logic equations for multiplication, division, finding squares, and cubes in GF(256) described above may be utilized for calculating the syndrome values of the code, combining the syndrome values, finding the roots of cubic and quartic polynomials, and finding the error values.

[0051] The encoding matrix can be found by taking the last k columns of the check matrix, inverting it, and multiplying it by the check matrix H(zz,C) to yield (Hi|I„-zt), where Hl is the encoding matrix:

[0052] In the particular example of a (12,8) FEC code, we have: / \

[0053] The left 8 columns of the matrix on the right correspond to the encoding matrix Hl. The encoding matrix may be implemented using combinatorial logic to generate the redundancy symbols for storage in the redundancy DRAMs.Decoding

[0054] Assume transmitted codewordis received as vector withup to errors in y. Suppose r = n-k. Decoding begins with computing the syndromes ofthe code

[0055] FIG. 2 is a block diagram illustrating the received codeword vector being provided to syndrome computation combinatorial logic, which is configured to apply the check matrix of the FEC code to the received vector ‘R’ using e.g., the combinatorial logic circuits described above. The computation of the syndromes in the decoder can be performed using similar combinatorial logic circuits as the encoder, because the output of the algorithms are computed solely from the elements of y without the use of memory or feedback.

[0056] Suppose during the transmission of a codeword of C(n,k) that e errors have occurred, and further suppose that syndromes So,...,Sr-i have been computed. From the syndromes, the error locator polynomial may be determined. Specifically, an error locator polynomial h(x) may take the form of:

[0057] Where are coefficients of the error locator polynomial. It is noted thatthe computation of particular coefficients is dependent on the particular error case. For example, the hi coefficient may be computed differently for the three- and four-error cases. The following are formulas for the error-locator polynomial h(x) based on the syndromes for various error cases. Specifically, the one-error case is a linear polynomial, the two-error case is a quadratic error locator polynomial, the three-error case is a cubic error locator polynomial, and the four-error case is a quartic error locator polynomial. While not explicitly shown, error locator polynomials may exist for quintic and higher orders as well.

[0058] In some embodiments, the error case selection combinatorial logic in the decoder is configured to determine an error case by sequentially calculating the highest order coefficient for each error case until a non-zero coefficient is determined, starting with the maximum error case. For the 4-error case, this would be the coefficient Av. If Av is non-zero, then there are four errors present, and the algorithm continues calculating the rest of the coefficients of the error polynomial h(x) based on the syndromes. If Av is zero, then there are less than four errors andthe combinatorial logic calculates the next highest-order coefficient for the highest power of x for the next-highest error case. The algorithm begins by calculating the highest-order term of the highest error case, and incrementally proceeds through the next-highest order cases until the first non-zero coefficient is calculated, which indicates the number of errors and responsively the rest of the coefficients of the error locator polynomial may be calculated using the syndromes via combinatorial logic.

[0059] In some embodiments, the error case selection logic may contain logic configured to calculate the highest-order coefficients for each possible error locator polynomial, and to assert an error case selection signal (e.g., the select_ / / ECC) based on the non-zero highest-order coefficient for the error locator polynomial associated with the highest error case. From there, the coefficient combinatorial logic circuit may generate the remaining coefficients of the error locator polynomial for the selected error case. In some embodiments, the coefficient combinatorial logic is part of e.g., the “3ECC Equation Solver”, “4ECC Equation Solver” circuits shown in FIG. 3.

[0060] Once the error locator polynomial is determined the roots may be found using combinatorial logic. As mentioned above, the roots correspond to the binary expansion of the column(s) of the check matrix for the symbol containing the error, and thus no Chien search is required, reducing latency.

[0061] In FIG. 3, the calculated syndromes are received. If all the syndromes are zero, then no errors are present in R, and the select O signal is asserted. Combinatorial logic is used to generate the quartic coefficient h4 from the syndromes, described above.

[0062] If the syndromes include at least one non-zero element and A4 is non-zero, then the select_4ECC signal is asserted, and the error solver evaluates the degree-4 polynomial over all field elements. If A4 is zero, then the logic moves to the 3 ECC equation solver to determine if three, two, or one error are present.

[0063] FIG. 4 is a block diagram of the error case selection circuit for identifying the 3 -error case, in accordance with some embodiments. FIG. 4 is more detailed with respect to FIG. 4, as the coefficient for the 3-error case error locator polynomial is less complex than the 4-error case. As shown, the syndromes are checked and if all syndromes are zero then the select O signal is asserted. This step may have already been determined in the previous FIG. 3, and is shown again for illustrative purposes that a circuit that corrects up to three errors would include similar logic for checking the syndromes. A3 is calculated from the syndromes, shown in FIG. 4 with functional arithmetic operations, each of which may take the form of the GF(256)combinatorial logic circuits previously described for such operations. The combinatorial shown implements the following equation:

[0064] If h3 is non-zero, then the error case selection circuit asserts the select_3ECC signal, indicating that three errors are present. The error case selection circuit proceeds to calculate the remaining coefficients of the cubic error locator polynomial, the equations of which are given above. The coefficients of the cubic error locator polynomial are provided to the cubic equation solving combinatorial logic circuit to determine the roots, either through solving the cubic equation or alternatively evaluating the error locator polynomial at each field index, depending on the implementation. If h3 is zero, then the algorithm proceeds to check the 2-error case.

[0065] FIG. 5 includes combinatorial logic for calculating A0, Al, and A2 using the following equations:

[0066] If h2 is zero, then the select lECC signal is asserted; otherwise the select_2ECC is asserted indicating that two errors are present. FIG. 5 further depicts the portion of the error solver circuit for finding the two error positions. Utilizing the check matrix above, the roots of the quadratic error locator polynomial are integer values that directly correspond to position indices of the errors within the received codeword. FIG. 6 illustrates combinatorial logic for the quadratic equation solver used for solving the error values for each of the two errors, which is based on the error positions and the syndromes SO and SI. The remaining equations for solving error values are described in further detail below. As shown, the multiplexers in FIG. 5 selectively output the two-error corrections based on the received selection signal error_case_2 (and output ‘0’ otherwise). FIG. 7 illustrates combinatorial logic used for identifying the error position in a one-error case, in accordance with some embodiments.

[0067] Once the error locator polynomial is determined of the formthe error solver circuit is configured to (i) find the position of each error and (ii) to find the error value of each error. In some embodiments, root-finding combinatorial logic circuits are used to find the error positions. In alternative embodiments, an error locator polynomialevaluation circuit composed of a plurality of parallel evaluation circuits is used. Both embodiments are described in more detail below.

[0068] For example, for a given FEC code, the combinatorial logic may include a syndrome calculation combinatorial logic circuit configured to receive bits of the symbols of the given FEC code as inputs to a plurality of gates, and to compute the syndrome values using a series of gates wherein the outputs of the syndrome calculation combinatorial logic circuit are a plurality of bits that correspond to the syndrome values. These bits may then be presented to an error locator polynomial combinatorial logic circuit (also referred to herein as a coefficient combinatorial logic circuit, for brevity), which utilizes a series of gates to implement the equations previously described to generate the coefficients of the error locator polynomial, each coefficient being a set of bits representing an element of the finite field. The syndrome values may be calculated as the symbols are read from e.g., a dynamic random-access memory (DRAM) device. Alternatively, the syndrome values may be calculated once the entire ECC codeword has been read out of the DRAMs.

[0069] The above table are preliminary synthesized combinatorial circuits for the decoding portions of the ECC circuit and may be further optimized. The encoding portions of the ECC circuit are less complex and involve far fewer logic gates and shorter critical path. In some embodiments, the various combinatorial logic stages of the ECC decoder may be pipelined if latency requirements allow.Combinatorial Root-Finding Circuits

[0070] Once the error locator polynomial is generated, the roots of the error locator polynomial are identified to find the error positions within the received input vector.

[0071] In some embodiments, in the 1 -error case, the error position involves syndrome computation only, as the syndrome provides the error location directly.

[0072] An algorithm for correcting two errors is given below and includes solving a quadratic equation to find the roots of a quadratic error locator polynomial. FIG. 8 includes an algorithm for solving the quadratic equation, and is implemented using combinatorial logic.

[0073] From this algorithm, a and b correspond to the positions of the symbols having errors, and λ and β correspond to the error values of the symbols in positions a and b respectively.

[0074] An algorithm for correcting three errors is given below, and involves solving a cubic error locator polynomial

[0075] The error positions correspond to the roots of the cubic error polynomial. The following describes the functions implemented by combinatorial logic to solve the cubic equation. In some embodiments, solving the cubic equations involves variable substitutions to solve a simplified quadratic equation. The coefficients may be normalized by the leading coefficient A3 as follows, and provided to cubic equation solving combinatorial logic implementing the algorithm of FIG. 9:

[0076] Available substitution may be used to convert the cubic equation into a depressed cubic as follows:

[0077] Which may be simplified into the equation:

[0078] The next step is to find the solution to the depressed cubic equation:

[0079] Solve the simplified quadratic equationusing the quadratic solving combinatorial logic. If the quadratic is solvable, the solutions are zxand z2. Compute the third root of each solutionthen assign the variable pos var with the value u2else the division of 'a' by u1

[0080] Solvability check : decoding error

[0081] Compute2are precomputed third roots of unity) using thefollowing:

[0082] The error positions are deduced by adding due to the previousvariable change.

[0083] The coefficients of the error-locator polynomial are provided to root-finding combinatorial logic to solve the quartic equation (FIG. 6) and return four error positions. The bits in the error positions are flipped to complete the decoding process. It may be observed that the inputs to each of the quadratic, cubic, and quartic equation solvers includes the highest order element having a coefficient of one. Combinatorial logic for division described above may be utilized to divide each coefficient by the leading coefficient to normalize the error locator polynomial.

[0084] The algorithm for the four-error case is given below, which involves solving a quartic error locator polynomial:

[0085] The combinatorial logic for solving the quartic equation may involve substitutions to solve a series of quadratic equations. Given:

[0086] Set b2 = a2, bl = al*a3, bO = al2+ a0*a32. Solve the simplified cubic equation x3+ b2*x2+bl*x+b0. Solving the simplified cubic may be performed using the above-described algorithm. If there are no three distinct solutions, return -1. If all solutions of the above equation are zero, return -1, else let beta be a nonzero solution, and gamma be another solution (can be zero). Solve the equation x2+ beta*x + aO and let z be any of the solutions. If no solutions exist, return -1.

[0087] Solve the equation x2+ (a3*z+al) / beta * x + z. If no solutions exist, return -1, else call the solutions alpha l and alpha_2.

[0088] Set alpha_3 = (gamma+a3*alpha_2) / (alpha_l+alpha_2) + alpha_2,

[0089] Set alpha_4 = a3 + alpha l + alpha_2 + alpha_3.

[0090] Return the solutions [alpha l, alpha_2, alpha_3, alpha_4].Finding Error Positions Using Parallel Evaluation Circuits

[0091] FIG. 11A illustrates a block diagram of a FEC decoder, in accordance with some embodiments. As shown, the FEC decoder includes similar block as the decoder shown in FIG. 1, with additional detail regarding the error solver. As shown, the decoder is configured to received the codeword vector and to compute the syndromes form the received codeword vector. Computing the syndromes includes applying the check matrix to the codeword, which may be performed e.g., using combinatorial logic. The error case selection and error locator polynomial coefficient generator is configured to receive the computed syndromes (i) determine an error case, and (ii) compute coefficients of an error locator polynomial associated with the determined error case.

[0092] As indicated by the name, error case selection circuit determines how many errors are present in received vector R. The error case selection circuit may include the circuits shown in FIGs. 3-7 and previously described. In some embodiments, the error case selection circuit incrementally generates the coefficient of the highest power of x for the error locator polynomial of the maximum error case first. If the coefficient is non-zero, then the maximum error case is selected and the remaining coefficients are generated. If the coefficient is zero, then the logic moves on to the next-highest error case and generates the coefficient for the highest power of x again. The process repeats until the number of errors is determined. Further, the error case selection circuit may analyze the syndromes to isolate the sections of an extended FEC code, described in more detail below.

[0093] In the particular example below, the (86,80) symbol-based code is considered over GF(256), however such a code should not be considered limiting as any of the previously-described codes are handled in similar ways. The codes which correct e.g., only one or two errors may either omit or otherwise disable the logic specific to the three- and four-error correcting codes. A given memory controller may have configurability to employ multiple codes.

[0094] Referring to FIG. 11 A, the error solver circuit includes n instances of error locator evaluation circuits in parallel; each error locator evaluation circuit configured to evaluate the determined error locator polynomial at a respective field index of the code. In some embodiments, the entire error correction process may happen during a single clock cycle. The received codeword vector ‘R’ may be fully received and stored in a buffer, for example. The codeword vector ‘R’ is read, using a latch operating according to a first clock cycle. The codeword vector ‘R’ is thus provided as an input to the aggregated FEC combinatorial logic circuit made up of e.g., the components shown in FIG. 11 A. The elements of ‘R’ are provided to the gates that make up the syndrome computation logic, the outputs of which are provided as inputs to the gates making up the error case selection and error locator polynomial generation logic, and so on. The entirety of the gates making up the aggregated FEC combinatorial logic circuit eventually settle, all within the time before the next clock cycle, upon which the corrected data vector is output. The evaluation of the error locator polynomial with parallel circuits is a key component for ensuring that the aggregated FEC combinatorial logic circuit settles within the period of the clock.

[0095] While the above examples describe error correction of up to four errors, it should be noted that utilization of the error locator polynomial evaluation circuit may extend the error correction capability to five or more errors. Such embodiments may generate quintic or higher error-locator polynomials, using the concepts previously described with respect to determinant operations to compute the matrix Mt. The parallel error locator polynomial evaluation circuits may be configured to identify five or more error positions in the received codeword vector, with the tradeoff of additional redundancy added to each codeword, thereby increasing the length of the codeword or reducing the amount of data within each codeword if codeword length remains the same.

[0096] Each evaluation circuit is associated with a respective symbol location in the received codeword vector, and performing the evaluations in parallel enables the error correction to be performed in a single pipelined stage, significantly reducing latency compared to iterative counterparts. Any error locator evaluation circuits that return a value of ‘0’ responsive to the evaluation of the respective field index corresponds to a root of the error locator polynomial, and thus corresponds to the position of an error in the codeword. This is an alternative approachto root finding combinatorial logic, as well as the Chien search, which is an iterative process of checking each field element α, α2, α3, and so on by iteratively computing the next element αiof the field to determine which elements of the field correspond to roots of the error locator polynomial (which are then be mapped to error positions). Rather, the embodiment of FIG. 11 A evaluates the error locator polynomial at every field element, by applying the coefficients of the error locator polynomial to an evaluation matrix:Where

[0097] Each Pi is e.g., an 8-bit value (assuming the code is over GF(256)). It is noted that in this particular example, the evaluation matrix conveniently corresponds to the check matrix H described above. Further, while all elements of the check matrix are present in the evaluation matrix, it should be noted that some rows of the evaluation matrix may not be utilized depending on the error case, e.g., if three errors occur then the last row of the elements raised to the fourth power are unused. As described above, in the case of three errors, the coefficient of A4 is equal to zero, thus zeroing out the effect of the fourth-power row. Functionally, this is described in more detail below. Further it should be noted that it is not required that the evaluation matrix be directly correspondent with the check matrix. The evaluation matrix and the error locator evaluation circuitry, however, maintains the property in that each evaluation performed according to the evaluation matrix is associated with a corresponding column of the check matrix, specifically identified by the element a, in the check matrix H above. It is this correspondence that provides the error position finding capability of the circuitry of FIG. 11 A.

[0098] FIG. 11B illustrates a block diagram of one error locator evaluation circuit, in accordance with some embodiments. The error locator evaluation circuit #i is shown, which includes the index value a, as well as all the second, third, and fourth order powers of a;. These particular values may be predetermined and specific to each error locator evaluation circuit, and may be represented as a hard-wired input of ‘ l’s and ‘0’s to a logic circuit. The error locator evaluation circuit i is further configured to receive the coefficients of the error locator polynomial previously generated by the error case selection and coefficient generator circuit. The error locator evaluation circuit is configured to evaluate A+vb- A3X3+A2X2+Ai.Y- d Abr x = at and to output an asserted flag signal flag i if all 8 bits of P i are 0. Each evaluation occurssimultaneously during e.g., a clock cycle, which significantly reduces the latency of finding the error positions compared to the iterative Chien search as described above. It is noted that each element of the second row of the check matrix is a unique element of the field, and is associated with an evaluation of the error locator polynomial for a specific position index of the codeword.

[0099] In some embodiments, the circuit of FIG. 11B may be further configured to include a fifth-power ofmultiplied by a corresponding coefficient of a quintic error locator polynomial

[0100] As described above, the entire aggregated FEC combinatorial logic circuit may be configured to perform the error correction during a single clock cycle. Thus, the input coefficients of the error locator polynomial will eventually settle from logic operating on the syndrome values. In the error cases having less errors than the maximum tolerable errors, higher order coefficients of the error locator polynomial (i.e., those being associated with the higher error cases) will be zero in the parallel evaluation circuits shown in FIG. 11B.

[0101] It should be noted that while the selection of the check matrix H described above is advantageous, the above-described error locator evaluation circuit may be implemented using other check matrices as well. For a Reed-Solomon code, the check matrix may be represented by:

[0102] As previously described, the Chien search evaluates the error locator polynomial at the first column of the above matrix, multiply the input by the primitive element a, repeat the evaluation, and continue iteratively multiplying the input by the primitive element a and evaluating until every column of the above matrix has been evaluated. Particular powers of ci correspond to roots of the error locator polynomial, which subsequently are looked up using a lookup table to find the positions of the error. On the contrary, the embodiment of FIG. 11 A identifies the positions directly.Solving Error Values

[0103] Once the error positions are identified, the error positions are provided to an error value solving circuit, which may include combinatorial logic configured to implement operations in the field GF(256). FIG. 12 is a block diagram of such an error value solving circuit. In some embodiments, the logic of FIG. 13 may be pipelined as previously described. As shown, thesyndromes [SO: S3] are received, as well as the flags from the parallel instantiations of the error locator evaluation circuits. The error value solver circuit may include logic to create the multibit values identifying error positions (a,b,c,d) based on the asserted flags from the error locator evaluation circuitry. Shown in FIG. 10 are block diagrams for each error case. The output of the error value circuit include the positions ‘pos’ (a,b,c,d) and corresponding eight-bit error values A shown, the outputs are of the form and(d,5).

[0104] In the one-error case, the error value corresponds to the syndrome value SO, and the error position is identified by the division of SI by SO. Such an operation may be computationally inexpensive. Thus, some embodiments may skip the parallel search for error positions in the one-error case, as a single divide in GF(256) may be utilized to find the error position. Other embodiments may perform the error location and value solving in the same manner, regardless of the number of errors.

[0105] In the two error case, the error positions (a,b) are provided, along with the syndromes A block diagram is illustrated to show the computation of λ and β, specificallyimplementing the calculations:

[0106] From this algorithm, a and b correspond to the positions of the symbols having errors, and 2 and / ? correspond to the error values of the symbols in positions a and b respectively. Each computation block may be implemented using GF(256) combinatorial logic circuits as described above.

[0107] In the three-error case, the error positions (a,b,c) are provided, along with the syndromes . Combinatorial logic circuits are configured to compute λ and an β, yaccording to the following equations:

[0108] From this algorithm, a, b, and c correspond to the positions of the symbols having errors, and correspond to the error values of the symbols in positions a, b, and crespectively.

[0109] Lastly, the four error correcting case is similarly given below to compute the error values for positions a,b,c,d, respectively:

[0110] It should be noted that some embodiments may pipeline the various stages. FIGs. 13 and 14 illustrate exemplary stages of the circuit in which pipelined flops may be included. In DRAM applications, clocks often operate at 1.333GHz (750ps). Thus, some embodiments may utilize pipelined stages to ensure all logic has sufficient time to settle at the respective outputs. FIGs. 13 and 14 report the simulated results of settling time for various blocks of the combinatorial FEC circuit. As shown in FIG. 13, pipelined flops are inserted throughout the FEC combinatorial logic circuit. In FIG. 13, the output of the syndrome computation combinatorial logic settles in approximately 515ps, the output of the root finding combinatorial logic (parallel evaluation version) settles in 436ps, and the output of the error value and correction combinatorial logic settles in 492ps. FIG. 14 is similar, illustrating one pipelined flop inserted within the root-finding combinatorial logic. In FIG. 14, the first pipelined stage settles in 804ps, while the second stage settles in 639ps.Extended Error Detection

[0111] Silent data corruption (SDC) occurs when a received input vector corresponding to a first valid codeword having been transmitted and received with one or more errors is corrected to a second valid codeword in the codespace. Mis-correction is another term which refers to such a scenario. One of the characteristics of multi-error correcting FEC codes described above is the larger minimum distance between any two codewords in the code. Embodiments herein take advantage of this to significantly reduce the probability of silent data corruption in e.g., a single or dual error correcting scenario. In a given error correcting code having an error capacity of t errors, the minimum distance between any two valid codewords is at least 2t+l. Thus, embodiments described below may perform e.g., single error correction while retaining the ability to detect up to 2t- 1 errors remain.

[0112] In some embodiments, a method includes receiving an input vector, which may correspond to a transmitted valid codeword having one or more errors imparted due to e.g., channel loss, a problem in the analog receiver, etc. Syndrome computation combinatorial logic is utilized to calculate the syndromes SO and SI as previously described, which are the syndromes associated with the all-one row and the row of binary expansions of sequential integers of the check matrix. The syndromes SO and SI are utilized to correct one symbol ofthe received input vector to generate an updated vector. In some embodiments, the syndrome SO corresponds to the error value while the symbol position index may be calculated as SI divided by SO. The syndromes of the updated vector are analyzed to determine a successful decoding was performed (only one error in the received input vector and was successfully corrected), or a decoding failure (two or more errors occurred in the received input vector). In the latter case, it is likely the single symbol correction made was incorrect. In any case, the presence of additional errors may indicate a decoding error, which may responsively prompt e.g., a retransmission request to be provided to the originating device. The larger the minimum distance between valid codewords (i.e., the higher the error-correcting capability / capacity), the more symbol errors are detectable and the lower the probability that SDC occurs. A table is given below illustrating the SDC probabilities for single symbol correct (SSC) scenarios for various FEC codes:

[0113] The table above assumes single symbol correction (SSC) for one-, two-, three-, and four-error correcting codes as previously described. In the first row, for a single symbol error correcting code, the minimum distance between any two valid codewords is three. The code successfully decodes a received input vector in the presence of one symbol error. Given two symbol errors in the received input vector, the probability of decoding to a different valid codeword within the codespace is 6.27E-2. It is important to note that not all received codewords have the minimum distance to another valid codeword, and thus the probability of silent data corruption occurring (e.g., two symbol errors occurred AND the received codeword is distance ‘3’ from another valid codeword) is even less.

[0114] The second row corresponds to a single symbol correction, three symbol detection (SSC-3SD) utilizing the codespace of a two-error correcting code. Such a code may include 64 bytes of data and 4 bytes of redundancy. The minimum distance between any two valid codewords in the (68,64) codespace is at least 5 symbols. Similar to above, if only one symbolis attempted to be corrected, the distance between the updated vector and the original codeword is at most one greater than the received input vector. Thus, if the number of symbol errors is no more than 3, then the probability of SDC is 0, as it is not possible to mis-correct to another codeword in the codespace. If 4 errors occurred, then the chance of mis-correcting the received codeword to another valid codeword that is distance 5 from the originally transmitted codeword is 3.86E-6.

[0115] The third row corresponds to single symbol correction, five symbol detection (SSC- 5SD) by utilizing the codespace of a three-error correcting code having a minimum distance of 7 between valid codewords. Similar to above, the probability of SDC in the presence of up to 5 symbol errors is 0. The third row corresponds to single symbol correction in a codespace of a four-error correcting code, having a minimum distance of 9 between valid codewords, utilizing the codespace. For the same error-correction ability, the same mean time to interrupt (MTTI), and a 6.25% overhead (1 redundancy symbol for every 16 data symbols), the mean time to failure (MTTF) increases by approximately 4 to 13 orders of magnitude.

[0116] FIG. 15 is a flowchart illustrating successful decoding utilizing the SSC-3SD scheme above. As shown, a 68-byte input vector is received having a single symbol containing an error in position ‘31’, illustrated by the hashed square. Combinatorial logic is utilized to compute syndromes SO and SI, and the symbol in position ‘31’ is corrected using the appropriate error mask. The syndromes S2 and S3 are updated (either by recomputing the syndromes by applying the check matrix to the updated vector, or by updating the originally computed S2 / S3 values directly described in more detail below). If S2 and S3 == 0, then a successful error correction has been performed, and the updated vector corresponds to the originally transmitted valid codeword.

[0117] FIG. 16 is a similar diagram illustrating a decoding error in the SSC-3SD scheme. As shown, the input vector contains two errors: one in position ‘31’ and another in position ’37’. Similarly, the syndromes SO and SI are computed, however, SO and SI now correspond to a combination of the errors values occurring in positions ‘31’ and ‘37’. The attempted single symbol correction thus targets a potentially third symbol position, e.g., ‘43’. In this case, the result is yet another invalid codeword, and thus the system returns a decoding error which may result in e.g., a retransmission.

[0118] FIG. 17 illustrates the extremely unlikely case of SDC. As shown, the input vector corresponds to an originally transmitted codeword having undergone three errors in positions '26', ‘31’, ‘37’, and ‘41’. The syndromes SO and SI are calculated, and the symbol in position ‘45’ is updated based on the calculated syndrome values. SDC occurs in the case that theupdated vector corresponds to a valid codeword that is different than the originally transmitted codeword. Thus, the probability of SDC occurring is the probability that (i) four symbol errors occurred, (ii) the originally transmitted codeword is distance 4 from another valid codeword, and (iii) the updated vector from the attempted decode corresponds to a different valid codeword.

[0119] In some embodiments, the syndrome computation logic may be configured to generate all syndromes, e.g., S0-S3, from the input vector. In such an embodiment, a first subset of the syndromes, e.g., syndromes SO and SI, may be used for the single symbol correction, and the syndrome computation logic updates the initially-generated higher-order syndromes (e.g., S2 and S3) to generate updated higher-order syndromes S2, S3. In alternative embodiments, the syndrome computation logic is configured to generate SO and SI from the received vector, and then to apply the check matrix to the updated vector to determine the higher-order syndromes S2, S3, etc. (SO and SI will be ‘0’ due to the attempted single-symbol correction). Consider the following equation:

[0120] Where H is the check matrix, c is a valid codeword, r is the received input vector, and the syndrome SO is the error mask applied to the symbol in position ‘a’ of the received input vector. SO + SO is equal to zero, as is SI + a* SO, due to the initial single symbol correction applied to the original input vector. Higher-order syndromes S2 and S3 may thus be updated by applying respectively, and checking if the result is zero. If the resultsare zero, then a single symbol contained an error in the original input vector and has been successfully corrected. If the higher-order syndromes S2 and / or S3 are not zero, however, then it is assumed the original input vector contained two or more errors to begin with, resulting in a decoding error and e.g., issuing an interrupt for a retransmission request.

[0121] The above examples are for single symbol correction cases, however, similar concepts may be utilized for dual-symbol correct in the three-and four-error correction codes. In such a scenario, a ‘t’ error correcting code may correct two symbol errors and detect 2t-2 symbol errors. As an additional symbol is being corrected, the number of detectable errors is also reduced by one. A table of some examples is given below:

[0122] In the dual-symbol correct (DSC) variants, the first subset of syndromes S0-S3 may be calculated and utilized to correct two symbols of the original input vector. The remaining initially-generated higher-order syndromes (e.g., S4 and S5 in the 3-error correcting codes or S4-S7 in the 4-error correcting codes) are updated or otherwise recalculated. If the updated higher-order syndromes are zero, then the corrections made to the two errors in the received input vector was a successful decode. If the remaining syndromes are non-zero, then it is assumed at least three errors occurred in the original input vector, resulting in a decoding error. Such concepts may be extended to e.g., n symbol correct with enhanced error detection capabilities as long as the number of corrections being made to original input vector is less than the minimum distance between any two codewords of a given code, which dictates the error correction capabilities. For example, if a five-error correction code is used, then an algorithm may correct three symbol errors and detect up to 7 additional errors.

[0123] FIG. 19 is a flowchart of a method 1900, in accordance with some embodiments. As shown, method 1900 includes receiving 1905 an input vector comprising a plurality of symbols, the plurality of symbols comprising redundancy symbols generated using a check matrix of a multi-error correction code (ECC) having an error capacity of ‘f , wherein t is an integer greater than 1. The method further includes generating 1910 a set of syndromes by applying a check matrix of a multi-error correction code (ECC) to the received input vector. The method further includes correcting 1915 at least one symbol of the received input vector using a subset of the set of syndromes, wherein a number of corrected symbols is less than t. The method further includes updating 1920 a plurality of higher-order syndromes based on the updated vector and the check matrix. The method further includes detecting 1925 at least one unresolved error remains in the updated vector according by determining one or more of the syndromes in the second set of syndromes are non-zero.

[0124] In some embodiments, one symbol is corrected to generate the updated vector. In some embodiments, the subset of the set of syndromes includes first and second syndromes SO and SI. In some embodiments, the first and second syndromes are generated, respectively,according to rows of the check matrix, the rows of the check matrix comprising (i) an all -one row and (ii) a row of binary expansions of integers fl , where a, is the binary expansion of integer 7’ being a column index that corresponds to a symbol position index. In some embodiments, the second set of syndromes comprises higher-order syndromes from rows of the check matrix that correspond to the row of binary expansions of integers raised to higher- order powers. In some embodiments, updating the higher-order syndromes includes updating initially -generated higher-order syndromes in the set of syndromes. In some embodiments, the one or more syndromes in the subset of the set of syndromes are updated based on an error position and an error value used in the correction of the one symbol. In some embodiments, updating the higher-order syndromes includes applying the updated vector to the rows of the check matrix that correspond to the row of binary expansions of integers raised to higher-order powers.

[0125] In some embodiments, any two codewords in the multi-ECC have a minimum distance of 2t+l, wherein t is an integer greater than 1 and is an error correctability of the multi-ECC, and wherein at least 2t-l unresolved errors are detectable.

[0126] In some embodiments, two errors are corrected using the first set of syndromes, wherein any two codeword in the multi-ECC have a minimum distance of 2t+ 1 , wherein t is an integer greater than 1 and is an error correctability of the multi-ECC, and wherein at least 2t-2 unresolved errors are detectable.

[0127] FIG. 18 is a block diagram of a memory controller interconnected to a LPDDR die, in accordance with some embodiments. As shown, the memory controller includes ECC encode / decode logic and PHYs that interface to the memory channel to the LPDDR die. In the embodiment shown, a channel having 16 bits for data and 1 bit for redundancy is shown. Additionally, the channel includes a command ‘cmd’ channel which may include e.g., a write or read request as well as the target address. During a memory write, data is received from e.g., a CPU along with an instruction to write the data. Redundancy bits are generated from the data. In FIG. 18, one redundancy bit is generated for every 16 bits of data by the memory controller. Assuming a burst length of 32, 512 data bits and 32 redundancy bits are transmitted to the DRAM die. In some embodiments, such as LPDDR, the RDQS pin may be used during write operations to transmit the redundant bits to the DRAM die. During a read operation, the data- mask inversion (DMI) pin may be used to read the redundant bits from DRAM die. In some embodiments, the [544,512] code described above with respect to FIG. 36 is used. In such an embodiment, 32 bits of redundancy are generated, and the 512 bits of data + 32 bits of redundancy are transmitted over the 16+1 interface to the LPDDR over a burst of 32 timeintervals. The LPDDR die similarly has PHY transceivers. As shown, the LPDDR is configured to store the redundancy without processing it as part of a decoding operation in what may be a dedicated portion of the LPDDR. The LPDDR similarly includes on-die ECC encode / decode logic for locally computing redundancy bits. The code used by the on-die ECC may be different than that of the memory controller ECC. For example, the one-die ECC may use a symbol based code, e.g., the (68,64) symbol based code having 64 8-bit data symbols and 4 8-bit redundancy symbols. Such a code is configured to correct multi-bit errors in up to two symbols.

[0128] During a read operation, the on-die ECC decoder is configured to receive the data bits and locally generated redundancy bits and perform error correction on the data. The corrected data is output along with the redundancy bits that were generated from the memory controller. This information is transmitted over the channel to the memory controller, which computes syndromes based on the received data bits and redundancy bits and performs further error correction on the data.

[0129] The choice of code used by each ECC (memory controller and on-die) may depend on various factors. In some embodiments, a code is selected having a ratio of data to redundancy that matches that of a DRAMs cells, i.e., that has a matching data cell to redundancy cell ratio. In some embodiments, a code may be selected based on the error correction capabilities. In some embodiments, the code is selected based on the type of errors occurring. For example, it may be that wire-line transmission errors are more often random errors. In such an embodiments, a binary -based code which corrects single bit errors may be preferred due to the higher number of individual errors and ability to detect additional errors. In some embodiments, such as in a DRAM die, the errors may be more correlated. For example, arrays within DRAM banks may be faulty. In such cases, symbol-based codes may be preferred as the data may be recoverable in the case of an array or bank failure when storing symbols in configurations previously described.

Claims

CLAIMS:

1. A method comprising: receiving an input vector comprising a plurality of symbols, the plurality of symbols comprising redundancy symbols generated using a check matrix of a multi-error correction code (ECC) having an error capacity of Z, wherein t is an integer greater than 1; generating a set of syndromes by applying the check matrix of a multi-error correction code (ECC) to the received input vector; generating an updated vector by correcting at least one symbol of the received input vector using the first subset of the set of syndromes, wherein a number of corrected symbols is less than Z; updating a plurality of higher-order syndromes of the set of syndromes based on the updated vector and the check matrix; and detecting at least one unresolved error remains in the updated vector by determining one or more of the updated higher-order syndromes are non-zero.

2. The method of claim 1, wherein generating the updated vector comprises correcting one symbol of the received input vector.

3. The method of claim 2, wherein the first subset of the set of syndromes comprises first and second syndromes.

4. The method of claim 3, wherein the first and second syndromes are generated, respectively, according to rows of the check matrix, the rows of the check matrix comprising (i) an all-one row and (ii) a row of binary expansions of integers where a, is the binaryexpansion of integerbeing a column index that corresponds to a symbol position index.

5. The method of claim 4, wherein the higher-order syndromes are generated according to rows of the check matrix that correspond to the row of binary expansions of integers raised to higher-order powers.

6. The method of claim 5, wherein the higher-order syndromes are generated by updating initially-generated higher-order syndromes in the set of syndromes.

7. The method of claim 6, wherein the higher-order syndromes are updated based on an error position and an error value used in the correction of the one symbol.

8. The method of claim 5, wherein updating the higher-order syndromes comprises applying the updated vector to the rows of the check matrix that correspond to the row of binary expansions of integers raised to higher-order powers.

9. The method as in any of claims 1-8, wherein any two codewords in the multi -ECC have a minimum distance of 2t+l, and wherein at least 2t- 1 unresolved errors are detectable.

10. The method as in any of claims 1-8, wherein two errors are corrected using the first subset of the set of syndromes, wherein any two codeword in the multi-ECC have a minimum distance of 2t+l, and wherein at least 2t-2 unresolved errors are detectable.

11. An apparatus comprising: an input buffer configured to receive and store an input vector comprising a plurality of symbols, the plurality of symbols comprising redundancy symbols generated using a check matrix of a multi-error correction code (ECC) having an error capacity of / , wherein t is an integer greater than 1; syndrome computation logic configured to generate a set of syndromes by applying a check matrix of the multi-error correction code (ECC) to the received input vector; error correction combinatorial logic configured to correct at least one symbol of the received input vector using a first subset of the set of syndromes to generate an updated vector in the input buffer, wherein a number of corrected symbols is less than / ; the syndrome computation logic further configured to update higher-order syndromes based on the updated vector and the check matrix, and to detect at least one unresolved error remains in the updated vector by determining one or more of the updated higher- order syndromes are non-zero.

12. The apparatus of claim 11, wherein the error correction combinatorial logic is configured to correct one symbol to generate the updated vector.

13. The apparatus of claim 12, wherein the first subset of the set of syndromes comprises first and second syndromes.

14. The apparatus of claim 13, wherein the syndrome computation logic is configured to generate the first and second syndromes, respectively, according to rows of the check matrix, the rows of the check matrix comprising (i) an all-one row and (ii) a row of binary expansions of integers where a, is the binary expansion of integer being a columnindex that corresponds to a symbol position index.

15. The apparatus of claim 14, wherein the higher-order syndromes are generated according to rows of the check matrix that correspond to the row of binary expansions of integers raised to higher-order powers.

16. The apparatus of claim 5, wherein the syndrome computation logic is configured to update the higher-order syndromes by updating initially-generated higher-order syndromes in the set of syndromes.

17. The apparatus of claim 16, wherein the updated higher-order syndromes are updated based on an error position and an error value used in the correction of the one symbol.

18. The apparatus of claim 15, wherein the syndrome computation logic is configured to update the higher-order syndromes by applying the updated vector to the rows of the check matrix that correspond to the row of binary expansions of integers raised to higher-order powers.

19. The apparatus as in any of claims 11-18, wherein any two codewords in the multi- ECC have a minimum distance of 2t+ 1 , and wherein at least 2t-l unresolved errors are detectable.

20. The apparatus as in any of claims 11-18, wherein two errors are corrected using the first set of syndromes, wherein any two codeword in the multi-ECC have a minimum distance of 2t+l, and wherein at least 2t-2 unresolved errors are detectable.

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