Generation of an optimal network-on-chip layout using a machine learning model

Abstract

An optimal layout of a network-on-chip (NoC) is generated. A plurality of candidate layouts of a NoC are generated from a system on chip (SoC) floorplan, socket locations, address maps, and key performance indicators (KPIs). The candidate layouts have different KPIs. A supervised machine learning (ML) model trained on optimized layouts for different KPIs is used to select one of the candidate layouts as an optimal layout for a given set of KPIs. Channels of the optimal layout are globally optimized to meet NoC requirements.

Description

Attorney Docket No. ART-144PCT PCT Serial No.: TBDTITLE

[0001] GENERATION OF AN OPTIMAL NETWORK-ON-CHIP LAYOUT USING A MACHINE LEARNING MODELCROSS REFERENCE TO RELATED APPLICATION

[0002] This application claims the benefit under 35 U.S.C. 119(e) of US Provisional Application Serial No. 63 / 701 ,550 filed on September 30, 2024 and titled GENERATION OF AN OPTIMAL NETWORK-ON-CHIP LAYOUT USING A MACHINE LEARNING MODEL by K. Charles JANAC et al., the entire disclosure of which is incorporated herein by reference.FIELD

[0003] The present technology is in the field of electronic computer-aided design of integrated circuits and, more specifically, related to layout generation for a system on chip (SoC) including a network-on-chip (NoC).BACKGROUND

[0004] Network-on-chip technology is being used at many semiconductor companies to support an ever-increasing number of cores on a single chip and a demand for ever-increasing processing power related to artificial intelligence (Al) and other applications. A NoC is superior to point-to-point connectivity by way of a more scalable communication architecture that makes use of packet transmissions.

[0005] An SoC may include a NoC to handle communication between Intellectual Property (IP) units of the SoC. Consider the design of an SoC that includes a NoC. An SoC specification provides a chip definition of technology, domains, and constraints, and it includes a chip floorplan. A chip floorplan refers to a schematic representation of tentative placement of a chip’s major functional blocks. The chip floorplan may indicate real estate and other constraints for the NoC.

[0006] A NoC designer generates a NoC layout that fits into that real estate. The NoC layout has to fulfill different performance requirements, such as connectivity and latency between source and destination, frequency of various elements, maximum area available for NoC logic and its associated routing (wiring), minimum throughput between sources and destinations, power consumption requirements, and position on the chip floorplan.

[0007] It is extremely difficult and time-consuming to design a layout that fulfills multiple performance requirements while minimizing logic and wires.SUMMARY

[0008] In accordance with various embodiments and aspects herein, an electronic computer- aided design method of generating an optimal layout of a NoC includes generating a plurality of candidate layouts of a NoC based on a system-on-chip (SoC) floorplan, socket locations, address maps, and key performance indicators (KPIs). The candidate layouts have different KPIs. The method further includes using a supervised machine learning (ML) model trained on optimizedAttorney Docket No. ART-144PCT PCT Serial No.: TBD layouts for different KPIs to identify one of the candidate layouts as an optimal layout for a given set of KPIs; and globally optimizing channels of the optimal layout to fulfill NoC requirements.

[0009] In accordance with various embodiments and aspects herein, a system for generating an optimal layout of a NoC includes an electronic computer-aided design too configured to generate a plurality of candidate layouts of a NoC from an SoC floorplan, socket locations, address maps, and KPIs. The candidate layouts have different KPIs. The system further includes a supervised ML model trained on optimized layouts for different KPIs for evaluating the plurality of candidate layouts for a given set of KPIs to identify an optimal layout; and a reinforced machine learning model configured to globally optimize channels and adjust blockages in the optimal layout to fulfill NoC requirements.

[0010] In accordance with various embodiments and aspects herein, a non-transitory computer readable medium includes code that, when executed, causes one or more processors to generate a plurality of candidate layouts of a NoC based on an SoC floorplan, socket locations, address maps, and KPIs, wherein the candidate layouts have different KPIs; use a supervised ML model trained on optimized layouts for different KPIs to select one of the candidate layouts as an optimal layout for a given set of KPIs; and globally optimize channels in the optimal layout to fulfill NoC requirements.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to understand the invention more fully, a reference is made to the accompanying drawings. The invention is described in accordance with the aspects and embodiments in the following description with reference to the drawings or figures (FIG.), in which like numbers represent the same or similar elements. Understanding that these drawings are not to be considered limitations in the scope of the invention, the presently described aspects and embodiments and the presently understood best mode of the invention are described with additional detail through the use of the accompanying drawings.

[0012] FIG. 1 shows an example of an SoC including a NoC.

[0013] FIG. 2 shows a method of generating a hardware description of a NoC layout for an SoC in accordance with various aspects and embodiments herein.

[0014] FIG. 3 shows a method of generating an optimal layout of a NoC in accordance with various aspects and embodiments herein.

[0015] FIG. 4 shows a method of using feedback from generation of the optimal layout in accordance with various aspects and embodiments herein.

[0016] FIG. 5 shows a system for generating an optimal layout of a NoC in accordance with various aspects and embodiments herein.DETAILED DESCRIPTION

[0017] The following describes various examples of the present technology. Generally, examples can use the described aspects in any combination. All statements herein recitingAttorney Docket No. ART-144PCT PCT Serial No.: TBD principles, aspects, and embodiments as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0018] It is noted that, as used herein, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Reference throughout this specification to “one embodiment,” “an embodiment,” “certain embodiment,” “various embodiments,” or similar language means that a particular aspect, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment.

[0019] Thus, appearances of the phrases “in one embodiment,” “in at least one embodiment,” “in an embodiment,” "in certain embodiments," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment or similar embodiments. Furthermore, aspects and embodiments described herein are merely exemplary, and should not be construed as limiting of the scope or spirit of the invention as appreciated by those of ordinary skill in the art. All statements herein reciting principles, aspects, and embodiments are intended to encompass both structural and functional equivalents thereof. It is intended that such equivalents include both currently known equivalents and equivalents developed in the future. Furthermore, to the extent that the terms "including", "includes”, “having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a similar manner to the term "comprising."

[0020] Reference is made to FIG. 1 , which illustrates a simple example of an SoC 100 including a plurality of initiators 110 and targets 120. Examples of the initiators 110 include central processing units (CPUs), graphics processing units (GPUs), video cards, accelerators, and direct memory access (DMA) controllers. Examples of the targets 120 include volatile memory, persistent memory, and peripherals.

[0021] The SoC 100 further includes a NoC 130. The NoC 130 sends request transactions from an initiator 110 to one or more targets 120 using industry-standard protocols. A request transaction includes an address of the target 120. The NoC 130 decodes the address and transports the request transaction. The target 120 handles the request transaction and may send a response transaction, which is transported back to the initiator 110 via the NoC 130.

[0022] The NoC 130 includes a plurality of network interface units (NIUs) 140 and 150 and a transport interconnect 160. Each initiator 110 is coupled to the transport interconnect 160 via a corresponding initiator NIU 140. Each target 120 is coupled to the transport interconnect 160 via a corresponding target NIU 150.

[0023] Each NIU 140 and 150 is configured to convert the protocol used by its corresponding core into a transport protocol used inside the NoC 130. The transport protocol is typically based on the transmission of packets.Attorney Docket No. ART-144PCT PCT Serial No.: TBD

[0024] The transport interconnect 160 transports packets between the initiator NIUs 140 and the target NIUs 150. The transport interconnect 160 includes switches, adapters, and buffers. Switches may be used to route flows of traffic between sources and destinations. Adapters may be used to deal with various conversions between data width, clock domains, and power domains. Buffers may be used to insert pipelining elements to span long distances, or to store packets to deal with rate adaptation between fast senders and slow receivers or vice-versa.

[0025] In general, the NoC 130 is highly configurable. Certain components such as the NIUs 140 and 150 and switches have many different possible configurations. Other components such as buffers have relatively fewer possible configurations. Values of these component parameters can be varied to optimize the cost, performance, and power consumption of each element.

[0026] FIG. 2 shows an example of a method of generating a hardware description of a NoC. At block 210, an SoC architect designs a specification that includes a floorplan for the SoC, power strategy, and constraints related to the environment (e.g., clocks and their frequencies, quality of service, and type of protocol used with macros). Among other things, the floorplan defines areas on the chip for major functional blocks of the chip, including initiators and targets. The floorplan also defines blockages. It also defines the area that will be used for the inter-connect communication (that is, the “free space” for the NoC). The SoC architect may place additional constraints on the NoC. Examples of additional constraints include frequency, routing congestion, and power consumption.

[0027] At block 220, a layout of the NoC is generated. Generating the layout involves placing and legalizing standard cells, and making wire connections between the NoC elements. The layout generation involves the use of a supervised machine learning (ML) model. The layout may be globally optimized by the use of a reinforcement learning model. The NoC layout may be generated by a party other than the SoC architect.

[0028] At block 230, a hardware description of the NoC layout is generated. Register T ransfer Level (RTL) may be used for design and verification flow. The RTL description may then be delivered to an SoC integrator.

[0029] At block 240, the SoC integrator performs integration, synthesis, and simulations to determine whether the NoC description fits into the free space defined by the floorplan, exhibits predictable results about operation frequency, and satisfies other constraints such as routing congestion, and power consumption.

[0030] At block 250, feedback analysis is performed. Feedback is derived from results of simulations, timing reports, congestion, and the like. The SoC integrator provides the feedback to the NoC designer. Advantageously, some of the feedback may be used to train the supervised ML model.

[0031] Reference is made to FIG. 3, which illustrates a method of generating a description of an optimum layout of a NoC. At block 310, a set of initial requirements for a NoC design isAttorney Docket No. ART-144PCT PCT Serial No.: TBD received. The requirements include any combination or information that includes: floorplan and constraints, socket locations, address maps, and key performance indicators (KPIs). Examples of KPIs for a NoC include, but are not limited to, frequency, power, wire length, wires per channel and area. As used herein, KPIs also include performance objectives.

[0032] At bock 320, a plurality of candidate NoC layouts that satisfy the initial requirements are generated. Some or all of the layouts may be created by a synthesis tool. Some or all of the layouts may be created by an automated NoC generator. Some of the layouts may be created manually. Both the initial requirements and the NoC layouts may be described in a computer readable representation, such as computer files, or in-memory data structures.

[0033] The plurality of candidate layouts may be generated from the same floorplan, the same socket locations, the same address maps, and the same NoC elements library. However, the KPIs are unique to each candidate layout. Each KPI may be assigned a numerical value. There may be hundreds or thousands of different combinations of values for the KPIs, and a layout can be generated for each combination of KPIs. A set of combinations may be selected. For instance, fifty combinations may be randomly selected to produce fifty candidate layouts.

[0034] At block 330, a supervised machine learning (ML) model is used to identify one of the candidate layouts as an optimal layout for a desired set of KPIs. The optimal layout may be identified as follows. The candidate layouts and a desired set of KPIs are provided to the ML model one at a time. The ML model generates a score (e.g., a probability or most compliant with constraints or parameters of the design representation) for each candidate layout. The candidate layout having the highest score is identified as the optimal layout for the desired set of KPIs.

[0035] The ML model used at block 330 may be a neural network that performs classification. The ML model has been trained on optimized layouts for different KPIs. In general, a supervised ML model, that is, an ML model based on a supervised learning algorithm, is trained with labeled data. Each input of training data has been assigned a specific outcome. Training layouts may include layouts optimized for a first KPI, layouts optimized for a second KPI, and so on. The training layouts may also include layouts optimized for different combinations of KPIs. The labels include scores.

[0036] At block 340, channels of the optimal layout are globally optimized. For example, global optimizations for all channels in the optimal layout may include channel length, number of traces in a channel, position of a channel, etc. The optimization may be performed manually or it may be automated.

[0037] The global optimization may also include optimization of the SoC floorplan to meet NoC requirements. For example, position and / or rotation of macros and blockages in the SoC floorplan may be made to adjust channel size.

[0038] In some embodiments, the optimization may be performed by a machine learning model that is based on a reinforcement learning algorithm. In general, a reinforcement learningAttorney Docket No. ART-144PCT PCT Serial No.: TBD algorithm uses a feedback system that is governed by a policy that rewards good actions and punishes bad actions and is optimized to guide this cyclic learning process towards a desired outcome. A reinforcement ML model may be used at block 340 to optimize the channels and blockages to meet NoC requirements.

[0039] It is extremely difficult and time-consuming to design a layout that fulfills multiple performance requirements while minimizing logic and wires. The method of FIG. 3 improves upon speed and efficiency of designing a layout that fulfills multiple performance requirements while minimizing logic and wires.

[0040] Reference is now made to FIG. 4, which shows a method of using the feedback. At block 410, feedback from the SoC integrator is used in the conventional way: to modify the layout of the NoC to satisfy the feedback. Corrective actions, if any, are taken. Updates to certain specifications are satisfied.

[0041] The feedback from the SoC integrator may also be used to retrain and / or fine-tune one or both of the ML models. In accordance with some aspects and embodiments, user feedback may be used for retraining and / or fine tuning. For instance, the optimal layout, KPIs and feedback on optimality (which might include an adjusted score) may be added to the training data. The supervised ML model may be retrained and / or re-tuned on the updated training data.

[0042] At block 430, additional feedback may be in the form of data generated from the layout generation, the identification of an optimal layout, and the global optimization. The additional feedback may also be used to retrain / fine-tune one or both of the ML models. The results from the design of one SoC / NoC may be used to generate future SoC / NoC designs. In accordance with some aspects and embodiments, past designs are used at an initial starting points for future designs.

[0043] Reference is now made to FIG. 5, which illustrates a system 500 for generating an optimal layout of a NoC. The system 500 includes a computer 510. The computer 510 includes a processing unit 520 and computer-readable memory 530. The computer-readable memory 530 stores a tool 540 including executable instructions that, when executed, cause the processing unit 520 to generate a plurality of candidate layouts of a NoC based on a SoC floorplan, socket locations, address maps, and different combinations of KPIs; use a supervised ML model 550 to identify one of the candidate layouts as an optimal layout for a desired set of KPIs; and globally optimize channels and adjust blockages of the optimal layout to fulfill NoC requirements.

[0044] In some embodiments, the tool 540 is a standalone application. In other embodiments, the tool 540 is integrated with another tool, such as a tool that automatically generates NoC layouts.

[0045] In some embodiments, the tool 540 and the supervised ML model 550 may both be on the computer 510. In other embodiments, the supervised ML model 550 may be on a cloud 560 (public or private) and accessed by the computer 510 via a network interface 535. If a reinforcedAttorney Docket No. ART-144PCT PCT Serial No.: TBD machine learning model 555 is used to perform the global optimization, then it too may be stored on the computer 510 or in the cloud 560.

[0046] In some embodiments, the additional feedback (e.g., user feedback, data generated from the layout generation, the identification of an optimal layout, and the global optimization) may be stored in the computer 510. In other embodiments, the additional feedback may be stored in the cloud 560 or at a remote facility.

[0047] In some embodiments, the computer 510 may further include a module 545 for retraining / fine-tuning the supervised ML model 550 and / or the reinforcement ML model. Data for the retraining / fine-tuning may be taken from any or all of user feedback, SoC integrator feedback, results of generating the plurality of candidate layouts, and results of globally optimizing the channels of the optimal layout.

[0048] Certain methods, which can be implemented in a product, according to the various aspects of the invention may be performed by instructions that are stored upon a non-transitory computer readable medium. The non-transitory computer readable medium stores code including instructions that, if executed by one or more processors, would cause a system or computer to perform steps of the method described herein. The non-transitory computer readable medium includes: a rotating magnetic disk, a rotating optical disk, a flash random access memory (RAM) chip, and other mechanically moving or solid-state storage media. Any type of computer-readable medium is appropriate for storing code comprising instructions according to various example.

[0049] Some examples are one or more non-transitory computer readable media arranged to store such instructions for methods described herein. Whatever machine holds non-transitory computer readable media comprising any of the necessary code may implement an example. Some examples may be implemented as: physical devices such as semiconductor chips; hardware description language representations of the logical or functional behavior of such devices; and one or more non-transitory computer readable media arranged to store such hardware description language representations.

[0050] Certain examples have been described herein and it will be noted that different combinations of different components from different examples may be possible. Salient features are presented to better explain examples; however, it is clear that certain features may be added, modified and / or omitted without modifying the functional aspects of these examples as described.

[0051] Various examples are methods that use the behavior of either or a combination of machines. Method examples are complete wherever in the world most constituent steps occur. For example, IP elements or units include: processors (e.g., CPUs or GPUs), random-access memory (RAM - e.g., off-chip dynamic RAM or DRAM), a network interface for wired or wireless connections such as ethernet, WiFi, 3G, 4G long-term evolution (LTE), 5G, and other wireless interface standard radios. The IP may also include various I / O interface devices, as needed for different peripheral devices such as touch screen sensors, geolocation receivers, microphones,Attorney Docket No. ART-144PCT PCT Serial No.: TBD speakers, Bluetooth peripherals, and USB devices, such as keyboards and mice, among others. By executing instructions stored in RAM devices processors perform steps of methods as described herein.

[0052] Descriptions herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements described herein as coupled have an effectual relationship realizable by a direct connection or indirectly with one or more other intervening elements.

[0053] Practitioners skilled in the art will recognize many modifications and variations. The modifications and variations include any relevant combination of the disclosed features. Descriptions herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements described herein as “coupled” or “communicatively coupled” have an effectual relationship realizable by a direct connection or indirect connection, which uses one or more other intervening elements. Embodiments described herein as “communicating” or “in communication with” another device, module, or elements include any form of communication or link and include an effectual relationship. For example, a communication link may be established using a wired connection, wireless protocols, near-filed protocols, or RFID.

[0054] To the extent that the terms "including", "includes”, “having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a similar manner to the term "comprising."

[0055] The scope of the invention, therefore, is not intended to be limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of present invention is embodied by the appended claims.

Claims

Attorney Docket No. ART-144PCT PCT Serial No.: TBDWhat is claimed is:1 . An electronic computer-aided design method of generating an optimal layout of a network-on-chip (NoC), the method comprising: generating a plurality of candidate layouts of a NoC based on a system on chip (SoC) floorplan, socket locations, address maps, and key performance indicators (KPIs), wherein the candidate layouts have different KPIs; using a supervised machine learning (ML) model trained on optimized layouts for different KPIs to identify one of the candidate layouts as an optimal layout for a given set of KPIs; and globally optimizing channels of the optimal layout to fulfill NoC requirements.

2. The method of claim 1 , wherein the plurality of candidate layouts are supplied to the ML model one at a time; wherein the ML model is a classification model that generates a score for each candidate layout; and wherein the candidate layout having a score that is highest is selected as the optimal layout.

3. The method of claim 1 , wherein the floorplan, the socket locations, and the address maps are used to generate each of the candidate layouts, but the KPIs of the candidate layouts are unique.

4. The method of claim 1 , wherein a reinforced learning model trained to perform optimization is used to globally optimize the channels of the optimal layout.

5. The method of claim 4, wherein the reinforced learning model is also used to modify the floorplan to adjust channel size.

6. The method of claim 1 , further comprising: providing a hardware description of the optimal layout after global optimization to an SoC integrator; receiving feedback on the hardware description; and using the feedback to retrain / fine-tune the ML model.

7. The method of claim 1 , further comprising retraining the ML model with feedback, wherein the feedback includes: results of generating the plurality of candidate layouts; and results of globally optimizing the channels of the optimal layout.

8. A system for generating an optimal layout of a network-on-chip (NoC), the system comprising: an electronic computer-aided design tool configured to generate a plurality of candidate layouts of a NoC from a system-on-chip (SoC) floorplan, socket locations, address maps, and key performance indicators (KPIs), wherein the candidate layouts have different KPIs;Attorney Docket No. ART-144PCT PCT Serial No.: TBD a supervised machine learning (ML) model trained on optimized layouts for different KPIs for evaluating the plurality of candidate layouts for a given set of KPIs to identify an optimal layout; and a reinforced machine learning model configured to globally optimize channels and adjust blockages in the optimal layout to fulfill NoC requirements.

9. The system of claim 8, wherein the supervised ML model is a classification model that generates a score for each candidate layout; and wherein the candidate layout having a highest score is selected as the optimal layout.

10. The system of claim 8, wherein the floorplan, the socket locations, and the address maps are used to generate each of the candidate layouts, but the KPIs are unique to each of the candidate layouts.11 . The system of claim 8, wherein the reinforced learning model is also configured to modify the floorplan to adjust channel size.

12. The system of claim 8, further comprising a module configured to retrain and / or fine-tune the supervised ML model based on feedback including SoC integrator feedback.

13. The system of claim 8, further comprising a module configured to retrain and / or fine-tune the supervised ML model based on feedback including: results of generating the plurality of candidate layouts; and results of globally optimizing the channels of the optimal layout.Attorney Docket No. ART-144PCT PCT Serial No.: TBD14. A non-transitory computer readable medium comprising code that, when executed, causes one or more processors to: generate a plurality of candidate layouts of a NoC based on a system-on-chip (SoC) floorplan, socket locations, address maps, and key performance indicators (KPIs), wherein the candidate layouts have different KPIs; use a supervised machine learning (ML) model trained on optimized layouts for different KPIs to select one of the candidate layouts as an optimal layout for a given set of KPIs; and globally optimize channels in the optimal layout to fulfill NoC requirements.

15. The computer readable medium of claim 14, wherein the plurality of candidate layouts are supplied to the supervised ML model one at a time; wherein the ML model generates a score for each candidate layout; and wherein the candidate layout having a highest score is selected as the optimal layout.

16. The computer readable medium of claim 14, wherein the floorplan, the socket locations, and the address maps are used to generate each of the candidate layouts, but the KPIs are unique to each of the candidate layouts.

17. The computer readable medium of claim 14, wherein a reinforced learning model is used to globally optimize the channels.

18. The computer readable medium of claim 17, wherein the reinforced learning model is also used to optimize the floorplan to adjust channel size.

19. The computer readable medium of claim 14, wherein the code, when executed, further causes the one or more processors to retrain and / or fine-tune the supervised ML model based on SoC integrator feedback.

20. The computer readable medium of claim 14, wherein the code, when executed, further causes the one or more processors to retrain and / or fine-tune the supervised ML model based on feedback including: results of generating the plurality of candidate layouts; and results of globally optimizing the channels of the optimal layout.

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