Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor that can achieve both an improved high-temperature reliability and prevention of deterioration in capacitance. A multilayer ceramic capacitor according to the present invention comprises: a first outer layer part 121 disposed at the side of one first surface F1 in a stacking direction for an inner layer part 11; and a third outer layer part 123 disposed at the side of one third surface F3 in a first direction that is orthogonal to the stacking direction for the inner layer part 11. The first outer layer part 121 contains Mn, and the third outer layer part contains Mg. In cross sections parallel to the stacking direction and the first direction, the Mn content in inner dielectric layers decreases from the first surface F1 side toward the center in the stacking direction of the inner layer part 11, and the Mg content in internal dielectric layers decreases from the third surface side toward the center in the first direction of the inner layer part 11.

Description

Multilayer ceramic capacitor

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Conventionally, there is a multilayer ceramic capacitor including a cover layer that covers the top and bottom of a capacitance portion in which an internal dielectric layer and an internal electrode layer are laminated, and side margin portions that cover both sides in the width direction of an inner layer portion that covers the left and right (see Patent Document 1). In this prior art, it is disclosed that the internal dielectric layer contains Mn as a sub-component and may contain Mg as an additive.

[0003] Japanese Unexamined Patent Application Publication No. 2024 - 100560

[0004] When Mn or Mg is added to the internal dielectric layer, grain growth during sintering is inhibited, so the particle size of crystal grains becomes smaller, and the high-temperature reliability of the multilayer ceramic capacitor is improved. On the other hand, when the particle size of crystal grains becomes smaller, the capacitance of the multilayer ceramic capacitor decreases.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor capable of satisfying both improvement in high-temperature reliability and prevention of capacitance decrease.

[0006] To solve the above problems, the present invention provides a laminate comprising: an inner layer portion including a plurality of alternately stacked internal dielectric layers and a plurality of internal electrodes; a first surface and a second surface facing each other in the stacking direction; a third surface and a fourth surface facing each other in a first direction intersecting the stacking direction; a fifth surface and a sixth surface facing each other in a second direction intersecting the stacking direction and the first direction; a first outer layer portion disposed on the first surface side of the inner layer portion; a second outer layer portion disposed on the second surface side of the inner layer portion; a third outer layer portion disposed on the third surface side of the inner layer portion; and a fourth outer layer portion disposed on the fourth surface side of the inner layer portion. The present invention provides a multilayer ceramic capacitor comprising two external electrodes arranged on the sixth surface side, wherein the internal electrodes include a first internal electrode with one end exposed to the fifth surface and a second internal electrode with one end exposed to the sixth surface, the first outer layer portion contains Mn, the third outer layer portion contains Mg, and in a cross section parallel to the stacking direction and the first direction, the Mn content of the internal dielectric layer decreases from the first surface side toward the center of the inner layer portion in the stacking direction, and the Mg content of the internal dielectric layer decreases from the third surface side toward the center of the inner layer portion in the first direction.

[0007] Furthermore, in order to solve the above problems, the present invention provides an inner layer portion including a plurality of alternately stacked internal dielectric layers and a plurality of internal electrodes, a first and second surface facing each other in the stacking direction, a third and fourth surface facing each other in a first direction intersecting the stacking direction, a fifth and sixth surface facing each other in a second direction intersecting the stacking direction and the first direction, a first outer layer portion disposed on the first surface side of the inner layer portion, a second outer layer portion disposed on the second surface side of the inner layer portion, a third outer layer portion disposed on the third surface side of the inner layer portion, and disposed on the fourth surface side of the inner layer portion The laminate comprises a fourth outer layer, and two external electrodes arranged on the fifth and sixth surfaces of the laminate, wherein the internal electrodes include a first internal electrode with one end exposed to the fifth surface and a second internal electrode with one end exposed to the sixth surface, the first outer layer contains Mn, and the third outer layer contains Mg, and in a cross section parallel to the lamination direction and the first direction, the internal layer is divided into two equal parts in the lamination direction and in the first direction, thereby creating regions 1-3 on the first surface side and the third surface side, and the first surface The structure is divided into four regions: region 1-4 on the side and the fourth side, region 2-3 on the second side and the third side, and region 2-4 on the second side and the fourth side. Region 1-3 is divided into three equal parts in the stacking direction and into three equal parts in the first direction to divide it into nine regions. The three regions on the first side are divided into regions 1-3-1, 1-3-2, and 1-3-3 in order from the third side, the three regions on the second side are divided into regions 1-3-7, 1-3-8, and 1-3-9 in order from the third side, and the three regions on the first side and the The present invention provides a multilayer ceramic capacitor in which, when the three regions between the three regions on the second surface are designated as regions 1-3-4, 1-3-5, and 1-3-6 in order from the third surface, the amount of Mg and Mn contained in the internal dielectric layer located in region 1-3-9 is less than the amount of Mg and Mn contained in the internal dielectric layer located in region 1-3-5, and the amount of Mg and Mn contained in the internal dielectric layer located in region 1-3-5 is less than the amount of Mg and Mn contained in the internal dielectric layer located in region 1-3-1.

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can satisfy both the need for improved high-temperature reliability and the need to prevent a decrease in capacitance.

[0009] This is a schematic perspective view of the multilayer ceramic capacitor 1 according to the embodiment. This is a partial cross-sectional view of the multilayer ceramic capacitor 1 along the line II-II in Figure 1. This is a cross-sectional view of the multilayer ceramic capacitor 1 along the line III-III in Figure 1. This is an enlarged view of the upper right region 1-3 in Figure 3. This is a flowchart showing the manufacturing method of the multilayer ceramic capacitor 1 according to the embodiment. This is a table showing the results of verifying the effects of the multilayer ceramic capacitor 1 of the embodiment.

[0010] Embodiments of the present invention will be described below. Figure 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment. Figure 2 is a partial cross-sectional view of the multilayer ceramic capacitor 1 along the line II-II in Figure 1. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 1 along the line III-III in Figure 1.

[0011] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 comprises a laminated body 2 in a substantially rectangular parallelepiped shape and a pair of external electrodes 3 provided at both ends of the laminated body 2. The laminated body 2 also includes an inner layer portion 11 which comprises multiple sets of internal dielectric layers 14 and internal electrode layers 15.

[0012] In the following explanation, the term used to describe the orientation of the multilayer ceramic capacitor 1 is defined as the stacking direction T, which is the direction in which the internal dielectric layer 14 and the internal electrode layer 15 are stacked.

[0013] The direction that intersects the stacking direction T and in which a pair of external electrodes 3 are provided is defined as the second direction L. The direction that intersects both the second direction L and the stacking direction T is defined as the first direction W. In this embodiment, the second direction L, the first direction W, and the stacking direction T are orthogonal to each other.

[0014] The present invention is not limited thereto, but it is preferable that the multilayer ceramic capacitor 1 has a dimension in the second direction L of 0.2 mm or more and 3.2 mm or less, a dimension in the first direction W of 0.10 mm or more and 1.60 mm or less, and a dimension in the stacking direction T of 0.10 mm or more and 1.60 mm or less.

[0015] (Laminate 2) Laminate 2 has a first surface F1 and a second surface F2 facing the lamination direction T, a third surface F3 and a fourth surface F4 facing the first direction W, and a fifth surface F5 and a sixth surface F6 facing the second direction L. The first direction W is the direction connecting the third surface and the fourth surface, and the second direction L is the direction connecting the fifth surface F5 and the sixth surface.

[0016] In this embodiment, the edges R1 between two adjacent faces and the corners between three adjacent faces of the laminate 2 are rounded off by a barreling process described later, giving them a rounded edge. This suppresses chipping at the angular parts of the laminate 2.

[0017] The laminate 2 comprises an inner layer 11 and an outer layer 12. The inner layer 11 is a region in which an internal electrode layer 15 and an internal dielectric layer 14 are laminated. The outer layer 12 comprises a first outer layer 121 and a second outer layer 122 that sandwich the inner layer 11 from the lamination direction T, and a third outer layer 123 and a fourth outer layer 124 that sandwich the inner layer 11 from a first direction W.

[0018] (Internal dielectric layer 14) The internal dielectric layer 14 is obtained by sintering a ceramic green sheet, which is formed into a sheet from a slurry made by mixing ceramic powder, glass particles, and a sintering aid as an additive, to which a binder, additives such as plasticizers and dispersants, and organic solvents are added. The ceramic powder is, for example, barium titanate (BaTiO). ３ ) and calcium zirconate (CaZrO ３ It is preferable to use a ceramic material mainly composed of a perovskite-type dielectric such as ), and in this embodiment, BaTiO ３ Its main component is [this].

[0019] (Internal electrode layer 15) The internal electrode layer 15 comprises a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. For example, the first internal electrode layers 15A are exposed on the fifth surface F5, and the second internal electrode layers 15B are exposed on the sixth surface F6. When there is no need to explain the first internal electrode layers 15A and the second internal electrode layers 15B separately, they are described together as the internal electrode layer 15.

[0020] The internal electrode layer 15 is preferably composed mainly of Ni (nickel), but is not limited thereto. A solid solution layer of Sn may be formed at the interface between the internal electrode layer 15 and the internal dielectric layer 14. The formation of the Sn solid solution layer can mitigate the concentration of the electric field at the interface between the internal electrode layer 15 and the internal dielectric layer 14. The width of the internal electrode layer 15 may be shorter in the first direction W toward the exposed end.

[0021] In this embodiment, as shown in Figure 3, the displacement d of the edges of adjacent internal electrode layers 15 in the first direction W in the stacking direction T is 1.0 μm or less. When the width in the first direction W decreases toward the exposed end, the displacement d of the edges of adjacent internal electrode layers 15 in the first direction W in the stacking direction T is the displacement d at the center of the second direction L.

[0022] The internal electrode layer 15 includes opposing portions 152 that face each other between the first internal electrode layer 15A and the second internal electrode layer 15B, and leading portions 151 that do not face each other between the first internal electrode layer 15A and the second internal electrode layer 15B, and are drawn out from the opposing portions 152 toward one of the fifth surface F5 or the sixth surface F6. The direction in which the leading portions 151 extend differs between the first internal electrode layer 15A and the second internal electrode layer 15B, and are drawn out alternately toward the fifth surface F5 side and the sixth surface F6 side. The end of the leading portion 151a of the first internal electrode layer 15A is exposed to the fifth surface F5 and is electrically connected to the first external electrode 3A. The end of the leading portion 151b of the second internal electrode layer 15B is exposed to the sixth surface F6 and is electrically connected to the second external electrode 3B. Charge accumulates between the opposing portions 152 of the first internal electrode layer 15A and the second internal electrode layer 15B, which are adjacent in the stacking direction T, and functions as a capacitor.

[0023] (Outer layer 12) The outer layer 12 comprises a first outer layer 121 positioned on the first surface F1 side of the inner layer 11, a second outer layer 122 positioned on the second surface F2 side of the inner layer 11, a third outer layer 123 positioned on the third surface F3 side of the inner layer 11, and a fourth outer layer 124 positioned on the fourth surface F4 side of the inner layer 11. The first outer layer 121 and the second outer layer 122 sandwich the inner layer 11 in the stacking direction T. The third outer layer 123 and the fourth outer layer 124 sandwich the inner layer 11 in the first direction W. At this time, the third outer layer 123 and the fourth outer layer 124 sandwich the first outer layer 121 and the second outer layer 122 in addition to the inner layer 11.

[0024] In one embodiment, the outer layer 12, like the inner dielectric layer 14, has BaTiO as its main component. ３ and glass. At least the first outer layer 121 of the first outer layer 121 and the second outer layer 122 further contains Mn (manganese). At least the third outer layer 123 of the third outer layer 123 and the fourth outer layer 124 further contains Mg (magnesium).

[0025] The amount of glass in the first outer layer 121 and the second outer layer 122 is between 1.2 mol% and 1.6 mol%. The amount of glass in the third outer layer 123 and the fourth outer layer 124 is greater than that in the first outer layer 121 and the second outer layer 122, and is between 2.3 mol% and 2.7 mol%.

[0026] Furthermore, of the interfaces between the first outer layer 121 and the third outer layer 123, the interface between the first outer layer 121 and the fourth outer layer 124, the interface between the second outer layer 122 and the third outer layer 123, and the interface between the second outer layer 122 and the fourth outer layer 124, it is preferable that at least the interface between the first outer layer 121 and the third outer layer 123 contains more Si than other parts of the outer layer 12. By including a large amount of Si at the interface, the propagation of cracks that occur at the interface can be suppressed.

[0027] Furthermore, it is preferable that Si is distributed in a straight line with a width of 1 μm to 5 μm in at least the region near the interface between the first outer layer portion 121 and the third outer layer portion 123 of these interfaces. That is, it is preferable that Si is meandering with a width of 1 μm to 5 μm that includes the interface. This can further suppress the propagation of cracks that occur at the interface.

[0028] (External Electrode 3) The external electrode 3 has a first external electrode 3A and a second external electrode 3B. The first external electrode 3A is positioned on the fifth surface F5 and further positioned on the first surface F1 and the second surface F2. The first external electrode 3A may also be positioned on the third surface F3 and the fourth surface F4. The second external electrode 3B is positioned on the sixth surface F6 and further positioned on the first surface F1 and the second surface F2. The second external electrode 3B may also be positioned on the third surface F3 and the fourth surface F4.

[0029] (Underlayment electrode layer 30) The external electrode 3 comprises an underlayment electrode layer 30 and a plating layer 31. The underlayment electrode layer 30 is connected to the internal electrode layer 15. The underlayment electrode layer 30 may be arranged not only on the fifth surface F5 and the sixth surface F6, but also on the first surface F1, the second surface F2, the third surface F3 and the fourth surface F4.

[0030] The base electrode layer 30 may have a configuration comprising a metal component and a glass component, or a metal component and a ceramic component. In this embodiment, the base electrode layer 30 contains Cu (copper) as a component. In this embodiment, the base electrode layer 30 is a coating film manufactured by a dip method. However, the base electrode layer 30 may also be a plated film (base plated layer) manufactured by plating, or it may be a thin film layer.

[0031] (Plating layer 31) The plating layer 31 includes a Ni (nickel) plating layer 31a disposed on the base electrode layer 30 and a Sn (tin) plating layer 31b disposed on the Ni plating layer 31a. The Ni plating layer 31a can prevent the base electrode layer 30 from being corroded by solder when mounting ceramic electronic components. The Sn plating layer 31b improves the wettability of the solder when mounting the multilayer ceramic capacitor 1.

[0032] However, the present invention is not limited thereto, and a resin electrode may be provided between the base electrode layer 30 and the plating layer 31. The resin electrode is arranged to cover a portion of the base electrode layer 30. The resin electrode contains resin and metal. Because the resin electrode contains resin, it is more flexible than the base electrode layer 30 and functions as a buffer layer. Therefore, when flexural stress is applied to the mounting substrate and a physical force is applied to the multilayer ceramic capacitor 1 due to this stress, cracks are less likely to occur in the multilayer ceramic capacitor 1.

[0033] Alternatively, a Ni underlayer may be formed first on the fifth surface F5 and the sixth surface F6 of the laminate 2, then sintered together with the laminate 2, and then the Ni plating layer 31a and the Sn plating layer 31b may be formed. By sintering the Ni underlayer together with the laminate 2, the contact between the internal electrode layer 15 and the external electrode 3 can be improved.

[0034] Furthermore, a Ni underlayer may be formed only on the fifth surface F5 and the sixth surface F6 of the laminate 2, then sintered together with the laminate 2, after which a Cu conductive paste is applied and sintered again, and then a Ni plating layer 31a and a Sn plating layer 31b may be formed. In this case as well, the contact between the internal electrode layer 15 and the external electrode can be improved by sintering the Ni layer together with the laminate 2.

[0035] Next, in the cross-section parallel to the stacking direction T and the first direction W shown in Figure 3, the inner layer portion 11 of the multilayer ceramic capacitor 1 of this embodiment is divided into four regions by dividing it in half along the stacking direction T and in half along the first direction W. Then, in these four regions, the side facing the first surface F1 and the third surface F3 is designated as region 1-3, the side facing the first surface F1 and the fourth surface F4 is designated as region 1-4, the side facing the second surface F2 and the third surface F3 is designated as region 2-3, and the side facing the second surface F2 and the fourth surface F4 is designated as region 2-4.

[0036] Figure 4 is an enlarged view of region 1-3 in the upper right of Figure 3. As shown in Figure 4, region 1-3 is further divided into nine regions by dividing it into three equal parts in the stacking direction T and three equal parts in the first direction W. In these nine regions, the three regions on the first surface F1 side are designated as region 1-3-1, region 1-3-2, and region 1-3-3 in order from the third surface F3 side, the three regions on the second surface F2 side are designated as region 1-3-7, region 1-3-8, and region 1-3-9 in order from the third surface F3 side, and the three regions between the three regions on the first surface F1 side and the three regions on the second surface F2 side are designated as region 1-3-4, region 1-3-5, and region 1-3-6 in order from the third surface F3 side.

[0037] In this embodiment, as described above, the first outer layer 121 contains Mn, and the third outer layer 123 contains Mg. The Mg contained in the third outer layer 123 flows during the sintering of the laminate 2 and penetrates into the internal dielectric layer 14. An internal electrode layer 15 exists between the first outer layer 121 and the internal dielectric layer 14, but the Mn contained in the first outer layer 121 has higher fluidity than Mg. Therefore, the Mn can penetrate through the internal electrode layer 15 and into the internal dielectric layer 14 during the sintering of the laminate 2.

[0038] Due to this penetration from the outer layer 12, the Mn content in the inner dielectric layer 14 is highest on the first surface F1 side and the second surface F2 side. From the first surface F1 side and the second surface F2 side, it decreases toward the center in the stacking direction T of the inner layer 11, and is lowest in the inner dielectric layer 14 in the central part of the stacking direction T of the inner layer 11.

[0039] The Mg content in the internal dielectric layer 14 is highest on the third surface F3 side and the fourth surface F4 side. From the third surface F3 side and the fourth surface F4 side, it decreases toward the center of the first direction W of the inner layer portion 11, and is lowest in the internal dielectric layer 14 in the central part of the first direction W of the inner layer portion 11.

[0040] That is, Mg and Mn contained in the internal dielectric layer 14 located in region 1-3-9 are less than Mg and Mn contained in the internal dielectric layer 14 located in region 1-3-5, and Mg and Mn contained in the internal dielectric layer 14 located in region 1-3-5 are less than Mg and Mn contained in the internal dielectric layer 14 located in region 1-3-1.

[0041] (Mg molar ratio) The molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-1 is 0.50 or more and 2.00 or less. The molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-5 is 0.20 or more and 1.00 or less, and it is preferably 40% or more and 50% or less with respect to the molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-1. The molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-9 is 0.05 or more and 0.40 or less, and it is preferably 10% or more and 20% or less with respect to the molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-1.

[0042] More preferably, the molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-1 is 0.50 or more and 1.00 or less. The molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-5 is 0.20 or more and 0.50 or less. The molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-9 is 0.05 or more and 0.20 or less.

[0043] (Molar ratio of Mn) The molar ratio of Mn to Ti contained in the internal dielectric layer 14 located in region 1-3-1 is preferably 0.50 or more and 1.00 or less. The molar ratio of Mn to Ti contained in the internal dielectric layer 14 located in region 1-3-5 is 0.20 or more and 1.00 or less, and preferably 40% or more and 50% or less with respect to the molar ratio of Mn to Ti contained in the internal dielectric layer 14 located in region 1-3-1. The molar ratio of Mn to Ti contained in the internal dielectric layer 14 located in region 1-3-9 is 0.05 or more and 0.40 or less, and preferably 10% or more and 20% or less with respect to the molar ratio of Mn to Ti contained in the internal dielectric layer 14 located within region 1-3-1.

[0044] Further, it is more preferable that the molar ratios of both Mn and Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-1 are 0.50 or more and 1.00 or less.

[0045] And when the molar ratios of both Mn and Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-1 are 0.50 or more and 1.00 or less, the molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-5 is preferably 0.20 or more and 0.50 or less. It is preferably 40% or more and 50% or less with respect to the molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-1. The molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-9 is 0.05 or more and 0.20 or less, and preferably 10% or more and 20% or less with respect to the molar ratio of Mg to Ti contained in the internal dielectric layer 14 located in region 1-3-1.

[0046] Furthermore, when the molar ratios of Mn and Mg to Ti in the internal dielectric layer 14 located in region 1-3-1 are both 0.50 or more and 1.00 or less, it is preferable that the molar ratio of Mn to Ti in the internal dielectric layer 14 located in region 1-3-5 is 0.20 or more and 0.50 or less, and is 40% or more and 50% or less of the molar ratio of Mn to Ti in the internal dielectric layer 14 located in region 1-3-1. It is preferable that the molar ratio of Mn to Ti in the internal dielectric layer 14 located in 1-3-9 is 0.05 or more and 0.20 or less, and is 10% or more and 20% or less of the molar ratio of Mn to Ti in the internal dielectric layer 14 located in region 1-3-1.

[0047] (Ni-Mn alloy layer 16 and Mg region 17) In the cross-section shown in Figure 4, the internal electrode layer 15 located closest to the first surface F1 has a Ni-Mn alloy layer 16, and the end of the internal electrode layer 15 located closest to the first surface F1 in the first direction W has an Mg region 17, which is a layer containing Mg. In the cross-section shown in Figure 4, the total dimension of the Ni-Mn alloy layer 16 in the first direction W is longer than the total dimension of the Mg region 17 in the first direction W.

[0048] The Ni-Mn alloy layer 16 has a larger shrinkage rate during firing compared to the internal electrode layer 15 alone. Therefore, compared to the case where the Ni-Mn alloy layer 16 is not formed, the shrinkage difference between it and the outer layer 12, which has a large shrinkage rate, can be buffered, and structural defects between the outer layer and the internal electrode layer 15 can be suppressed.

[0049] Furthermore, during sintering, Mn contained in the first outer layer 121 diffuses outward in the first direction W (towards the third outer layer 123) from the interface between the first outer layer 121 and the third outer layer 123. This further improves the density of the third outer layer 123 near the interface with the first outer layer 121. Also, Mg contained in the third outer layer 123 diffuses inward in the first direction W (towards the first outer layer 121). This further improves the density of the first outer layer 121 near the interface with the third outer layer 123. Because the density is improved near the interface in this way, structural defects caused by stress concentration occurring at the corners of the inner layer 11 can be suppressed.

[0050] In the cross-section shown in Figure 4, the third outer layer 123 contains Mn within a distance W(Mn) from the interface between the first outer layer 121 and the third outer layer 123, and the first outer layer 121 contains Mg within a distance W(Mg) from the interface, where distance W(Mn) is narrower than W(Mg).

[0051] In the cross-section shown in Figure 4, Si is distributed in a straight line with a length of 1 μm to 5 μm in the region including the interface between the first outer layer 121 and the third outer layer 123. The Si distribution line is indicated by reference numeral 18.

[0052] In cases where the interface position cannot be recognized after sintering, for example, the line extending the inner electrode layer 15 on the first surface F1 side in the stacking direction T can be used as the interface.

[0053] (Method for manufacturing the multilayer ceramic capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment will be described. Figure 5 is a flowchart showing the method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment.

[0054] (Laminate Manufacturing Process S1) First, a material sheet is prepared in which the pattern of the internal electrode layer 15 is printed with conductive paste on a ceramic green sheet for lamination, which is formed from a ceramic slurry into a sheet. Then, multiple material sheets are stacked so that the patterns of the internal electrode layer 15 are offset by half a pitch in the length direction between adjacent material sheets. Furthermore, ceramic green sheets for the outer layer containing Mn, which will become the first outer layer 121 and the second outer layer 122, are stacked on both sides of the multiple stacked material sheets, and a mother block member is formed by heat-pressing them together. The mother block member is then cut along the cutting line. Then, ceramic green sheets containing Mg, which will become the third outer layer 123 and the fourth outer layer 124, are attached to both sides of the cut member in the first direction W, respectively, to manufacture the laminate 2. In this case, for example, the molar ratio of Mn contained in the ceramic green sheet for the outer layer, which will become the first outer layer 121 and the second outer layer 122, can be 0.5 or more and 1.0 or less, and the molar ratio of Mg contained in the ceramic green sheet for the third outer layer 123 and the fourth outer layer 124 can be 2.0 or more and 2.5 or less.

[0055] (First firing step S2) The divided laminate 2 is degreased in a nitrogen atmosphere under predetermined conditions, and then fired in a nitrogen-hydrogen-water vapor mixed atmosphere at a predetermined temperature. This manufacturing method includes this first firing step S2 for firing the laminate 2 and a second firing step S5 for forming the base electrode layer, which will be described later. However, it is not limited to this, and the firing of the laminate 2 and the firing of the base electrode layer may be performed in a single firing step. At this time, the Mn contained in the first outer layer 121 and the second outer layer 122 and the Mg contained in the third outer layer 123 and the fourth outer layer 124 diffuse into the inner layer. However, the diffusion distance changes depending on the firing temperature and time, so the firing conditions are adjusted to achieve the structure of the present invention.

[0056] (Barrel polishing process S3) Next, the laminate 2 is subjected to barrel polishing. This rounds the edges R1 of the laminate 2.

[0057] (Underlayment electrode layer formation process S4) Subsequently, using the dip method, a paste for the underlayment electrode layer, which will become the underlayment electrode layer 30, is applied from the fifth surface F5 side and the sixth surface F6 side. At this time, the paste for the underlayment electrode layer is also applied to the first surface F1, second surface F2, third surface F3, and fourth surface F4 of the laminate 2.

[0058] (Second firing step S5) Thereafter, the laminate 2 on which the base electrode layer 30 is formed is fired in an oxidizing atmosphere with a continuous supply of nitrogen and water. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0059] (Plating layer formation process S6) Next, a Ni plating layer 31a is first formed on the outer periphery of the base electrode layer 30 so as to cover the base electrode layer 30. Then, a Sn plating layer 31b is formed on the outer periphery of the Ni plating layer 31a so as to cover the Ni plating layer 31a.

[0060] Through the above process, a multilayer ceramic capacitor 1 is manufactured.

[0061] As described above, in the multilayer ceramic capacitor of this embodiment, Mn is present in a higher concentration in the internal dielectric layer 14 near the first outer layer 121 and the second outer layer 122 compared to other parts, and Mg is present in a higher concentration in the internal dielectric layer 14 near the third outer layer 123 and the fourth outer layer 124 compared to other parts. The presence of Mn and Mg in the internal dielectric layer 14 inhibits grain growth during sintering, resulting in a smaller particle size of crystal grains and thus densification, which improves the high-temperature reliability of the multilayer ceramic capacitor.

[0062] On the other hand, if the particle size of the crystal grains in the internal dielectric layer 14 becomes too small, the capacitance of the multilayer ceramic capacitor decreases. In the multilayer ceramic capacitor of this embodiment, the concentration of Mn and Mg in the internal dielectric layer 14 decreases as you move away from the outer layer 12. Therefore, the effect of capacitance reduction due to suppression of grain growth during sintering can be minimized.

[0063] In other words, it is possible to provide a multilayer ceramic capacitor 1 that can satisfy both the need for improved high-temperature reliability and the need to prevent a decrease in capacitance.

[0064] (Verification Results) Next, the results of the verification of the effects of the multilayer ceramic capacitor 1 of this embodiment will be described. Figure 6 is a table showing the results of the verification of the effects of the multilayer ceramic capacitor 1 of this embodiment. The multilayer ceramic capacitor 1 used for verification has dimensions of 0.8 mm in the stacking direction T, 0.8 mm in the first direction W, and 1.6 mm in the second direction L. The main component of the internal electrode layer 15 is Ni, and the main component of the internal dielectric layer 14 is BaTiO ３ The external electrode 3 includes a Cu baking layer as the base electrode layer 30, and a Ni plating layer 31a and a Sn plating layer 31b as the plating layers.

[0065] In the diagram, "high-temperature reliability" means that after leaving the multilayer ceramic capacitor 1 at a temperature of 105°C and a voltage of 4V for 1000 hours, the insulation resistance does not fall below 50 Ω·F. Multilayer ceramic capacitors 1 with an insulation resistance greater than 50 Ω·F were marked with ◎ (pass). Multilayer ceramic capacitors 1 with an insulation resistance between 10 Ω·F and 50 Ω·F were marked with ○ (acceptable range). Multilayer ceramic capacitors 1 with an insulation resistance less than 10 Ω·F were marked with × (fail).

[0066] Regarding the "relative permittivity," multilayer ceramic capacitors 1 with a relative permittivity greater than 4800 were marked with ◎ (pass). Multilayer ceramic capacitors 1 with a relative permittivity between 4500 and 4800 were marked with ○ (acceptable). Multilayer ceramic capacitors 1 with a relative permittivity between 4200 and less than 4500 were marked with △ (acceptable). Multilayer ceramic capacitors 1 with a relative permittivity less than 4200 were marked with × (fail). However, there were no failures this time.

[0067] In Comparative Example 1, unlike the example, the internal dielectric layer 14 located in region 1-3-9, the internal dielectric layer 14 located in region 1-3-5, and the internal dielectric layer 14 located in region 1-3-1 do not contain Mg. In Comparative Example 2, unlike the example, the internal dielectric layer 14 located in region 1-3-9, the internal dielectric layer 14 located in region 1-3-5, and the internal dielectric layer 14 located in region 1-3-1 do not contain Mn. As shown in Figure 6, neither Comparative Example 1 nor Comparative Example 2 met the high-temperature reliability requirements.

[0068] In contrast, as shown in Figure 6, in all of Examples 1 to 9, the amount of Mg and Mn contained in the internal dielectric layer 14 located in region 1-3-9 is less than the amount of Mg and Mn contained in the internal dielectric layer 14 located in region 1-3-5, and the amount of Mg and Mn contained in the internal dielectric layer 14 located in region 1-3-5 is less than the amount of Mg and Mn contained in the internal dielectric layer 14 located in region 1-3-1. As shown in Figure 6, the high-temperature reliability of all of these Examples 1 to 9 was within an acceptable range.

[0069] Based on the above results, it has been proven that the multilayer ceramic capacitor of the embodiment exhibits improved high-temperature reliability and also has minimal impact from capacitance reduction.

[0070] Although preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications are possible.

[0071] F1 First surface F2 Second surface F3 Third surface F4 Fourth surface F5 F5 F6 Sixth surface L Second direction T Lamination direction W First direction 1 Multilayer ceramic capacitor 2 Laminate 3 External electrode 11 Inner layer 12 Outer layer 121 First outer layer 122 Second outer layer 123 Third outer layer 124 Fourth outer layer 14 Internal dielectric layer 15 Internal electrode layer 152 Opposing part 16 Ni-Mn alloy layer 17 Mg region 18 Si distribution line

Claims

1. A laminate comprising: an inner layer portion including a plurality of alternately stacked inner dielectric layers and a plurality of inner electrodes; a first and second surface facing the stacking direction; a third and fourth surface facing the first direction intersecting the stacking direction; a fifth and sixth surface facing the second direction intersecting the stacking direction and the first direction; a first outer layer portion disposed on the first surface side of the inner layer portion; a second outer layer portion disposed on the second surface side of the inner layer portion; a third outer layer portion disposed on the third surface side of the inner layer portion; and a fourth outer layer portion disposed on the fourth surface side of the inner layer portion; and two outer electrodes disposed on the fifth and sixth surface sides of the laminate, wherein the inner electrodes include a first inner electrode with one end exposed to the fifth surface and a second inner electrode with one end exposed to the sixth surface; the first outer layer portion contains Mn; the third outer layer portion contains Mg; and in a cross section parallel to the stacking direction and the first direction, A multilayer ceramic capacitor wherein the Mn content of the internal dielectric layer decreases from the first surface towards the center of the inner layer in the stacking direction, and the Mg content of the internal dielectric layer decreases from the third surface towards the center of the inner layer in the first direction.

2. A laminate comprising: an inner layer portion including a plurality of alternately stacked inner dielectric layers and a plurality of inner electrodes; a first and second surface facing the stacking direction; a third and fourth surface facing the first direction intersecting the stacking direction; a fifth and sixth surface facing the second direction intersecting the stacking direction and the first direction; a first outer layer portion disposed on the first surface side of the inner layer portion; a second outer layer portion disposed on the second surface side of the inner layer portion; a third outer layer portion disposed on the third surface side of the inner layer portion; and a fourth outer layer portion disposed on the fourth surface side of the inner layer portion; and two outer electrodes disposed on the fifth and sixth surface sides of the laminate, wherein the inner electrodes include a first inner electrode with one end exposed to the fifth surface and a second inner electrode with one end exposed to the sixth surface; the first outer layer portion contains Mn; the third outer layer portion contains Mg; and in a cross section parallel to the stacking direction and the first direction, By dividing the inner layer into two equal parts in the stacking direction and into two equal parts in the first direction, it is divided into four regions: region 1-3 on the first and third side, region 1-4 on the first and fourth side, region 2-3 on the second and third side, and region 2-4 on the second and fourth side. By dividing region 1-3 into three equal parts in the stacking direction and into three equal parts in the first direction, it is divided into nine regions: the three regions on the first side are named region 1-3-1, region 1-3-2, and region 1-3-3 in order from the third side, the three regions on the second side are named region 1-3-7, region 1-3-8, and region 1-3-9 in order from the third side, and the three regions between the three regions on the first side and the three regions on the second side are named region 1-3-4, region 1-3-5, and region 1-3-6 in order from the third side. A multilayer ceramic capacitor in which the amount of Mg and Mn contained in the internal dielectric layer located in region 1-3-9 is less than the amount of Mg and Mn contained in the internal dielectric layer located in region 1-3-5, and the amount of Mg and Mn contained in the internal dielectric layer located in region 1-3-5 is less than the amount of Mg and Mn contained in the internal dielectric layer located in region 1-3-1.

3. The internal dielectric layer is BaTiO ３ The multilayer ceramic capacitor according to claim 2, wherein the main component is Mg, and the molar ratio of Mg to Ti in the internal dielectric layer located in region 1-3-1 is 0.50 or more and 2.00 or less.

4. The molar ratio of Mg to Ti in the internal dielectric layer located in region 1-3-5 is 0.20 or more and 1.00 or less, and is 40% or more and 50% or less compared to the molar ratio of Mg to Ti in the internal dielectric layer located in region 1-3-1, as described in claim 3.

5. The multilayer ceramic capacitor according to claim 4, wherein the molar ratio of Mg contained in the internal dielectric layer located in region 1-3-9 to Ti is 0.05 or more and 0.40 or less, and is 10% or more and 20% or less compared to the molar ratio of Mg contained in the internal dielectric layer located in region 1-3-1 to Ti.

6. The internal dielectric layer is BaTiO ３ The multilayer ceramic capacitor according to claim 2, wherein the main component is Mn, and the molar ratio of Mn to Ti in the internal dielectric layer located in region 1-3-1 is 0.50 or more and 1.00 or less.

7. The multilayer ceramic capacitor according to claim 6, wherein the molar ratio of Mn to Ti in the internal dielectric layer located in region 1-3-5 is 0.20 or more and 1.00 or less, and is 40% or more and 50% or less compared to the molar ratio of Mn to Ti in the internal dielectric layer located in region 1-3-1.

8. The molar ratio of Mn to Ti in the internal dielectric layer located in region 1-3-9 is 0.05 or more and 0.40 or less, and is 10% or more and 20% or less compared to the molar ratio of Mn to Ti in the internal dielectric layer located in region 1-3-1, as described in claim 7.

9. The multilayer ceramic capacitor according to claim 3, wherein the molar ratio of Mn and Mg contained in the internal dielectric layer located in region 1-3-1 to Ti is 0.50 or more and 1.00 or less for both.

10. The multilayer ceramic capacitor according to claim 9, wherein the molar ratio of Mg contained in the internal dielectric layer located in region 1-3-5 to Ti is 0.20 or more and 0.50 or less, and is 40% or more and 50% or less compared to the molar ratio of Mg contained in the internal dielectric layer located in region 1-3-1 to Ti.

11. The multilayer ceramic capacitor according to claim 10, wherein the molar ratio of Mg contained in the internal dielectric layer located in region 1-3-9 to Ti is 0.05 or more and 0.20 or less, and is 10% or more and 20% or less compared to the molar ratio of Mg contained in the internal dielectric layer located in region 1-3-1 to Ti.

12. The multilayer ceramic capacitor according to claim 11, wherein the molar ratio of Mn to Ti in the internal dielectric layer located in region 1-3-5 is 0.20 or more and 0.50 or less, and is 40% or more and 50% or less compared to the molar ratio of Mn to Ti in the internal dielectric layer located in region 1-3-1.

13. The multilayer ceramic capacitor according to claim 12, wherein the molar ratio of Mn to Ti in the internal dielectric layer located at 1-3-9 is 0.05 or more and 0.20 or less, and is 10% or more and 20% or less compared to the molar ratio of Mn to Ti in the internal dielectric layer located at 1-3-1.

14. The multilayer ceramic capacitor according to claim 1 or 2, wherein the inner electrode on the first surface side has a Ni-Mn alloy layer, the end of the inner electrode on the first surface side in the first direction has an Mg region, and the total dimension of the Ni-Mn alloy layer in the first direction in a cross section passing through the stacking direction and the first direction at the center in the second direction is longer than the total dimension of the Mg region in the first direction.

15. In a cross-section passing through the stacking direction and the first direction at the center of the second direction, the third outer layer contains Mn within a distance W(Mn) from the interface between the first outer layer and the third outer layer, the first outer layer contains Mg within a distance W(Mg) from the interface, and W(Mn) is less than W(Mg), the multilayer ceramic capacitor according to claim 1 or 2.

16. The multilayer ceramic capacitor according to claim 1 or 2, wherein in a region including the interface between the first outer layer and the third outer layer in a cross section passing through the stacking direction and the first direction at the center of the second direction, Si is distributed with a straight-line propagation of 1 μm to 5 μm.

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