Motor control device

Abstract

The present invention addresses the problem of providing a motor control device with which the responsiveness of multi-edge PWM control can be improved. A motor control device 1 comprises: an edge number determination unit 7 that determines a switch number Ndet which is the number of times that a switching element of an inverter 3 is switched On / Off within a control cycle; a current detection unit 5 that detects the current of an AC motor 2 connected to the inverter 3, and that derives the current value of the AC motor 2 for each control cycle from a detection value of the current; a voltage command value generation unit 4 that generates a voltage command value for each control cycle on the basis of the current value derived by the current detection unit 5; and a pulse generation unit 6 that calculates a switch timing on the basis of the voltage command value. A control delay time corresponding to the switch number Ndet is smaller than a control delay time corresponding to a minimum switch number Nmin.

Description

Motor control device

[0001] The present invention relates to a motor control device.

[0002] In a motor drive system, higher efficiency is required. In modern motor drives, the output voltage is controlled by PWM (pulse width modulation), but the harmonic current generated by the harmonic voltage contained in the pulse voltage is a factor increasing the motor iron loss and magnet loss. On the other hand, in the asynchronous PWM region (PWM where the carrier signal and the electrical angle of the motor are not synchronized), in order to reduce the harmonic current generated by PWM and suppress the motor loss, it is effective to use a higher switching frequency. In particular, in wide bandgap semiconductors such as SiC, which have been increasingly applied in recent years, the switching loss of the inverter does not increase much with the increase in the switching frequency. Therefore, the reduction effect of the loss due to the harmonic current of the motor is superior, and the region where the efficiency as a drive system is improved is expanding.

[0003] In general inverter control, the switching timing for one time within the next control period is calculated in one control period. Therefore, in order to improve the switching frequency of the inverter, it is necessary to shorten the control period. However, in reality, there is a limit to shortening the control period, so the switching frequency cannot necessarily be increased to the desired frequency. Therefore, in Patent Document 1, PWM control is shown in which a plurality of switching timings are calculated in one control period and switched a plurality of times, so that the effective switching frequency can be increased to an integer multiple of the control period.

[0004] International Publication No. 2024 / 095330

[0005] When realizing PWM control (multi-edge PWM control) in which a certain switching frequency is switched a plurality of times in the above-mentioned one control period, the relationship of Equation (1) holds among the switching frequency fsw, the number of switchings N per control, and the control frequency fc.

[0006]

[0007] In multi-edge PWM control, there are various combinations of the number of switches N and the control frequency fc that can achieve a given switching frequency fsw, so it is necessary to select the appropriate N and fc.

[0008] Therefore, we consider minimizing the control delay time. In this specification, the control delay time refers to the time taken from the moment a current is detected until the voltage command value based on the detected current is output as a PWM voltage waveform. In control, it is desirable that the control delay time be as short as possible from the viewpoint of stability and responsiveness. Generally, the control delay time is determined in proportion to the control period, so to shorten the control delay time, the control period should be shortened. In other words, it can be said that we should select the combination that maximizes fc among the many possible combinations.

[0009] However, in reality, due to the processing power limitations of microcontrollers and other devices, there is an upper limit to fc. Therefore, we select the largest possible combination of fc and N that does not exceed the maximum executable control frequency fcM. In this case, N is the smallest possible combination of fc and N, and will be referred to as Nmin from now on.

[0010] The above-described method for selecting N and fc is correct when the current detection method is fixed relative to N. However, when the current detection method changes depending on N, the combination of Nmin and fc may not minimize the control delay time.

[0011] The present invention has been made in view of the above, and the object of the present invention is to provide a motor control device that can improve the responsiveness of multi-edge PWM control.

[0012] To achieve the above objective, the motor control device of the present invention comprises: an edge count determination unit that determines the number of times the switching elements of the inverter are switched on / off within a control cycle; a current detection unit that detects the current of the AC motor connected to the inverter and derives the current value of the AC motor from the detected current value for each control cycle; a voltage command value generation unit that generates a voltage command value for each control cycle based on the current value derived by the current detection unit; and a pulse generation unit that calculates the switch timing based on the voltage command value, wherein the control delay time corresponding to the number of switches is smaller than the control delay time corresponding to the minimum number of switches.

[0013] According to the present invention, the responsiveness of multi-edge PWM control can be improved. Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

[0014] This is a functional block diagram showing the configuration of the motor control device along with related configurations. This is a functional block diagram showing the processing content of the edge count determination unit according to the first embodiment. This is a diagram showing an example of setting the detection timing of the current detection unit according to the first embodiment (number of switches N=1). This is a diagram showing an example of setting the detection timing of the current detection unit according to the first embodiment (number of switches N=2). This is a diagram showing an example of setting the reference phase. This is a diagram schematically showing the state of the control delay time (number of switches N=1). This is a diagram schematically showing the state of the control delay time (number of switches N=2). This is a diagram showing how the control delay time changes with the number of switches. This is a functional block diagram showing the processing content of the edge count determination unit according to the second embodiment. This is a diagram showing the relationship between the detection timing of the current detection unit and the current waveform according to the second embodiment (number of switches N=4). This is a diagram showing the relationship between the detection timing of the current detection unit and the current waveform according to the second embodiment (number of switches N=2).

[0015] Embodiments of the present invention will be described in detail below with reference to the drawings. In this embodiment, a three-phase AC motor and an inverter are used as examples of the control targets of the motor control device, but the invention is not limited to these, and for example, multi-phase AC motors and inverters other than three-phase may be used as control targets. The objective of this embodiment is to provide a motor control device that minimizes the control delay time that occurs when a certain switching frequency is achieved using multi-edge PWM control, for example.

[0016] <First Embodiment> The first embodiment of the present invention will be described with reference to Figures 1 to 6.

[0017] Figure 1 is a functional block diagram showing the configuration of the motor control device according to this embodiment, along with related components.

[0018] As shown in Figure 1, the AC motor 2, which is the target of control by the motor control device 1, is connected to the motor control device 1 via an inverter 3 having multiple switching elements. The inverter 3 controls the three-phase AC voltage supplied to the AC motor 2 by switching the ON / OFF state of the switching elements in response to the gate drive signal output by the motor control device 1.

[0019] The AC motor 2 is a synchronous motor that is driven by a three-phase AC voltage supplied from the inverter 3. The AC motor 2 has a rotational position sensor 2a to control the phase of the three-phase AC voltage applied from the inverter 3 to match the phase of the induced voltage of the AC motor 2. Here, the rotational position sensor 2a can be, for example, a resolver composed of an iron core and windings. Alternatively, the rotational position sensor 2a may be configured using a GMR (Giant Magneto Resistive effect) sensor or a Hall element.

[0020] The motor control device 1 includes a voltage command value generation unit 4, a current detection unit 5, a pulse generation unit 6, an edge count determination unit 7, and a rotation position detection unit 8. The motor control device 1 is, for example, a microcontroller and consists of a storage device such as memory, a processor such as a CPU (Central Processing Unit), and a gate driver circuit. The processor functions as the voltage command value generation unit 4, current detection unit 5, pulse generation unit 6, edge count determination unit 7, and rotation position detection unit 8 by executing a program stored in the storage device.

[0021] The rotation position detection unit 8 detects the rotation position θ of the rotor in the AC motor 2 based on the output signal of the rotation position sensor 2a. Alternatively, instead of detecting the rotation position θ of the rotor from the output signal of the rotation position sensor 2a, the rotation position θ of the rotor of the AC motor 2 may be estimated from the current and voltage of various parts, and this value may be used as the detected value.

[0022] The voltage command value generation unit 4 has a control function for controlling the output of the AC motor 2. It generates and outputs voltage command values ​​(Vd*, Vq*) (dq-axis voltage command values) so that the output (motor output) of the AC motor 2 calculated from the command value input from the motor control device 1, AC motor 2, inverter 3, etc., and the detected current obtained from the current detection unit 5 matches. The voltage command value generation unit 4 recalculates and updates the voltage command values ​​(Vd*, Vq*) at each update cycle (control cycle). For example, current, magnetic flux, torque, etc., can be used as the control amount for the motor output.

[0023] The edge count determination unit 7 uses information received from the higher-level control device 9 to determine the number of switches input to the current detection unit 5 and the pulse generation unit 6 (motor control device 1). The number of switches determined by the edge count determination unit 7 is the number of times the switching element of the inverter 3 is switched ON / OFF during one control cycle. For example, if the number of switches is 3, the switching element of the inverter 3 will switch ON / OFF 3 times within one control cycle. Note that the number of switches can also be called the number of edges (rising or falling edges of the voltage waveform).

[0024] Figure 2 is a functional block diagram showing the processing details of the edge count determination unit 7.

[0025] As shown in Figure 2, the edge count determination unit 7 consists of a minimum switch count calculation unit 71, a switch count determination unit 72, and a control frequency determination unit 73. The required switching frequency 91 and the maximum control frequency 92 are obtained from the higher-level control unit 9. The required switching frequency 91 is determined by the designer and the higher-level control unit 9 based on multiple factors such as system efficiency, thermal constraints of the switching elements, and sound vibration. The maximum control frequency 92 is the maximum configurable value of the update cycle of the control command value set by the higher-level control unit 9, and is a value determined by the computational load and the performance of the computer.

[0026] The minimum number of switches calculation unit 71 calculates the minimum number of switches Nmin from the required switching frequency fsw(91) and the maximum control frequency fcM(92) obtained from the higher-level control device 9 using equation (2).

[0027]

[0028] However, the parentheses on the right side indicate a rounding up operation. Nmin is the minimum number of switches required to achieve the requested FSW. With fewer than Nmin, the control cycle becomes extremely short, and the calculation of command values ​​cannot be completed, causing the control to fail.

[0029] The switch count determination unit 72 determines the switch count Ndet such that the control delay time is minimized for switch counts of Nmin or more. Detailed operation will be described later.

[0030] The control frequency determination unit 73 calculates the control frequency fc using the number of switches Ndet determined by the switch count determination unit 72 as fsw / Ndet.

[0031] The current detection unit 5 shown in Figure 1 detects the current based on the switch count 74 and control frequency 75 output from the edge count determination unit 7. Figures 3A and 3B show the control period, phase voltage, phase current, and current detection timing when the switch count N is 1 and 2, respectively. Current detection is performed by holding the sensor value at the detection timing and then converting it to a digital value using an A / D converter. In this example, the current is detected at timings that divide the control period into two equal parts. In reality, there are three phases, U, B, C, and W, but the U phase is shown as a representative example.

[0032] The current detection unit 5 converts the two three-phase current values ​​iuvw1 and iuvw2 detected in the i-th control cycle to the dq axis using the electrical angle at the corresponding time, and calculates idq1 and idq2. It also selects a value to output to the voltage command value generation unit 4 from the detected current values ​​according to the number of switches 74. For example, as shown in Figure 3A, when N=1, the current detection unit 5 outputs idq1, and as shown in Figure 3B, when N=2, the current detection unit 5 outputs the average of idq1 and idq2, <idq>=(idq1+idq2) / 2.

[0033] When generalizing the output value for the number of switches N, the current detection unit 5 outputs idq1 when N is odd, and outputs the average of idq1 and idq2 when N is even. This is because when N is odd, switching may occur around the second current detection timing, resulting in a current value that includes the influence of carrier harmonics, so idq2 is not used as the detected current value. On the other hand, when N is even, the influence of carrier harmonic current due to switching is small at both the first and second current detection timings, so both idq1 and idq2 are used and averaged for output. By taking the average, even if the current detection timing fluctuates slightly due to variations in the microcontroller, the discrepancies in the detected current values ​​cancel each other out, making it less likely for the influence to appear in the current value.

[0034] The pulse generation unit 6 uses the voltage command values ​​(Vd*, Vq*) generated by the voltage command value generation unit 4, the DC voltage DCV connected to the inverter 3, the rotation position θ of the AC motor 2 detected by the rotation position detection unit 8, and the switch count 74 output from the edge count determination unit 7 to generate switch timings for each of the U, V, and W phases. These timings are set in a format suitable for a microcomputer (MPC) and the like as the timings at which the switching elements of the inverter 3 should be switched ON / OFF, and these timings are output to the inverter 3 as gate drive signals.

[0035] The switching timing can be determined, for example, as follows:

[0036] First, the pulse generation unit 6 divides the control period into equal parts by the number of switches N (= Ndet) obtained from the edge number determination unit 7, and sets the center of each divided section as the reference phase θn (n = 1, 2, ..., N). Next, the pulse generation unit 6 converts the voltage command values ​​(Vd*, Vq*) from the voltage command value generation unit 4 into three-phase voltages using the following equation (3), and calculates the three-phase modulation rate command value by dividing the converted value by the DC voltage DCV (voltage value: Vdc).

[0037]

[0038] At this point, by substituting θn for θ, n modulation rate command values ​​can be obtained.

[0039] In the case shown in Figure 4, the nth reference phase θn for which the modulation rate should be determined can be calculated using the following equation (4), where T is the control period, ω is the electrical angular velocity, and θS is the phase corresponding to the beginning of the control period.

[0040]

[0041] Note that in this embodiment, the electrical angular velocity ω is obtained by differentiating the electrical angle of the rotational position detection unit 8, but an electrical angular velocity obtained by other methods may also be used. For example, a command value in speed control may be used. Also, in this embodiment, the case where the electrical angular velocity is constant is assumed for explanation, but it is not limited to this. For example, angular acceleration may be acquired in advance, and the phase θn may be obtained on the premise that the electrical angular velocity changes gradually. By substituting the phase θn obtained by the above formula (4) into θ in formula (3), the pulse generation unit 6 calculates the modulation rate command value mun* corresponding to the nth phase.

[0042] Next, based on the modulation rate command value mun* corresponding to the phase θn, the pulse generation unit 6 generates a duty command value. For example, taking the U phase as a representative example, the pulse generation unit 6 uses the following formula (5) to convert the modulation rate command value mun* into a duty command value Dun*, with the case of always ON in one control cycle being 1.

[0043]

[0044] Finally, based on the finally generated duty command value Dun*, the pulse generation unit 6 calculates and sets the timing (the timing to be switched) at which the ON / OFF of the switching element of the inverter 3 should be switched in a form suitable for a microcomputer (microcontroller), etc., and outputs it to the inverter 3 as a gate drive signal.

[0045] The operation and effect of this embodiment configured as described above will be described.

[0046] The change in control delay time in this embodiment will be explained using Figures 5A and 5B. As shown in Figure 5A, when N is odd, it takes an average of control period (i) for current detection, control period (i+1) for voltage command value generation, and control period (i+2) / 2 for the switch to be executed as a pulse. Therefore, if all control periods Tc are equal, a control delay time of 2.5Tc occurs. As shown in Figure 5B, when N is even, it takes an average of (control period (i) + control period (i) / 2) / 2 = 0.75 control periods (i) for current detection. Since the time taken for voltage command value generation and switch execution as a pulse is the same, a total control delay time of 2.25Tc occurs.

[0047] Since Tc = 1 / fc, the control delay time is inversely proportional to the control frequency. Therefore, in conventional control where the current detection method is fixed relative to N, fsw is constant, and to minimize the control delay time, fc should be maximized (number of switches N min). However, in this embodiment, where the operation of the current detection unit 5 changes according to the number of switches N, the relationship between N and the control delay time due to current detection changes, so it is not always possible to minimize the control delay time by setting the number of switches to N min as in the conventional method.

[0048] In contrast, this embodiment provides a motor control device 1 for controlling an inverter 3 having a plurality of switching elements, comprising: an edge count determination unit 7 that determines the number of times the switching elements are switched on / off within a control cycle; a current detection unit 5 that detects the current flowing through the coil of the AC motor at a current detection timing determined according to the number of switches; a voltage command value generation unit 4 that generates a voltage command value at predetermined intervals based on the output current value of the current detection unit; and a pulse generation unit 6 that determines the same number of switch timings as the number of switches of the switching elements based on the voltage command value. The edge count determination unit 7 is configured to determine the number of switches in such a way that the control delay time is shortened based on the switching frequency and control frequency constraints. This makes it possible to expand the phase margin in control by minimizing the control delay time, thereby improving the stability and responsiveness of the control. Furthermore, for example, low-latency current control can contribute to advanced vehicle control in automobiles.

[0049] In other words, in this embodiment, as shown in Figure 6, the control delay time at a switch count of Nmin is compared with the control delay time at a switch count of N greater than Nmin. It is checked whether the control delay time becomes smaller than Nmin at N greater than Nmin, and if it does, N is determined as the switch count Ndet. This minimizes the control delay time within the feasible control frequency.

[0050] Alternatively, by substituting Tc = 1 / fc = N / fsw into the control delay time relation and expressing even and odd values ​​as a natural number for m, the relationship in equation (6) can be derived.

[0051]

[0052] In this case, since we know in advance that the condition for minimizing the control delay time with a number of switches greater than Nmin is m ≥ 6, we can also determine the number of switches using a conditional branch, such as "If Nmin ≥ 11 and Nmin is odd, set the number of switches Ndet to Nmin + 1."

[0053] In this embodiment, for illustrative purposes, we considered a case where the current detection timing is detected twice at equal intervals during one control cycle, and the current calculation method is switched according to whether the number of switches is even or odd. However, current detection may be performed at any number of times and timings as long as the performance of the current detection AD converter and computer allows. In that case as well, if the delay time caused by current detection can be defined as a function of the control cycle and can be calculated in advance in relation to N, the switch count determination unit 72 can determine the number of switches Ndet that minimizes the control delay time, as discussed above.

[0054] The main features of the first embodiment can also be summarized as follows:

[0055] As shown in Figure 1, the motor control device 1 includes an edge count determination unit 7 that determines the number of switches Ndet, which is the number of times the switching elements of the inverter 3 are switched on / off within a control cycle; a current detection unit 5 that detects the current of the AC motor 2 connected to the inverter 3 and derives the current value of the AC motor 2 from the detected current value for each control cycle; a voltage command value generation unit 4 that generates a voltage command value for each control cycle based on the current value derived by the current detection unit 5; and a pulse generation unit 6 that calculates the switch timing based on the voltage command value. The control delay time corresponding to the number of switches Ndet is smaller than the control delay time corresponding to the minimum number of switches Nmin (Figure 6). By reducing the control delay time, the responsiveness of multi-edge PWM control can be improved.

[0056] The current detection unit 5 detects the current of the AC motor 2 at timings corresponding to the number of switches Ndet for each control cycle (Figures 5A, 5B), or derives the current value of the AC motor 2 from the detected current value in a manner corresponding to the number of switches Ndet for each control cycle (Figures 3A, 3B, 5A, 5B). This makes it possible to avoid the influence of carrier harmonics on the current value of the AC motor 2.

[0057] The pulse generation unit 6 calculates the switch timing based on the number of switches N = Ndet (Equations (3) to (5), Figure 1). This makes it possible to generate pulses (gate drive signals) that switch the switching elements of the inverter 3 on / off a number of times N = Ndet within the control cycle.

[0058] The pulse generation unit 6 of this embodiment uses the number of switches N = Ndet to derive the phase (reference phase θn, equation (4), Figures 1 and 4) or the number of phases (= number of switches N, Figure 4) for calculating the switch timing. This makes it possible to calculate the switch timing for each phase.

[0059] As shown in Figures 5A and 5B, the control delay time includes the time required to detect the current corresponding to the number of switches. Thus, the control delay time reflects the time required to detect the current corresponding to the number of switches. In this embodiment, the control delay time includes not only the time required to detect the current corresponding to the number of switches, but also the time required to generate the voltage command value and the time required to generate the voltage waveform, although it is not necessary to include both.

[0060] Furthermore, the control delay time includes the time required to generate the voltage command value or the time required to generate the voltage waveform. As a result, the control delay time reflects the time required to generate the voltage command value or the time required to generate the voltage waveform. In this embodiment, the control delay time includes both the time required to detect the current based on the number of switches, as well as the time required to generate the voltage command value and the time required to generate the voltage waveform (Figures 5A and 5B), but it may also include only one of them.

[0061] The current detection unit 5 switches between at least two types of current detection operations according to the number of switches Ndet (Figures 5A and 5B). This makes it possible to avoid the influence of carrier harmonics on the detected current value according to the number of switches Ndet.

[0062] The edge number determination unit 7 calculates the minimum number of switches Nmin required to achieve the switching frequency fsw from the constraints on the control frequency (for example, the maximum control frequency fcM) and the switching frequency fsw (Equation (2), Figure 2). This makes it easy to calculate the minimum number of switches Nmin.

[0063] For example, if the number of switches Ndet is odd, the current detection unit 5 may detect the current near the start of the control cycle and derive the detected current value as the current value of the AC motor 2 (Figure 5A). Alternatively, if the number of switches Ndet is even, the current detection unit 5 may detect the current near the start of the control cycle and near the center of the control cycle and derive the average of the two detected current values ​​as the current value of the AC motor 2 (Figure 5B). This makes it possible to avoid the influence of carrier harmonics on the detected current value depending on whether the number of switches Ndet is even or odd.

[0064] The edge count determination unit 7 determines the number of switches Ndet as the minimum number of switches Nmin plus 1 if Nmin is an odd number greater than or equal to 11. This eliminates the need to search for Ndet when Nmin is an odd number greater than or equal to 11, allowing for high-speed determination of Ndet.

[0065] <Second Embodiment> A second embodiment of the present invention will be described with reference to Figure 7.

[0066] This embodiment shows a case where the selection of a specific number of switches is prohibited when determining the number of switches. In this embodiment, the same reference numerals are used for components similar to those in the first embodiment, and their descriptions are omitted as appropriate.

[0067] In this embodiment, the selection avoidance switch count setting unit 76 is located within the edge count determination unit 7. The other configurations are the same as in the first embodiment.

[0068] For example, consider the case where the current detection timing coincides with the timing when the slope of the harmonic current is always positive (or negative), as shown in Figure 8A. In this case, if detection timing 1 and detection timing 2 are shifted by roughly the same amount due to various variations, as indicated by the dashed triangles in Figure 8A, the detected current will shift in one direction, positive or negative, and an offset will be added to the detected current value. If control is performed with such a current offset, the actual output current will be offset relative to the control target current, resulting in a decrease in torque accuracy and other problems.

[0069] Therefore, as shown in Figure 8A, the number of switches that are detected for the same slope of the harmonic current across multiple control cycles is set in the selection avoidance switch count setting unit, and these are excluded from the number of switches for checking the control delay time in the switch count determination unit. For the current detection shown as a specific example in the first embodiment, the number of selection avoidance switches is a multiple of 4. For numbers other than multiples of 4, the current detection timing will alternately detect the positive and negative of the current slope. For example, as shown in Figure 8B with N=2, the effect of the shift is canceled out on average.

[0070] In this embodiment configured as described above, the same effects as in the first embodiment can be obtained.

[0071] Furthermore, because it can suppress current offset caused by timing discrepancies in detection, it can improve the accuracy of current and torque control.

[0072] The main features of the second embodiment can also be summarized as follows:

[0073] The edge count determination unit 7 determines the number of switches Ndet from the number of switches N greater than the minimum number of switches Nmin, excluding a predetermined number of switches (for example, a multiple of 4) (for example, Nmin < N, N ≠ 4m, m: a natural number) (Figure 7). This avoids problems (for example, current offset) that may occur if the number of switches Ndet becomes a predetermined number of switches.

[0074] Within a predetermined number of switches (for example, a multiple of 4), the number of timings in which the current slope is positive among the multiple timings in which current is detected within two consecutive control cycles is different from the number of timings in which the current slope is negative (Figure 8A). This makes it possible to suppress current offset.

[0075] <Note> The present invention is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of the invention. For example, the embodiments described above are described in detail for the purpose of explaining the present invention in an easy-to-understand manner, and are not necessarily limited to those having all the configurations described.

[0076] For example, while the explanation has described the case where the control delay time is calculated as in the first embodiment, the system is not limited to this, and other possible elements of the control delay time may be incorporated.

[0077] Furthermore, while examples were given for setting the number of selection avoidance switch cycles to a multiple of 4, as in the second embodiment, the invention is not limited to this. Design constraints may be taken into consideration, or the setting value may be changed according to the current detection operation.

[0078] Furthermore, each of the above configurations, functions, processing units, and processing procedures may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. Alternatively, each of the above configurations and functions may be implemented in software by having the processor interpret and execute programs that realize each function.

[0079] Furthermore, the signal lines and information lines shown are those deemed necessary for explanation and do not necessarily represent all control lines or information lines. Also, the above configurations, functions, processing units, and processing procedures do not necessarily need to be in the same physical location; for example, some may reside on a network or in the cloud via communication.

[0080] Embodiments of the present invention may also be as follows.

[0081] (C1). A motor control device for controlling a power converter (inverter 3) having a plurality of switching elements, comprising: an edge count determination unit that determines the number of times the switching elements are switched on / off within a control cycle; a current detection unit that detects the current flowing through the coil of the AC motor at a current detection timing determined according to the number of switches; a voltage command value generation unit that generates a voltage command value at predetermined intervals based on the output current value of the current detection unit; and a pulse generation unit that determines the same number of switch timings as the number of switches of the switching elements based on the voltage command value, wherein the edge count determination unit determines the number of switches such that the control delay time is reduced from the constraints of the switching frequency and the control frequency.

[0082] (C2) A motor control device as described in (C1), wherein the current detection unit switches the current detection timing or the method of calculating the detected current value based on the number of switches.

[0083] (C3). A motor control device as described in (C1), wherein the pulse generation unit switches the phase and the number of phases for calculating the switch timing based on the number of switches.

[0084] (C4). A motor control device as described in (C1), wherein the edge number determination unit determines the number of switches from the number of switches excluding the number of switches that satisfy a specific condition.

[0085] (C5) A motor control device as described in (C1), characterized in that the control delay time includes any of the time required for current detection, the time required for voltage command value generation, or the time required for the set value of the pulse generation unit to be reflected in the power converter.

[0086] (C6). A motor control device according to (C2), wherein the current detection unit switches between at least two types of current detection operations according to the number of switches.

[0087] According to (C1)-(C6), improvements in the stability and responsiveness of the control system can be achieved.

[0088] 1...Motor control device, 2...AC motor, 2a...Rotation position sensor, 3...Inverter, 4...Voltage command value generation unit, 5...Current detection unit, 6...Pulse generation unit, 7...Edge count determination unit, 8...Rotation position detection unit, 9...Higher-level control device

Claims

1. A motor control device comprising: an edge count determination unit that determines the number of times the switching elements of an inverter are switched on / off within a control cycle; a current detection unit that detects the current of an AC motor connected to the inverter and derives the current value of the AC motor from the detected current value for each control cycle; a voltage command value generation unit that generates a voltage command value for each control cycle based on the current value derived by the current detection unit; and a pulse generation unit that calculates the switch timing based on the voltage command value, wherein the control delay time corresponding to the number of switches is smaller than the control delay time corresponding to the minimum number of switches.

2. A motor control device according to claim 1, wherein the current detection unit detects the current of the AC motor at timings corresponding to the number of switches for each control cycle, or derives the current value of the AC motor from the detected current value in a manner corresponding to the number of switches for each control cycle.

3. A motor control device according to claim 1, wherein the pulse generation unit calculates the switch timing based on the number of switches.

4. A motor control device according to claim 3, wherein the pulse generation unit derives a phase or number of phases for calculating the switch timing using the number of switches.

5. A motor control device according to claim 1, wherein the edge number determination unit determines the number of switches from a number of switches greater than the minimum number of switches, excluding a predetermined number of switches.

6. A motor control device according to claim 1, characterized in that the control delay time includes the time required for detecting the current corresponding to the number of switches.

7. A motor control device according to claim 6, characterized in that the control delay time includes the time required for generating the voltage command value or the time required for generating the voltage waveform.

8. A motor control device according to claim 1, wherein the current detection unit switches between at least two types of current detection operations according to the number of switches.

9. A motor control device according to claim 1, wherein the edge number determination unit calculates the minimum number of switches required to achieve the switching frequency from the constraints of the control frequency and the switching frequency.

10. A motor control device according to claim 5, characterized in that, within a predetermined number of switches, the number of timings in which the slope of the current is positive among a plurality of timings in which the current is detected within two consecutive control cycles is different from the number of timings in which the slope of the current is negative.

11. A motor control device according to claim 2, wherein the current detection unit detects a current near the start of the control cycle when the number of switches is odd, and derives the detected current value as the current value of the AC motor; and when the number of switches is even, it detects a current near the start of the control cycle and near the center of the control cycle, and derives the average of the two detected current values ​​as the current value of the AC motor.

12. A motor control device according to claim 11, wherein the edge number determination unit determines the number of switches as the minimum number of switches plus 1 when the minimum number of switches is an odd number of 11 or more.

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