Current sampling method and apparatus, device, and medium

Abstract

A current sampling method and apparatus, a device, and a medium. The method comprises: outputting an interrupt control signal and a MOS transistor drive signal (S11), the interrupt control signal and the MOS transistor drive signal having a harmonic relationship; when a first counter corresponding to the interrupt control signal reaches a first preset count value, sampling an induction current (S12), the induction current being an induction current formed by an on-off state of a MOS transistor driven by the MOS transistor drive signal, and the induction current being at the midpoint of a rising edge or a falling edge when the first counter reaches the first preset count value. In this way, the stability of current sampling can be improved, so as to achieve more stable control.

Description

A current sampling method, apparatus, device and medium

[0001] This application claims priority to Chinese Patent Application No. 202411425727.4, filed on October 12, 2024, entitled "A Current Sampling Method, Apparatus, Device and Medium", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of current sampling technology, and in particular to a current sampling method, apparatus, device and medium. Background Technology

[0003] Currently, typical energy storage systems use direct, fixed-point current sampling, which is then applied to control systems. This method results in a significant DC component and corresponding current harmonics in the output, impacting grid quality. It also leads to additional losses and heat generation, shortening equipment lifespan. Furthermore, various certification standards now have requirements for controlling the DC component and current harmonics within a limited range. However, traditional sampling methods struggle to effectively control this component; the lack of stability in current sampling results in a lack of stability in the control system. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a current sampling method, apparatus, device, and medium that can improve the stability of current sampling, thereby achieving more stable control. The specific solution is as follows:

[0005] Firstly, this application provides a current sampling method, including:

[0006] Output interrupt control signal and MOS transistor drive signal, wherein the interrupt control signal and the MOS transistor drive signal have a frequency multiplication relationship;

[0007] When the first counter corresponding to the interrupt control signal reaches the first pre-designed value, the inductor current is sampled. The inductor current is the inductor current formed by the on / off state of the MOS transistor driven by the MOS transistor drive signal. When the first counter reaches the first pre-designed value, the inductor current is at the midpoint of the rising edge or the falling edge.

[0008] Optionally, the output interrupt control signal and the MOS transistor drive signal include:

[0009] An interrupt control signal is output based on the first enhanced pulse width modulation module, wherein the first enhanced pulse width modulation module adopts a rising and falling edge mode;

[0010] The second enhanced pulse width modulation module outputs a MOS transistor drive signal, wherein the second enhanced pulse width modulation module adopts a rising and falling edge mode.

[0011] Optional, also includes:

[0012] When the second count value of the second counter corresponding to the MOS transistor drive signal reaches the comparison value set in the second enhanced pulse width modulation module, the MOS transistor is driven to perform the corresponding on / off operation to realize the inductor current flipping.

[0013] Optionally, when the second count value of the second counter corresponding to the MOS transistor drive signal reaches the comparison value set in the second enhanced pulse width modulation module, the MOS transistor is driven to perform a corresponding on / off operation, including:

[0014] When the second count value of the second counter corresponding to the MOS transistor drive signal is in an upward state, and the second count value reaches the comparison value, the upper MOS transistor is driven to close and the lower MOS transistor is driven to open.

[0015] When the second count value of the second counter corresponding to the MOS transistor drive signal is in a decreasing state, and the second count value reaches the comparison value, the upper MOS transistor is driven to disconnect and the lower MOS transistor is driven to close.

[0016] Optionally, before the output interrupt control signal and the MOSFET drive signal, the following further includes:

[0017] Align the count values ​​of the first counter and the second counter.

[0018] Optionally, sampling the inductor current includes:

[0019] When a sampling signal is detected, the inductor current is sampled, wherein the sampling signal is a signal triggered when the first counter corresponding to the interrupt control signal reaches a first pre-designed value.

[0020] Optionally, after sampling the inductor current, the method further includes:

[0021] When the cycle end point corresponding to the interrupt control signal is reached, grid-connected output control is performed based on the sampled inductor current.

[0022] Secondly, this application discloses a current sampling device, comprising:

[0023] The signal output module includes an output interrupt control signal and a MOS transistor drive signal, wherein the interrupt control signal and the MOS transistor drive signal have a frequency multiplication relationship;

[0024] An inductor current sampling module is used to sample the inductor current when the first counter corresponding to the interrupt control signal reaches a first pre-designed value. The inductor current is the inductor current formed by the on / off state of the MOS transistor driven by the MOS transistor drive signal. When the first counter reaches the first pre-designed value, the inductor current is at the midpoint of the rising edge or the falling edge.

[0025] Thirdly, this application discloses an electronic device, including a memory and a processor, wherein:

[0026] The memory is used to store computer programs;

[0027] The processor is used to execute the computer program to implement the aforementioned current sampling method.

[0028] Fourthly, this application discloses a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the aforementioned current sampling method.

[0029] As can be seen from the above scheme, the present invention provides a current sampling method, including: outputting an interrupt control signal and a MOS transistor drive signal, wherein the interrupt control signal and the MOS transistor drive signal have a frequency multiplication relationship; when the first counter corresponding to the interrupt control signal reaches a first pre-designed value, the inductor current is sampled, wherein the inductor current is the inductor current formed by the on-off state of the MOS transistor driven by the MOS transistor drive signal, and when the first counter reaches the first pre-designed value, the inductor current is at the midpoint of the rising edge or the falling edge.

[0030] As can be seen, the beneficial effects of this application are: the output interrupt control signal and MOSFET drive signal with a frequency multiplication relationship are convenient to determine the periodic sampling point, ensure that the sampling point of the inductor current is always located at the midpoint of the inductor current, avoid the noise influence of MOSFET switching, effectively avoid the influence of excessive DC component and current harmonics on the power grid under grid connection, and improve the stability of current sampling to achieve more stable control.

[0031] Correspondingly, the current sampling device, equipment, and readable storage medium provided in this application also have the above-mentioned technical effects. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0033] Figure 1 is a flowchart of a current sampling method provided in an embodiment of this application;

[0034] Figure 2 is a schematic diagram of a signal waveform provided in an embodiment of this application;

[0035] Figure 3 is a schematic diagram of the hardware circuit of an application current sampling method provided in an embodiment of this application;

[0036] Figure 4 is a schematic diagram of a test waveform based on a conventional current sampling method;

[0037] Figure 5 is a schematic diagram of a test waveform based on a conventional current sampling method;

[0038] Figure 6 is a schematic diagram of a test waveform based on a conventional current sampling method;

[0039] Figure 7 is a schematic diagram of a test waveform based on a conventional current sampling method;

[0040] Figure 8 is a schematic diagram of the test waveform corresponding to a current sampling method provided in an embodiment of this application;

[0041] Figure 9 is a schematic diagram of the test waveform corresponding to a current sampling method provided in an embodiment of this application;

[0042] Figure 10 is a schematic diagram of the test waveform corresponding to a current sampling method provided in an embodiment of this application;

[0043] Figure 11 is a schematic diagram of the test waveform corresponding to a current sampling method provided in an embodiment of this application;

[0044] Figure 12 is a schematic diagram of a current sampling device provided in an embodiment of this application;

[0045] Figure 13 is a structural diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] Referring to Figure 1, this application discloses a current sampling method, including:

[0048] Step S11: Output an interrupt control signal and a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) drive signal, wherein the interrupt control signal and the MOS transistor drive signal have a frequency multiplication relationship.

[0049] The interrupt control signal is used to control grid-connected output when a preset interrupt condition is met. The MOSFET drive signal is used to drive the on / off state of the MOSFET. A frequency multiplication relationship refers to an integer multiple relationship between signal frequencies. In this embodiment, the frequency of the MOSFET drive signal is higher than the frequency of the interrupt control signal; for example, a 3x frequency multiplication relationship, meaning the frequency of the MOSFET drive signal is three times the frequency of the interrupt control signal. Both the interrupt control signal and the MOSFET drive signal can be triangular waves, and both can be in the form of a rising edge followed by a falling edge.

[0050] In one optional implementation, an interrupt control signal can be output based on a first enhanced pulse width modulation (PWM) module, wherein the first PWM module employs a rising-falling edge mode; and a MOS transistor drive signal can be output based on a second enhanced PWM module, wherein the second enhanced PWM module also employs a rising-falling edge mode. The first and second enhanced PWM modules can be enhanced PWM modules within an MCU (Microcontroller Unit). The rising-falling edge mode can be understood as the configuration of the enhanced PWM modules using rising and falling edges, causing the pulse width modulation waveform to undergo specific actions or changes on both the rising and falling edges of the counter. An increment / decrement counting mode is used, meaning the counter first increments and then decrements.

[0051] In this embodiment, when the second count value of the second counter corresponding to the MOS transistor drive signal reaches the comparison value set in the second enhanced pulse width modulation module, the MOS transistor is driven to perform a corresponding on / off operation to achieve the inductor current switching. The MOS transistor drive signal has rising and falling edges. Reaching the second count value and the comparison value set in the second enhanced pulse width modulation module on both the rising and falling edges will drive the MOS transistor to perform a corresponding on / off operation to achieve the inductor current switching. For example, if the counter peak value is 1000, 500 will switch during the rising state and also during the falling state. Thus, the inductor current corresponding to the peak value of 1000 is the inductor midpoint.

[0052] In one optional implementation, when the second count value of the second counter corresponding to the MOSFET drive signal is rising and reaches the comparison value, the upper MOSFET is driven to close and the lower MOSFET is driven to open; when the second count value of the second counter corresponding to the MOSFET drive signal is falling and reaches the comparison value, the upper MOSFET is driven to open and the lower MOSFET is driven to close. By controlling the opening and closing states of the upper and lower MOSFETs, the charging and discharging of the inductor can be controlled, realizing the reversal of the inductor current direction. The upper MOSFET can be understood as the MOSFET connected between the positive terminal (or high potential terminal) of the power supply and the load, responsible for controlling the switching of power from the power supply to the load. The lower MOSFET can be understood as the MOSFET connected between the load and ground (or low potential terminal), responsible for controlling the switching of the load and ground.

[0053] An initial comparison value can be set, and subsequent comparison values ​​are determined based on the target current of the grid-connected output control. The target current is the ideal current.

[0054] Step S12: When the first counter corresponding to the interrupt control signal reaches the first pre-designed value, the inductor current is sampled, wherein the inductor current is the inductor current formed by the on / off state of the MOS transistor driven by the MOS transistor drive signal, and when the first counter reaches the first pre-designed value, the inductor current is at the midpoint of the rising edge or the falling edge.

[0055] In this embodiment, the count values ​​of the first counter and the second counter can be aligned before the output interrupt control signal and the MOS transistor drive signal. For example, both can start counting from 0.

[0056] It is understood that in this embodiment, the sampling point can be set as the midpoint of the inductor current by setting a first pre-designed value.

[0057] In one alternative implementation, the inductor current can be sampled when a sampling signal is detected, wherein the sampling signal is a signal triggered when the first counter corresponding to the interrupt control signal reaches a first pre-designed value. That is, when the sampling signal triggered when the first counter corresponding to the interrupt control signal reaches the first pre-designed value is detected, such as an ADC (Analog-to-Digital Converter) signal, the inductor current is sampled.

[0058] Furthermore, when the cycle end point corresponding to the interrupt control signal is reached, grid-connected output control is performed based on the sampled inductor current. Grid-connected output control refers to the process of converting electrical energy generated by distributed energy sources (such as solar and wind power) into alternating current with the same voltage and frequency as the grid through an inverter, and safely and stably integrating it into the grid. By using the output inductor current as the control quantity, the inverter outputs a current signal with the same frequency and phase as the grid voltage to achieve grid connection.

[0059] In this embodiment, the inductor current can be sampled once within the period corresponding to the interrupt control signal, and grid-connected output control can be performed at the end of the period, thus enabling periodic control.

[0060] In a specific implementation, when the first counter reaches the first pre-designed value, the inductor current can be at the midpoint of the rising edge or at the midpoint of the falling edge. The first pre-designed value can be the count value in the rising state of the interrupt control signal or the count value in the falling state.

[0061] In this embodiment, the PWM (Pulse Width Modulation) controlling the sampling (i.e., the interrupt control signal) and the PWM driving the MOS transistor (i.e., the MOS transistor drive signal) have a frequency multiplication relationship, and this is used as the basis for sampling the midpoint of the inductor current. The midpoint of the inductor current is the midpoint between the MOS transistor's turn-on and turn-off. Since signal noise is usually generated during turn-on and turn-off, the influence of MOS switch noise on sampling can be effectively avoided by avoiding the corresponding MOS switch time points.

[0062] As can be seen, the output interrupt control signal and MOSFET drive signal of this application embodiment have a frequency multiplication relationship, which makes it easy to determine the periodic sampling point, ensure that the sampling point of the inductor current is always located at the midpoint of the inductor current, avoid the noise influence of MOSFET switching, effectively avoid the influence of excessive DC component and current harmonics on the power grid under grid connection, and improve the stability of current sampling to achieve more stable control.

[0063] The following example, using a 32-bit floating-point microcontroller unit (MCU) to control the current sampling process, further illustrates the current sampling scheme provided in this application. The frequency multiplication relationship between the sampling PWM and the MOSFET driving PWM is controlled by software. Referring to Figure 1, EPWM (Enhanced Pulse Width Modulation) 1 is used as the sampling PWM, and EPWM2 is used as the DC-AC (DC-AC inverter) MOSFET control signal. The software configuration is aligned, and EPWM2 is 3 times the frequency of EPWM1.

[0064] The MCU's EPWM1 ​​generates an interrupt control signal with a period of 60µs, and the MCU's EPWM2 generates a DC-AC drive signal (i.e., a MOSFET drive signal) with a control period of 20µs and a frequency of 50kHz. Simultaneously, the counts of EPWM1 ​​and EPWM2 are aligned via software configuration. At this time, the DC-AC drive signal is three times the frequency of the timing control signal (i.e., the interrupt control signal). See Figure 2, which is a schematic diagram of a signal waveform provided in an embodiment of this application. The interrupt control EPWM (i.e., EPWM1) outputs an interrupt control signal. The CLA interrupt (i.e., the interrupt control signal) has a period of 60µs, using the EPWM mode with rising and falling edges, and a period of 2*3000*10ns. The ADC signal is triggered at the 1000th count on the falling edge to sample the inductor current. The MOSFET control EPWM (i.e., EPWM2) outputs a MOSFET drive signal. The DC-AC MOSFET drive (i.e., the MOSFET drive signal) has a period of 20µs, using the EPWM mode with rising and falling edges, and a period of 2*1000*10ns. For EPWM2, CMPA is the comparison value for EPWM2: when the counter rises, reaching this value turns the upper transistor on and the lower transistor off; when the counter falls, reaching this value turns the upper transistor off and the lower transistor on. CMPA is an internal register of the MCU, and its value is used to change the on-time of the upper and lower transistors. For example, configuring CMPA to 500 means that when the count value reaches 500 on the rising edge, the upper transistor is on and the lower transistor is off; when the count value reaches 500 on the falling edge, the upper transistor is off and the lower transistor is on. The upper transistor drive, lower transistor drive, and inductor current waveforms are shown in Figure 2. Further, refer to Figure 3, which is a hardware circuit diagram of an application current sampling method provided in this embodiment. MOSFETs Q1 and Q4 are controlled by the same signal, and Q2 and Q3 are controlled by the same signal. The control signals for Q1 and Q2 are complementary. Q1 and Q4 are the upper transistors, that is, Q1 and Q4 are controlled by the upper transistor drive signal, and Q2 and Q3 are the lower transistors. Q2 and Q3 are controlled by the lower drive signal of the MOSFET, and L1 and L2 are inductors. a For inductor current, u a S1 is the inductor voltage, AC is the AC power supply, and Ve is the bus voltage.

[0065] By configuring the sampling point at the 1000th count position of the EPWM1 ​​interrupt falling edge, it can be seen that the current sampling point is perfectly aligned with the midpoint of the inductor current. Furthermore, due to the use of fixed-frequency control, the changes in the CMPA comparison value are complementary between the upper and lower transistors, and the falling edge of the timer is always aligned with the midpoint of the falling edge of the inductor current. Sampling at other positions would cause the sampled current value to fluctuate continuously at different points in the inductor current, resulting in very poor current sampling stability.

[0066] The 32-bit floating-point microcontroller unit can be an F28004x device, such as the F280049C. This resource is suitable for micro-inverter and energy storage applications. The F280049C can be used to implement DC-AC control. Specifically, the F280049C's EPWM1 ​​output interrupt control signal is used, and its EPWM2 outputs the DC-AC drive signal.

[0067] This embodiment uses a 32-bit floating-point microcontroller unit to implement the DC-AC control process. Based on PWM fixed-frequency control and midpoint current sampling, it effectively avoids noise generated when the MOSFET is turned on, and allows for stable current sampling for control, resulting in more stable control. By using PWM fixed-frequency control, it achieves better stable control of the grid-connected output. This solution can be applied to the field of distributed energy grid-connected power generation technology, such as photovoltaic grid-connected power generation technology. By optimizing the inverter control system through this method, and sampling the midpoint of the inductor current for corresponding grid-connected output control, it better controls the DC component and current harmonics, effectively avoiding interference to the grid from the grid-connected energy storage inverter. It also reduces its own additional losses and heat.

[0068] Referring to Figures 4 to 7, which are schematic diagrams of test waveforms based on the conventional current sampling method, purple represents the grid-side voltage and yellow represents the inductor current. It can be seen that the symmetry of the inductor current waveform is very poor, which leads to poor Idc (Direct Current) and Ithd (Total Harmonic Distortion of Current) of the device. Figures 4 to 7 correspond to waveforms under different power levels. Referring to Figures 8 to 11, which are schematic diagrams of test waveforms corresponding to the current sampling method provided in the embodiments of this application, using the current sampling scheme provided in this application, purple represents the grid-side voltage and yellow represents the inductor current. It can be seen that the symmetry of the inductor current waveform is very good, reducing the presence of Idc. Such a waveform has better Idc and Ithd, and has less impact on the grid environment. Figures 8 to 11 correspond to waveforms under different power levels.

[0069] Referring to Figure 12, an embodiment of this application discloses a current sampling device, including:

[0070] The signal output module 11 includes an output interrupt control signal and a MOS transistor drive signal, wherein the interrupt control signal and the MOS transistor drive signal have a frequency multiplication relationship;

[0071] The inductor current sampling module 12 is used to sample the inductor current when the first counter corresponding to the interrupt control signal reaches the first pre-designed value. The inductor current is the inductor current formed by the on / off state of the MOS transistor driven by the MOS transistor drive signal. When the first counter reaches the first pre-designed value, the inductor current is at the midpoint of the rising edge or the falling edge.

[0072] Specifically, the signal output module 11 is used to: output an interrupt control signal based on the first enhanced pulse width modulation module, wherein the first enhanced pulse width modulation module adopts a rising and falling edge mode; and output a MOS transistor drive signal based on the second enhanced pulse width modulation module, wherein the second enhanced pulse width modulation module adopts a rising and falling edge mode.

[0073] Furthermore, the device also includes a MOS transistor driving module, which drives the MOS transistor to perform corresponding switching operations when the second count value of the second counter corresponding to the MOS transistor driving signal reaches the comparison value set in the second enhanced pulse width modulation module, so as to realize the flipping of the inductor current.

[0074] Specifically, the MOS transistor driving module is used to: drive the upper MOS transistor to close and the lower MOS transistor to open when the second count value of the second counter corresponding to the MOS transistor driving signal is in an upward state and the second count value reaches the comparison value; and drive the upper MOS transistor to open and the lower MOS transistor to close when the second count value of the second counter corresponding to the MOS transistor driving signal is in a downward state and the second count value reaches the comparison value.

[0075] Furthermore, the device also includes a count value alignment module for aligning the count values ​​of the first counter and the second counter before the output interrupt control signal and the MOS transistor drive signal.

[0076] In this embodiment, the inductor current sampling module 12 is specifically used to sample the inductor current when a sampling signal is detected, wherein the sampling signal is a signal triggered when the first counter corresponding to the interrupt control signal reaches a first pre-designed value.

[0077] Furthermore, the device also includes a control module, which, after sampling the inductor current, performs grid-connected output control based on the sampled inductor current when the cycle end point corresponding to the interrupt control signal is reached.

[0078] As can be seen, the output interrupt control signal and MOSFET drive signal of this application embodiment have a frequency multiplication relationship, which makes it easy to determine the periodic sampling point, ensure that the sampling point of the inductor current is always located at the midpoint of the inductor current, avoid the noise influence of MOSFET switching, effectively avoid the influence of excessive DC component and current harmonics on the power grid under grid connection, and improve the stability of current sampling to achieve more stable control.

[0079] Referring to Figure 13, this application discloses an electronic device 20, including a processor 21 and a memory 22; wherein, the memory 22 is used to store a computer program; the processor 21 is used to execute the computer program, the current sampling method disclosed in the foregoing embodiments.

[0080] For details regarding the specific process of the above current sampling method, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0081] Furthermore, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk, or optical disk, and the storage method can be temporary storage or permanent storage.

[0082] In addition, the electronic device 20 also includes a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26; wherein, the power supply 23 is used to provide operating voltage for the various hardware devices on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0083] Furthermore, embodiments of this application also disclose a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the current sampling method disclosed in the foregoing embodiments.

[0084] For details regarding the specific process of the above current sampling method, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0085] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0086] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0087] The above provides a detailed description of a current sampling method, apparatus, device, and medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A current sampling method, characterized in that, include: Output interrupt control signal and MOS transistor drive signal, wherein the interrupt control signal and the MOS transistor drive signal have a frequency multiplication relationship; When the first counter corresponding to the interrupt control signal reaches the first pre-designed value, the inductor current is sampled. The inductor current is the inductor current formed by the on / off state of the MOS transistor driven by the MOS transistor drive signal. When the first counter reaches the first pre-designed value, the inductor current is at the midpoint of the rising edge or the falling edge.

2. The current sampling method according to claim 1, characterized in that, The output interrupt control signal and the MOS transistor drive signal include: An interrupt control signal is output based on the first enhanced pulse width modulation module, wherein the first enhanced pulse width modulation module adopts a rising and falling edge mode; The second enhanced pulse width modulation module outputs a MOS transistor drive signal, wherein the second enhanced pulse width modulation module adopts a rising and falling edge mode.

3. The current sampling method according to claim 2, characterized in that, Also includes: When the second count value of the second counter corresponding to the MOS transistor drive signal reaches the comparison value set in the second enhanced pulse width modulation module, the MOS transistor is driven to perform the corresponding on / off operation to realize the inductor current flipping.

4. The current sampling method according to claim 3, characterized in that, When the second count value of the second counter corresponding to the MOS transistor drive signal reaches the comparison value set in the second enhanced pulse width modulation module, the MOS transistor is driven to perform a corresponding on / off operation, including: When the second count value of the second counter corresponding to the MOS transistor drive signal is in an upward state, and the second count value reaches the comparison value, the upper MOS transistor is driven to close and the lower MOS transistor is driven to open. When the second count value of the second counter corresponding to the MOS transistor drive signal is in a decreasing state, and the second count value reaches the comparison value, the upper MOS transistor is driven to disconnect and the lower MOS transistor is driven to close.

5. The current sampling method according to claim 3, characterized in that, Before the output interrupt control signal and the MOSFET drive signal, the following is also included: Align the count values ​​of the first counter and the second counter.

6. The current sampling method according to claim 1, characterized in that, The sampling of inductor current includes: When a sampling signal is detected, the inductor current is sampled, wherein the sampling signal is a signal triggered when the first counter corresponding to the interrupt control signal reaches a first pre-designed value.

7. The current sampling method according to any one of claims 1 to 6, characterized in that, After sampling the inductor current, the method further includes: When the cycle end point corresponding to the interrupt control signal is reached, grid-connected output control is performed based on the sampled inductor current.

8. A current sampling device, characterized in that, include: The signal output module includes an output interrupt control signal and a MOS transistor drive signal, wherein the interrupt control signal and the MOS transistor drive signal have a frequency multiplication relationship; An inductor current sampling module is used to sample the inductor current when the first counter corresponding to the interrupt control signal reaches a first pre-designed value. The inductor current is the inductor current formed by the on / off state of the MOS transistor driven by the MOS transistor drive signal. When the first counter reaches the first pre-designed value, the inductor current is at the midpoint of the rising edge or the falling edge.

9. An electronic device, characterized in that, Includes memory and processor, wherein: The memory is used to store computer programs; The processor is configured to execute the computer program to implement the current sampling method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store a computer program, wherein the computer program, when executed by a processor, implements the current sampling method as described in any one of claims 1 to 7.

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