Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a plurality of circuit units; the circuit units each comprise a pixel driving circuit; the pixel driving circuit comprises a first transistor (T1), a second transistor (T2), and a third transistor (T3); a gate electrode of the second transistor (T2) is connected to a fourth scanning signal line (24); a second electrode of the second transistor (T2) is connected to a second electrode of the first transistor (T1) and a second electrode of the third transistor (T3) by means of a third node electrode (52); in at least one circuit unit, the first transistor (T1) and the second transistor (T2) are arranged on two sides of the third transistor (T3) in a unit column direction; and the orthographic projection of the third node electrode (52) on the plane of the display substrate does not overlap the orthographic projection of the fourth scanning signal line (24) on the plane of the display substrate.

Description

Display substrate and its preparation method, display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display substrate including multiple circuit units forming multiple cell rows and multiple cell columns. At least one circuit unit includes a pixel driving circuit, which includes at least a first transistor as a first reset transistor, a second transistor as a compensation transistor, and a third transistor as a driving transistor. The first transistor and the third transistor are polysilicon transistors, and the second transistor is an oxide transistor. The gate electrode of the second transistor is connected to a fourth scan signal line, the first electrode of the second transistor is connected to the gate electrode of the third transistor, and the second electrode of the second transistor is connected to the second electrodes of the first transistor and the second electrode of the third transistor through a third node electrode. In at least one circuit unit, the first transistor and the second transistor are disposed on opposite sides of the third transistor cell column direction, and the orthographic projection of the third node electrode on the display substrate plane does not overlap with the orthographic projection of the fourth scan signal line on the display substrate plane.

[0006] In an exemplary embodiment, the first transistor includes at least a first active layer, the second transistor includes at least a second active layer, and the third transistor includes at least a third active layer; in at least one circuit unit, the first end of the third node electrode is connected to the second region of the second active layer through a via, the third node electrode is a strip shape extending along the unit column direction, the second end of the third node electrode is connected to the second region of the first active layer through a via, and the portion between the first end and the second end of the third node electrode is connected to the first region of the third active layer through a via.

[0007] In an exemplary embodiment, the pixel driving circuit further includes a fourth transistor as a data writing transistor, the gate electrode of the fourth transistor being connected to the first scan signal line, the first electrode of the fourth transistor being connected to the data signal line, and the second electrode of the fourth transistor being connected to the first electrode of the third transistor; in at least one circuit unit, the orthographic projection of the third node electrode on the display substrate plane does not overlap with the orthographic projection of the first scan signal line on the display substrate plane.

[0008] In an exemplary embodiment, the pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor, the gate electrode of the fifth transistor being connected to the light-emitting signal line, the first electrode of the fifth transistor being connected to the first power supply line, and the second electrode of the fifth transistor being connected to the first electrode of the third transistor; in at least one circuit unit, the orthographic projection of the third node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the light-emitting signal line on the display substrate plane.

[0009] In an exemplary embodiment, the gate electrode of the first transistor is connected to the third scan signal line, and the first electrode of the first transistor is connected to the first initial signal line; in at least one circuit unit, the orthographic projection of the first initial signal line on the display substrate plane does not overlap with the orthographic projection of the light-emitting signal line on the display substrate plane.

[0010] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first initial signal line on the display substrate plane at least partially overlaps with the orthographic projection of the third scan signal line on the display substrate plane.

[0011] In an exemplary embodiment, in at least one circuit unit, the third scan signal line and the fourth scan signal line are disposed on both sides of the third node electrode unit column direction, and the orthographic projection of the third node electrode on the display substrate plane does not overlap with the orthographic projection of the third scan signal line on the display substrate plane.

[0012] In an exemplary embodiment, the pixel driving circuit further includes a seventh transistor as a second reset transistor, the gate electrode of the seventh transistor being connected to the second scan signal line, and the first electrode of the seventh transistor being connected to the second initial signal line; in at least one circuit unit, the orthographic projection of the second initial signal line on the display substrate plane does not overlap with the orthographic projection of the light-emitting signal line on the display substrate plane.

[0013] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second initial signal line on the display substrate plane at least partially overlaps with the orthographic projection of the second scan signal line on the display substrate plane.

[0014] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the third node electrode on the display substrate plane at least partially overlaps with the orthographic projections of the second scan signal line and the second initial signal line on the display substrate plane.

[0015] In an exemplary embodiment, the pixel driving circuit further includes an eighth transistor as a third reset transistor. The gate electrode of the eighth transistor is connected to the second scan signal line, the first electrode of the eighth transistor is connected to the third initial signal line, and the second electrode of the eighth transistor is connected to the first electrode of the third transistor and the second electrode of the fifth transistor. The orthographic projection of the third initial signal line on the display substrate plane does not overlap with the orthographic projection of the light-emitting signal line on the display substrate plane.

[0016] In an exemplary embodiment, the orthographic projection of the third initial signal line onto the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line onto the display substrate plane.

[0017] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the third node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the third initial signal line on the display substrate plane.

[0018] In an exemplary embodiment, the display substrate includes a plurality of conductive layers disposed on a substrate in a direction perpendicular to the display substrate, wherein the second initial signal line and the third initial signal line are disposed in different conductive layers.

[0019] In an exemplary embodiment, the plurality of conductive layers includes at least a first conductive layer disposed on a substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, a fourth conductive layer disposed on a side of the third conductive layer away from the substrate, and a fifth conductive layer disposed on a side of the fourth conductive layer away from the substrate. The light-emitting signal line and the second scanning signal line are disposed in the first conductive layer, the second initial signal line is disposed in the third conductive layer, the third node electrode is disposed in the fourth conductive layer, and the third initial signal line is disposed in the fifth conductive layer.

[0020] In an exemplary embodiment, the display substrate further includes at least one first connecting line extending along the pixel row direction and at least one second connecting line extending along the pixel column direction. The second connecting line is connected to the first connecting line through a via. The first connecting line and the second connecting line are configured to transmit data signals. In at least one circuit unit, the orthographic projection of the first connecting line on the display substrate plane does not completely overlap with the orthographic projection of the second initial signal line on the display substrate plane.

[0021] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first connecting line on the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line on the display substrate plane, or the orthographic projection of the first connecting line on the display substrate plane does not overlap with the orthographic projection of the second initial signal line on the display substrate plane.

[0022] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the third node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the first connecting line on the display substrate plane.

[0023] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0024] In another aspect, this disclosure also provides a method for fabricating a display substrate, comprising forming multiple circuit units that constitute multiple cell rows and multiple cell columns; the fabrication method includes:

[0025] A pixel driving circuit is formed in at least one circuit unit, the pixel driving circuit including at least a first transistor as a first reset transistor, a second transistor as a compensation transistor, and a third transistor as a driving transistor, the first transistor and the third transistor being polysilicon transistors, and the second transistor being an oxide transistor; the gate electrode of the second transistor is connected to a fourth scan signal line, the first electrode of the second transistor is connected to the gate electrode of the third transistor, and the second electrode of the second transistor is connected to the second electrodes of the first transistor and the second electrode of the third transistor through a third node electrode; in at least one circuit unit, the first transistor and the second transistor are disposed on opposite sides of the column direction of the third transistor unit, and the orthographic projection of the third node electrode on the display substrate plane does not overlap with the orthographic projection of the fourth scan signal line on the display substrate plane.

[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0027] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0028] Figure 1 is a schematic diagram of a display device;

[0029] Figure 2 is a schematic diagram of a display substrate;

[0030] Figure 3 is a schematic diagram of the planar structure of the display area in a display substrate;

[0031] Figure 4 is a schematic cross-sectional view of the display area in a display substrate;

[0032] Figure 5 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0033] Figure 6 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] Figure 7 is a schematic diagram of a display substrate forming a shielding layer pattern according to the present disclosure;

[0035] Figures 8A and 8B are schematic diagrams of a display substrate after the formation of a first semiconductor layer pattern according to the present disclosure;

[0036] Figures 9A and 9B are schematic diagrams of a display substrate after the formation of the first conductive layer pattern according to the present disclosure.

[0037] Figures 10A and 10B are schematic diagrams of a display substrate after the formation of a second conductive layer pattern according to the present disclosure;

[0038] Figures 11A and 11B are schematic diagrams of a display substrate after a second semiconductor layer pattern has been formed in this disclosure;

[0039] Figures 12A and 12B are schematic diagrams of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0040] Figure 13 is a schematic diagram of a display substrate after the formation of the sixth insulating layer pattern according to the present disclosure;

[0041] Figures 14A and 14B are schematic diagrams of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure.

[0042] Figure 15 is a schematic diagram of a display substrate after the formation of a first planarization layer pattern according to the present disclosure;

[0043] Figures 16A and 16B are schematic diagrams of a display substrate after the formation of the fifth conductive layer pattern according to the present disclosure.

[0044] Figure 17 is a schematic diagram of a display substrate after the formation of a second planarization layer pattern according to the present disclosure;

[0045] Figures 18A and 18B are schematic diagrams of a display substrate after the formation of the sixth conductive layer pattern according to the present disclosure. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0047] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0048] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0049] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0050] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0051] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0052] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0053] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0054] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0055] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0056] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0057] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0058] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0059] Figure 2 is a schematic diagram of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, including multiple sub-pixels forming a pixel array. The multiple sub-pixels are configured to display dynamic or still images, and the display area 100 may be referred to as the active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and therefore the display substrate may be deformable, such as being rolled, bent, folded, or rolled up.

[0060] In an exemplary embodiment, the bonding region 200 may include a lead area, a bending area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The lead area is connected to the display area 100 and includes at least data leads. The bending area is connected to the lead area and may include at least a composite insulating layer with grooves configured to bend the bonding area to the back side of the display area. The driver chip area may include an integrated circuit (IC) configured to connect to multiple data leads. The bonding pin area may include bonding pads configured to bond to an external flexible printed circuit (FPC).

[0061] In an exemplary embodiment, the bezel region 300 may include a circuit region, a power line region, a crack dam region, and a cutting region sequentially arranged along a direction away from the display region 100. The circuit region is connected to the display region 100 and may include at least a gate driving circuit connected to scan signal lines and light emission signal lines in the display region 100. The power line region is connected to the circuit region and may include at least bezel power leads extending parallel to the edge of the display region and connected to a cathode in the display region 100. The crack dam region is connected to the power line region and may include at least a plurality of cracks formed on the composite insulating layer. The cutting region is connected to the crack dam region and may include at least a cutting groove formed on the composite insulating layer, configured such that after all film layers of the display substrate have been prepared, a cutting device cuts along the cutting grooves respectively.

[0062] In an exemplary embodiment, the lead-out area in the binding area 200 and the power line area in the border area 300 may be provided with isolation dams. The isolation dams may extend along a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100. The edge of the display area is the edge of the binding area or the border area of ​​the display area.

[0063] In an exemplary embodiment, the display area 100 may further include multiple data signal lines 70, multiple first connection lines 81, and multiple second connection lines 82. The multiple first connection lines 81 may be straight lines or broken lines extending along a first direction X, and the multiple data signal lines 70 and multiple second connection lines 82 may be straight lines or broken lines extending along a second direction Y.

[0064] In an exemplary embodiment, multiple data signal lines 70 are sequentially arranged at predetermined intervals in a first direction X. At least one data signal line 70 is connected to multiple pixel driving circuits in a pixel column, and the data signal line 70 is configured to provide data signals to the connected pixel driving circuits. Multiple first connection lines 81 are sequentially arranged at predetermined intervals in a second direction Y, and multiple second connection lines 82 are sequentially arranged at predetermined intervals in the first direction X. The first end of at least one first connection line 81 is connected to a data signal line 70, and the second end is connected to the first end of a second connection line 82. The second end of the second connection line 82 extends to the bonding area and is connected to a data lead-out line 80, such that the data signal lines 70 in the display area are connected to the data lead-out lines 80 in the bonding area 200 through the first connection lines 81 and the second connection lines 82, forming a fanout in pixel (FIP). In an exemplary embodiment, the first connection lines 81 and the second connection lines 82 are collectively referred to as data connection lines.

[0065] In an exemplary embodiment, the lead-out area of ​​the binding region 200 can be provided with multiple data leads 80. These data leads 80 extend in a direction away from the display area. The first ends of some data leads 80 are connected to the second connecting line 82 in the display region 100, while the first ends of another portion of data leads 80 are connected to the data signal line 70 in the display region 100. The second ends of all data leads 80 extend along the second direction Y and are connected to the integrated circuit, allowing the data signal output by the integrated circuit to be transmitted to the data signal line through the data leads and data connecting lines. Since the first connecting line 81 and the second connecting line 82 are located in the display area, the length of the binding region in the second direction Y can be effectively reduced, significantly decreasing the bottom bezel width and increasing the screen-to-body ratio, which is beneficial for achieving a full-screen display.

[0066] In an exemplary embodiment, the display area may have a center line O, and multiple data signal lines 70, multiple first connection lines 81, and multiple second connection lines 82 on the display substrate may be symmetrically arranged relative to the center line O. The center line O may be a straight line that bisects multiple unit columns of the display area and extends along the second direction Y.

[0067] Figure 3 is a schematic diagram of the planar structure of a display area in a display substrate. As shown in Figure 3, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0068] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the third sub-pixel P3 can be a blue sub-pixel (B) that emits blue light, and the second sub-pixel P2 and the fourth sub-pixel P4 can be green sub-pixels (G) that emit green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the four sub-pixels can be arranged in an RGBG pattern.

[0069] In other exemplary embodiments, a pixel unit may include three sub-pixels, which may be arranged in a horizontal or vertical manner, and this disclosure does not limit this arrangement.

[0070] Figure 4 is a cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area. As shown in Figure 4, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0071] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving structure layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include a light-emitting device. The light-emitting device can include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0072] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 5, the pixel driving circuit may include eight transistors (first transistor T1 to eighth transistor T8) and one storage capacitor C. The pixel driving circuit is connected to ten signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power supply line VDD).

[0073] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first terminal of the storage capacitor C. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8. The third node N3 is connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0074] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power line VDD.

[0075] In an exemplary embodiment, the first transistor T1 may be referred to as the first reset transistor. The gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the third node N3.

[0076] In an exemplary embodiment, the second transistor T2 can be referred to as a compensation transistor. The gate electrode of the second transistor T2 is connected to the fourth scan signal line S4, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0077] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0078] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor. The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0079] In an exemplary embodiment, the fifth transistor T5 can be referred to as the first light-emitting control transistor. The gate electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0080] In an exemplary embodiment, the sixth transistor T6 can be referred to as the second light-emitting control transistor. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0081] In an exemplary embodiment, the seventh transistor T7 can be referred to as the second reset transistor. The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0082] In an exemplary embodiment, the eighth transistor T8 can be referred to as the third reset transistor. The gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

[0083] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0084] In an exemplary embodiment, the first power line VDD is configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS is configured to provide a constant second voltage signal to the light-emitting device. The voltage of the first voltage signal can be greater than the voltage of the second voltage signal. The first voltage signal can be referred to as a high-level signal, and the second voltage signal can be referred to as a low-level signal. The first initial voltage signal, the second initial voltage signal, and the third initial voltage signal can all be constant voltage signals.

[0085] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include both P-type and N-type transistors.

[0086] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be a low-temperature polycrystalline silicon (LTPS) transistor, or an oxide transistor, or a combination of LTPS and metal-oxide transistors. The active layer of the LTPS transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the metal-oxide transistor is made of metal-oxide semiconductor (Oxide). LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and metal-oxide transistors onto a single display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0087] An exemplary embodiment of this disclosure provides a display substrate. In an exemplary embodiment, the display substrate includes a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns. At least one circuit unit includes a pixel driving circuit, which includes at least a first transistor as a first reset transistor, a second transistor as a compensation transistor, and a third transistor as a driving transistor. The first transistor and the third transistor are polysilicon transistors, and the second transistor is an oxide transistor. The gate electrode of the second transistor is connected to a fourth scan signal line, the first electrode of the second transistor is connected to the gate electrode of the third transistor, and the second electrode of the second transistor is connected to the second electrodes of the first transistor and the second electrode of the third transistor through a third node electrode. In at least one circuit unit, the first transistor and the second transistor are disposed on opposite sides of the third transistor cell column direction, and the orthographic projection of the third node electrode on the display substrate plane does not overlap with the orthographic projection of the fourth scan signal line on the display substrate plane.

[0088] In an exemplary embodiment, the pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor, the gate electrode of the fifth transistor being connected to the light-emitting signal line, the first electrode of the fifth transistor being connected to the first power supply line, and the second electrode of the fifth transistor being connected to the first electrode of the third transistor; in at least one circuit unit, the orthographic projection of the third node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the light-emitting signal line on the display substrate plane.

[0089] In an exemplary embodiment, the pixel driving circuit further includes a seventh transistor as a second reset transistor, the gate electrode of the seventh transistor being connected to the second scan signal line, and the first electrode of the seventh transistor being connected to the second initial signal line; in at least one circuit unit, the orthographic projection of the second initial signal line on the display substrate plane does not overlap with the orthographic projection of the light-emitting signal line on the display substrate plane.

[0090] In an exemplary embodiment, the pixel driving circuit further includes an eighth transistor as a third reset transistor. The gate electrode of the eighth transistor is connected to the second scan signal line, the first electrode of the eighth transistor is connected to the third initial signal line, and the second electrode of the eighth transistor is connected to the first electrode of the third transistor and the second electrode of the fifth transistor. The orthographic projection of the third initial signal line on the display substrate plane does not overlap with the orthographic projection of the light-emitting signal line on the display substrate plane.

[0091] In an exemplary embodiment, the orthographic projection of the third initial signal line onto the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line onto the display substrate plane.

[0092] In an exemplary embodiment, the display substrate includes a plurality of conductive layers disposed on a substrate in a direction perpendicular to the display substrate, wherein the second initial signal line and the third initial signal line are disposed in different conductive layers.

[0093] In an exemplary embodiment, the display substrate further includes at least one first connecting line extending along the pixel row direction and at least one second connecting line extending along the pixel column direction. The second connecting line is connected to the first connecting line through a via. The first connecting line and the second connecting line are configured to transmit data signals. In at least one circuit unit, the orthographic projection of the first connecting line on the display substrate plane does not completely overlap with the orthographic projection of the second initial signal line on the display substrate plane.

[0094] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first connecting line on the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line on the display substrate plane, or the orthographic projection of the first connecting line on the display substrate plane does not overlap with the orthographic projection of the second initial signal line on the display substrate plane.

[0095] The display substrate provided in the exemplary embodiments of this disclosure may include a display area, a bonding area on one side of the display area, and a border area on other sides of the display area in a plane parallel to the display substrate. In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate. The driving structure layer of the display area may include multiple circuit units constituting multiple cell rows and multiple cell columns. At least one circuit unit may include a pixel driving circuit configured to output a corresponding current to a connected light-emitting device. The light-emitting structure layer of the display area may include multiple light-emitting units. At least one light-emitting unit may include a light-emitting device connected to the pixel driving circuit of the corresponding circuit unit. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0096] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0097] In an exemplary embodiment, multiple circuit units arranged sequentially along a first direction X can be referred to as a unit row, and multiple circuit units arranged sequentially along a second direction Y can be referred to as a unit column. The multiple unit rows and multiple unit columns constitute an array of circuit units, with the first direction X intersecting the second direction Y. In an exemplary embodiment, the first direction X can be referred to as the pixel row direction, and the second direction Y can be referred to as the pixel column direction.

[0098] Figure 6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 6, the display substrate may include multiple circuit units constituting multiple unit rows and multiple unit columns. At least one circuit unit may include a pixel driving circuit, which may be connected to a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a fourth scan signal line 24, a light emission signal line 25, a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, a data signal line 70, and a first power supply line 71, respectively.

[0099] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, and the light emission signal line 25 are configured to provide a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a light emission control signal to the pixel driving circuit, respectively. The first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 are configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively. The data signal line is configured to provide a data signal to the pixel driving circuit, and the first power line is configured to provide a first power signal to the pixel driving circuit. The multiple signal lines connected to the pixel driving circuit can be located within corresponding circuit units.

[0100] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light emission signal line 25, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 can be straight lines or broken lines extending along the first direction X of the main body, and the shapes of the data signal line 70 and the first power line 71 can be straight lines or broken lines extending along the second direction Y of the main body.

[0101] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0102] In an exemplary embodiment, the pixel driving circuit may include at least a storage capacitor and a plurality of transistors. The storage capacitor may include a first electrode 31 and a second electrode 32 stacked together, wherein the orthographic projection of the second electrode 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode 31 on the substrate. The plurality of transistors may include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, a seventh transistor T7 as a second reset transistor, and an eighth transistor T8 as a third reset transistor. The second transistor T2 may be a metal-oxide-semiconductor transistor (N-type transistor), and the first transistor T1, the third transistor T3 to the eighth transistor T8 may be low-temperature polysilicon transistors (P-type transistors).

[0103] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the third scan signal line 23, and the first electrode of the first transistor T1 is connected to the first initial signal line 41. The gate electrode of the second transistor T2 is connected to the fourth scan signal line 24, and the first electrode of the second transistor T2 can be connected to the first plate 31 of the storage capacitor (which is also the gate electrode of the third transistor T3) via the first connection electrode 51. The second electrode of the second transistor T2 can be connected to the second electrode of the first transistor T1, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 via the second connection electrode 52, which serves as the third node electrode. The first electrode of the third transistor T3 is connected to the second electrodes of the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8, respectively. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, and the first electrode of the fourth transistor T4 is connected to the data signal line. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 25, and the first electrode of the fifth transistor T5 is connected to the second plate 32 of the storage capacitor and the first power supply line 71, respectively. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line 25, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the second scan signal line 22, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42. The gate electrode of the eighth transistor T8 is connected to the second scan signal line 22, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 43.

[0104] In an exemplary embodiment, in at least one circuit unit, the fourth scan signal line 24 may be disposed on the side opposite to the second direction Y of the second electrode plate 32, and the first scan signal line 21 may be disposed on the side of the fourth scan signal line 24 away from the second electrode plate 32. The light emission signal line 25 may be disposed on the side of the second direction Y of the second electrode plate 32, the second scan signal line 22 may be disposed on the side of the light emission signal line 25 away from the second electrode plate 32, and the third scan signal line 23 may be disposed on the side of the second scan signal line 22 away from the second electrode plate 32.

[0105] In an exemplary embodiment, in at least one circuit unit, the second connection electrode 52 may be disposed between the third scan signal line 23 and the fourth scan signal line 24, or the third scan signal line 23 and the fourth scan signal line 24 may be disposed on both sides of the second connection electrode 52 in the second direction Y. The first transistor T1 may include at least a first active layer 11, the second transistor T2 may include at least a second active layer 12, and the third transistor T3 may include at least a third active layer 13. The shape of the second connection electrode 52 may be a strip extending along the second direction Y. The first end of the second connection electrode 52 is connected to the first region of the second active layer 12 through a via, the second end of the second connection electrode 52 is connected to the second region of the first active layer 11 through a via, and the portion between the first end and the second end of the second connection electrode 52 is connected to the first region of the third active layer 13 through a via.

[0106] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second connection electrode 52 on the substrate does not overlap with the orthographic projection of the fourth scan signal line 24 on the substrate.

[0107] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second connection electrode 52 on the substrate does not overlap with the orthographic projections of the first scan signal line 21 and the third scan signal line 23 on the substrate.

[0108] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second connection electrode 52 on the substrate at least partially overlaps with the orthographic projections of the second scan signal line 22 and the light emission signal line 25 on the substrate.

[0109] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second connection electrode 52 on the substrate does not overlap with the orthographic projection of the first initial signal line 41 on the substrate.

[0110] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second connection electrode 52 on the substrate at least partially overlaps with the orthographic projections of the second initial signal line 42 and the third initial signal line 43 on the substrate.

[0111] In an exemplary embodiment, in at least one circuit unit, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 may be disposed on the side of the light-emitting signal line 25 away from the second electrode plate 32, and the orthographic projections of the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 on the substrate do not overlap with the orthographic projection of the light-emitting signal line 25 on the substrate.

[0112] In an exemplary embodiment, in at least one circuit unit, a second initial signal line 42 and a third initial signal line 43 may be disposed between the light-emitting signal line 25 and the first initial signal line 41. The orthographic projection of the first initial signal line 41 on the substrate at least partially overlaps with the orthographic projection of the third scanning signal line 23 on the substrate. The orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line 22 on the substrate. The orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the second initial signal line 42 on the substrate.

[0113] In an exemplary embodiment, the display substrate may further include at least one first connection line 81 extending along a first direction X and at least one second connection line 82 extending along a second direction Y. The second connection line 82 may be connected to one end of the first connection line 81 through a via, and the other end of the first connection line 81 may be connected to a data signal line 70. The first connection line 81 and the second connection line 82 are configured to transmit data signals.

[0114] In one exemplary embodiment, in at least one circuit unit, the orthographic projection of the first connection line 81 on the substrate at least partially overlaps with the orthographic projection of the second initial signal line 42 on the substrate.

[0115] In another exemplary embodiment, in at least one circuit unit, the orthographic projection of the first connection line 81 on the substrate does not overlap with the orthographic projection of the second initial signal line 42 on the substrate.

[0116] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first connecting line 81 on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode 52 on the substrate.

[0117] In an exemplary embodiment, the display substrate may include a plurality of conductive layers disposed on the substrate in a direction perpendicular to the substrate. The first initial signal line 41 and the second initial signal line 42 may be disposed in the same conductive layer, while the second initial signal line 42 and the third initial signal line 43 may be disposed in different conductive layers.

[0118] In an exemplary embodiment, the plurality of conductive layers may include at least a first conductive layer disposed on a substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, a fourth conductive layer disposed on a side of the third conductive layer away from the substrate, a fifth conductive layer disposed on a side of the fourth conductive layer away from the substrate, and a sixth conductive layer disposed on a side of the fifth conductive layer away from the substrate. Specifically, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the light emission signal line 25, and the first electrode plate 31 may be disposed in the first conductive layer; the second electrode plate 32 may be disposed in the second conductive layer; the fourth scan signal line 24, the first initial signal line 41, and the second initial signal line 42 may be disposed in the third conductive layer; the second connecting electrode 52 may be disposed in the fourth conductive layer; the third initial signal line 43 and the first connecting line 81 may be disposed in the fifth conductive layer; and the data signal line 70, the first power line 71, and the second connecting line 82 may be disposed in the sixth conductive layer.

[0119] In an exemplary embodiment, the pixel driving circuits of adjacent cell columns can be mirror-symmetrical with respect to a column boundary line, which can be a broken line located between adjacent cell columns and extending along a second direction Y. For example, the pixel driving circuits of the Nth cell column and the (N+1)th cell column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the positions and shapes of the pixel driving circuits in multiple cell rows can be substantially the same.

[0120] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film, coating with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as coating with organic materials, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0121] In an exemplary embodiment, taking two circuit units (one unit row and two unit columns) as an example, the fabrication process of the display substrate in this embodiment may include the following operations.

[0122] (11) Forming a masking layer pattern. In an exemplary embodiment, forming a masking layer pattern may include: depositing a masking film on a substrate, patterning the masking film using a patterning process, and forming a masking layer pattern on the substrate, as shown in FIG7. In an exemplary embodiment, the masking layer may be referred to as the underlying metal (LS) layer.

[0123] In an exemplary embodiment, the shielding layer pattern of each circuit unit in the display area may include at least a shielding electrode 90, a first shielding connecting strip 91, a second shielding connecting strip 92, a third shielding connecting strip 93, and a fourth shielding connecting strip 94.

[0124] In an exemplary embodiment, the shielding electrode 90 can be rectangular in shape, with chamfered or recessed corners. The shielding electrode 90 can be disposed in the middle region of the circuit unit in the first direction X and the second direction Y. In an exemplary embodiment, the shielding electrode 90 is configured to shield the channel region of the third transistor T3.

[0125] In an exemplary embodiment, the shape of the first shielding connecting strip 91 can be a straight line or a broken line extending along the first direction X of the main body. The first shielding connecting strip 91 can be disposed on one side of the shielding electrode 90 in the first direction X or on the opposite side of the first direction X. The first end of the first shielding connecting strip 91 is connected to the shielding electrode 90 of this circuit unit, and the second end of the first shielding connecting strip 91 is connected to the shielding electrode 90 of the adjacent circuit unit in the first direction X.

[0126] In an exemplary embodiment, in at least one circuit unit, the shielding electrode 90 and the first shielding connecting strip 91 can be an integral structure that is interconnected.

[0127] In an exemplary embodiment, the second shielding connecting strip 92 and the third shielding connecting strip 93 can be zigzag-shaped, with the main body extending along the second direction Y. The second shielding connecting strip 92 can be disposed on one side of the shielding electrode 90 in the second direction Y, and the third shielding connecting strip 93 can be disposed on the opposite side of the shielding electrode 90 in the second direction Y. The first end of the second shielding connecting strip 92 is connected to the shielding electrode 90 of this circuit unit, and the second end of the second shielding connecting strip 92 extends along the second direction Y and is connected to the third shielding connecting strip 93 of the circuit unit in the next unit row. The first end of the third shielding connecting strip 93 is connected to the shielding electrode 90 of this circuit unit, and the second end of the third shielding connecting strip 93 extends along the opposite direction Y and is connected to the second shielding electrode 92 of the circuit unit in the previous unit row.

[0128] In an exemplary embodiment, in at least one circuit unit, the shielding electrode 90, the second shielding connecting strip 92, and the third shielding connecting strip 93 can be an integral structure that is interconnected.

[0129] In an exemplary embodiment, in at least one unit column, the plurality of shielding electrodes 90, the plurality of second shielding connecting strips 92 and the plurality of third shielding connecting strips 93 can be an integral structure that is interconnected.

[0130] In an exemplary embodiment, the shape of the fourth shielding connecting strip 94 can be a straight line or a broken line extending along the first direction X of the main body. The fourth shielding connecting strip 94 can be disposed on one side of the third shielding connecting strip 93 in the first direction X or on the opposite side of the first direction X. The first end of the fourth shielding connecting strip 94 is connected to the third shielding connecting strip 93 of this circuit unit, and the second end of the fourth shielding connecting strip 94 is connected to the third shielding connecting strip 93 of the adjacent circuit unit in the first direction X.

[0131] In an exemplary embodiment, in at least one circuit unit, the third shielding connecting strip 93 and the fourth shielding connecting strip 94 can be an integral structure that is interconnected.

[0132] In an exemplary embodiment, the shielding layer may extend to the border area or the bonding area and be connected to the first power lead transmitting the first power signal. The shielding layers in multiple cell rows and multiple cell columns are interconnected as an integral structure, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects in the display substrate, and ensuring the display effect of the display substrate.

[0133] In an exemplary embodiment, the occlusion layers of adjacent cell columns can be mirror-symmetrical with respect to the column boundaries. For example, the occlusion layers of the Nth cell column and the (N+1)th cell column can be mirror-symmetrical with respect to the column boundaries. In an exemplary embodiment, the positions and shapes of the occlusion layers in multiple cell rows can be substantially the same.

[0134] (12) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: depositing a first insulating film and a first semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the first semiconductor film by a patterning process to form a first insulating layer covering the shielding layer, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG8A and FIG8B, FIG8B being a planar schematic diagram of the first semiconductor layer in FIG8A.

[0135] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are an integral structure interconnected, while the first active layer 11 and the eighth active layer 18 are separately configured.

[0136] In an exemplary embodiment, in the first direction X, the first active layer 11 and the sixth active layer 16 may be located on one side of the third active layer 13 in this circuit unit, and the fourth active layer 14 and the fifth active layer 15 may be located on the other side of the third active layer 13 in this circuit unit. In the second direction Y, the fourth active layer 14 may be located on the opposite side of the third active layer 13 in the second direction Y in this circuit unit, and the first active layer 11, the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may be located on one side of the third active layer 13 in the second direction Y in this circuit unit.

[0137] In an exemplary embodiment, the third active layer 13 may be in the shape of an inverted "Ω", the first active layer 11, the fourth active layer 14, the fifth active layer 15 and the seventh active layer 17 may be in the shape of an "I", and the sixth active layer 16 and the eighth active layer 18 may be in the shape of an "L".

[0138] In an exemplary embodiment, the first active layer 11 and the third active layers 13 to the eighth active layers 18 may each include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be interconnected, and the first region 13-1 of the third active layer may simultaneously serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer may be interconnected, and the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be interconnected, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first active layer's first zone 11-1, the first active layer's second zone 11-2, the fourth active layer's first zone 14-1, the fifth active layer's first zone 15-1, the seventh active layer's first zone 17-1, the eighth active layer's first zone 18-1, and the eighth active layer's second zone 18-2 can be set individually.

[0139] In an exemplary embodiment, the channel region of the first active layer and the second region 11-2 of the first active layer can be disposed in this circuit unit, the first region 11-1 of the first active layer can be disposed in the circuit unit of the next unit row, and the first region 11-1 of the first active layer in the circuit unit of the previous unit row can be disposed in this circuit unit.

[0140] In an exemplary embodiment, in at least one cell row, the first regions 15-1 of the fifth active layers in some adjacent circuit cells can be interconnected, and the fifth active layers in the two circuit cells can be an integral structure interconnected. For example, the fifth active layers of the Nth cell column and the fifth active layers of the N+1th cell column can be an integral structure interconnected. Since the first region of the fifth active layer is configured to be connected to the subsequently formed first power line, by forming an integral structure interconnected with the fifth active layers of adjacent circuit cells, it can be ensured that the first electrodes of the fifth transistors T5 of adjacent circuit cells have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0141] In an exemplary embodiment, in at least one cell row, the first regions 18-1 of the eighth active layers in some adjacent circuit cells can be interconnected, and the eighth active layers in the two circuit cells can be an integral structure interconnected. For example, the eighth active layers of the Nth cell column and the eighth active layers of the N+1th cell column can be an integral structure interconnected. Since the first regions 18-1 of the eighth active layers are configured to be connected to the subsequently formed third initial signal line, by forming an integral structure interconnected with the eighth active layers of adjacent circuit cells, it can be ensured that the first electrodes of the eighth transistors of adjacent circuit cells have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0142] In an exemplary embodiment, the first semiconductor layers of adjacent cell columns may be mirror-symmetrical with respect to the column boundary. For example, the first semiconductor layer of the Nth cell column and the first semiconductor layer of the N+1th cell column may be mirror-symmetrical with respect to the column boundary. In an exemplary embodiment, the positions and shapes of the first semiconductor layers in multiple cell rows may be substantially the same.

[0143] In an exemplary embodiment, the first semiconductor layer may be polycrystalline silicon (p-Si), meaning that the first transistor T1 and the third transistors T3 through T8 are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; performing a hydrogen removal treatment on the amorphous silicon thin film; and then performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the pattern of the first semiconductor layer.

[0144] (13) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the first semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, as shown in Figures 9A and 9B, where Figure 9B is a planar schematic diagram of the first conductive layer in Figure 9A. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0145] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area includes at least: a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light-emitting signal line 25, and a first electrode 31 of a storage capacitor.

[0146] In an exemplary embodiment, the first electrode plate 31 can be rectangular in shape, with chamfered corners. The orthographic projection of the first electrode plate 31 onto the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 onto the substrate. In an exemplary embodiment, the first electrode plate 31 can simultaneously serve as the lower electrode plate of the storage capacitor and the gate electrode of the third transistor T3.

[0147] In an exemplary embodiment, the shape of the first scan signal line 21 can be a straight line or a broken line extending along the first direction X of the main body. The first scan signal line 21 can be located on the side opposite to the second direction Y of the first electrode plate 31. The area where the first scan signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0148] In an exemplary embodiment, the shape of the second scan signal line 22 can be a straight line or a broken line extending along the first direction X of the main body. The second scan signal line 22 can be located on one side of the first electrode plate 31 in the second direction Y. The area where the second scan signal line 22 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7. The area where the second scan signal line 22 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0149] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line extending along the first direction X of the main body. The third scan signal line 23 can be located on the side of the second scan signal line 22 away from the first electrode plate 31. The area where the third scan signal line 23 overlaps with the first active layer can serve as the gate electrode of the first transistor T1.

[0150] In an exemplary embodiment, the shape of the light-emitting signal line 25 can be a straight line or a broken line extending along the first direction X of the main body. The light-emitting signal line 25 can be located between the second scan signal line 22 and the first electrode plate 31. The area where the light-emitting signal line 25 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5. The area where the light-emitting signal line 25 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0151] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission signal line 25 can be designed in a zigzag shape, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0152] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission signal line 25 can be designed with non-uniform widths, with the width being the dimension of the second direction Y. The aforementioned signal lines can include regions that overlap with the first semiconductor layer and regions that do not overlap with the first semiconductor layer. The width of the signal line in the region that overlaps with the first semiconductor layer can be greater than the width of the signal line in the region that does not overlap with the first semiconductor layer.

[0153] In an exemplary embodiment, the first conductive layer of adjacent cell columns may be mirror-symmetrical with respect to the column boundary line. For example, the first conductive layer of the Nth cell column and the first conductive layer of the N+1th cell column may be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the position and shape of the first conductive layer in multiple cell rows may be substantially the same.

[0154] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1, the third transistor T3 to the eighth transistor T8. The first semiconductor layer in the area not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first transistor T1, the third transistor T3 to the eighth transistor T8 are both conducted.

[0155] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, as shown in Figures 10A and 10B, where Figure 10B is a planar schematic diagram of the second conductive layer in Figure 10A. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0156] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display area includes at least: a second electrode 32 for storing capacitors and a shielding line 35.

[0157] In an exemplary embodiment, the outline of the second electrode plate 32 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as the upper electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit.

[0158] In an exemplary embodiment, in at least one circuit unit, an opening 33 is provided on the second electrode plate 32. The opening 33 may be rectangular in shape and may be located in the middle of the second electrode plate 32, so that the second electrode plate 32 forms an annular structure. The opening 33 exposes a third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a subsequently formed thirteenth via. The thirteenth via is located within the opening 33 and exposes the first electrode plate 31, so that a subsequently formed first connection electrode is connected to the first electrode plate 31.

[0159] In an exemplary embodiment, in at least one circuit unit, a second electrode plate 32 is provided with an electrode plate connecting strip 34, which can be a component of the second electrode plate 32. In a unit row, the second electrode plates 32 of some adjacent circuit units can be interconnected via the electrode plate connecting strip 34 to form an interconnected integrated structure. For example, the second electrode plates 32 of the Nth unit column and the second electrode plates 32 of the N+1th unit column can be interconnected via the electrode plate connecting strip 34. Since the second electrode plate 32 is connected to the subsequently formed first power line, by forming an interconnected integrated structure of the second electrode plates 32 of some adjacent circuit units, the integrated structure of the second electrode plates can be reused as power signal lines. This ensures that the second electrode plates of adjacent circuit units have the same potential, which is beneficial for improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0160] In an exemplary embodiment, the shape of the shielding line 35 can be a straight line or a broken line extending along the first direction X of the main body, and can be located between the first scan signal line 21 and the second electrode 32. The shielding line 35 is configured as a shielding layer of the second transistor T2, shielding the channel region of the second transistor T2 to ensure the electrical performance of the oxide second transistor T2, and is also configured as the bottom gate electrode of the second transistor T2.

[0161] In an exemplary embodiment, the masking line 35 can be designed with non-uniform width, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines.

[0162] In an exemplary embodiment, the second conductive layers of adjacent cell columns can be mirror-symmetrical with respect to the column boundary line. For example, the second conductive layers of the Nth cell column and the N+1th cell column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the positions and shapes of the second conductive layers in multiple cell rows can be substantially the same.

[0163] (15) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: depositing a fourth insulating film and a second semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the second semiconductor film by a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in Figures 11A and 11B, where Figure 11B is a planar schematic diagram of the second semiconductor layer in Figure 11A.

[0164] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit in the display area includes at least the second active layer 12 of the second transistor T2.

[0165] In an exemplary embodiment, the second active layer 12 may be in the shape of an inverted "L", and the orthographic projection of the second active layer 12 on the substrate and the orthographic projection of the shielding line 35 on the substrate may at least partially overlap.

[0166] In an exemplary embodiment, the first region 12-1 of the second active layer may be located on the side of the shielding line 35 away from the second electrode plate 32, and the second region 12-2 of the second active layer may be located on the side of the shielding line 35 close to the second electrode plate 32.

[0167] In an exemplary embodiment, the second semiconductor layers in adjacent cell columns may be mirror-symmetrical with respect to the column boundary. For example, the second semiconductor layer in the Nth cell column and the second semiconductor layer in the (N+1)th cell column may be mirror-symmetrical with respect to the column boundary. In an exemplary embodiment, the positions and shapes of the second semiconductor layers in multiple cell rows may be substantially identical.

[0168] In an exemplary embodiment, the second semiconductor layer can be an oxide layer, i.e., the second transistor T2 is an oxide transistor. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage current. In an exemplary embodiment, the second semiconductor thin film can be indium gallium zinc oxide (IGZO).

[0169] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer; and a third conductive layer pattern disposed on the fifth insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a planar schematic diagram of the third conductive layer in Figure 12A. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0170] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display area includes at least: a fourth scan signal line 24, a first initial signal line 41, and a second initial signal line 42.

[0171] In an exemplary embodiment, the shape of the fourth scan signal line 24 can be a straight line or a broken line extending along the first direction X of the main body. The fourth scan signal line 24 can be located between the first scan signal line 21 and the second electrode 32. The area where the fourth scan signal line 24 overlaps with the second active layer can serve as the gate electrode of the second transistor T2.

[0172] In an exemplary embodiment, the orthographic projection of the fourth scan signal line 24 on the substrate and the orthographic projection of the blocking line 35 on the substrate at least partially overlap. The fourth scan signal line 24 and the blocking line 35 can be connected to the same signal source, so that the blocking line 35 can serve as the bottom gate electrode of the second transistor T2 and the fourth scan signal line 24 can serve as the top gate electrode of the second transistor T2, forming a top-gate and bottom-gate structure for the second transistor T2.

[0173] In an exemplary embodiment, the shape of the first initial signal line 41 can be a straight line or a broken line extending along the first direction X of the main body. The first initial signal line 41 can be located on the side of the second scan signal line 22 away from the second electrode plate 32. A first initial connection block 41-1 can be provided on the first initial signal line 41 of each circuit unit. The shape of the first initial connection block 41-1 can be block-shaped (such as rectangular) and connected to the first initial signal line 41. The first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a subsequently formed seventh connection electrode.

[0174] In an exemplary embodiment, the orthographic projection of the first initial signal line 41 on the substrate and the orthographic projection of the third scan signal line 23 on the substrate at least partially overlap. The first initial signal line 41, which transmits a constant voltage, can shield the influence of the third scan signal line 23 on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0175] In an exemplary embodiment, the orthographic projection of the first initial signal line 41 on the substrate and the orthographic projection of the light-emitting signal line 25 on the substrate do not overlap. This not only avoids instability of the first initial signal caused by the jump of the light-emitting signal, but also reduces the parasitic capacitance of the light-emitting signal line.

[0176] In an exemplary embodiment, since the first region 11-1 of the first active layer in this circuit unit is located in the circuit unit of the next unit row, and the first region of the first active layer in the circuit unit of the previous unit row is located in this circuit unit, the first initial signal line 41 may not be provided between the first unit row and the upper frame.

[0177] In some possible implementations, a first initial signal line 41 may be provided between the first unit row and the upper border, but the first initial signal line 41 is a dummy trace and does not transmit the first initial signal.

[0178] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line extending along the first direction X of the main body. The second initial signal line 42 can be located between the light-emitting signal line 25 and the first initial signal line 41. A second initial connection block 42-1 can be provided on the second initial signal line 42 of each circuit unit. The shape of the second initial connection block 42-1 can be block-shaped (such as rectangular) and connected to the second initial signal line 42. The second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer through a subsequently formed eighth connection electrode.

[0179] In an exemplary embodiment, the orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps with the orthographic projection of the second scan signal line 22 on the substrate. The second initial signal line 42, which transmits a constant voltage, can shield the second scan signal line 22 from the influence on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0180] In an exemplary embodiment, the orthographic projection of the second initial signal line 42 on the substrate does not overlap with the orthographic projection of the light-emitting signal line 25 on the substrate. This not only avoids instability of the second initial signal caused by the jump of the light-emitting signal, but also reduces the parasitic capacitance of the light-emitting signal line.

[0181] In an exemplary embodiment, the third conductive layer of adjacent cell columns can be mirror-symmetrical with respect to the column boundary line. For example, the third conductive layer of the Nth cell column and the third conductive layer of the (N+1)th cell column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the position and shape of the third conductive layer in multiple cell rows can be substantially the same.

[0182] (17) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the sixth insulating layer, as shown in FIG13.

[0183] In an exemplary embodiment, the plurality of vias of each circuit unit in the display area include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, and a sixteenth via V16.

[0184] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer. The first via V1 is configured to allow a subsequently formed seventh connection electrode to be connected to the first region of the first active layer through the via.

[0185] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second region of the first active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the second via V2 are etched away, exposing the surface of the second region of the first active layer. The second via V2 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the first active layer through the via.

[0186] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the second active layer onto the substrate. The sixth and fifth insulating layers within the third via V3 are etched away, exposing the surface of the first region of the second active layer. The third via V3 is configured to allow a subsequently formed first connection electrode to be connected to the first region of the second active layer through the via.

[0187] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the second region of the second active layer onto the substrate. The sixth and fifth insulating layers within the fourth via V4 are etched away, exposing the surface of the second region of the second active layer. The fourth via V4 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the second active layer through the via.

[0188] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the orthographic projection of the first region of the third active layer (which is also the second region of the fourth active layer and the second region of the fifth active layer) onto the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the third active layer (which is also the second region of the fourth active layer and the second region of the fifth active layer). The fifth via V5 is configured to allow a subsequently formed fifth connection electrode to be connected to the first region of the third active layer (which is also the second region of the fourth active layer and the second region of the fifth active layer) through the via.

[0189] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is located within the range of the orthographic projection of the second region of the third active layer (which is also the first region of the sixth active layer) onto the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the second region of the third active layer (which is also the first region of the sixth active layer). The sixth via V6 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the third active layer (which is also the first region of the sixth active layer) through the via.

[0190] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the fourth active layer. The seventh via V7 is configured to allow a subsequently formed third connection electrode to be connected to the first region of the fourth active layer through the via.

[0191] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the first region of the fifth active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the fifth active layer. The eighth via V8 is configured to allow a subsequently formed fourth connection electrode to connect to the first region of the fifth active layer through this via. In an exemplary embodiment, since the first regions of the fifth active layer of some adjacent circuit units in a cell row are interconnected, some adjacent circuit units can share a single eighth via V8.

[0192] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate lies within the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the ninth via V9 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The ninth via V9 is configured to allow a subsequently formed sixth connection electrode to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.

[0193] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the first region of the seventh active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the tenth via V10 are etched away, exposing the surface of the first region of the seventh active layer. The tenth via V10 is configured to allow the subsequently formed eighth connection electrode to be connected to the first region of the seventh active layer through the via.

[0194] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the orthographic projection of the first region of the eighth active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the first region of the eighth active layer. The eleventh via V11 is configured to allow a subsequently formed ninth connection electrode to connect to the first region of the eighth active layer through this via. In an exemplary embodiment, since the first regions of the eighth active layer of some adjacent circuit units in a cell row are interconnected, some adjacent circuit units can share an eleventh via V11.

[0195] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the range of the orthographic projection of the second region of the eighth active layer onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the twelfth via V12 are etched away, exposing the surface of the second region of the eighth active layer. The twelfth via V12 is configured to allow a subsequently formed fifth connection electrode to be connected to the second region of the eighth active layer through the via.

[0196] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the opening 33 on the substrate. The sixth, fifth, fourth and third insulating layers in the thirteenth via V13 are etched away, exposing the surface of the first electrode plate 31. The thirteenth via V13 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate 31 through the via.

[0197] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate lies within the orthographic projection of the electrode connecting strip 34 of the second electrode 32 onto the substrate. The sixth, fifth, and fourth insulating layers within the fourteenth via V14 are etched away, exposing the surface of the electrode connecting strip 34. The fourteenth via V14 is configured to allow a subsequently formed fourth connection electrode to be connected to the electrode connecting strip 34 through this via. In an exemplary embodiment, since the second electrode 32 of some adjacent circuit units in a cell row are interconnected via the electrode connecting strip 34, some adjacent circuit units in a cell row can share a fourteenth via V14.

[0198] In an exemplary embodiment, a fifteenth via V15 may be provided in each circuit unit. The orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate. The sixth insulating layer within the fifteenth via V15 is etched away, exposing the surface of the first initial connection block 41-1. The fifteenth via V15 is configured to allow the subsequently formed seventh connection electrode to be connected to the first initial connection block 41-1 through the via.

[0199] In an exemplary embodiment, a sixteenth via V16 may be provided in each circuit unit. The orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate. The sixth insulating layer within the sixteenth via V16 is etched away, exposing the surface of the second initial connection block 42-1. The sixteenth via V16 is configured to allow the subsequently formed eighth connection electrode to be connected to the second initial connection block 42-1 through the via.

[0200] (18) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in Figures 14A and 14B, where Figure 14B is a planar schematic diagram of the fourth conductive layer in Figure 14A. In an exemplary embodiment, the fourth conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0201] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display area includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, a sixth connecting electrode 56, a seventh connecting electrode 57, an eighth connecting electrode 58, a ninth connecting electrode 59, and a power connection strip 60.

[0202] In an exemplary embodiment, the first connecting electrode 51 can be a strip shape in which the main body extends along the second direction Y. The first end of the first connecting electrode 51 is connected to the first region of the second active layer through the third via V3. After the second end of the first connecting electrode 51 extends along the second direction Y, it is connected to the first electrode plate 31 through the thirteenth via V13. In an exemplary embodiment, since the first electrode plate 31 also serves as the gate electrode of the third transistor T3, the first connecting electrode 51 realizes the interconnection between the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31, forming the first node N1 of the pixel driving circuit.

[0203] In an exemplary embodiment, the second connecting electrode 52 can be a strip shape in which the main body extends along the second direction Y. The first end of the second connecting electrode 52 is connected to the second region of the first active layer through a second via V2. The second end of the second connecting electrode 52 extends in the opposite direction of the second direction Y and is connected to the second region of the second active layer through a fourth via V4. The portion between the first and second ends of the second connecting electrode 52 is connected to the second region of the third active layer (which is also the first region of the sixth active layer) through a sixth via V6. In an exemplary embodiment, the second connecting electrode 52 enables interconnection between the second electrodes of the first transistor T1, the second electrodes of the second transistor T2, the second electrodes of the third transistor T3, and the first electrode of the sixth transistor T6, forming the third node N3 of the pixel driving circuit. In an exemplary embodiment, the second connecting electrode 52 can serve as the third node electrode of this disclosure.

[0204] In an exemplary embodiment, the third connection electrode 53 may be block-shaped (e.g., rectangular), and the third connection electrode 53 is connected to the first region of the fourth active layer through the seventh via V7. The third connection electrode 53 is configured to be connected to the subsequently formed eleventh connection electrode.

[0205] In an exemplary embodiment, the fourth connecting electrode 54 can be a strip extending along the second direction Y. The first end of the fourth connecting electrode 54 is connected to the first region of the fifth active layer through the eighth via V8. The second end of the fourth connecting electrode 54 extends in the opposite direction of the second direction Y and is connected to the electrode connecting strip 34 through the fourteenth via V14. Since the electrode connecting strip 34 is connected to the second electrode 32, the interconnection between the first electrode of the fifth transistor T5 and the second electrode 32 of the storage capacitor in the circuit unit is realized.

[0206] In an exemplary embodiment, since some adjacent circuit cells in a cell row share the same eighth via V8 and fourteenth via V14, some adjacent circuit cells can share a fourth connection electrode 54. Because the fourth connection electrode 54 is configured to connect to the first power line, and since some adjacent circuit cells share the same first region of the fifth active layer, the first power line can write a first power signal into the first electrode of the fifth transistor T5 in the two adjacent circuit cells through the fourth connection electrode 54.

[0207] In an exemplary embodiment, the fifth connecting electrode 55 can be a strip shape extending along the second direction Y of the main body. The first end of the fifth connecting electrode 55 is connected to the first region of the third active layer through the fifth via V5, and the second end of the fifth connecting electrode 55 is connected to the second region of the eighth active layer through the twelfth via V12. In an exemplary embodiment, since the first region of the third active layer also serves as the second region of the fourth active layer and the second region of the fifth active layer, the fifth connecting electrode 55 enables the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, forming the second node N2 of the pixel driving circuit.

[0208] In an exemplary embodiment, the sixth connection electrode 56 can be block-shaped (e.g., rectangular), and is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via the ninth via V9. In an exemplary embodiment, the sixth connection electrode 56 can simultaneously serve as the second electrode of both the sixth transistor T6 and the seventh transistor T7, and is configured to connect to a subsequently formed thirteenth connection electrode.

[0209] In an exemplary embodiment, the seventh connection electrode 57 can be a strip extending along the second direction Y. The first end of the seventh connection electrode 57 is connected to the first region of the first active layer through a first via V1, and the second end of the seventh connection electrode 57 is connected to the first initial connection block 41-1 through a fifteenth via V15. In this exemplary embodiment, since the first initial connection block 41-1 is connected to the first initial signal line 41, the seventh connection electrode 57 enables the writing of the first initial signal transmitted by the first initial signal line 41 to the first electrode of the first transistor T1.

[0210] In an exemplary embodiment, the eighth connection electrode 58 can be a strip extending along the second direction Y. The first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer through a tenth via V10, and the second end of the eighth connection electrode 58 is connected to the second initial connection block 42-1 through a sixteenth via V16. In this exemplary embodiment, since the second initial connection block 42-1 is connected to the second initial signal line 42, the eighth connection electrode 58 enables the writing of the second initial signal transmitted by the second initial signal line 42 to the first electrode of the seventh transistor T7.

[0211] In an exemplary embodiment, the ninth connection electrode 59 may be block-shaped (e.g., rectangular), and the ninth connection electrode 59 is connected to the first region of the eighth active layer through the eleventh via V11. The ninth connection electrode 59 is configured to connect to the subsequently formed third initial signal line.

[0212] In an exemplary embodiment, the power connector 60 may be shaped like an "L"-shaped zigzag. The first end of the power connector 60 is connected to the second end of the fourth connection electrode 54, and the second end of the power connector 60 extends toward the direction close to the fourth scan signal line 24 and away from the fourth connection electrode 54.

[0213] In an exemplary embodiment, in a cell row, two power connection strips 60 in some adjacent circuit cells and the fourth connection electrode 54 shared by the two circuit cells can be an integral structure that is interconnected, and the fourth connection electrode 54 and the two power connection strips 60 form a "Y" shape.

[0214] In an exemplary embodiment, the second connecting electrode 52 may be disposed between the third scanning signal line 23 and the fourth scanning signal line 24, or the third scanning signal line 23 and the fourth scanning signal line 24 may be disposed on both sides of the second connecting electrode 52 in the second direction Y.

[0215] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second connection electrode 52 on the substrate and the orthographic projection of the fourth scan signal line 24 on the substrate do not overlap, thus completely eliminating the parasitic capacitance between the third node N3 and the fourth scan signal line 24, minimizing the impact of the characteristic change of the second transistor T2 on the pixel driving circuit, minimizing the risk of the pixel driving circuit in the reliability test process, and avoiding display defects in the reliability test of the display substrate.

[0216] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second connection electrode 52 on the substrate does not overlap with the orthographic projections of the first scan signal line 21, the third scan signal line 23, and the first initial signal line 41 on the substrate.

[0217] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second connection electrode 52 on the substrate at least partially overlaps with the orthographic projections of the second scan signal line 22, the light emission signal line 25, and the second initial signal line 42 on the substrate.

[0218] In an exemplary embodiment, the fourth conductive layer of adjacent cell columns can be mirror-symmetrical with respect to the column boundary line. For example, the third conductive layer of the Nth cell column and the fourth conductive layer of the (N+1)th cell column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the position and shape of the fourth conductive layer in multiple cell rows can be substantially the same.

[0219] (19) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, and patterning the first planarization film using a patterning process to form a first planarization layer covering the pattern of the fourth conductive layer, wherein a plurality of vias are provided on the first planarization layer, as shown in FIG15.

[0220] In an exemplary embodiment, the plurality of vias in each circuit unit in the display area include at least: a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, and a twenty-fourth via V24.

[0221] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the third connection electrode 53 on the substrate. The first planarization layer within the 21st via V21 is etched away, exposing the surface of the third connection electrode 53. The 21st via V21 is configured to allow the subsequently formed 11th connection electrode to be connected to the third connection electrode 53 through the via.

[0222] In an exemplary embodiment, the orthographic projection of the 22nd via V22 on the substrate is within the range of the orthographic projection of the power connector 60 on the substrate. The first planarization layer within the 22nd via V22 is etched away, exposing the surface of the power connector 60. The 22nd via V22 is configured to allow the subsequently formed 12th connection electrode to be connected to the power connector 60 through the via.

[0223] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the 6th connection electrode 56 on the substrate. The first planarization layer within the 23rd via V23 is etched away, exposing the surface of the 6th connection electrode 56. The 23rd via V23 is configured to allow the subsequently formed 13th connection electrode to be connected to the 6th connection electrode 56 through the via.

[0224] In an exemplary embodiment, the orthographic projection of the 24th via V24 on the substrate is within the range of the orthographic projection of the 9th connection electrode 59 on the substrate. The first planarization layer within the 24th via V24 is etched away, exposing the surface of the 9th connection electrode 59. The 24th via V24 is configured to allow a subsequently formed third initial signal line to be connected to the 9th connection electrode 59 through the via.

[0225] (20) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on the first planarization layer, as shown in Figures 16A and 16B, where Figure 16B is a planar schematic diagram of the fifth conductive layer in Figure 16A. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0226] In an exemplary embodiment, the fifth conductive layer of each circuit unit in the display area includes at least: a third initial signal line 43, an eleventh connecting electrode 61, a twelfth connecting electrode 62, and a thirteenth connecting electrode 63.

[0227] In an exemplary embodiment, the shape of the third initial signal line 43 can be a straight line or a broken line extending along the first direction X. The third initial signal line 43 can be located between the first initial signal line 41 and the second initial signal line 42. A third initial connection block 43-1 can be provided on the third initial signal line 43. The shape of the third initial connection block 43-1 can be block-shaped (such as rectangular) and connected to the third initial signal line 43. The third initial connection block 43-1 is connected to the ninth connection electrode 59 through the twenty-fourth via V24. Since the ninth connection electrode 59 is connected to the first region of the eighth active layer through the via, the third initial signal transmitted by the third initial signal line 43 is written to the first electrode of the eighth transistor T8.

[0228] In an exemplary embodiment, the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the second initial signal line 42 on the substrate, which can increase the stability of the second initial signal.

[0229] In an exemplary embodiment, the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 52 on the substrate.

[0230] In an exemplary embodiment, the eleventh connection electrode 61 may be a strip shape in which the main body extends along the second direction Y. The eleventh connection electrode 61 is connected to the third connection electrode 53 through the twenty-first via V21. The eleventh connection electrode 61 is configured to be connected to a subsequently formed data signal line.

[0231] In an exemplary embodiment, the twelfth connecting electrode 62 may be a block shape extending along the second direction Y. The twelfth connecting electrode 62 is connected to the power connection strip 60 through the twelfth through-hole V22. The twelfth connecting electrode 62 is configured to be connected to the first power line subsequently formed.

[0232] In an exemplary embodiment, the orthographic projection of the twelfth connecting electrode 62 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 51 on the substrate. Since the twelfth connecting electrode 62 is connected to the subsequently formed first power line, the twelfth connecting electrode 62, having a constant potential, can effectively shield the effects of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, preventing data voltage jumps and other signals from affecting the potential of the first node N1 and improving the driving performance of the pixel driving circuit.

[0233] In an exemplary embodiment, the orthographic projection of the twelfth connection electrode 62 onto the substrate at least partially overlaps with the orthographic projection of the second active layer of the second transistor T2 onto the substrate. In an exemplary embodiment, the twelfth connection electrode 62 can block the second active layer, preventing the light emitted by the light-emitting device and the reflected light from the film layer from illuminating the oxide second transistor T2, thereby preventing the oxide transistor from experiencing characteristic drift due to light exposure and improving the electrical characteristics of the oxide transistor.

[0234] In an exemplary embodiment, in at least one cell row, the twelfth connection electrodes 62 in a subset of two adjacent circuit cells can be an integrally connected structure, which can improve the shielding effect of the second transistor T2. For example, the twelfth connection electrodes 62 of the (N-1)th cell column and the Nth cell column are interconnected, and the twelfth connection electrodes 62 in the two circuit cells are an integrally connected structure. As another example, the twelfth connection electrodes 62 of the N+1th cell column and the N+2th cell column are interconnected, and the twelfth connection electrodes 62 in the two circuit cells are an integrally connected structure.

[0235] In an exemplary embodiment, in at least one cell row, the twelfth connection electrode 62 in two adjacent circuit cells are interconnected via a power connection strip 60. For example, the twelfth connection electrode 62 of the Nth cell column and the N+1th cell column are interconnected via the power connection strip 60.

[0236] In an exemplary embodiment, a plurality of twelfth connecting electrodes 62 and a plurality of power connecting strips 60 in a unit row are interconnected to form a transverse power connecting line extending along the first direction X. The transverse power connecting line and the subsequently formed first power line extending along the second direction Y form a mesh-like interconnected structure for transmitting the first power signal. This not only effectively reduces the resistance of the first power signal line and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves display uniformity, and enhances display quality.

[0237] In an exemplary embodiment, the thirteenth connecting electrode 63 may be a strip shape in which the main body extends along the second direction Y. The thirteenth connecting electrode 63 is connected to the sixth connecting electrode 56 through the twenty-third through-hole V23. The thirteenth connecting electrode 63 is configured to be connected to the subsequently formed anode connecting electrode.

[0238] In an exemplary embodiment, the fifth conductive layer of the display area may further include at least one first connecting line 81. The shape of the first connecting line 81 may be a straight line or a broken line extending along the first direction X of the main body portion, and may be located on the side of the light-emitting signal line 25 away from the second electrode plate 32. The first end of the first connecting line 81 is configured to be connected to a subsequently formed data signal line, and the second end of the first connecting line 81 is configured to be connected to a subsequently formed second connecting line.

[0239] In an exemplary embodiment, the orthographic projection of the first connecting line 81 on the substrate does not completely overlap with the orthographic projection of the second initial signal line 42 on the substrate.

[0240] In one exemplary embodiment, the orthographic projection of the first connection line 81 on the substrate at least partially overlaps with the orthographic projection of the second initial signal line 42 on the substrate, but the overlap area is small, which can reduce the impact of data voltage jumps in the first connection line on the second initial signal.

[0241] In another exemplary embodiment, the orthographic projection of the first connection line 81 on the substrate does not overlap with the orthographic projection of the second initial signal line 42 on the substrate, which can eliminate the influence of data voltage jumps in the first connection line on the second initial signal.

[0242] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a data connection block 83. The data connection block 83 may be block-shaped (e.g., rectangular) and is configured to connect to a subsequently formed second connection line.

[0243] In an exemplary embodiment, in the first direction X, the data connection block 83 may be disposed between two partially adjacent circuit units, and the orthographic projection of the data connection block 83 on the substrate at least partially overlaps with the orthographic projection of the first end of the fourth connection electrode 54 on the substrate.

[0244] In an exemplary embodiment, a break may be provided on the first connecting line 81, which is not limited herein.

[0245] In an exemplary embodiment, the fifth conductive layer of adjacent cell columns can be mirror-symmetrical with respect to the column boundary line. For example, the fifth conductive layer of the Nth cell column and the fifth conductive layer of the (N+1)th cell column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the position and shape of the fifth conductive layer in multiple cell rows can be substantially the same.

[0246] (21) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form a second planarization layer covering the pattern of the fifth conductive layer, wherein a plurality of vias are provided on the second planarization layer, as shown in FIG17.

[0247] In an exemplary embodiment, the plurality of vias in each circuit unit in the display area include at least: a thirty-first via V31, a thirty-second via V32, and a thirty-third via V33.

[0248] In an exemplary embodiment, the orthographic projection of the 31st via V31 on the substrate is within the range of the orthographic projection of the 11th connecting electrode 61 on the substrate. The second planarization layer within the 31st via V31 is etched away, exposing the surface of the 11th connecting electrode 61. The 31st via V31 is configured to allow subsequently formed data signal lines to be connected to the 11th connecting electrode 61 through the via.

[0249] In an exemplary embodiment, the orthographic projection of the 32nd via V32 on the substrate is within the range of the orthographic projection of the 12th connecting electrode 62 on the substrate. The second planarization layer within the 32nd via V32 is etched away, exposing the surface of the 12th connecting electrode 62. The 32nd via V32 is configured to allow a subsequently formed first power line to be connected to the 12th connecting electrode 62 through the via.

[0250] In an exemplary embodiment, the orthographic projection of the 33rd via V33 onto the substrate is within the range of the orthographic projection of the 13th connecting electrode 63 onto the substrate. The second planarization layer within the 33rd via V33 is etched away, exposing the surface of the 13th connecting electrode 63. The 33rd via V33 is configured to allow a subsequently formed anode connecting electrode to be connected to the 13th connecting electrode 63 through the via.

[0251] In an exemplary embodiment, the display area may further include a 34th via V34. The orthographic projection of the 34th via V34 onto the substrate is within the range of the orthographic projection of the data connection block 83 onto the substrate. The second planarization layer within the 34th via V34 is removed, exposing the surface of the data connection block 83. The 34th via V34 is configured to allow a subsequently formed second connection line to be connected to the data connection block 83 through the via.

[0252] (22) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: depositing a sixth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the sixth conductive thin film using a patterning process to form a sixth conductive layer disposed on the second planarization layer, as shown in Figures 18A and 18B, where Figure 18B is a planar schematic diagram of the sixth conductive layer in Figure 18A. In an exemplary embodiment, the sixth conductive layer may be referred to as the third source / drain metal (SD3) layer.

[0253] In an exemplary embodiment, the sixth conductive layer of each circuit unit in the display area includes at least: a data signal line 70, a first power supply line 71, and an anode connection electrode 72.

[0254] In an exemplary embodiment, the data signal line 70 can be a straight line or a broken line extending along the second direction Y. The data signal line 70 is connected to the eleventh connection electrode 61 through the thirty-first via V31. Since the eleventh connection electrode 61 is connected to the third connection electrode 53 through the via, and the third connection electrode 53 is connected to the first region of the fourth active layer through the via, the connection between the data signal line 70 and the first electrode of the fourth transistor T4 is realized, and the data signal line 70 can write data signals to the first electrode of the fourth transistor T4.

[0255] In an exemplary embodiment, since the data signal line is disposed in the third source-drain metal (SD3) layer and is separated from the corresponding signal line by a thicker first planarization layer and a second planarization layer, the distance between the data signal line and the corresponding signal line is increased, the parasitic capacitance between the data signal line and the corresponding signal line is reduced, and thus the capacitive load of the data signal line is effectively reduced.

[0256] In an exemplary embodiment, the shape of the first power line 71 can be a straight line or a broken line extending along the second direction Y. The first power line 71 is connected to the twelfth connecting electrode 62 through the thirty-second via V32. Since the twelfth connecting electrode 62 is connected to the fourth connecting electrode 54 through the power connection strip 60, and the fourth connecting electrode 54 is connected to the first region of the fifth active layer and the second electrode 32 of the storage capacitor, the first power line 71 writes the first power signal into the fifth transistor T5 and the second electrode 32 of the storage capacitor.

[0257] In an exemplary embodiment, the first power line 71 can be a non-uniform width polygonal line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data signal line.

[0258] In an exemplary embodiment, in a cell row, the first power lines 71 in some adjacent circuit cells can be an integral structure that is interconnected. For example, the first power lines 71 of the (N-1)th cell column and the Nth cell column are interconnected, and the first power lines 71 in the two adjacent circuit cells are an integral structure that is interconnected. As another example, the first power lines 71 of the N+1th cell column and the N+2th cell column are interconnected, and the first power lines 71 in the two adjacent circuit cells are an integral structure that is interconnected.

[0259] In an exemplary embodiment, the anode connection electrode 72 can be block-shaped (e.g., rectangular). The anode connection electrode 72 is connected to the thirteenth connection electrode 63 via the thirty-third via V33, and is configured to connect with the subsequently formed anode. Since the thirteenth connection electrode 63 is connected to the sixth connection electrode 56 via a via, and the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer via a via, the connection between the subsequently formed anode and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 can be achieved, allowing the pixel driving circuit to drive the light-emitting device to emit light.

[0260] In an exemplary embodiment, the sixth conductive layer of the display area may further include a second connecting line 82. The shape of the second connecting line 82 may be a straight line or a broken line extending along the second direction Y, and it may be located between two data signal lines 70 in adjacent unit columns. The second connecting line 82 may be connected to the data connecting block 83 through the thirty-fourth via V34. Since the data connecting block 83 is connected to the first connecting line 81, and the first connecting line 81 is configured to be connected to the data signal line 70, the second connecting line 82 is connected to the data signal line 70 through the first connecting line 81, and the second connecting line 82 can transmit data signals to the data signal line 70.

[0261] In an exemplary embodiment, the second connecting line 82 may be provided with a break, which is not limited herein.

[0262] In an exemplary embodiment, since the second connection line is disposed in the third source-drain metal (SD3) layer and is spaced apart from the corresponding signal line by a thicker first planarization layer and a second planarization layer, the distance between the second connection line and the corresponding signal line is increased, the parasitic capacitance between the second connection line and the corresponding signal line is reduced, and thus the capacitive load of the second connection line is effectively reduced.

[0263] In an exemplary embodiment, since the first connecting line is disposed on the second source-drain metal (SD2) layer and the second connecting line is disposed on the third source-drain metal (SD3) layer, the first connecting line and the second connecting line only need one planarization layer via to achieve connection, which minimizes the space occupied and is beneficial to achieving high-resolution display.

[0264] In an exemplary embodiment, the sixth conductive layer of adjacent cell columns can be mirror-symmetrical with respect to the column boundary line. For example, the fifth conductive layer of the Nth cell column and the sixth conductive layer of the (N+1)th cell column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the position and shape of the sixth conductive layer in multiple cell rows can be substantially the same.

[0265] (23) A third planarization layer covering the pattern of the sixth conductive layer is formed. Multiple anode vias are provided on the third planarization layer, and the anode vias expose the anode connection electrodes. At this point, the driving structure layer is fabricated on the substrate.

[0266] In an exemplary embodiment, in a plane parallel to the display substrate, the driving structure layer may include multiple circuit units. At least one circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light emission signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving structure layer may include a shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planarization layer, a fifth conductive layer, a second planarization layer, a sixth conductive layer, and a third planarization layer, sequentially disposed on the substrate. The shielding layer may include at least a shielding electrode; the first semiconductor layer may include at least an active layer of a first transistor, a third transistor to an eighth transistor; the first conductive layer may include at least a first scan signal line, a second scan signal line, a third scan signal line, a light emission signal line, and a first electrode of a storage capacitor; the second conductive layer may include at least a second electrode of a storage capacitor; the second semiconductor layer may include at least an active layer of a second transistor; the third conductive layer may include at least a first initial signal line, a second initial signal line, and a fourth scan signal line; the fourth conductive layer may include at least multiple connection electrodes; the fifth conductive layer may include at least a third initial signal line and a first connection line; and the sixth conductive layer may include at least a data signal line, a first power supply line, and a second connection line.

[0267] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0268] In an exemplary embodiment, the first, second, third, fourth, fifth, and sixth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, fourth, fifth, and sixth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first, second, and third planarization layers can be made of organic materials, such as resins.

[0269] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit cells within a cell row can be substantially mirror-symmetric with respect to the column boundary. For example, the pixel driving circuits in the Nth cell column and the N+1th cell column can be mirror-symmetric with respect to the column boundary.

[0270] In an exemplary embodiment, after the driving structure layer is fabricated, a light-emitting structure layer can be fabricated on the driving structure layer. The fabrication process of the light-emitting structure layer may include: first, forming an anode conductive layer, which includes multiple anodes, each of which can be connected to the anode connection electrode of its respective circuit unit through anode vias. Then, forming a pixel definition layer, which has multiple pixel openings that expose the anodes. Next, forming an organic light-emitting layer using vapor deposition or inkjet printing, followed by forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is positioned between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0271] A reliability test of an LTPO display substrate revealed display defects. Research found that these defects were caused by a large parasitic capacitance between the third node N3 and the fourth scan signal line. In the existing display substrate layout, there is overlap between the second connection electrode (third node N3) and the fourth scan signal line, and the overlap area is large. The parasitic capacitance between the third node N3 and the fourth scan signal line amplifies the characteristic changes of the oxide second transistor T2, increasing the sensitivity of the pixel driving circuit to these changes. This exacerbates the risk to the pixel driving circuit during reliability testing, thus leading to display defects in the reliability test of the display substrate.

[0272] An exemplary embodiment of this disclosure provides a display substrate in which a first transistor T1 and a second transistor T2 are respectively disposed on both sides of a third transistor T3 in the second direction Y. Therefore, the second connection electrode (third node N3) connecting the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the second electrode of the third transistor T3 does not overlap with the fourth scan signal line, thus completely eliminating the parasitic capacitance between the third node N3 and the fourth scan signal line. This minimizes the impact of the characteristic changes of the second transistor T2 on the pixel driving circuit, reduces the risk of the pixel driving circuit in the reliability test process, and avoids display defects in the reliability test of the display substrate.

[0273] An LTPO display substrate also exhibits a multi-screen defect. Research has found that this defect is caused by a large parasitic capacitance between the third initial signal line and the light-emitting signal line. In existing display substrate layouts, the third initial signal line located in the third conductive layer (GATE3) overlaps with the light-emitting signal line located in the first conductive layer (GATE1), resulting in a large parasitic capacitance between them. When the light-emitting signal line switches between on and off multiple times within a frame, the transitions in the light-emitting signal are coupled to the third initial signal due to the parasitic capacitance, causing instability in the third initial signal and thus resulting in the multi-screen phenomenon.

[0274] The display substrate provided in this exemplary embodiment has a third initial signal line disposed in the fifth conductive layer (SD2), and the third initial signal line does not overlap with the light-emitting signal line, thus completely eliminating the parasitic capacitance between the third initial signal line and the light-emitting signal line, ensuring the stability of the third initial signal, and avoiding multi-screen defects of the display substrate. Furthermore, by ensuring that the light-emitting signal line does not overlap with other initial signal lines, the parasitic capacitance of the light-emitting signal line is effectively reduced, the load on the light-emitting signal line is effectively reduced, and the power consumption of the gate driving circuit is lowered.

[0275] This embodiment of the disclosure, by setting the first initial signal line to overlap with the third scan signal line, and the second initial signal line to overlap with the second scan signal line, can effectively reduce the routing difficulty, avoid short circuits between signal lines, and effectively improve product yield. By setting the third initial signal line to overlap with the second initial signal line, the stability of the second initial signal can be increased. By setting a small overlap area or no overlap between the first connecting line and the second initial signal line, the impact of data voltage jumps in the first connecting line on the second initial signal can be effectively reduced, improving display quality and display effect.

[0276] This embodiment of the disclosure achieves an FIP structure by setting a first connecting line and a second connecting line within the display area, which can greatly reduce the width of the bottom bezel, increase the screen ratio, and facilitate the realization of full-screen display.

[0277] The preparation process disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0278] The structure and its preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs, and this disclosure does not limit them.

[0279] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0280] This disclosure also provides a method for fabricating a display substrate to produce the display substrate provided in the above embodiments. In an exemplary embodiment, the display substrate may include multiple circuit units forming multiple cell rows and multiple cell columns; the fabrication method may include:

[0281] A pixel driving circuit is formed in at least one circuit unit, the pixel driving circuit including at least a first transistor as a first reset transistor, a second transistor as a compensation transistor, and a third transistor as a driving transistor, the first transistor and the third transistor being polysilicon transistors, and the second transistor being an oxide transistor; the gate electrode of the second transistor is connected to a fourth scan signal line, the first electrode of the second transistor is connected to the gate electrode of the third transistor, and the second electrode of the second transistor is connected to the second electrodes of the first transistor and the second electrode of the third transistor through a third node electrode; in at least one circuit unit, the first transistor and the second transistor are disposed on opposite sides of the column direction of the third transistor unit, and the orthographic projection of the third node electrode on the display substrate plane does not overlap with the orthographic projection of the fourth scan signal line on the display substrate plane.

[0282] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate comprising a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first transistor as a first reset transistor, a second transistor as a compensation transistor, and a third transistor as a driving transistor, the first transistor and the third transistor being polysilicon transistors, and the second transistor being an oxide transistor; the gate electrode of the second transistor being connected to a fourth scan signal line, the first electrode of the second transistor being connected to the gate electrode of the third transistor, and the second electrode of the second transistor being connected to the second electrodes of the first transistor and the second electrode of the third transistor via a third node electrode; in at least one circuit unit, the first transistor and the second transistor are disposed on opposite sides of the third transistor cell column direction, and the orthographic projection of the third node electrode on the display substrate plane does not overlap with the orthographic projection of the fourth scan signal line on the display substrate plane.

2. The display substrate according to claim 1, wherein, The first transistor includes at least a first active layer, the second transistor includes at least a second active layer, and the third transistor includes at least a third active layer; In at least one circuit unit, the first end of the third node electrode is connected to the second region of the second active layer through a via, the third node electrode is a strip shape extending along the column direction of the unit, the second end of the third node electrode is connected to the second region of the first active layer through a via, and the portion between the first end and the second end of the third node electrode is connected to the first region of the third active layer through a via.

3. The display substrate according to claim 1, wherein, The pixel driving circuit further includes a fourth transistor as a data writing transistor, the gate electrode of the fourth transistor is connected to the first scan signal line, the first electrode of the fourth transistor is connected to the data signal line, and the second electrode of the fourth transistor is connected to the first electrode of the third transistor; in at least one circuit unit, the orthographic projection of the third node electrode on the display substrate plane does not overlap with the orthographic projection of the first scan signal line on the display substrate plane.

4. The display substrate according to any one of claims 1 to 3, wherein, The pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor, the gate electrode of the fifth transistor is connected to the light-emitting signal line, the first electrode of the fifth transistor is connected to the first power supply line, and the second electrode of the fifth transistor is connected to the first electrode of the third transistor; in at least one circuit unit, the orthographic projection of the third node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the light-emitting signal line on the display substrate plane.

5. The display substrate according to claim 4, wherein, The gate electrode of the first transistor is connected to the third scan signal line, and the first electrode of the first transistor is connected to the first initial signal line; in at least one circuit unit, the orthographic projection of the first initial signal line on the display substrate plane does not overlap with the orthographic projection of the light-emitting signal line on the display substrate plane.

6. The display substrate according to claim 5, wherein, In at least one circuit unit, the orthographic projection of the first initial signal line on the display substrate plane at least partially overlaps with the orthographic projection of the third scan signal line on the display substrate plane.

7. The display substrate according to claim 5, wherein, In at least one circuit unit, the third scan signal line and the fourth scan signal line are disposed on both sides of the third node electrode unit column direction, and the orthographic projection of the third node electrode on the display substrate plane does not overlap with the orthographic projection of the third scan signal line on the display substrate plane.

8. The display substrate according to claim 4, wherein, The pixel driving circuit further includes a seventh transistor as a second reset transistor, the gate electrode of the seventh transistor is connected to the second scan signal line, and the first electrode of the seventh transistor is connected to the second initial signal line; in at least one circuit unit, the orthographic projection of the second initial signal line on the display substrate plane does not overlap with the orthographic projection of the light-emitting signal line on the display substrate plane.

9. The display substrate according to claim 8, wherein, In at least one circuit unit, the orthographic projection of the second initial signal line on the display substrate plane at least partially overlaps with the orthographic projection of the second scan signal line on the display substrate plane.

10. The display substrate according to claim 8, wherein, In at least one circuit unit, the orthographic projection of the third node electrode on the display substrate plane at least partially overlaps with the orthographic projections of the second scan signal line and the second initial signal line on the display substrate plane.

11. The display substrate according to claim 8, wherein, The pixel driving circuit further includes an eighth transistor as a third reset transistor. The gate electrode of the eighth transistor is connected to the second scan signal line, the first electrode of the eighth transistor is connected to the third initial signal line, and the second electrode of the eighth transistor is connected to the first electrode of the third transistor and the second electrode of the fifth transistor. The orthographic projection of the third initial signal line on the display substrate plane does not overlap with the orthographic projection of the light-emitting signal line on the display substrate plane.

12. The display substrate according to claim 11, wherein, The orthographic projection of the third initial signal line on the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line on the display substrate plane.

13. The display substrate according to claim 11, wherein, In at least one circuit unit, the orthographic projection of the third node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the third initial signal line on the display substrate plane.

14. The display substrate according to claim 11, wherein, In a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers disposed on the substrate, and the second initial signal line and the third initial signal line are disposed in different conductive layers.

15. The display substrate according to claim 14, wherein, The plurality of conductive layers include at least a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, a third conductive layer disposed on the side of the second conductive layer away from the substrate, a fourth conductive layer disposed on the side of the third conductive layer away from the substrate, and a fifth conductive layer disposed on the side of the fourth conductive layer away from the substrate. The light-emitting signal line and the second scanning signal line are disposed in the first conductive layer, the second initial signal line is disposed in the third conductive layer, the third node electrode is disposed in the fourth conductive layer, and the third initial signal line is disposed in the fifth conductive layer.

16. The display substrate according to claim 8, wherein, The display substrate further includes at least one first connection line extending along the pixel row direction and at least one second connection line extending along the pixel column direction. The second connection line is connected to the first connection line through a via. The first connection line and the second connection line are configured to transmit data signals. In at least one circuit unit, the orthographic projection of the first connecting line on the display substrate plane does not completely overlap with the orthographic projection of the second initial signal line on the display substrate plane.

17. The display substrate according to claim 16, wherein, In at least one circuit unit, the orthographic projection of the first connecting line on the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line on the display substrate plane, or the orthographic projection of the first connecting line on the display substrate plane does not overlap with the orthographic projection of the second initial signal line on the display substrate plane.

18. The display substrate according to claim 16, wherein, In at least one circuit unit, the orthographic projection of the third node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the first connecting line on the display substrate plane.

19. A display device comprising a display substrate as described in any one of claims 1 to 18.

20. A method for fabricating a display substrate, comprising forming a plurality of circuit units with a plurality of cell rows and a plurality of cell columns; the fabrication method comprising: A pixel driving circuit is formed in at least one circuit unit, the pixel driving circuit including at least a first transistor as a first reset transistor, a second transistor as a compensation transistor, and a third transistor as a driving transistor, wherein the first transistor and the third transistor are polysilicon transistors, and the second transistor is an oxide transistor; the gate electrode of the second transistor is connected to a fourth scan signal line, the first electrode of the second transistor is connected to the gate electrode of the third transistor, and the second electrode of the second transistor is connected to the second electrode of the first transistor and the third transistor through a third node electrode. The second electrode of the third transistor is connected; in at least one circuit unit, the first transistor and the second transistor are disposed on both sides of the column direction of the third transistor unit, and the orthographic projection of the third node electrode on the display substrate plane does not overlap with the orthographic projection of the fourth scan signal line on the display substrate plane.

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