Chip and method for configuring electronic fuse

Abstract

The present application provides a chip and method for configuring an electronic fuse. The chip comprises: a state machine, the states of which comprise a programming state, a reading state, and a serial control state; a shift register, which receives and temporarily stores externally sent first control information and data to be programmed, and is configured to receive, store and output a programming result, wherein the first control information is used for controlling the state machine to enter the programming state or the reading state; and a first pin, the shift register receiving, by means of the first pin, the externally sent first control information. The state machine is configured to: in the serial control state, acquire, from the shift register according to a clock counting cycle, first control information and data to be programmed; in the programming state, write the data to be programmed in the shift register into an electronic fuse; in the reading state, read a programming result of the electronic fuse and then store same into the shift register; and on the basis of a reset signal, read the programming result of the electronic fuse and then store same into the shift register.

Description

A chip and method for configuring an electronic fuse

[0001] Cross-reference to related applications

[0002] This disclosure is based on and claims priority to Chinese Patent Application No. 202411440666.9, filed on October 15, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to, but is not limited to, a chip and method for configuring an electronic fuse. Background Technology

[0004] Chips typically require read-only memory (ROM) to store fixed information, such as the chip ID, security code, and TRIM data. ROM usually includes non-volatile storage devices for storing this information. Electronic fuses (EFuses) have become widely used non-volatile storage devices due to their ease of use.

[0005] Compared to other fuses that use laser cutting or mechanical cutting, electronic fuses can be programmed through pure circuitry. Taking a polysilicon fuse as an example: a polysilicon fuse is typically a very thin section of polysilicon. When the chip leaves the factory, the thin polysilicon fuse is in an unfused state, exhibiting low resistance between its two ends. To program data, a high voltage is applied across the thin polysilicon fuse, resulting in a large current flowing through it. The heat generated burns the polysilicon fuse, causing high resistance between its ends. To read data, a low voltage or low current is applied across the polysilicon fuse, and measuring the resistance of the polysilicon fuse generates the corresponding binary data. During the use of electronic fuses, several problems can affect their yield. For example, due to manufacturing defects, an electronic fuse that should be unfused may become fused; or various reasons may prevent the electronic fuse from being properly fused. Summary of the Invention

[0006] In view of this, the present disclosure provides a chip and method for configuring electronic fuses. By using the chip to configure the electronic fuses, chip pin resources and chip area can be saved, while ensuring calibration effect.

[0007] This disclosure provides a chip with an configured electronic fuse, comprising: a state machine, the states of which include a programming state, a reading state, and a serial control state; a shift register configured to receive and temporarily store externally transmitted first control information and data to be programmed, and configured to receive, store, and output programming results; wherein the first control information is used to control the state machine to enter the programming state or the reading state; a first pin through which the shift register receives the externally transmitted first control information; the state machine is configured to: in the serial control state, acquire the first control information and the data to be programmed from the shift register at clock counting cycles, the clock counting cycle being an integer multiple of the number of bits in the shift register; in the programming state, write the data to be programmed from the shift register into the electronic fuse; in the reading state, read the programming result of the electronic fuse and store it in the shift register; and based on a reset signal, read the programming result of the electronic fuse and store it in the shift register.

[0008] This disclosure also provides a configuration method for an electronic fuse, comprising: receiving external first control information and data to be programmed via the same pin and temporarily storing them in a shift register; wherein, the first control information is used to determine the operation state of the electronic fuse, the operation state including a programming state, a reading state, and a serial control state; in the serial control state, acquiring the temporarily stored first control information and the data to be programmed at clock counting cycles; the clock counting cycle is an integer multiple of the number of bits in the shift register; in the programming state, parsing the temporarily stored data to be programmed and writing it into the electronic fuse; in the reading state, parsing the programming result of the electronic fuse, reading it, and storing it in the shift register; and based on a reset signal, reading the programming result of the electronic fuse and storing it in the shift register.

[0009] This disclosure provides a chip with an configured electronic fuse, comprising: a state machine, the states of which include a programming state, a reading state, and a serial control state; a shift register configured to receive and temporarily store externally transmitted first control information and data to be programmed, and configured to receive, store, and output programming results; wherein the first control information is used to control the state machine to enter the programming state or the reading state; and a first pin through which the shift register receives the externally transmitted first control information.

[0010] In serial control mode, the state machine retrieves the first control information and the data to be programmed from the shift register in clock counting cycles, where the clock counting cycle is an integer multiple of the number of bits in the shift register. Because the clock counting cycle is an integer multiple of the number of bits in the shift register, when the state machine reads from the shift register, the first control information and the data to be programmed are located at fixed positions in the shift register, allowing the state machine to accurately distinguish between them. Therefore, the chip does not require dedicated decoders or other devices to parse the first control information and the data to be programmed, reducing chip area and improving integration density. Using a shift register, only a single first pin can be used to retrieve the first control information and the data to be programmed from the outside, saving on the number of chip pins.

[0011] In the programming state, the state machine writes the data to be programmed from the shift register into the electronic fuse; in the reading state, the state machine reads the programming result of the electronic fuse and stores it in the shift register. Using a state machine, programming and reading of electronic fuses can be easily implemented.

[0012] The state machine, based on the reset signal, reads the electronic fuse programming result and stores it in a shift register. When the chip powers on, the state machine can be reused to read the electronic fuse programming result, and the shift register can be reused to store the programming result. Because the electronic fuse programming result is stored in the shift register, the programming result stored in the shift register can be used for calibration after the chip powers on, without directly using the data stored in the electronic fuse for calibration. The electronic fuse does not need to be in a constantly operating state, which can prevent the electronic fuse from being damaged due to long-term operation.

[0013] In some solutions, the chip also includes a module to be calibrated, with a shift register connected to the module and configured to output the programming result to it. In other words, this disclosure can output the programming result to the module to be calibrated via a shift register, eliminating the need for multiple electronic fuses in the electronic fuse to be individually connected to the module, thus further saving chip area. Furthermore, after the programming result is read, the electronic fuse does not need to continuously output the result, and therefore does not need to operate, further saving power consumption.

[0014] In some designs, the chip also includes a first port and / or a second port. The first port is used to send a first external clock signal to the state machine and shift register, and the second port includes a first pin. The second port is used to send first control information and data to be programmed to the shift register, and the second port also includes a first pin. The first port and / or the second port are also configured to transmit second control information, which is an analog signal provided to the chip during operation. Before the chip leaves the factory, the first port can be used to provide the first clock signal to the state machine and shift register, and the second port can be used to send the first control information and data to be programmed to the shift register. After the chip leaves the factory and begins operation, the pins in the first port and / or the second port can be used to transmit the second control information, achieving pin multiplexing and further saving the chip's pin resources. Attached Figure Description

[0015] Figure 1 is a schematic diagram of the chip structure provided in an embodiment of this disclosure;

[0016] Figure 2 is a schematic diagram of the interface of the control module provided in an embodiment of this disclosure;

[0017] Figure 3 is a schematic diagram of the structure of the chip provided in an embodiment of this disclosure;

[0018] Figure 4 is a schematic diagram of the state machine provided in an embodiment of this disclosure;

[0019] Figure 5 is a schematic diagram of the chip structure provided in the embodiment of this disclosure;

[0020] Figure 6 is a schematic diagram of the structure of the first port provided in an embodiment of this disclosure;

[0021] Figure 7 is a schematic diagram of the structure of the second port provided in an embodiment of this disclosure;

[0022] Figure 8 is a schematic diagram of the chip structure provided in the embodiment of this disclosure;

[0023] Figure 9 is a schematic diagram of the chip structure provided in an embodiment of this disclosure;

[0024] Figure 10 is a flowchart illustrating the configuration method of an electronic fuse provided in an embodiment of this disclosure. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0026] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0029] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0030] Figure 1 is an optional structural diagram of the chip 100 provided in an embodiment of this disclosure. The chip 100 can embed some debugging and calibration chip data. The embedded debugging and calibration chip data of the chip 100 can be transmitted to the calibration module 30 inside the chip for debugging and calibration of the calibration module 30. For example, the calibration module 30 can be an RF module, and the embedded data can be used to calibrate the gain of the gain amplifier in the RF module to ensure the gain consistency of the chip 100 at the time of manufacture.

[0031] In this embodiment of the disclosure, referring to FIG1, chip 100 may include a shift register 11, a state machine 12, an electronic fuse 20, and a first pin PAD2. Chip 100 can utilize shift register 11 and state machine 12 to program some debugging and calibration chip data to the electronic fuse 20; that is, shift register 11 and state machine 12 are used to configure the electronic fuse 20. For example, shift register 11 can receive data to be programmed, which may include some debugging and calibration chip data that chip 100 needs to solidify. The data to be programmed may come from a host computer outside the chip. The electronic fuse 20 may include multiple electronic fuses, each of which can store one or more data bits. State machine 12 can program all data bits of the data to be programmed from shift register 11 into the corresponding electronic fuse of electronic fuse 20 for storage.

[0032] In some embodiments, chip 100 may include a control module 10, which controls the programming and reading of electronic fuse 20 and controls the reception of data to be programmed from outside chip 100. The control module 10 may include a shift register 11 and a state machine 12. Figure 2 is a schematic diagram of an optional interface of the control module 10. It should be noted that the serial digital interface 10 in Figure 2 mainly includes an input interface and an output interface. As shown in Figure 2, the input interface mainly includes a reset signal RST interface 101, a clock signal CLK interface 102, and an input data signal SDI interface 103. The output interface mainly includes a transmit output data signal SDO interface 104, a parallel output data bus interface 105, a clock control interface 106, and an enable signal interface 107. First control information and data to be programmed from outside the chip can be transmitted to the control module 10 via the input data signal SDI interface 103. Programming results and other data can be output to the outside of the chip via the output data signal SDO interface 104. The first clock signal from outside the chip or the second clock signal generated inside the chip can be input to the control module 10 via the clock signal CLK interface 102.

[0033] In this embodiment of the disclosure, referring to FIG1, the control module 10 may include a shift register 11. The shift register 11 can be used to transmit and temporarily store external first control information and data to be programmed. The shift register 11 can receive and temporarily store external first control information and data to be programmed from the first pin PAD2. The first control information is used to control the state of the state machine 12, and the first control information and data to be programmed can be used to configure the electronic fuse 20. For example, the control module 10 can receive a first clock signal from outside the chip through the input clock signal CLK interface 102 shown in FIG2. In some embodiments, as shown in FIG1, the chip 100 further includes a second pin PAD1, which is connected to the input clock signal CLK interface 102 shown in FIG2 for transmitting the first clock signal. The precision of the first clock signal is higher than that of the second clock signal. The first clock signal can originate from a host computer outside the chip. During programming, the first clock signal can ensure that the phase of the clock driving the shift register 11 and the data received by the shift register 11 is controllable, avoiding data transmission errors. Driven by the first clock signal, the shift register 11 can receive the first control information and the data to be programmed from the input data signal SDI interface 103 shown in Figure 2 from outside the chip, and temporarily store the received first control information and the data to be programmed in the shift register 11.

[0034] In this embodiment of the present disclosure, referring to FIG1, the control module 10 may further include a state machine 12. The state machine 12 may be a Moore-type state machine or a Mealy-type state machine. For example, the states of the state machine 12 may include a programming state, a reading state, and a serial control state. The programming state is when the state machine 12 controls the programming of the electronic fuse 20; the reading state is when the state machine 12 controls the reading of the electronic fuse 20; and the serial control state is when the state machine 12 controls the shift register 11 to perform serial input or serial output. When programming or reading is not required, the state machine 12 remains in the serial control state. In the serial control state, the state machine 12 obtains first control information and data to be programmed from the shift register 11 at clock counting cycles, thereby periodically obtaining the first control information from the shift register 11 to monitor the status of the first control information and determine whether it is necessary to jump to the programming state or the reading state. The state machine 12 can periodically obtain the first control information according to the counting of the clock signal, wherein the clock signal may be a first clock signal or a second clock signal. The clock counting period is an integer multiple of the number of bits in shift register 11. Because the clock counting period is an integer multiple of the number of bits in shift register 11, when state machine 12 reads from shift register 11, the first control information and the data to be programmed are located at fixed positions in shift register 11, and state machine 12 can accurately distinguish between the first control information and the data to be programmed. Therefore, chip 100 does not need to set up a dedicated decoder or other devices to parse the first control information and the data to be programmed. Compared with obtaining the first control information through serial peripheral interface (SPI) or I2C (Inter-Integrated Circuit) interface, the embodiments of this disclosure do not require a decoder in the serial peripheral interface or I2C interface to decode the first control information, which can reduce the chip area and improve the integration.

[0035] In this embodiment of the disclosure, referring to FIG1, state machine 12 is connected to shift register 11 and electronic fuse 20. State machine 12 is configured to receive first control information and data to be programmed. For example, state machine 12 can call the first control information and data to be programmed received by shift register 11, or shift register 11 can send the temporarily stored first control information and data to be programmed to state machine 12. The first control information can be a control instruction used to control the state of state machine 12. The first control information can be encoded using sequential encoding, Gray encoding, or one-hot encoding. For example, when the first control information is encoded using sequential encoding, the encoding corresponding to the programming state of state machine 12 is "10"; the encoding corresponding to the reading state of state machine 12 is "01"; and the encoding corresponding to the serial control state of state machine 12 is "00" or "11".

[0036] In this embodiment of the disclosure, referring to FIG1, state machine 12 can write the data to be programmed into electronic fuse 20 based on first control information, or read the programming result of the data to be programmed from electronic fuse 20 based on first control information. For example, state machine 12 can generate third control information based on the received first control information. The third control information is a control signal that electronic fuse 20 can recognize, and the third control information can control electronic fuse 20 to perform programming or reading. The third control information may include reading waveform and programming waveform. State machine 12 can be implemented by a flip-flop, which can be a D flip-flop. The flip-flop may include two input terminals, which can respectively receive the first control information and a clock signal, and realize state transition based on the control of the first control information and the clock signal. The clock signal can be a first clock signal or a second clock signal.

[0037] If the state corresponding to the first control information received by state machine 12 is "10", then state machine 12 will be in the programming state. At this time, under the control of the first clock signal, state machine 12 generates third control information based on the data in shift register 11. The third control information generated by state machine 12 is the programming waveform. When the third control information is the programming waveform, the programming waveform may also include the data to be programmed. Then, state machine 12 can transmit the data to be programmed and the programming waveform to electronic fuse 20. Based on the programming waveform, electronic fuse 20 solidifies the data to be programmed into the corresponding electronic fuse wire in electronic fuse 20.

[0038] If the state corresponding to the first control information received by state machine 12 is "01", then state machine 12 will be in the reading state. At this time, under the control of the first clock signal, the third control information generated by state machine 12 is the reading waveform. Then, state machine 12 can transmit the reading waveform to electronic fuse 20. Based on the reading waveform, electronic fuse 20 reads the data stored in the corresponding electronic fuse wire, which can be understood as the writing result of the data to be written, and transmits the writing result to state machine 12.

[0039] In this embodiment, only the first pin PAD2 and the second pin PAD1 of the electronic fuse 20 are needed to complete the read and write control of the chip 100 and input the data to be burned before leaving the factory. Compared with the related technology that configures the electronic fuse 20 through a serial peripheral interface or I2C interface, this embodiment requires fewer pins, thereby saving pin resources and improving integration.

[0040] When the chip is manufactured and powered on, it generates a reset signal. State machine 12 then reads the programming result of electronic fuse 20 and stores it in shift register 11 based on this reset signal. Because the programming result of electronic fuse 20 is stored in shift register 11, the result can be used for calibration after chip 100 is powered on. This eliminates the need to directly use the data stored in electronic fuse 20 for calibration, and prevents electronic fuse 20 from being continuously powered on, thus avoiding damage due to prolonged operation.

[0041] It should be noted that, referring to Figure 1, both the state machine 12 and the shift register 11 in the control module 10 require a clock signal during operation. In some embodiments, the chip can be configured using a first clock signal before leaving the factory, which can improve the accuracy of the configuration; after the chip is delivered to the customer, the chip's second clock signal can be used, which can save power consumption.

[0042] Therefore, to save power consumption, chip 100 may also include a clock generation module 50. After the chip leaves the factory, chip 100 can use the clock generation module 50 to generate a second clock signal. Thus, chip 100 can use the second clock signal to drive the state machine 12 and shift register 11 in the control module 10 to operate.

[0043] In this embodiment of the present disclosure, referring to FIG1, the state machine 12 can generate a clock control signal after the chip 100 is powered on. The clock control signal controls the on and off of the clock generation module 50. For example, the clock generation module 50 may include an oscillator. The control module 10 can output a clock control signal to the oscillator through the "clock control" interface 106 as shown in FIG2. The oscillator is in a closed state when it does not receive a clock control signal. After receiving a clock control signal, the oscillator is in a closed state, generates a second clock signal, and transmits the second clock signal to the control module 10. In this way, this embodiment of the present disclosure can control the clock generation module 50 to control its on and off states, thereby avoiding the clock generation module 50 from operating for a long time and increasing chip power consumption.

[0044] Referring to FIG1, in this embodiment of the present disclosure, when the state machine 12 can operate and be powered on by the chip 100, after receiving the second clock signal, the state machine 12 is configured to read the burning result of the data to be burned from the electronic fuse 20 based on the second clock signal, and store the burning result in the shift register 11. For example, the state machine 12 can receive the second clock signal and, based on the control of the second clock signal, realize state transition and generate third control information to read the electronic fuse 20. The shift register 11 can count the second clock signal and use the clock counting result to control the data scheduling, that is, store the burning result in the shift register 11. In other words, this embodiment of the present disclosure can both use the shift register 11 to receive the data to be burned and the first control information from outside the chip, and can also reuse the shift register 11 to store the burning result. Furthermore, the chip can be debugged and calibrated by storing the burning result in the shift register 11.

[0045] Thus, during chip power-on calibration, this disclosure can reuse state machine 12 to read the programming result, reuse shift register 11 to store the programming result, and drive the clock signal of state machine 12 and shift register 11 to the second clock signal generated by clock generation module 50. In other words, this disclosure only needs to set up internal clock module 50, reuse shift register 11 and state machine 12 to complete chip calibration after power-on. Therefore, this embodiment does not require other circuit structures, achieving chip miniaturization.

[0046] In other embodiments, when the chip 100 is powered on, the state machine 12 can also read the burning result of the electronic fuse 20 and store it in the shift register 11 according to the received first clock signal.

[0047] In some embodiments of this disclosure, referring to FIG1, before the chip leaves the factory, the state machine 12 is also configured to control the shift register 11 to output the programming result to the outside when in a serial control state. For example, the state machine 12 is also configured to control the shift register 11 to serially input or serially output data when in a serial control state.

[0048] If the state corresponding to the first control information received by state machine 12 is "00", state machine 12 can issue a control command to shift register 11 to enter serial transmission mode. At this time, shift register 11 can enter the serial input sub-state based on the control command of serial transmission mode and the drive of the first clock signal, and receive data such as the data to be programmed and the first control information from the external chip from the input data signal SDI interface 103 as shown in Figure 2.

[0049] If the state corresponding to the first control information received by state machine 12 is "11", state machine 12 can issue a control command for serial transmission mode to shift register 11. At this time, shift register 11 can enter the serial output sub-state based on the received control command for serial transmission mode and the drive of the first clock signal, and output the stored writing result from the output data signal SDO interface 104 as shown in Figure 2 to the host computer outside the chip. In this way, the host computer outside the chip can monitor whether the data in shift register 11 meets the expectations. That is, the host computer can verify the writing result by comparing the writing result with the data to be written, so as to determine whether the electronic fuse 20 has been successfully written. In other words, the embodiment of this disclosure reuses shift register 11, and there is no need to set up additional devices for verifying the writing result, thereby further reducing the chip area and improving the integration.

[0050] It should be noted that, typically, for cost reasons, some small chips use simpler electronic fuses. Due to design limitations such as overload protection and aging resistance, these electronic fuses lack internal protection circuits for overload protection and anti-aging, making them unsuitable for continuous operation. Prolonged continuous operation of such fuses may damage components (such as transistors), causing them to malfunction. Therefore, during the debugging and calibration of the module 30 by chip 100, these electronic fuses cannot continuously output stored debugging and calibration chip data to the module 30.

[0051] To address this issue, in some embodiments of this disclosure, referring to FIG1, the chip 100 further includes a calibration module 30. A shift register 11 is connected to the calibration module 30. The shift register 11 is configured to output the programming result to the calibration module 30 to calibrate the chip according to the programming result stored in the electronic fuse 20.

[0052] In some implementations, the module to be calibrated 30 may include a register, and the programming result may be output to the register of the module to be calibrated 30, so that the programming result can be temporarily stored in the register and calibration can be continuously performed based on the programming result without powering off.

[0053] In this embodiment of the present disclosure, referring to FIG1, the shift register 11 can receive a first clock signal or a second clock signal through the clock signal CLK interface 102 shown in FIG2. The shift register 11 can count the received first clock signal or second clock signal through a built-in clock counter. Furthermore, the shift register 11 can transmit the programming result received from the state machine 12 to the calibration module 30 inside the chip in real time or according to the result of clock counting, so as to achieve the purpose of debugging and calibration.

[0054] In other words, this embodiment of the present disclosure can debug and calibrate the chip through the programming results in the shift register 11. In this way, this embodiment of the present disclosure can use the shift register 11 to continuously output debugging and calibration data (i.e., programming results of the data to be programmed) to the calibration module 30 inside the chip, without the need for multiple electronic fuses in the electronic fuse 20 to be connected to the calibration module 30 separately, making the circuit connection simpler.

[0055] Furthermore, when the chip is in operation after leaving the factory, the electronic fuse 20 only needs to output the programming result to the shift register 11 each time the chip is powered on. After the electronic fuse 20 has finished reading, it does not need to continuously output the programming result to the module to be calibrated 30. The electronic fuse 20 can be powered off without working for a long time, which can effectively reduce the power consumption and cost of the chip.

[0056] In addition, the embodiments disclosed herein can reuse the shift register 11, eliminating the need for additional devices for verifying the programming results and continuously outputting the programming results. This allows for a further reduction in chip area and an increase in integration density.

[0057] Figure 3 is a schematic diagram of an optional control module 10 provided in an embodiment of this disclosure. It should be noted that the clock signal CLK, input data signal SDI, and output data signal SDO in Figure 3 can be understood with reference to Figure 2, and will not be repeated here. To clearly show the structure of the shift register 11, the electronic fuse 20 is not shown in Figure 3.

[0058] It should also be noted that the data transmitted between shift register 11 and the host computer is usually in serial form. For example, the data to be programmed into the electronic fuse 20 is usually input serially from the host computer, and the programming result temporarily stored in shift register 11 needs to be output serially to the host computer for verification. The data transmission between shift register 11 and the internal chip is usually in parallel form. For example, the data to be programmed temporarily stored in shift register 11 needs to be transmitted in parallel to state machine 12, and the programming result temporarily stored in shift register 11 needs to be transmitted in parallel to calibration module 30.

[0059] In some embodiments of this disclosure, referring to FIG3, the shift register 11 includes a serial input terminal, a serial output terminal, and a parallel input / output terminal. The serial input terminal of the shift register 11 is configured to receive first control information and data to be programmed from an external source. For example, the serial input terminal of the shift register 11 is connected to the input data signal SDI interface 103 as shown in FIG2. The shift register 11 can receive the serially input first control information and data to be programmed from the input data signal SDI interface 103 of the control module 10, and store the first control information and data to be programmed in the first register unit 110 and the second register unit 111, respectively.

[0060] In the embodiments of this disclosure, referring to FIG3, the parallel input / output terminals of the shift register 11 can perform parallel input and parallel output of data. The parallel input / output terminals are respectively connected to the state machine 12 and the data bus 40, and are configured to output first control information and data to be programmed to the state machine 12, and / or receive programming results and output the programming results to the data bus 40. For example, the parallel input / output terminals of the shift register 11 are connected to the state machine 12. Both the parallel input / output terminals of the shift register 11 and the data bus 40 are connected to the "parallel output data bus" interface 105 of the control module 10 as shown in FIG2 for parallel input and output.

[0061] In this way, shift register 11 can output the first control information and the data to be written to state machine 12 in parallel, and receive the writing result of the data to be written from electronic fuse 20 from state machine 12. That is, shift register 11 is used to store the data to be written to electronic fuse 20 and to store the writing result of the data to be written read from electronic fuse 20.

[0062] In this embodiment of the present disclosure, referring to FIG3, the serial output terminal of shift register 11 is configured to output the programming result to the outside. For example, the serial output terminal of shift register 11 is connected to the output data signal SDO interface 104 as shown in FIG2. Shift register 11 can output the programming result stored inside shift register 11 bit by bit to the outside of the chip through the output data signal SDO interface 104, for example, outputting the programming result to a host computer to provide feedback on the programming result of electronic fuse 20, so as to facilitate the judgment of whether the programming of electronic fuse 20 meets expectations. The external host computer can verify the programming result by comparing the programming result with the data to be programmed to determine whether electronic fuse 20 has been programmed successfully. In some embodiments, after programming electronic fuse 20, state machine 12 automatically enters the reading state and transmits the programming result of electronic fuse 20 to shift register 11. Shift register 11 can output the programming result stored inside shift register 11 bit by bit to the outside of the chip through the output data signal SDO interface 104.

[0063] In some embodiments of this disclosure, referring to FIG3, the shift register 11 includes a first register unit 110 and a second register unit 111. Both the first register unit 110 and the second register unit 111 may include one or more data bits. The arrangement order of the first register unit 110 and the second register unit 111 is not limited to the arrangement order shown in FIG3. In embodiments of this disclosure, referring to FIG3, driven by a first clock signal, the shift register 11 can receive a first control signal and data to be programmed from a host computer outside the chip. The first control signal and the data to be programmed are sequentially and serially fed into the first register unit 110 and the second register unit 111. The first control signal and the data to be programmed are distinguished by reading the data in the first register unit 110 at clock counting cycles.

[0064] In some embodiments, when the first control information is encoded using timing coding, the encoding of the first control information can be 2 bits. The first register unit 110 may include two cascaded flip-flops, each of which stores one bit of the encoding of the first control information. The number of flip-flops included in the second register unit 111 may be greater than or equal to the number of data bits in the electronic fuse 20. Each flip-flop in the second register unit 111 stores one bit of the encoding of the data to be programmed.

[0065] In this embodiment of the present disclosure, referring to FIG3, both the first register unit 110 and the second register unit 111 are connected to the state machine 12. The first register unit 110 is configured to transmit first control information to the state machine 12. For example, the state machine 12 can read the first control information (control instruction) in the first register unit 110 once every fixed clock cycle based on the control of a first clock signal or a second clock signal, thereby determining the next jump to the state corresponding to the first control information. It should be noted that the fixed clock cycle is related to the number of bits in the shift register 11. For example, if the number of bits in the shift register 11 is N bits, the state machine 12 can read once every N, 2N, 3N, etc. clock cycles to ensure that the first control information and data can be correctly distinguished, so as to avoid missed or incorrect readings.

[0066] The second register unit 111 is configured to transmit the data to be programmed to the state machine 12. For example, if the state machine 12 jumps to the programming state shown in FIG. 4 according to the encoding of the first control information, the second register unit 111 transmits the stored data to be programmed to the state machine 12 in parallel. Alternatively, if the state machine 12 jumps to the read state shown in FIG. 4 according to the encoding of the first control information, the state machine 12 transmits the programming result read from the electronic fuse 20 to the second register unit 111 for storage. If the state machine 12 jumps to the serial control state shown in FIG. 4 according to the encoding of the first control information, the second register unit 111 can serially output the stored programming result bit by bit to the outside of the chip through the output data signal SDO interface 104 shown in FIG. 2, for example, outputting the programming result to the host computer to provide feedback on the programming result of the electronic fuse 20, so as to determine whether the programming of the electronic fuse 20 meets the expectations.

[0067] In a specific example, assume that the first register 110 is 2 bits, the second register 111 is 2 bits, and the initial value of shift register 11 is 0000, where the first two bits are the data bits of the first register 110 and the last two bits are the data bits of the second register 111:

[0068] During the first clock count, shift register 11 is fed with 1, so the value of shift register 11 is 1000;

[0069] During the second clock count, a 1 is inserted into shift register 11, so the value of shift register 11 is 1100;

[0070] During the third clock count, a 0 is inserted into shift register 11, so the value of shift register 11 is 0110;

[0071] During the fourth clock count, a 1 is inserted into shift register 11, so the value of shift register 11 is 1011;

[0072] After four clock cycles, state machine 12 reads the first control information from the first register unit 110, which is "10". State machine 12 then enters the programming state. The data to be programmed in the second register unit 111 is "11", and state machine 12 writes "11" into the electronic fuse. At the same time, the data to be programmed "11" can be transmitted to the calibration module 30.

[0073] In this embodiment of the present disclosure, referring to FIG3, the chip 100 further includes a data bus 40. A second register unit 111 is also connected to the data bus 40. The second register unit 111 is further configured to output the stored programming result to the data bus 40. For example, driven by a first clock signal or a second clock signal, the second register unit 111 can output the stored programming result to the data bus 40 through the "parallel output data bus" interface 105 of the control module 10 shown in FIG2. Furthermore, the data bus 40 is only connected to the second register unit 111 and not to the first register unit 110. Therefore, interference from the first register unit 110 on the process of the second register unit 111 transmitting data to the data bus 40 can be avoided.

[0074] It should be noted that the output data signal SDO interface 104 and the input data signal SDI interface 103 shown in Figure 2 can be connected to the same first pin PAD2 shown in Figure 1. In some embodiments, the first pin PAD2 is a pin of the bidirectional interface, and the state machine 12 can control whether the bidirectional interface is in the input or output state. For example, if the first control information received by the state machine 12 is encoded as "00", the state machine 12 controls the shift register 11 to perform serial input. At this time, the bidirectional interface is in the input state, and the first control information and the data to be programmed from outside the chip can be transmitted to the shift register 11 along the bidirectional interface. If the first control information received by the state machine 12 is encoded as "11", the state machine 12 controls the shift register 11 to perform serial output. At this time, the bidirectional interface is in the output state, and the programming result stored in the shift register 11 can be output to the outside of the chip along the bidirectional interface.

[0075] In some embodiments of this disclosure, referring to FIG1, chip 100 further includes a power-on reset module 60. The power-on reset module 60 is configured to generate a reset signal RST after chip 100 is powered on. State machine 12, connected to the power-on reset module 60, is further configured to receive the reset signal RST, and based on the reset signal RST, enter a read state to read the writing result of the data to be written from the electronic fuse 20.

[0076] In this embodiment of the present disclosure, referring to FIG1, after the chip 100 is powered on, the control module 10 can generate an enable signal and a clock control signal. Thus, the clock generation module 50 can provide the control module 10 with a second clock signal to drive the state machine 12 and the shift register 11 to operate. Furthermore, the first selector Mux1, triggered by the enable signal, can transmit the second clock signal to the state machine 12 and the shift register 11 in the control module 10.

[0077] In this embodiment, referring to FIG1, after the chip 100 is powered on, the reset module 60 sends a reset signal RST to the control module 10. Upon receiving the reset signal RST, the state machine 12 defaults to a read state. Then, based on the control of the second clock signal, it generates a read waveform and sends it to the electronic fuse 20. The electronic fuse 20 reads the programming result based on the read waveform. Thus, the control module 10 can automatically read the programming result from the electronic fuse 20 after power-on. Therefore, the chip can be used directly after leaving the factory without any configuration. Simultaneously, the shift register 11 is connected to the data bus 40, which can transmit the stored programming result to devices such as the module to be calibrated via the data bus 40 for debugging and calibration of the module to be calibrated.

[0078] In this embodiment of the present disclosure, referring to FIG1, after state machine 12 reads the data in electronic fuse 20 based on reset signal RST, state machine 12 can automatically jump to serial control mode. At this time, control module 10 can stop generating clock control signals and enable signals, and shut down clock generation module 50. In this way, neither state machine 12 nor shift register 11 receives clock signals, and state machine 12 and shift register 11 do not work, thereby further reducing power consumption.

[0079] In some embodiments of this disclosure, referring to FIG1, chip 100 further includes a first selector Mux1. Control module 10 is also configured to generate an enable signal based on a reset signal. The first selector Mux1, connected to control module 10, is configured to receive the enable signal, a first clock signal, and a second clock signal, and is configured to select one of the first and second clock signals for transmission based on the enable signal. The enable signal can be transmitted from control module 10 to the first selector Mux1 via the "Enable Signal" interface 107 shown in FIG2.

[0080] In the embodiments of this disclosure, referring to FIG1, before the chip leaves the factory, the control module 10 needs to receive a first clock signal to configure the electronic fuse 20. At this time, the control module 10 may not generate an enable signal, or the enable signal generated by the control module 10 may be low. After receiving the enable signal, or receiving a low-level enable signal, the first selector Mux1 transmits the first clock signal to the control module 10. After the chip leaves the factory, the control module 10 may not be able to receive the first clock signal from outside the chip. At this time, the control module 10 may generate an enable signal based on the reset signal RST. The generated enable signal may be high. After receiving the high-level enable signal, the first selector Mux1 transmits the second clock signal generated by the clock generation module 50 to the control module 10.

[0081] Figure 5 is a schematic diagram of an optional chip 100 provided in an embodiment of this disclosure. In Figure 5, the clock generation module 50 includes an oscillator 51, which can conveniently generate a second clock signal. It should be noted that analog signals A and B can also be other signals to be processed by the chip. Furthermore, analog signals A and B can be the same or different, which is not limited here.

[0082] In some embodiments of this disclosure, referring to FIG5, chip 100 further includes a first port 41 and a second port 42, wherein the first port 41 may include the second pin shown in FIG1, and the second port 42 may include the first pin shown in FIG1. ​​The first port 41 and / or the second port 42 are configured to transmit second control information. For example, the second control information may include analog signal A and analog signal B. For example, chip 100 may also include analog devices such as amplifiers, phase shifters, or attenuators, in which case analog signal A or analog signal B may be the input signal of the aforementioned analog device. When the chip is working normally, analog signal A or analog signal B is input to the input terminal of the analog device, and the analog device performs amplification, phase shifting, or attenuation processing on analog signal A or analog signal B.

[0083] Analog signal A can be transmitted to the inside of chip 100 through the first port 41, and analog signal B can be transmitted to the inside of chip 100 through the second port 42. In this embodiment of the present disclosure, referring to FIG5, the first port 41 is connected to the state machine 12 and the shift register 11, respectively. The first port 41 is configured to send an external first clock signal to the state machine 12 and the shift register 11. For example, the structure of the first port 41 can be understood with reference to FIG6. The first port 41 includes a second pin PAD1, through which the first clock signal from outside the chip can be received and transmitted to the state machine 12 and the shift register 11.

[0084] The second port 42 is connected to the shift register 11. The second port 42 is configured to send first control information and the data to be programmed to the shift register. For example, the structure of the second port 42 can be understood with reference to Figure 7. The second port 42 includes a first pin PAD2, through which it receives the first control information and the programming data, and transmits the first control information and programming data to the shift register 11. The second port 42 can also receive the programming result of the data to be programmed and transmit the programming result from the first pin PAD2 to a host computer outside the chip.

[0085] This embodiment utilizes the first port 41 and the second port 42, as well as the pins of the first port 41 and the second port 42, to receive the second control information. Furthermore, the pins of the first port 41 and the second port 42 can also be used to transmit the first clock signal, the first control information, and the data to be programmed required for configuring the electronic fuse 20. In other words, this embodiment can reuse the pins for transmitting the second control information to configure the electronic fuse 20. Therefore, this embodiment does not require additional pins to transmit the data for configuring the electronic fuse 20, further saving pin resources and improving integration.

[0086] In some embodiments of this disclosure, referring to FIG5, the first port 41 is further configured to receive a multiplexing control signal and select one of a first clock signal and a second control information for transmission based on the multiplexing control signal. For example, as shown in FIG6, the first port 41 may include a selector Mux2. The selector Mux2 selects one of the first clock signal and the second control information for transmission based on the level of the multiplexing control signal. Before the chip leaves the factory, the multiplexing control signal can be low, and the first port 41 can send the first clock signal to the control module 10. After the chip leaves the factory, the multiplexing control signal can be high, and the first port 41 can send analog signal A to other devices such as the calibration module 30. Thus, embodiments of this disclosure can multiplex the first port 41 and the second pin PAD1, further saving pin resources and improving integration.

[0087] In this embodiment of the present disclosure, referring to FIG5, the second port 42 is further configured to receive a multiplexed control signal and select one of the first control information and the second control information for transmission based on the multiplexed control signal. For example, as shown in FIG7, the second port 42 may include a selector Mux3. The selector Mux3 selects one of the first control information and the second control information for transmission based on the level of the multiplexed control signal. Before the chip leaves the factory, the multiplexed control signal can be low, and the second port 42 can send a first clock signal and the data to be programmed to the shift register 11. After the chip leaves the factory, the multiplexed control signal can be high, and the second port 42 can send an analog signal B to other devices such as the calibration module 30. Thus, this embodiment of the present disclosure can multiplex the second port 42 and the first pin PAD2, further saving pin resources and improving integration.

[0088] Figure 8 is a schematic diagram of an optional serial control circuit 100 provided in an embodiment of this disclosure.

[0089] In some embodiments of this disclosure, referring to FIG8, chip 100 further includes a control pin PAD5 (incorrect labeling). Control pin PAD5 is connected to a first port 41 and a second port 42, respectively. Control pin PAD5 is configured to send multiplexed control signals to the first port 41 and the second port 42.

[0090] In this embodiment of the present disclosure, referring to FIG8, before the chip leaves the factory, the control module 10 needs to receive a first clock signal, first control information, and data to be programmed from outside the chip to configure the electronic fuse 20. At this time, the host computer outside the chip can transmit a multiplexed control signal to the first port 41 and the second port 42 through the control pin PAD5. The multiplexed control signal can be high level. After receiving the high level multiplexed control signal, the selector in the first port 41 receives the first clock signal, and after receiving the high level multiplexed control signal, the selector in the second port 42 receives the first control information and data to be programmed.

[0091] In this embodiment of the present disclosure, referring to FIG8, after the chip leaves the factory, the chip 100 needs to transmit second control information from outside the chip through the first port 41 and / or the second port 42. At this time, the host computer outside the chip can transmit a low-level multiplexed control signal to the first port 41 and the second port 42 through the control pin PAD5. After the selector in the first port 41 and / or the second port 42 receives the low-level multiplexed control signal or does not receive the multiplexed control signal, it transmits the second control signal from outside the chip to the calibration module 30. That is to say, compared with the related technology scheme of configuring the electronic fuse 20 through the serial peripheral interface or the I2C interface, the embodiment of the present disclosure only needs to add a control pin PAD5 for transmitting multiplexed control signals to configure the electronic fuse 20. Thus, it is possible to further save pin resources and improve integration.

[0092] Figure 9 is a schematic diagram of another optional serial control circuit 100 provided in this embodiment. It should be noted that Bit0-BitN shown in Figure 9 can each correspond to an electronic fuse. The first port 41 and the second port 42 share the electronic fuse corresponding to BitX. Furthermore, the electronic fuse corresponding to BitX is used to solidify the multiplexing control signal, and the remaining electronic fuses can solidify debugging and calibration data. Multiple electronic fuses can also be used to solidify the multiplexing control signal, and the first port 41 and the second port 42 can each correspond to an electronic fuse; this is not a limitation.

[0093] In some embodiments of this disclosure, referring to FIG9, the electronic fuse 20 is also configured to store multiplexed control signals. The first port 41 and the second port 42 are both connected to the electronic fuse 20 and configured to receive multiplexed control signals from the electronic fuse 20.

[0094] In this embodiment of the disclosure, referring to FIG9, the data to be programmed may further include a reset control signal. The electronic fuse 20 may reserve one or more electronic fuses to program the multiplexed control signal. For example, the electronic fuse corresponding to BitX in the electronic fuse 20 may be used to store the multiplexed control signal. After chip testing is completed and the data used for debugging and calibration has been solidified into the electronic fuse 20, the state machine 12 may blow the electronic fuse corresponding to BitX.

[0095] Thus, before the chip leaves the factory, the electronic fuse corresponding to BitX is not blown, and the corresponding voltage level is high. The first port 41 and the second port 42 can receive the first clock signal, the first control information, and the data to be programmed from outside the chip to configure the electronic fuse 20. After the chip leaves the factory, since the electronic fuse corresponding to BitX is blown, the corresponding voltage level is high, and the first port 41 and the second port 42 can receive the second control information from outside the chip. Therefore, this disclosure does not require setting a pin for transmitting multiplexed control signals, thereby further saving pin resources and improving integration. Figure 10 is an optional flowchart illustrating the configuration method of the electronic fuse provided in an embodiment of this disclosure. This configuration method can be used to operate the chip 100 described above, and this configuration method can be executed by a host computer program.

[0096] S101. After receiving the first control information and the data to be programmed from the outside through the same pin, the data is temporarily stored in the shift register. The first control information is used to determine the operation state of the electronic fuse. The operation state includes programming state, reading state, and serial control state.

[0097] In this embodiment of the disclosure, as illustrated in FIG9, before the chip leaves the factory, the host computer can configure the electronic fuse 20 through the state machine 12 and shift register 11 in the control circuit 10, and solidify some debugging and calibration data into the electronic fuse 20. Then, the electronic fuse 20 can send the solidified debugging and calibration data to the module to be calibrated 30 to calibrate the module to be calibrated.

[0098] Specifically, shift register 11 can obtain a first clock signal from outside the chip via the first port 41 to receive first control information and data to be programmed from the outside. The first port 41 may include another pin (e.g., a second pin). Shift register 11 can serve as a data exchange medium between the outside and inside of the chip. Before the chip leaves the factory, shift register 11 can receive the first control information and data to be programmed from the second port 42 and temporarily store the external first control information and data to be programmed. The second port 42 includes a first pin, which is the same pin shared by the first control information and the data to be programmed.

[0099] S102. In serial control mode, the first control information and the data to be burned are temporarily stored in a clock counting cycle. The clock counting cycle is an integer multiple of the number of bits in the shift register.

[0100] Referring to Figure 9, when chip 100 is not being programmed or read, state machine 12 remains in serial control state. Before the chip leaves the factory, state machine 12 obtains the first control information and the data to be programmed from shift register 11 at clock count cycles to correctly distinguish between the first control information and the data to be programmed, thereby determining whether to enter programming state or reading state based on the first control information.

[0101] S103. In the writing state, the temporarily stored data to be written is parsed and written to the electronic fuse.

[0102] This analysis can be performed using a state machine, which is used to determine whether to transition from the serial control state to the programming state or the reading state. Referring to Figure 9, in some embodiments, when the first control information indicates entry into the programming state, the state machine 12, triggered by the first control information and the first clock signal, enters the programming state and generates the corresponding programming waveform. The electronic fuse 20, based on the received programming waveform and the data to be programmed, programs the corresponding electronic fuse, completing the solidification of the data to be programmed.

[0103] S104. In the read state, the writing result of the electronic fuse is parsed, read, and stored in the shift register.

[0104] Referring to Figure 9, when the first control information indicates entry into the read state, state machine 12 also enters the read state based on the triggering of the first control information and the first clock signal, generating a corresponding read waveform. Based on the received read waveform, electronic fuse 20 reads the read result of the data to be written and transmits it to shift register 11 via state machine 12. State machine 12 can output the writing result to the host computer outside the chip via the output data signal SDO interface of shift register 11. The host computer program can monitor whether the data in shift register 11 meets expectations by comparing the writing result with the data to be written, and thus determine whether electronic fuse 20 has been successfully written.

[0105] In some embodiments, after the programming or reading state is completed, the system automatically returns to the serial control state. Alternatively, after the programming state is completed, the system automatically transitions to the reading state.

[0106] S105. Based on the reset signal, the burning result of the electronic fuse is read and stored in the shift register.

[0107] In this embodiment of the disclosure, referring to FIG9, after the chip leaves the factory, it is generally desirable to enable the chip 100 to perform automatic calibration directly without any configuration after power-on. Therefore, when the chip 100 is powered on after leaving the factory, the chip 100 generates a reset signal. Based on the reset signal, the state machine 12 reads the programming result of the electronic fuse 20 and stores it in the shift register 11. Thus, the data stored in the shift register 11 can be used directly for calibration. For example, the programming result stored in the shift register 11 can be output to the module 30 to be calibrated for calibration.

[0108] Specifically, the power-on reset module 60 can automatically generate a reset signal RST after the chip is powered on. After the chip is powered on, the control module 10 can generate an enable signal and a clock control signal based on the reset signal RST. Then, the clock generation module 50 can generate a second clock signal based on the triggering of the clock control signal. The first selector Mux1 can transmit the second clock signal to the state machine 12 and shift register 11 in the control module 10 under the triggering of the enable signal. In some embodiments, the enable signal can reuse the clock control signal, that is, the clock control signal can be reused to trigger the first selector Mux1. Based on the second clock signal, the writing result of the data to be written is read from the electronic fuse and stored in the shift register.

[0109] In this embodiment of the present disclosure, referring to FIG9, after the state machine 12 receives the reset signal RST, it enters the read state, automatically jumps to the read mode, generates a read waveform, and sends it to the electronic fuse 20. Then, the state machine 12 reads the data stored in the electronic fuse 20 and stores it in the shift register 11.

[0110] Furthermore, after state machine 12 reads the data from electronic fuse 20 based on the reset signal RST, state machine 12 can automatically jump to serial control mode. At this time, control module 10 can stop generating clock control signals and enable signals, and shut down clock generation module 50. Shift register 11 can output the data inside shift register 11 to the calibration module 30 inside the chip in real time or in parallel according to the clock count result, to achieve the purpose of debugging and calibration.

[0111] Referring to Figure 9, after the chip leaves the factory, analog signals can be provided to the chip 100 through the first port 41 and / or the second port 42, thereby reusing the pins in the first port 41 and the pins in the second port 42 to further save the chip's pin resources.

[0112] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0113] In some embodiments, the chip includes: a state machine, the states of which include a programming state, a read state, and a serial control state; a shift register configured to receive and temporarily store first control information and data to be programmed externally, and configured to receive, store, and output programming results; wherein the first control information is used to control the state machine to enter the programming state or the read state; a first pin through which the shift register receives the first control information sent externally; the state machine is configured to: in the serial control state, acquire the first control information and the data to be programmed from the shift register at clock counting cycles, the clock counting cycle being an integer multiple of the number of bits in the shift register; in the programming state, write the data to be programmed in the shift register into an electronic fuse; and in the read state, read the programming result of the electronic fuse and store it in the shift register. Before the chip leaves the factory: in serial control mode, it acquires first control information and data to be programmed from a shift register at clock count cycles; in programming mode, it writes the data to be programmed from the shift register to an electronic fuse; in read mode, it reads the programming result from the electronic fuse and stores it in the shift register. After the chip leaves the factory, it can be directly calibrated using the programming result from the electronic fuse. The chip does not require dedicated decoders or other devices to parse the first control information and the data to be programmed, thus reducing chip area and increasing integration density.

[0114] In some embodiments, the chip includes: a state machine, the states of which include a programming state, a read state, and a serial control state; a shift register configured to receive and temporarily store first control information and data to be programmed sent externally, and configured to receive, store, and output programming results; wherein the first control information is used to control the state machine to enter the programming state or the read state; a first pin through which the shift register receives the first control information sent externally; the state machine is configured to: in the serial control state, obtain the first control information and the data to be programmed from the shift register, wherein the clock counting period is an integer multiple of the number of bits in the shift register; in the programming state, write the data to be programmed in the shift register into an electronic fuse; in the read state, read the programming result of the electronic fuse and store it in the shift register; and based on a reset signal, read the programming result of the electronic fuse and store it in the shift register. Before the chip leaves the factory: it can receive externally transmitted first control information and data to be programmed using the SPI interface (including the first pin); and the decoder of the SPI interface can distinguish between the first control information and the data to be programmed; the state machine controls the programming or reading of the electronic fuse based on the decoded content. After the chip leaves the factory, the programming result of the electronic fuse can be read and stored in the shift register based on the reset signal. Therefore, the programming result stored in the shift register can be used for calibration after the chip is powered on, without directly using the data stored in the electronic fuse for calibration. The electronic fuse does not need to be kept in a working state all the time, which can avoid damage to the electronic fuse due to long-term operation.

[0115] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A chip (100) with a configured electronic fuse (20), characterized in that, include: The state machine (12) includes a burning state, a reading state, and a serial control state. The shift register (11) is configured to receive and temporarily store the first control information and the data to be burned sent from the outside, and is configured to receive, store and output the burning result; wherein, the first control information is used to control the state machine (12) to enter the burning state or the reading state; The shift register (11) receives the first control information sent from the outside through the first pin (PAD2); The state machine (12) is configured as follows: In the serial control state, the first control information and the data to be programmed are obtained from the shift register (11) in a clock counting cycle, wherein the clock counting cycle is an integer multiple of the number of bits in the shift register (11); In the programming state, the data to be programmed in the shift register (11) is written into the electronic fuse (20); In the read state, the writing result of the electronic fuse (20) is read and stored in the shift register (11); Based on the reset signal, the burning result of the electronic fuse (20) is read and stored in the shift register (11).

2. The chip (100) according to claim 1, characterized in that The chip (100) further includes: a calibration module (30); wherein, The shift register (11) is connected to the module to be calibrated (30) and is configured to output the programming result to the module to be calibrated (30).

3. The chip (100) according to claim 2, characterized in that The chip (100) further includes: a data bus (40); the shift register (11) includes: a first register unit (110) and a second register unit (111); wherein, The first register unit (110), connected to the state machine (12), is configured to transmit the first control information to the state machine (12); The second register unit (111) is connected to the state machine (12) and the data bus (40) respectively, and is configured to transmit the data to be programmed to the state machine (12) and output the programming result to the calibration module (30) through the data bus (40).

4. The chip (100) according to claim 3, characterized in that The shift register (11) is transmitted serially to the first pin (PAD2), and the shift register (11) is transmitted in parallel to the state machine (12) or the data bus (40).

5. The chip (100) according to any one of claims 1 to 4, characterized in that The chip (100) further includes: a first port (41) and / or a second port (42); wherein, The first port (41) is used to send a first clock signal from outside the chip (100) to the state machine (12) and the shift register (11). The first port (41) includes a second pin (PAD1). The second port (42) is used to send the first control information and the data to be programmed to the shift register (11). The second port (42) includes the first pin (PAD2). The first port (41) and / or the second port (42) are also configured to transmit second control information, which is an analog signal provided by the chip (100) to the chip (100) when it is in operation.

6. The chip (100) according to claim 5, characterized in that, The first port (41) is also configured to receive a multiplexing control signal and, based on the multiplexing control signal, select one of the first clock signal and the second control information for transmission; and / or, The second port (42) is also configured to receive the multiplexing control signal and select one of the first control information and the second control information for transmission based on the multiplexing control signal.

7. The chip (100) according to claim 6, characterized in that The electronic fuse (20) stores the multiplexed control signal; The first port (41) or the second port (42) obtains the multiplexing control signal from the electronic fuse (20).

8. The chip (100) according to claim 6, characterized in that The chip (100) also includes a control pin (PAD5); The control pin (PAD5) sends the multiplexed control signal to the first port (41) and / or the second port (42).

9. The chip (100) according to any one of claims 1 to 4, characterized in that Also includes: The power-on reset module (60) is configured to generate the reset signal after the chip (100) is powered on; The state machine (12) is also configured to enter the read state from the serial control state based on the reset signal.

10. The chip (100) according to claim 9, characterized in that Also includes: A clock generation module (50) is used to generate a second clock signal; The state machine (12) is also configured to generate a clock control signal based on the reset signal; The clock generation module (50) is further configured to generate the second clock signal after receiving the clock control signal; The state machine (12) is also configured to shut down the clock generation module (50) after storing the programming result in the shift register (11).

11. The chip (100) according to claim 10, characterized in that The chip (100) further includes: a first selector; wherein, The state machine (12) is also configured to generate an enable signal based on the reset signal; The first selector, connected to the state machine (12), is configured to receive the enable signal, the second clock signal and an external first clock signal, and is configured to select one of the first clock signal and the second clock signal based on the enable signal to transmit to the state machine (12) and the shift register (11).

12. A method of configuring an electronic fuse (20), characterized by, include: After receiving the first control information and the data to be programmed from the outside through the same pin, the data is temporarily stored in the shift register (11); wherein, the first control information is used to determine the operation state of the electronic fuse (20), and the operation state includes programming state, reading state, and serial control state; In serial control mode, the temporarily stored first control information and the data to be burned are acquired in clock counting cycles; the clock counting cycle is an integer multiple of the number of bits of the shift register (11); In the burning state, the temporarily stored data to be burned is parsed and written into the electronic fuse (20); In the read state, the writing result of the electronic fuse (20) is parsed, read, and stored in the shift register (11); Based on the reset signal, the burning result of the electronic fuse (20) is read and stored in the shift register (11).

13. The configuration method of claim 12, wherein, The burning result stored in the shift register (11) is output to the calibration module (30).

14. The configuration method according to claim 12 or 13, characterized in that, The analysis is performed through a state machine (12).

15. The configuration method of claim 12, wherein, Also includes: Configure a clock signal, wherein the clock signal includes a second clock signal and a first clock signal; The second clock signal comes from the chip (100) where the electronic fuse (20) is located, and the first clock signal comes from outside the chip (100) where the electronic fuse (20) is located; During the programming state, the first clock signal is selected as the clock signal for the configuration method; During the read state, the first clock signal is selected as the clock signal for the configuration method; When the chip (100) is reset, the second clock signal is selected as the clock signal for the configuration method.

16. The configuration method of claim 15, wherein, Also includes: The first clock signal is received through another pin.

17. The configuration method of claim 16, wherein, Also includes: Analog signals are received in a time-division manner via the pin or the other pin.

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