Array substrate, display panel, and display device

Abstract

An array substrate, comprising a first conductive layer (20), a buffer layer, a semiconductor layer (30), a gate insulating layer, and a second conductive layer (40) which are arranged in a direction moving away from a base (10). The first conductive layer (20) comprises a plurality of data signal lines (21), wherein the plurality of data signal lines (21) are distributed at intervals in a first direction and extend in a second direction. The semiconductor layer (30) is located on the side of the buffer layer distant from the base (10), and comprises a semiconductor pattern (31). The semiconductor pattern (31) comprises a channel portion (32), and a first electrode portion (33) and a second electrode portion (34) located on two sides of the channel portion (32). The gate insulating layer comprises a first pattern (11). The second conductive layer (40) comprises at least two of a source pattern (41), a drain pattern (42), and a gate pattern (43). The source pattern (41) is separately electrically connected to the first electrode portion (33) and a data signal line (21), and the drain pattern (42) comprises a first boundary (421) close to a first data signal line (211). The first pattern (11) comprises a first opening (12). The first opening (12) is located on the side of the first boundary (421) distant from the first data signal line (211) and coincides with at least part of the boundary of the drain pattern (42).

Description

Array substrate, display panel and display device

[0001] This application claims priority to international patent application No. PCT / CN2024 / 124923, filed on October 15, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0003] With the continuous development of display technology, display panels have been widely used, and people's requirements for display panels are becoming increasingly demanding. Among these, high pixel density (Pixels Per Inch, or PPI) is an important development direction for display panels. Common display panels include Liquid Crystal Display (LCD) panels and Organic Light-Emitting Diode (OLED) panels. Thanks to the simpler pixel circuit structure of LCD panels (which can contain fewer thin-film transistors and capacitors), LCD panels have a greater advantage in ultra-high pixel densities (such as greater than or equal to 200 PPI). As pixel density increases, the risk of pixel circuit interference (signal crosstalk) increases. How to improve the stability of pixel circuits is a crucial technical problem faced in further increasing the pixel density of LCD panels. Summary of the Invention

[0004] On one hand, an array substrate is provided. The array substrate may include a substrate, a first conductive layer, a buffer layer, a semiconductor layer, a gate insulating layer, and a second conductive layer. The first conductive layer is located on one side of the substrate and includes a plurality of data signal lines, which are spaced apart along a first direction and extend along a second direction. The buffer layer is located on the side of the first conductive layer away from the substrate. The semiconductor layer is located on the side of the buffer layer away from the substrate, and includes a semiconductor pattern, which includes a channel portion and a first electrode portion and a second electrode portion located on both sides of the channel portion. The gate insulating layer is located on the side of the semiconductor layer away from the substrate and includes a first pattern. The second conductive layer is located on the side of the gate insulating layer away from the substrate and includes at least two of a source pattern, a drain pattern, and a gate pattern. The source pattern is electrically connected to the first electrode portion and the data signal lines, respectively, and the drain pattern includes a first boundary near the first data signal line. The array substrate further includes a first transistor, which includes the semiconductor pattern, the gate pattern, the source pattern, and the drain pattern. The first pattern is at least partially located between the drain pattern and the second electrode portion, and includes a first opening. The first opening is located on the side of the first boundary away from the first data signal line and coincides with at least a portion of the boundary of the drain pattern; the drain pattern is connected to the second electrode portion through the first opening. The first data signal line is the one of the plurality of data signal lines that is closest to the second electrode portion. The first direction and the second direction intersect each other.

[0005] In some embodiments, the second conductive layer further includes a scan signal line extending along the first direction, and the gate pattern is connected to the scan signal line. The first electrode portion and the second electrode portion of the semiconductor pattern are located on the same side of the scan signal line along the second direction. The drain pattern further includes a second boundary along the second direction away from the scan signal line, and a third boundary along the first direction near the channel portion. The first opening at least partially coincides with the second boundary and / or the third boundary.

[0006] In some embodiments, the second electrode portion includes a first sub-portion and a second sub-portion, the first sub-portion extending along the first direction, the second sub-portion located on the side of the first sub-portion away from the scan signal line along the second direction, and connected to the end of the first sub-portion near the first data signal line.

[0007] In some embodiments, the corner of the first sub-section near the scan signal line and near the first data signal line includes a second opening. At least a portion of the drain pattern is located within the second opening.

[0008] In some embodiments, the second conductive layer further includes a scan signal line extending along the first direction, and the gate pattern is connected to the scan signal line. The first electrode portion and the second electrode portion of the semiconductor pattern are located on the same side of the scan signal line along the second direction; the drain pattern further includes a fourth boundary along the second direction near the scan signal line, and a third boundary along the first direction near the channel portion. The first opening at least partially coincides with the third boundary and / or the fourth boundary.

[0009] In some embodiments, the second electrode portion extends along the first direction. At least a portion of the drain pattern is located on the side of the second electrode portion away from the scan signal line along the second direction.

[0010] In some embodiments, the distance between the boundary of the drain pattern coinciding with the first opening and the boundary of the second electrode portion away from the drain pattern is greater than or equal to 1.5 μm.

[0011] In some embodiments, the data signal line includes a widened portion, at least a portion of which protrudes along the first direction toward a side away from the channel portion. The array substrate further includes a first via penetrating the gate insulating layer and the buffer layer, and exposing at least a portion of the widened portion. The source pattern is electrically connected to the widened portion through the first via. The side of the widened portion away from the channel portion includes at least one chamfer, and / or, the side of the source pattern away from the channel portion includes at least one chamfer.

[0012] In some embodiments, the angle between the extension direction of the chamfer boundary and the first direction is 45°, and the dimension of the chamfer along the first direction is 1μm to 2μm.

[0013] In some embodiments, the second conductive layer further includes scan signal lines extending along the first direction. The first electrode portion and the second electrode portion of the semiconductor pattern are respectively located on opposite sides of the scan signal lines along the second direction. At least a portion of the second electrode portion coincides with the centerline of two adjacent data signal lines along the first direction.

[0014] In some embodiments, the drain pattern extends along the first direction, and the drain pattern further includes a fifth boundary along the second direction adjacent to the scan signal line, a sixth boundary along the second direction away from the scan signal line, and a seventh boundary along the first direction away from the first data signal line. The first opening at least partially coincides with the fifth boundary and / or the sixth boundary, but does not coincide with the seventh boundary.

[0015] In some embodiments, the array substrate further includes a first passivation layer, a planarization layer, a first electrode layer, a second passivation layer, a second electrode layer, and a third via. The first passivation layer is located on the side of the second conductive layer away from the substrate. The planarization layer is located on the side of the first passivation layer away from the substrate. The first passivation layer includes a second via, the orthographic projection of the second via onto the substrate at least partially overlapping the orthographic projection of the drain pattern onto the substrate. The first electrode layer is located on the side of the planarization layer away from the substrate. The second passivation layer is located on the side of the first electrode layer away from the substrate. The third via penetrates the second passivation layer and the first passivation layer, exposing at least a portion of the drain pattern and the second electrode portion, the orthographic projection of the third via onto the substrate being within the range of the orthographic projection of the second via onto the substrate. The second electrode layer is located on the side of the second passivation layer away from the substrate, and the second electrode layer is electrically connected to the drain pattern and the second electrode portion respectively through the third via. The orthographic projections of the second via and the third via onto the substrate at least partially overlap with the orthographic projection of the first opening onto the substrate.

[0016] In some embodiments, the drain pattern includes a third sub-section and a fourth sub-section. The third sub-section extends along the first direction, and the fourth sub-section is located on the side of the third sub-section closer to the scan signal line along the second direction and connected to the end of the third sub-section closer to the first data signal line. The third sub-section includes an eighth boundary along the second direction closer to the scan signal line, a ninth boundary along the second direction farther from the scan signal line, and a tenth boundary along the first direction farther from the first data signal line. The first opening at least partially coincides with the eighth boundary and / or the ninth boundary, but does not coincide with the tenth boundary.

[0017] In some embodiments, the array substrate further includes a first passivation layer, a planarization layer, a first electrode layer, a second passivation layer, a second electrode layer, and a third via. The first passivation layer is located on the side of the second conductive layer away from the substrate. The planarization layer is located on the side of the first passivation layer away from the substrate, and the planarization layer includes a second via. The orthographic projection of the second via onto the substrate at least partially coincides with the orthographic projection of the fourth sub-part onto the substrate. The first electrode layer is located on the side of the planarization layer away from the substrate. The second passivation layer is located on the side of the first electrode layer away from the substrate. The third via penetrates the second passivation layer and the first passivation layer, and exposes at least a portion of the fourth sub-part. The orthographic projection of the third via onto the substrate is within the range of the orthographic projection of the second via onto the substrate. The second electrode layer is located on the side of the second passivation layer away from the substrate, and the second electrode layer is electrically connected to the fourth sub-part through the third via. The orthographic projection of the second via onto the substrate does not coincide with the orthographic projection of the first opening onto the substrate.

[0018] In some embodiments, the second conductive layer further includes a plurality of scan signal lines, which are spaced apart along the second direction and extend along the first direction. The orthogonal projections of the scan signal lines and the data signal lines on the substrate intersect to form a grid structure, with each grid defining a pixel region. The array substrate further includes an etch stop layer located on the side of the buffer layer away from the substrate and in contact with the buffer layer. The etch stop layer has a different etch selectivity than the gate insulating layer. The etch stop layer covers at least a portion of the pixel region and does not coincide with the semiconductor pattern.

[0019] In some embodiments, the etch barrier layer and the semiconductor layer comprise the same material and are disposed in the same layer.

[0020] In some embodiments, the etch barrier layer comprises a transparent conductive material; and / or, the semiconductor layer comprises a semiconductor material.

[0021] In some embodiments, the etch barrier layer includes a plurality of etch barrier patterns, one of the barrier patterns being located within one of the pixel regions.

[0022] In some embodiments, the array substrate includes a display area and a peripheral area surrounding the display area. The etch stop layer includes a plurality of etch stop strips, one of which passes through a row of pixel areas arranged along the first direction and extends into the peripheral area.

[0023] In some embodiments, the etching barrier is electrically connected to a constant voltage signal terminal.

[0024] In some embodiments, the array substrate further includes a first electrode layer and a second electrode layer. The first electrode layer is located on the side of the second conductive layer away from the substrate. The second electrode layer is located on the side of the first electrode layer away from the substrate, and the second electrode layer is electrically connected to the drain pattern. The etch stop bar and the first electrode layer are configured to transmit the same voltage signal.

[0025] On the other hand, a display panel is provided, comprising an array substrate, a color filter substrate, and a liquid crystal layer as described in any of the above embodiments. The color filter substrate is disposed opposite to the array substrate, and the liquid crystal layer is disposed between the color filter substrate and the array substrate.

[0026] In another aspect, a display device is provided. The display device may include the aforementioned display panel and backlight module. The backlight module is disposed on the backlight side of the display panel. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0028] Figure 1 is a schematic diagram of the structure of a display device according to some embodiments;

[0029] Figure 2 is a structural diagram of a display device according to some embodiments;

[0030] Figure 3 is a schematic diagram of a planar structure of an array substrate according to some embodiments;

[0031] Figure 4 is a planar structural diagram of an array substrate according to some embodiments;

[0032] Figure 5 is another planar structure diagram of the array substrate according to some embodiments;

[0033] Figure 6 is a partial enlarged view of the first transistor T1 in region A1 of Figure 4;

[0034] Figure 7 is a cross-sectional view of section line B1-B1 in Figure 6;

[0035] Figure 8 is a structural diagram of a first pattern and a drain pattern according to some embodiments;

[0036] Figure 9 is another structural diagram of the first pattern and the drain pattern according to some embodiments;

[0037] Figure 10 is another enlarged view of the first transistor T1 in region A1 of Figure 4;

[0038] Figure 11 is a structural diagram of a semiconductor pattern according to some embodiments;

[0039] Figure 12 is another enlarged view of the first transistor T1 in region A1 of Figure 4;

[0040] Figure 13 is another structural diagram of the first pattern and the drain pattern according to some embodiments;

[0041] Figure 14 is another enlarged view of the first transistor T1 in region A1 of Figure 4;

[0042] Figure 15 is another planar structural diagram of the first transistor T1 according to some embodiments;

[0043] Figure 16 is another planar structural diagram of the first transistor T1 according to some embodiments;

[0044] Figure 17 is another planar structure diagram of the array substrate according to some embodiments;

[0045] Figure 18 is a cross-sectional view of section lines B2-B2 and B3-B3 in Figure 17;

[0046] Figure 19 is another planar structure diagram of an array substrate according to some embodiments. Detailed Implementation

[0047] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0048] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0049] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0050] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0051] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0052] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0053] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0054] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0055] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0056] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0057] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0058] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0059] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0060] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0061] Referring to FIG1, an embodiment of the present disclosure provides a display device, the display device 1000 being a product having image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0062] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of rearview camera in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, in-vehicle display, flying display, etc.

[0063] In some embodiments, the above-mentioned display device may be a liquid crystal display (LCD). Referring to FIG2, the liquid crystal display device may include a display panel 1100, a backlight module 1200, and a driving circuit board 1300. The display panel 1100 is disposed on the light-emitting side of the backlight module 1200. The driving circuit board 1300 may be electrically connected to the backlight module 1200 and the display panel 1100 respectively. The driving circuit board 1300 may be used to transmit control signals to the backlight module 1200 and the display panel 1100 to control the backlight module 1200 to emit light and to control the display panel 1100 to adjust the grayscale of each sub-pixel. In addition, the display device 1000 may also include, but is not limited to, a touch structure, an under-display camera, and an under-display fingerprint recognition sensor, so that the display device 1000 can realize various functions such as touch, photography, video recording, or fingerprint recognition, which will not be listed here.

[0064] Referring to Figure 2, the driver circuit board 1300 may include, for example, a timing controller (TCON), a power management chip (DC / DC), a gate driver chip, and an adjustable resistor voltage divider circuit (generating Vcom). Of course, the driver circuit board 1300 may also include other circuit structures, which will not be listed here. The driver circuit board 1300 may be located on the side of the backlight module 1200 away from the display panel 1100, or it may be at least partially located on the side of the backlight module 1200. The position of the driver circuit board 1300 shown in the figure is only one example.

[0065] The backlight module 1200 can be a direct-lit backlight module 1200 or an edge-lit backlight module 1200, wherein the backlight module 1200 is used to emit light and provide a light source for the display panel 1100. Exemplarily, the driving circuit board 1300 can control the brightness of the backlight module 1200 and the grayscale of each sub-pixel in the display panel. In one example, the backlight module 1200 may include multiple light-emitting chips, which can be light-emitting diodes, such as mini-LEDs or micro-LEDs, where the size of a mini-LED is approximately 100μm to 300μm and the size of a micro-LED is approximately less than 100μm. Of course, the type of light-emitting chip is not limited to these, and any other suitable light-emitting chip can be used.

[0066] Referring again to Figure 2, the display panel 1100 may include an array substrate 100 and a color filter substrate 200 disposed opposite to each other, and a liquid crystal layer 300 located between the array substrate 100 and the color filter substrate 200. The color filter substrate 200 may include a black matrix and a color filter layer. The color filter layer may include at least two different color filters to enable the display panel to display in color; for example, the color filter layer may include a red filter, a blue filter, and a green filter. Of course, the structure of the display panel 1100 is not limited to this; the display panel 1100 may also include other structures, as long as the same technical concept is adopted. For example, the display panel 1100 may also include a first alignment film disposed on the side of the array substrate 100 near the liquid crystal layer 300, and a second alignment film disposed on the side of the color filter substrate 200 near the liquid crystal layer 300, etc.

[0067] Referring to Figure 3, the array substrate 100 may include a display area AA and a peripheral area BB located on at least one side of the display area AA. Exemplarily, the peripheral area BB may be disposed around the display area AA. The display area AA refers to the area of ​​the array substrate 100 in the display panel that is actually used to display images. Exemplarily, the display area AA may include a plurality of sub-pixels P arranged in an array, where each sub-pixel P is the smallest light-emitting unit of the display panel. The peripheral area BB refers to the area of ​​the array substrate 100 in the display panel where various circuits (including but not limited to gate drive circuit 110 and source drive circuit 120) and signal lines (including but not limited to clock signal lines and power supply voltage signal lines) are disposed to transmit control signals to the display area. Of course, the structure and function of the peripheral area BB are not limited to this, and will not be listed here. To increase the transparency of the display panel, opaque or light-blocking components of the display device (including but not limited to batteries, printed circuit boards, and metal frames) may be arranged in the peripheral area BB instead of the display area AA.

[0068] Multiple sub-pixels P are arranged in an array in the display area AA, and are arranged in rows along the first direction X. The display panel 1100 includes multiple rows of sub-pixels P, and the multiple sub-pixels P are arranged in rows along the second direction Y. The display panel 1100 includes multiple columns of sub-pixels P. The first direction Y intersects with the second direction X, for example, the first direction Y and the second direction X are perpendicular to each other. Sub-pixels P may include pixel circuits, pixel electrodes, and common electrodes. The pixel circuit may include at least one thin-film transistor (TFT) and a storage capacitor. For example, the pixel circuit may include a first transistor, and a storage capacitor may be formed between the pixel electrode and the common electrode.

[0069] Referring to Figures 4 to 8, in some embodiments, the array substrate 100 may include a substrate 10, and a first conductive layer 20, a buffer layer BUF, a semiconductor layer 30, a gate insulating layer GI, and a second conductive layer 40 disposed along a direction perpendicular to and away from the substrate 10 (from bottom to top in Figure 7).

[0070] The substrate 10 can be a transparent substrate, such as a glass substrate, so that the light emitted by the backlight module can pass through the substrate 10, which is beneficial to improving the light transmittance of the array substrate 100.

[0071] The first conductive layer 20 is located on one side of the substrate 10 (e.g., the upper side in FIG7). The first conductive layer 20 includes a plurality of data signal lines 21, which are spaced apart along a first direction X and extend generally along a second direction Y. The data signal lines 21 can be configured to transmit data signals.

[0072] The statement that the data signal line 21 extends along the second direction Y means that, from a macroscopic perspective, the data signal line 21 extends along the second direction Y; for example, the line connecting the two ends of the data signal line 21 along the second direction Y can be parallel or approximately parallel to the second direction Y. However, from a microscopic perspective, the extension direction of the data signal line 21 can have a certain angle with the second direction Y. For example, as shown in Figure 4, the extension direction of the data signal line 21 is parallel to the second direction Y; or, as shown in Figure 5, within the range corresponding to the opening area of ​​a row of sub-pixels, the extension direction of the data signal line 21 has a first angle α with the second direction Y. The first angle α can be 5° to 11°. When the first angle is within the range of 5° to 11°, the transmittance and aperture ratio of the array substrate 100 can reach a larger value. For example, the first angle α can be 5° to 8°, such as 5°, 6°, 7.5°, or 8°. Alternatively, by way of example, the first included angle α can be 8° to 11°, for example, the first included angle α can be 8°, 9°, 10° or 11°, etc., and the embodiments disclosed herein will not be listed one by one.

[0073] The buffer layer BUF is located on the side of the first conductive layer 20 away from the substrate 10, for example, the buffer layer BUF is located between the first conductive layer 20 and the semiconductor layer 30. The buffer layer BUF may include an insulating material, so that the buffer layer BUF can be used to separate the first conductive layer 20 and the semiconductor layer 30, preventing short circuits between the first conductive layer 20 and the semiconductor layer 30. In addition, the buffer layer BUF can be a single-layer structure (e.g., a single-layer silicon oxide), a double-layer structure (e.g., a stacked structure formed by silicon nitride and silicon oxide), or a triple-layer structure (e.g., a stacked structure formed by silicon nitride, silicon oxynitride, and silicon oxide). In one embodiment, the buffer layer BUF can be a double-layer structure, and the buffer layer BUF includes a silicon nitride layer and a silicon oxide layer, with the silicon nitride layer located on the side of the silicon oxide layer closer to the substrate 10.

[0074] The semiconductor layer 30 is located on the side of the buffer layer BUF away from the substrate 10. The semiconductor layer 30 can also be referred to as an active layer or a semiconductor material layer. The semiconductor layer 30 includes a semiconductor pattern 31, which includes a channel portion 32 and a first electrode portion 33 and a second electrode portion 34 located on both sides of the channel portion 32. The first electrode portion 33 and the second electrode portion 34 are connected through the channel portion 32. The first electrode portion 33 is used for electrical connection to the data signal line 21, and the second electrode portion 34 is used for electrical connection to the pixel electrode. The channel portion 32 and the first electrode portion 33 and the second electrode portion 34 may include the same semiconductor material. The difference between the channel portion 32 and the first electrode portion 33 and the second electrode portion 34 is that at least a portion of the first electrode portion 33 and the second electrode portion 34 undergoes a process to make them more conductive (a conductor-enhancing process), which includes, but is not limited to, doping and annealing processes. The conductivity of the first electrode portion 33 and the second electrode portion 34 is different from the conductivity of the channel portion 32. For example, the channel portion 32 may include a semiconductor material, and the first electrode portion 33 and the second electrode portion 34 may include doped semiconductor materials.

[0075] The aforementioned semiconductor materials may include metal oxide materials and / or metal oxide nitride materials. Metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In₂O₃:Sn, In₂O₃:Mo, Cd₂SnO₄, ZnO:Al, TiO₂:Nb, and Cd-Sn-O, or one or more of these. Metal oxide nitride materials include, but are not limited to: zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. The material of the semiconductor layer 30 can be amorphous, partially crystalline, single-crystal or polycrystalline. In addition, the semiconductor layer 30 can be a single-layer film structure or a multi-layer film structure.

[0076] As display devices develop towards higher PPI, the spacing between the semiconductor pattern 31 and the adjacent data signal line 21 becomes smaller, and the spacing between the second electrode portion 34 of the semiconductor pattern 31 and the adjacent data signal line 21 (first data signal line 211) also becomes smaller, resulting in an increase in the parasitic capacitance between the second electrode portion 34 and the first data signal line 211. This parasitic capacitance causes signal interference (or signal crosstalk) to the pixel electrode, and the intensity of the signal interference increases with the increase in parasitic capacitance. For example, the "signal interference caused by parasitic capacitance to the pixel electrode" can manifest as follows: when the voltage transmitted on the first data signal line 211 fluctuates, the voltage of the pixel electrode also fluctuates under the influence of the parasitic capacitance. This causes fluctuations in the electric field between the pixel electrode and the common electrode, leading to fluctuations in the grayscale (display brightness) of the sub-pixel. The first data signal line 211 is the one among the multiple data signal lines 21 that is closest to the second electrode portion 34.

[0077] The gate insulating layer GI is located on the side of the semiconductor layer 30 away from the substrate 10. For example, the gate insulating layer GI can be located between the semiconductor layer 30 and the second conductive layer 40.

[0078] The second conductive layer 40 is disposed on the side of the gate insulating layer GI away from the substrate 10. The second conductive layer 40 includes at least two of a source pattern 41, a drain pattern 42, and a gate pattern 43. Exemplarily, the second conductive layer 40 may include a source pattern 41 and a drain pattern 42; or, the second conductive layer 40 may include a drain pattern 42 and a gate pattern 43; or, the second conductive layer 40 may include a drain pattern 42; or, the second conductive layer 40 may include a source pattern 41, a drain pattern 42, and a gate pattern 43. The embodiments disclosed herein will not be listed in detail. When the second conductive layer 40 includes a source pattern 41, the source pattern 41 is electrically connected to the first electrode portion 33 and the data signal line 31, respectively, for electrically connecting the first electrode portion 33 and the data signal line 31. When the second conductive layer 40 includes a drain pattern 42, the drain pattern 42 is used to form the drain of the first transistor T1. When the second conductive layer 40 includes a gate pattern 43, the gate pattern 43 can be used to form the gate of the first transistor T1. The present disclosure will now be described exemplarily using the example of a second conductive layer 40 that simultaneously includes a source pattern 41, a drain pattern 42, and a gate pattern 43.

[0079] In embodiments of this disclosure, the drain pattern 42 includes a first boundary 421 near the first data signal line 211, which is the one among the plurality of data signal lines 21 that is closest to the second electrode portion 34. The gate insulating layer GI includes a first pattern 11, at least a portion of which is located between the drain pattern 42 and the second electrode portion 34. The first pattern 11 includes a first opening 12, which is located on the side of the first boundary 421 away from the first data signal line 211, and the first opening 12 coincides with at least a portion of the boundary of the drain pattern 42. Thus, the drain pattern 42 can contact the lower second electrode portion 34 through the first opening 12, and a conductive channel can be formed between the drain pattern 42 and the second electrode portion 34 at the position where the first opening 12 and the boundary of the drain pattern 42 coincide, thereby achieving an electrical connection between the drain pattern 42 and the second electrode portion 34. To ensure the formation of the aforementioned conductive channel and its connection to the channel portion 33, at least a portion of the second electrode portion 34 must be located outside the boundary where the drain pattern 42 coincides with the first opening 12. In other words, at least a portion of the second electrode portion 34 must be provided on the side of the boundary where the drain pattern 42 coincides with the first opening 12, away from the drain pattern 42. In the embodiments of this disclosure, placing the first opening 12 on the side of the first boundary 421 away from the first data signal line 211 helps reduce the width of the second electrode portion 34 on the side of the first boundary 421 closer to the first data signal line 211. This reduces the gap between the second electrode portion 34 and the first data signal line 211, decreases the parasitic capacitance between the second electrode portion 34 and the first data signal line 211, reduces signal crosstalk from the first data signal line 211 to the pixel electrode, and reduces fluctuations in the sub-pixel display brightness.

[0080] In the embodiments of this disclosure, the term "boundary coinciding with the drain pattern 42 and the first opening 12" refers to the portion of the boundary of the drain pattern 42 that coincides with the first opening 12. The "first opening 12" can be considered as the portion of the first pattern 11 missing from the drain pattern 42. In the orthographic projection of the first pattern 11 onto the substrate 11, the first opening 12 can be a groove-like structure recessed towards the center of the first pattern 11 (as shown in Figures 8 and 9). Exemplarily, during the patterning etching process of the gate insulating layer GI using the second conductive layer 40 as a mask, the gate insulating layer GI located outside the range of the drain pattern 42 can be completely removed. At this time, the first pattern 11 can be completely located between the drain pattern 42 and the second electrode portion 34, and the boundaries of the first pattern 11, except for the boundary at the first opening 12, at least partially coincide with the boundary of the drain pattern 42. Exemplarily, during the patterning etching process of the gate insulating layer GI using the second conductive layer 40 as a mask, if the portion of the gate insulating layer GI near the boundary of the second conductive layer 40 is not completely etched away (forming a trail at the edge), then at least a portion of the first pattern 11 is located outside the range of the drain pattern 42. Hereinafter, an embodiment of the present disclosure will be described exemplarily, assuming that the first pattern 11 is completely located between the drain pattern 42 and the second electrode portion 34.

[0081] As shown in Figures 6 and 7, in the array substrate 100 provided in the embodiments of this disclosure, the data signal line 21 is disposed on the side of the semiconductor layer 30 near the substrate 10. This facilitates increasing the spacing between the data signal line 21 and the common electrode (first electrode layer 51), thereby reducing the parasitic capacitance between the data signal line 21 and the common electrode. This is beneficial for improving the pixel density and refresh rate of the array substrate 100, and also helps to reduce the power consumption of the data signal line 21, thus reducing the overall power consumption of the array substrate 100. The first transistor T1 may include a semiconductor pattern 31, a source pattern 41, a drain pattern 42, and a gate pattern 43. The gate pattern 43 of the first transistor T1 is located on the side of the semiconductor pattern 31 away from the substrate 10, that is, the first transistor T1 is a top-gate transistor. Compared with a bottom-gate transistor, the top-gate transistor has lower parasitic capacitance and higher on-state current, which can improve the performance of the first transistor T1.

[0082] In some embodiments, the first conductive layer 20 and the second conductive layer 40 may include a metallic material. The metallic material may include a single-layer metallic structure formed from a single metallic material, such as one of titanium, aluminum, copper, molybdenum, niobium, nickel, and their alloys. Alternatively, the metallic material may include a multi-layered metallic stacked structure, which may include a titanium-aluminum-titanium (Ti / Al / Ti) stacked structure, a molybdenum-aluminum (Mo / Al) stacked structure, a molybdenum-aluminum-molybdenum (Mo / Al / Mo) stacked structure, a molybdenum-niobium-titanium (MoNb / Ti) stacked structure, a molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) stacked structure, a molybdenum-niobium-copper (MoNb / Cu) stacked structure, a molybdenum-niobium-titanium-copper (MTD / Cu) stacked structure, or a molybdenum-niobium-copper... The structure can be one or a combination of the following: a molybdenum-niobium-titanium (MoNb / Cu / MTD) stacked structure, a molybdenum-niobium-titanium-copper-molybdenum-niobium-titanium (MTD / Cu / MTD) stacked structure, a molybdenum-titanium-copper (MoTi / Cu / MTD) stacked structure, a molybdenum-titanium-copper-molybdenum-titanium (MoTi / Cu / MoTi) stacked structure, a molybdenum-neodymium-copper stacked structure, a MoNb-copper-MoNb stacked structure, and an AlNb-molybdenum-AlNd stacked structure. The material and structure of the first conductive layer 20 can be the same as, or different from, the material and structure of the second conductive layer 40.

[0083] In some embodiments, as shown in FIG6, the distance D1 between the boundary of the drain pattern 42 coinciding with the first opening 12 and the boundary of the second electrode portion 34 away from the drain pattern 42 is greater than or equal to 1.5 μm. In this way, a conductive path with a width of D1 can be formed on the second electrode portion 34, which is beneficial for the drain pattern 42 to achieve electrical connection with the channel portion 32 through the second electrode portion 34.

[0084] For example, the interval D1 between the boundary of the drain pattern 42 that coincides with the first opening 12 and the boundary of the second electrode portion 34 that is away from the drain pattern 42 can be 1.5μm, 1.6μm, 1.8μm or 2.0μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0085] Referring to Figures 6 and 7, in some embodiments, the data signal line 21 includes a widened portion 213, at least a portion of which protrudes along a first direction X toward a side away from the channel portion 33. The array substrate 100 also includes a first via V1 that penetrates the gate insulating layer GI and the buffer layer BUF, and exposes at least a portion of the widened portion 213 of the data signal line 21. When the array substrate 100 includes a source pattern 41, the source pattern 41 is electrically connected to the widened portion 213 through the first via V1. In addition, the source pattern 41 is also electrically connected to the first electrode portion 33, thus enabling the source pattern 41 to electrically connect the first electrode portion 33 to the widened portion 213 of the data signal line 21. Providing a widened portion 213 on the data signal line 21 helps to increase the area of ​​the widened portion 213, thereby increasing the overlap area between the source pattern 41 and the widened portion 213, reducing the contact resistance between them, and also reducing the positional accuracy requirements between the semiconductor pattern 31 (first electrode portion 33) and the widened portion 213. It also makes it easier for the orthogonal projection of part of the semiconductor pattern 31 on the substrate 10 to only cover part of the orthogonal projection area of ​​the widened portion 213 on the substrate 10.

[0086] In some embodiments, the orthographic projection of the first electrode portion 33 onto the substrate 10 partially coincides with the orthographic projection of the widened portion 213 onto the substrate 10. The orthographic projection of the semiconductor pattern 31 onto the substrate 10 at least partially coincides with the orthographic projection of the data signal line 21 onto the substrate 10. Thus, during the fabrication of the array substrate 100, the formation of a deep first via V1 between the semiconductor pattern 31 and the data signal line 21 can be avoided, reducing the difficulty of the source pattern 41 climbing the sidewall of the first via V1, ensuring the continuity of the source pattern 41 within the first via V1, and guaranteeing the connection stability between the semiconductor pattern 31 and the data signal line 21.

[0087] For example, the orthographic projection of the end of the first electrode portion 33 near the data signal line 21 (the right end of the semiconductor pattern 31 in FIG. 6) onto the substrate 10 is located within the orthographic projection range of the data signal line 21 onto the substrate 10. Furthermore, the orthographic projection of the semiconductor pattern 31 onto the substrate 10 does not completely cover the data signal line 21 in the first direction X; that is, the portion along the first direction X where the orthographic projections of the semiconductor pattern 31 and the data signal line 21 overlap is smaller than the linewidth of the data signal line 21. This ensures that the first via V1 simultaneously exposes part of the semiconductor pattern 31 and part of the data signal line 21, which is beneficial for the overlap between the source pattern 41 and the semiconductor pattern 31 and the data signal line 21.

[0088] Referring to Figures 6 and 7, in some embodiments, the array substrate 100 further includes a first passivation layer PVX1, a planarization layer PLN, a first electrode layer 51, a second passivation layer PVX2, and a second electrode layer 52 disposed on the side of the second conductive layer 40 away from the substrate 10, along a direction away from the substrate 10. The first passivation layer PVX1 is located on the side of the second conductive layer 40 away from the substrate 10, and the planarization layer PLN is located on the side of the first passivation layer PVX1 away from the substrate 10. The planarization layer PLN may include a second via V2, the orthographic projection of the second via V2 on the substrate 10 at least partially coinciding with the orthographic projections of the second electrode portion 34 and the drain pattern 42 on the substrate 10. The first electrode layer 51 is disposed on the side of the planarization layer PLN away from the substrate 10, and the second passivation layer PVX2 is disposed on the side of the first electrode layer 51 away from the substrate 10. The second electrode layer 52 is disposed on the side of the second passivation layer PVX2 away from the substrate 10. In this embodiment, one of the first electrode layer 51 and the second electrode layer 52 is used to form a pixel electrode, and the other is used to form a common electrode. In this embodiment, the first electrode layer 51 is used to form a common electrode and the second electrode layer 52 is used to form a pixel electrode as an example to illustrate the embodiment of this disclosure.

[0089] When the second electrode layer 52 is used to form a pixel electrode, the array substrate 100 further includes a third via V3. The third via V3 penetrates the second passivation layer PVX2 and the first passivation layer PVX1, and exposes at least a portion of the second electrode portion 34 and the drain pattern 42. The orthographic projection of the third via V3 onto the substrate 10 is located within the orthographic projection range of the second via V2 onto the substrate 10. The second electrode layer 52 is electrically connected to the second electrode portion 34 and the drain pattern 42 respectively through the third via V3.

[0090] As shown in Figures 6 and 7, in some embodiments, the first conductive layer 20 further includes a plurality of light-shielding patterns 22. The orthographic projection of the channel portion 33 of the semiconductor pattern 31 onto the substrate 10 is located within the range of the orthographic projection of the light-shielding pattern 22 onto the substrate 10. In this way, the risk of light directly irradiating the channel portion 33 of the semiconductor pattern 31 can be reduced, and the stability of the switching characteristics (on-state voltage) of the first transistor T1 in the light environment can be improved.

[0091] For example, the orthographic projection of the light-shielding pattern 22 onto the substrate 10 completely covers the orthographic projection of the channel portion 33 onto the substrate 10, and at least a portion of the boundary of the orthographic projection of the light-shielding pattern 22 onto the substrate 10 does not coincide with the boundary of the orthographic projection of the channel portion 33 onto the substrate 10. That is, the area of ​​the light-shielding pattern 22 is larger than the area of ​​the channel portion 33, so that the light-shielding pattern 22 can block as much light as possible from hitting the channel portion 33. For example, at least a portion of the orthographic projection of the first electrode portion 33 and the second electrode portion 34 near the channel portion 33 onto the substrate 10 is located within the range of the orthographic projection of the light-shielding pattern 22 onto the substrate 10. This improves the light-shielding effect of the light-shielding pattern 22 on the channel portion 33 of the first transistor T1, reducing the risk of lateral light entering the channel portion 33.

[0092] For example, the orthogonal projection of the gate pattern 43 on the substrate 10 is within the range of the orthogonal projection of the light-shielding pattern 22 on the substrate 10. The gate pattern 43 can also be completely blocked by the light-shielding pattern 22, which can reduce the light directly incident on the gate pattern 43 by the backlight module, thereby reducing the risk of the first gate GI reflecting light toward the channel portion 33 near the surface (lower surface) of the substrate 10, and improving the characteristic stability of the first transistor T1.

[0093] Of course, in some other embodiments, the first conductive layer 20 may not have the light-shielding pattern 22. In this case, the semiconductor layer 30 can be formed using a material with stronger light stability. For example, the material of the semiconductor layer 30 may include a high-mobility metal oxide semiconductor (HMOS) material. High-mobility metal oxide semiconductor materials also have good light stability, which is beneficial to improving the light stability of the first transistor T1. High-mobility metal oxide semiconductor materials include, but are not limited to, rare earth element-doped IZO and IGZO, or oxide semiconductor materials doped with trace amounts of rare earth elements. For example, InXYO:Ln, where Ln includes lanthanide rare earth elements such as Pr and Tb. X and Y are metal elements, such as one or more of Ga, Sn, Zn, Ta, and W. The concentration of rare earth element doping can be between 0.1% and 2%.

[0094] Referring to Figures 4 and 6, the second conductive layer 40 further includes multiple scan signal lines 44, which extend along a first direction X and are spaced apart along a second direction Y. The multiple scan signal lines 44 and multiple data signal lines 21 intersect to form a grid structure. Each grid cell of the grid structure can define a pixel region 101, and each pixel region 101 is used to form a sub-pixel. A scan signal line 44 is electrically connected to the pixel circuit of a row of sub-pixels P; for example, the scan signal line 44 is electrically connected to the first transistor T1 (e.g., the gate of the first transistor) of a row of pixel circuits. Each scan signal line is also electrically connected to a gate driving circuit. A data signal line 21 is electrically connected to the pixel circuit of a column of sub-pixels P; for example, it is electrically connected to the first transistor T1 (e.g., the source of the first transistor) of a column of sub-pixels P. The first transistor T1 is configured to be turned on or off under the control of the scan signal of the scan signal line 44. When the first transistor T1 is turned on, the first transistor T1 transmits the data signal from the data signal line 21 to the pixel electrode. When the first transistor T1 is turned off, the voltage of the pixel electrode remains unchanged under the action of the storage capacitor, and an electric field can be formed between the pixel electrode and the common electrode. This electric field can drive the liquid crystal molecules in the liquid crystal layer to deflect, thereby adjusting the gray level of the sub-pixel.

[0095] The gate pattern 43 is connected to the scan signal line 44. For example, the gate pattern 43 and the scan signal line 44 can be an integral structure so that the scan signal line 44 can transmit a scan signal to the gate pattern 43, thereby controlling the conduction state of the first transistor T1.

[0096] Referring to Figures 6, 8, and 9, in some embodiments, the first electrode portion 33 and the second electrode portion 34 of the semiconductor pattern 31 are located on the same side of the scan signal line 44 along the second direction Y. In this case, when the second conductive layer 40 includes a source pattern 41 and a drain pattern 42, the source pattern 41 and the drain pattern 42 are also located on the same side of the scan signal line GL. This helps to reduce the influence of the first transistor T1 on adjacent sub-pixels. The source pattern 41 and the drain pattern 42 are arranged along the first direction X. The drain pattern 42 also includes a second boundary 422 along the second direction Y away from the scan signal line GL, and a third boundary 423 along the first direction X near the channel portion 32. The first opening 12 of the first pattern 11 at least partially overlaps with the second boundary 422 and / or the third boundary 423. This helps to reduce the width of the second electrode portion 34 on the side of the drain pattern 42 closer to the first data signal line 211, thereby reducing the gap between the second electrode portion 34 and the scan signal line 44, reducing the parasitic capacitance between the second electrode portion 34 and the scan signal line 44, reducing the signal crosstalk of the scan signal line 44 to the pixel electrode, and reducing the fluctuation of the sub-pixel display brightness.

[0097] Referring, as exemplarily to Figures 6 and 8, in Figure 8, (a) shows the structure of the first pattern 11, (b) shows the structure of the drain pattern 42, and (c) shows the structure after the first pattern 11 and the drain pattern 42 are superimposed. The first opening 12 of the first pattern 11 partially coincides with the second boundary 422 and partially coincides with the third boundary 423. This is beneficial to increase the total length of the boundary where the drain pattern 42 coincides with the first opening 12, thereby increasing the size of the conductive channel formed between the drain pattern 42 and the second electrode portion 34, and increasing the conductivity between the drain pattern 42 and the second electrode portion 34. The first opening 12 can be a notch opened at the corner of the first pattern 11, and the shape of the notch can be rectangular, or the shape of the boundary of the notch can be arc.

[0098] For example, referring to FIG9, (a) is the structure of the first pattern 11, (b) is the structure of the drain pattern 42, and (c) is the structure after the first pattern 11 and the drain pattern 42 are superimposed. The first opening 12 of the first pattern 11 partially coincides with the second boundary 422 and does not coincide with the third boundary 423. In this case, the first opening 12 can be a C-shaped groove structure opened on the first pattern 11. In addition, the shape of the first opening 12 can be rectangular, semi-circular, or semi-elliptical, etc.

[0099] Referring to FIG6, in some embodiments, the second electrode portion 34 includes a first sub-portion 341 and a second sub-portion 342. The first sub-portion 341 extends along a first direction X, and the second sub-portion 342 is located on the side of the first sub-portion 341 away from the scan signal line 44 along a second direction Y, and is connected to the end of the first sub-portion 341 near the first data signal line 211. That is, the second electrode portion 34 can form an "L"-shaped structure. At least a portion of the orthographic projection of the drain pattern 42 onto the substrate 10 is located within the range of the orthographic projection of the second sub-portion 342 of the second electrode portion 34 onto the substrate 10.

[0100] Referring to Figures 10 and 11, in some embodiments, the corner of the first sub-part 341 near the scan signal line 44 and the first data signal line 211 (the lower left corner of the first sub-part 341 in Figure 11) includes a second opening 343. That is, the corner of the first sub-part 341 near the scan signal line 44 and the first data signal line 211 forms a notch. This helps to reduce the relative area between the first sub-part 341 and the first data signal line 211, and also reduces the relative area between the first sub-part 341 and the scan signal line 44, thereby reducing the parasitic capacitance between the second electrode portion 34 and the first data signal line 211, and between the second electrode portion 34 and the scan signal line 44. This significantly reduces the signal interference generated by the first data signal line 211 and the scan signal line 44 on the pixel electrode. At least a portion of the drain pattern 42 is located within the second opening 343 to reduce structural adjustments to the drain pattern 42 and simplify its structure.

[0101] In some embodiments, referring to Figures 12 and 13, the second conductive layer 40 further includes a scan signal line 44, and the gate pattern 43 is connected to the scan signal line 44. The first electrode portion 33 and the second electrode portion 34 of the semiconductor pattern 31 are located on the same side of the scan signal line 44 along the second direction Y. The drain pattern 42 further includes a fourth boundary 424 along the second direction Y near the scan signal line 44, and a third boundary 423 along the first direction X near the channel portion 32. The first opening 12 of the first pattern 11 at least partially overlaps with the third boundary 423 and / or the fourth boundary 424. In this way, by reducing the parasitic capacitance between the second electrode portion 34 and the first data signal line 211, the size of the second electrode portion 34 and the drain pattern 42 in the second direction Y can be reduced, which is beneficial to reducing the space occupied by the first transistor T1 in the second direction Y, thereby increasing the aperture ratio of the pixel region 101 and improving the pixel density of the array substrate 100 and the display panel.

[0102] For example, as shown in FIG13, (a) is the structure of the first pattern 11, (b) is the structure of the drain pattern 42, and (c) is the structure after the first pattern 11 and the drain pattern 42 are superimposed. The first opening 12 of the first pattern 11 partially coincides with the third boundary 423 and partially coincides with the fourth boundary 424. In this case, it is beneficial to increase the total length of the boundary where the drain pattern 42 coincides with the first opening 12, thereby increasing the size of the conductive channel formed between the drain pattern 42 and the second electrode portion 34 and increasing the conductivity between the drain pattern 42 and the second electrode portion 34. The first opening 12 can be a notch opened at the corner (lower right corner) of the first pattern 11. The shape of the notch can be rectangular, or the shape of the boundary of the notch can be arc.

[0103] As shown in Figure 12, the second electrode portion 34 extends along the first direction X, which greatly simplifies the structure of the second electrode portion 34 and significantly reduces its size in the second direction Y. At least a portion of the drain pattern 42 is located on the side of the second electrode portion 34 away from the scan signal line 44 along the second direction Y.

[0104] Referring to Figure 14, the shape of the first via V1 can be circular, elliptical, semi-circular, or semi-elliptical, etc., that is, the boundary of the first via V1 is arc-shaped. Based on this, the side of the widened portion 213 away from the channel portion 33 includes at least one chamfer 13, and / or the side of the source pattern 41 away from the channel portion 33 includes at least one chamfer 13. In this way, without reducing the minimum spacing between the first via V1 and the boundaries of the widened portion 213 and / or the source pattern 41, the spacing between the widened portion 213 and / or the source pattern 41 and the second electrode portion 34 of the semiconductor pattern 31 in the adjacent sub-pixel can be reduced, the spacing between the widened portion 213 and / or the source pattern 41 and the first data signal line 211 can be increased, and the parasitic capacitance between the widened portion 213 and / or the source pattern 41 and the first data signal line 211 can be reduced, thereby reducing the signal interference of the first data signal line 211 to the second electrode portion 34 and the pixel electrode.

[0105] In some embodiments, the angle between the extension direction of the chamfer 13 boundary and the first direction can be 30° to 60°. The dimension of the chamfer 13 along the first direction X is 1μm to 2μm. In this way, without reducing the minimum spacing between the first via V1 and the widened portion 213 and the source pattern 41, the spacing between the widened portion 213 and / or the source pattern 41 and the first data signal line 211 can be greatly increased, and the parasitic capacitance between the widened portion 213 and / or the source pattern 41 and the first data signal line 211 can be reduced.

[0106] For example, the angle β between the extension direction of the boundary of the chamfer 13 and the first direction can be 30°, 35°, 40°, 45°, 50° or 60°. The dimension of the chamfer 13 along the first direction X is 1μm, 1.3μm, 1.5μm, 1.7μm or 2μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0107] In one example, as shown in FIG14, the side of the widened portion 213 away from the channel portion 33 includes two of the aforementioned chamfers 13, and the side of the source pattern 41 away from the channel portion 33 also includes two of the aforementioned chamfers 13. Of course, the embodiments of this disclosure are not limited to this. For example, the side of the widened portion 213 away from the channel portion 33 may include two of the aforementioned chamfers 13, and the side of the source pattern 41 away from the channel portion 33 may include one of the aforementioned chamfers 13; or, the side of the widened portion 213 away from the channel portion 33 may include one of the aforementioned chamfers 13, and the side of the source pattern 41 away from the channel portion 33 may not include the aforementioned chamfers. The embodiments of this disclosure will not be listed one by one. Furthermore, the angle and size of the chamfers 13 at different locations may be equal, or at least one of the angle and size of the chamfers at different locations may be unequal.

[0108] Referring to FIG15, in some embodiments, the first electrode portion 33 and the second electrode portion 34 of the semiconductor pattern 31 are respectively located on both sides of the scan signal line 44 along the second direction Y. At least a portion of the second electrode portion 34 coincides with the midline of two adjacent data signal lines 21 along the first direction X. In this way, the second electrode portion 34 can be located in the middle of the two adjacent data signal lines 21 along the first direction X as much as possible, which is beneficial to increase the spacing between the second electrode portion 34 and the first data signal line 211, thereby reducing the parasitic capacitance formed between the second electrode portion 34 and the first data signal line 21, and reducing the interference of voltage fluctuations on the first data signal line 211 on the second electrode portion 34 and the pixel electrode.

[0109] Referring again to Figure 15, the drain pattern 42 extends along the first direction X. The drain pattern 42 also includes a fifth boundary 425 along the second direction Y, close to the scan signal line 44; a sixth boundary 426 along the second direction Y, away from the scan signal line 44; and a seventh boundary 427 along the first direction X, away from the first data signal line 211. The first opening 12 at least partially overlaps with the fifth boundary 425 and / or the sixth boundary 426, but does not overlap with the seventh boundary 427. Based on this, a conductive channel can be formed with the second electrode portion 34 on the fifth boundary 425 and / or the sixth boundary 426 of the drain pattern 42. This helps to reduce the size of the second electrode portion in the first direction X, thereby reducing the spacing between the second electrode portion 34 and the first data signal line 211, reducing the parasitic capacitance between the second electrode portion 34 and the first data signal line 211, and further reducing the signal interference of the first data signal line 211 to the second electrode portion 34. In Figure 15, the embodiment of this disclosure is illustrated by way of the first opening 12 and the fifth boundary 425 partially overlapping, but the embodiment of this disclosure is not limited thereto.

[0110] Referring to Figures 7 and 15, in some embodiments, the array substrate includes a first passivation layer PVX1, a planarization layer PLN, a first electrode layer 51, a second passivation layer PVX2, a second via V2, a second electrode layer 52, and a third via V3. The structures of the first passivation layer PVX1, the planarization layer PLN, the first electrode layer 51, the second passivation layer PVX2, the second via V2, the second electrode layer 52, and the third via V3 are described above and will not be repeated here.

[0111] The orthographic projections of the second via V2 and the third via V3 onto the substrate 10 at least partially overlap with the orthographic projection of the first opening 11 onto the substrate 10. Thus, the second via V2 and the third via V3 are also located in the middle region of the two data signal lines 21 along the first direction X. This helps to increase the spacing between the second via V2 and the third via V3 and the first data signal line 211, and also helps to increase the spacing between the second electrode layer (pixel electrode) located in the third via V3 and the first data signal line 211, as well as the parasitic capacitance between the second electrode layer located in the third via V3 and the first data signal line 211, thereby reducing the signal interference caused by voltage fluctuations on the first data signal line 211 to the second electrode layer.

[0112] Referring to FIG16, in some embodiments, the drain pattern 42 may include a third sub-part 45 and a fourth sub-part 46. The third sub-part 45 extends along a first direction X, and the fourth sub-part 46 is located on the side of the third sub-part 45 along a second direction Y near the scan signal line 44 and is connected to the end of the third sub-part 45 near the first data signal line 211. That is, the fourth sub-part 46 is the portion of the third sub-part 45 that protrudes towards the scan signal line 44. The third sub-part 45 includes an eighth boundary 451 along the second direction Y near the scan signal line 44, a ninth boundary 452 along the second direction Y away from the scan signal line 44, and a tenth boundary 453 along the first direction X away from the first data signal line 211. The first opening 12 at least partially coincides with the eighth boundary 451 and / or the ninth boundary 452, but does not coincide with the tenth boundary 453. Based on this, a conductive channel can be formed between the second electrode portion 34 and the eighth boundary 451 and / or the ninth boundary 452 of the third sub-part 45, which helps to reduce the size of the second electrode portion 34 in the first direction X, thereby reducing the spacing between the second electrode portion 34 and the first data signal line 211 and reducing the parasitic capacitance between the second electrode portion 34 and the first data signal line 211.

[0113] As shown in Figure 16, in some embodiments, the third via V3 exposes at least a portion of the fourth sub-part 46. The second electrode layer is electrically connected to the fourth sub-part 46 through the third via V3, but does not contact the second electrode part 34. The orthographic projection of the second via V2 on the substrate 10 does not coincide with the orthographic projection of the first opening 12 on the substrate 10. Based on this, at least a portion of the second via V2 and the third via V3 can be disposed on one side of the second electrode part 34 and the drain pattern 42 along the first direction X. This helps to reduce the space occupied by the second via V2 and the third via V3 in the second direction Y, thereby reducing the width of the black matrix on the color filter substrate used to block the second via V2 and the third via V3. This helps to increase the aperture ratio of the array substrate and the display panel, and also helps to improve the pixel density of the array substrate and the display panel.

[0114] As shown in Figures 15 and 16, in some embodiments, the second conductive layer 40 may not include the gate pattern. The portion of the orthographic projection of the scan signal line 44 on the substrate 10 that overlaps with the orthographic projection of the semiconductor pattern 31 on the substrate 10 forms the gate of the first transistor T1.

[0115] The embodiments of this disclosure also provide a method for fabricating an array substrate. This method may include: forming a first conductive layer, a buffer layer, and a semiconductor layer on a substrate; the structures of the first conductive layer, buffer layer, and semiconductor layer can be referred to in any of the above embodiments, and will be described in detail here; then forming an initial gate insulating layer on the side of the semiconductor layer away from the substrate, and performing a first patterning etching process on the initial gate insulating layer to form a first via and an intermediate via; forming a second conductive layer on the side of the initial gate insulating layer away from the substrate, the second conductive layer including a drain pattern, the drain pattern covering a portion of the intermediate via, and exposing at least a portion of the intermediate via; other structures of the second conductive layer are referred to above and will not be repeated here; performing a second patterning etching process on the initial gate insulating layer using the second conductive layer as a mask to remove the portion of the initial gate insulating layer not covered by the second conductive layer, to form a gate insulating layer with the desired pattern; the portion of the initial gate insulating layer surrounding the intermediate via and not covered by the second conductive layer is removed, and the intermediate via forms a first opening. In the process of the second patterning etching of the initial gate insulating layer, in order to ensure that the part of the initial gate insulating layer not covered by the second conductive layer can be completely removed, a certain amount of over-etching of the initial gate insulating layer is required.

[0116] In related technologies, within the pixel region, the gate insulating layer and the buffer layer are in direct contact. During the second patterning etching process of the initial gate insulating layer, a portion of the buffer layer is etched away. Furthermore, due to the poor etching uniformity within the pixel region, the thickness of the resulting buffer layer within the pixel region may be uneven. This leads to significant differences in the transmittance spectrum of the buffer layer in areas of different thicknesses, resulting in color shift issues in the display panel.

[0117] To address the aforementioned technical problems, referring to Figures 17 and 18, in the embodiments of this disclosure, the array substrate 100 further includes an etch stop layer 53. The etch stop layer 53 is disposed on the side of the buffer layer BUF away from the substrate 10 and is in contact with the buffer layer BUF. The etch stop layer 53 covers at least a portion of the pixel region 101, and the etch stop layer 53 does not overlap with the semiconductor pattern 31. The etch stop layer 53 has a different etching selectivity than the gate insulating layer GI. Thus, during the second patterning etching process of the initial gate insulating layer, even if there is a certain amount of over-etching, the etching can be stopped on the surface of the etch stop layer 53, avoiding damage to the etch stop layer 53 and the buffer layer BUF. This is beneficial for improving the thickness uniformity of the buffer layer BUF within the pixel region and reducing the risk of color shift in the display panel.

[0118] For example, the buffer layer BUF may include a first sublayer BUF1 and a second sublayer BUF2 stacked together, with the second sublayer BUF2 located on the side of the first sublayer BUF1 away from the substrate 10. The material of the first sublayer BUF1 may include, for example, silicon nitride, and the material of the second sublayer BUF2 may include, for example, silicon oxide. In the area of ​​the second sublayer BUF2 not covered by the etch barrier layer 53, a groove 15 may be formed.

[0119] In some embodiments, the etch stop layer 53 and the semiconductor layer 30 are made of the same material and are disposed in the same layer. This allows the etch stop layer 53 to be formed using existing fabrication processes, simplifying the fabrication process of the array substrate and thus reducing the fabrication cost of the array substrate. The etch stop layer 53 may be spaced from the semiconductor pattern 31 to prevent short circuits between the etch stop layer 53 and the semiconductor pattern 31.

[0120] In other embodiments, the etch barrier layer 53 may include a transparent conductive material, and / or the semiconductor layer 30 may include a semiconductor material. In other words, the etch barrier layer and the semiconductor layer 30 are made of different materials and can be fabricated separately in different processes. For example, the transparent conductive material may include, but is not limited to, indium tin oxide (ITO) and indium zinc oxide (IZO). Semiconductor materials are described above and will not be repeated here.

[0121] As shown in Figure 17, in some embodiments, the etch barrier layer 53 may include multiple etch barrier patterns 531, with one etch barrier pattern 531 located within a pixel area. This can greatly reduce the overlap area between the etch barrier pattern 531 and the data signal line 21, reduce the parasitic capacitance between the etch barrier pattern 531 and the data signal line 21, and help reduce the load on the data signal line 21.

[0122] As shown in Figure 19, in some embodiments, the etch stop layer 53 includes a plurality of etch stop strips 532, one of which passes through a row of pixel areas 101 arranged along the first direction X and extends to the peripheral area. This simplifies the pattern of the etch stop layer 53 and reduces the fabrication difficulty of the etch stop layer 53.

[0123] When the etching barrier layer 53 includes multiple etching barrier strips 532, the etching barrier strips 532 can be electrically connected to a constant voltage signal terminal. This can prevent the etching barrier strips 532 from becoming floating electrodes and reduce voltage fluctuations on the etching barrier strips 532.

[0124] In some embodiments, the etching barrier 532 can be configured to transmit the same voltage signal as the first electrode layer (common electrode). In this way, the etching barrier 532 can form a parallel structure with the first electrode layer, which can reduce the resistance of the first electrode layer and reduce the voltage drop on the first electrode layer.

[0125] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising: Substrate; A first conductive layer, located on one side of the substrate, includes multiple data signal lines, which are spaced apart along a first direction and extend along a second direction; the first direction and the second direction intersect each other. A buffer layer is located on the side of the first conductive layer away from the substrate; A semiconductor layer is located on the side of the buffer layer away from the substrate. The semiconductor layer includes a semiconductor pattern, and the semiconductor pattern includes a channel portion and a first electrode portion and a second electrode portion located on both sides of the channel portion. A gate insulating layer, located on the side of the semiconductor layer away from the substrate, includes a first pattern; The second conductive layer is located on the side of the gate insulating layer away from the substrate. The second conductive layer includes at least two of a source pattern, a drain pattern, and a gate pattern. The source pattern is electrically connected to the first electrode portion and the data signal line, respectively. The drain pattern includes a first boundary close to the first data signal line. The first data signal line is the one of the plurality of data signal lines that is closest to the second electrode portion. The array substrate further includes a first transistor, which includes the semiconductor pattern, the gate pattern, the source pattern, and the drain pattern. The first pattern is at least partially located between the drain pattern and the second electrode portion, and includes a first opening. The first opening is located on the side of the first boundary away from the first data signal line and coincides with at least a portion of the boundary of the drain pattern. The drain pattern is connected to the second electrode portion through the first opening.

2. The array substrate according to claim 1, wherein, The second conductive layer further includes a scan signal line extending along the first direction, and the gate pattern is connected to the scan signal line; The first electrode portion and the second electrode portion of the semiconductor pattern are located on the same side of the scan signal line along the second direction. The drain pattern also includes a second boundary along the second direction away from the scan signal line and a third boundary along the first direction close to the channel portion. The first opening at least partially coincides with the second boundary and / or the third boundary.

3. The array substrate according to claim 2, wherein, The second electrode portion includes a first sub-portion and a second sub-portion. The first sub-portion extends along the first direction, and the second sub-portion is located on the side of the first sub-portion away from the scan signal line along the second direction, and is connected to the end of the first sub-portion close to the first data signal line.

4. The array substrate according to claim 3, wherein, The corner of the first sub-part near the scan signal line and near the first data signal line includes a second opening; At least a portion of the drain pattern is located within the second opening.

5. The array substrate according to claim 1, wherein, The second conductive layer further includes a scan signal line extending along the first direction, and the gate pattern is connected to the scan signal line; The first electrode portion and the second electrode portion of the semiconductor pattern are located on the same side of the scan signal line along the second direction; the drain pattern further includes a fourth boundary along the second direction near the scan signal line, and a third boundary along the first direction near the channel portion; The first opening at least partially coincides with the third boundary and / or the fourth boundary.

6. The array substrate according to claim 5, wherein, The second electrode portion extends along the first direction; At least a portion of the drain pattern is located on the side of the second electrode portion away from the scan signal line along the second direction.

7. The array substrate according to any one of claims 1 to 6, wherein, The distance between the boundary of the drain pattern coinciding with the first opening and the boundary of the second electrode portion away from the drain pattern is greater than or equal to 1.5 μm.

8. The array substrate according to any one of claims 2 to 6, wherein, The data signal line includes a widened portion, at least a portion of which protrudes along the first direction toward a side away from the channel portion; The array substrate further includes a first via, which penetrates the gate insulating layer and the buffer layer and exposes at least a portion of the widened portion. The source pattern is electrically connected to the widened portion through the first via. The widened portion has at least one chamfer on its side away from the channel portion, and / or the source pattern has at least one chamfer on its side away from the channel portion.

9. The array substrate according to claim 8, wherein, The angle between the extension direction of the chamfer boundary and the first direction is 45°, and the dimension of the chamfer along the first direction is 1μm to 2μm.

10. The array substrate according to claim 1, wherein, The second conductive layer further includes scan signal lines that extend along the first direction; The first electrode portion and the second electrode portion of the semiconductor pattern are respectively located on both sides of the scan signal line along the second direction; At least a portion of the second electrode portion coincides with the centerline of the two adjacent data signal lines along the first direction.

11. The array substrate according to claim 10, wherein, The drain pattern extends along the first direction, and the drain pattern further includes a fifth boundary along the second direction that is close to the scan signal line, a sixth boundary along the second direction that is far away from the scan signal line, and a seventh boundary along the first direction that is far away from the first data signal line. The first opening at least partially coincides with the fifth boundary and / or the sixth boundary, but does not coincide with the seventh boundary.

12. The array substrate according to claim 11, further comprising: The first passivation layer is located on the side of the second conductive layer away from the substrate; A planarization layer, located on the side of the first passivation layer away from the substrate, includes a second via, the orthographic projection of the second via on the substrate at least partially overlapping the orthographic projection of the drain pattern on the substrate; The first electrode layer is located on the side of the planarization layer away from the substrate; The second passivation layer is located on the side of the first electrode layer away from the substrate; The third via penetrates the second passivation layer and the first passivation layer, and exposes at least a portion of the drain pattern and the second electrode portion. The orthographic projection of the third via on the substrate is located within the orthographic projection range of the second via on the substrate. The second electrode layer is located on the side of the second passivation layer away from the substrate, and the second electrode layer is electrically connected to the drain pattern and the second electrode portion through the third via, respectively. The orthographic projections of the second via and the third via on the substrate at least partially coincide with the orthographic projection of the first opening on the substrate.

13. The array substrate according to claim 10, wherein, The drain pattern includes a third sub-section and a fourth sub-section. The third sub-section extends along the first direction, and the fourth sub-section is located on the side of the third sub-section close to the scan signal line along the second direction and is connected to the end of the third sub-section close to the first data signal line. The third sub-section includes an eighth boundary along the second direction that is close to the scan signal line, a ninth boundary along the second direction that is far away from the scan signal line, and a tenth boundary along the first direction that is far away from the first data signal line. The first opening at least partially coincides with the eighth and / or ninth boundary, but does not coincide with the tenth boundary.

14. The array substrate according to claim 13, further comprising: The first passivation layer is located on the side of the second conductive layer away from the substrate; A planarization layer, located on the side of the first passivation layer away from the substrate, includes a second via, the orthographic projection of the second via on the substrate at least partially overlapping the orthographic projection of the fourth sub-part on the substrate; The first electrode layer is located on the side of the planarization layer away from the substrate; The second passivation layer is located on the side of the first electrode layer away from the substrate; The third via penetrates the second passivation layer and the first passivation layer, and exposes at least a portion of the fourth sub-part. The orthographic projection of the third via on the substrate is located within the orthographic projection range of the second via on the substrate. The second electrode layer is located on the side of the second passivation layer away from the substrate, and the second electrode layer is electrically connected to the fourth sub-part through the third via. The orthographic projection of the second via on the substrate does not coincide with the orthographic projection of the first opening on the substrate.

15. The array substrate according to any one of claims 1 to 14, wherein, The second conductive layer further includes multiple scan signal lines, which are spaced apart along the second direction and extend along the first direction. The orthogonal projections of the multiple scan signal lines and the multiple data signal lines on the substrate intersect to form a grid structure, with each grid defining a pixel area. The array substrate further includes an etch barrier layer located on the side of the buffer layer away from the substrate and in contact with the buffer layer. The etch barrier layer has a different etch selectivity ratio than the gate insulating layer. The etch barrier layer covers at least a portion of the pixel area and does not overlap with the semiconductor pattern.

16. The array substrate according to claim 15, wherein, The etching barrier layer and the semiconductor layer are made of the same material and are disposed in the same layer.

17. The array substrate according to claim 15, wherein, The etching barrier layer comprises a transparent conductive material; and / or, the semiconductor layer comprises a semiconductor material.

18. The array substrate according to any one of claims 15 to 17, wherein, The etching barrier layer includes multiple etching barrier patterns, with one of the barrier patterns located within one of the pixel regions.

19. The array substrate according to any one of claims 15 to 17, wherein, The array substrate includes a display area and a peripheral area surrounding the display area; The etching barrier layer includes a plurality of etching barrier strips, one of which passes through a row of pixel areas arranged along the first direction and extends to the peripheral area.

20. The array substrate according to claim 19, wherein, The etching barrier is electrically connected to the constant voltage signal terminal.

21. The array substrate according to claim 20, further comprising: The first electrode layer is located on the side of the second conductive layer away from the substrate; The second electrode layer is located on the side of the first electrode layer away from the substrate, and the second electrode layer is electrically connected to the drain pattern; The etching barrier and the first electrode layer are configured to transmit the same voltage signal.

22. A display panel, comprising: The array substrate as described in any one of claims 1 to 21; A color filter substrate is disposed opposite to the array substrate; A liquid crystal layer is located between the array substrate and the color filter substrate.

23. A display device, comprising: The display panel as described in claim 22; The backlight module is located on the backlight side of the display panel.

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