Accelerator instruction processing method and apparatus, and electronic device

Abstract

Disclosed in the present application are an accelerator instruction processing method and apparatus, and an electronic device. The method is executed by a processor, and comprises: dispatching an accelerator instruction to a shared reservation station of an execution unit of an accelerator and an execution unit of a processor; determining whether there is a free entry in an accelerator instruction data transmission unit in the processor, and in response to there being a free entry in the accelerator instruction data transmission unit, issuing the accelerator instruction from the shared reservation station to the execution unit; monitoring a write-back port of the execution unit, and determining configuration information of the execution unit; on the basis of the configuration information of the execution unit, writing the accelerator instruction back to a re-order buffer area; and controlling the accelerator instruction data transmission unit to sequentially send instruction information of the accelerator instruction to the execution unit of the accelerator.

Description

Accelerator command processing methods, devices and electronic equipment

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202411462325.1, filed on October 18, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer processor technology, and in particular to methods, apparatus and electronic devices for processing accelerator instructions. Background Technology

[0004] With the rapid development of computationally intensive applications such as artificial intelligence, scientific computing, video processing, network transmission, encryption / decryption, and digital signal processing, the demands on chip data processing capabilities are increasing. To improve the processing capabilities of domain-specific architectures (DSA) for computationally intensive applications, chips generally adopt a heterogeneous architecture combining processors and accelerators. The processor is responsible for control flow processing, while the accelerator is responsible for data flow processing. Chips use artificial intelligence (AI) processors, graphics processing units (GPUs), digital signal processing units (DSPs), cryptographic accelerators, data processing units (DPUs), and stream processors as accelerators, which together with the central processing unit (CPU) form the heterogeneous core of the chip's processor and accelerator architecture. Summary of the Invention

[0005] This application aims to at least partially address one of the technical problems in the related art. To this end, embodiments of this application provide a method, apparatus, electronic device, storage medium, and computer program product for processing accelerator instructions.

[0006] To achieve the above objectives, a first aspect of this application provides a method for processing accelerator instructions, executed by a processor. The method includes: dispatching accelerator instructions to a shared reservation station of the accelerator and the processor's execution unit; determining whether an accelerator instruction data transmission unit in the processor has an empty entry; and, in response to the empty entry in the accelerator instruction data transmission unit, transmitting the accelerator instructions from the shared reservation station to the execution unit; monitoring the write-back port of the execution unit to determine the configuration information of the execution unit, wherein the configuration information of the execution unit indicates that the execution unit exclusively uses the write-back port or that the execution unit shares the write-back port; writing the accelerator instructions back to a reordering buffer according to the configuration information of the execution unit; and controlling the accelerator instruction data transmission unit to send the instruction information of the accelerator instructions to the execution unit of the accelerator in sequence, wherein the instruction information includes an opcode and a source operand.

[0007] To achieve the above objectives, a second aspect of this application provides an accelerator instruction processing apparatus applied to a processor. The apparatus includes: a dispatch module for dispatching accelerator instructions to a shared reservation station of the accelerator and the processor's execution unit; a transmit module for determining whether there is an empty entry in the accelerator instruction data transmission unit of the processor, and, in response to an empty entry in the accelerator instruction data transmission unit, transmitting the accelerator instruction from the shared reservation station to the execution unit; a monitoring module for monitoring the write-back port of the execution unit and determining the configuration information of the execution unit, wherein the configuration information of the execution unit indicates that the execution unit exclusively uses the write-back port or that the execution unit shares the write-back port; a write-back module for writing the accelerator instructions back to a reordering buffer according to the configuration information of the execution unit; and a sending module for controlling the accelerator instruction data transmission unit to send the instruction information of the accelerator instructions to the execution unit of the accelerator in sequence, wherein the instruction information includes an opcode and a source operand.

[0008] To achieve the above objectives, a third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements a method for processing accelerator instructions as described in any one of the first aspects of this application.

[0009] To achieve the above objectives, a fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements a processing method for accelerator instructions as described in any one of the first aspects of this application.

[0010] To achieve the above objectives, the fifth aspect of this application provides a computer program product, including a computer program that, when executed by a processor, implements a processing method for accelerator instructions as described in any one of the embodiments of the first aspect above. Attached Figure Description

[0011] Figure 1 is a schematic diagram of an accelerator instruction processing method disclosed in an embodiment of this application.

[0012] Figure 2 is a schematic diagram of the processing of accelerator commands disclosed in another embodiment of this application.

[0013] Figure 3 is a schematic diagram of an accelerator command processing method disclosed in another embodiment of this application.

[0014] Figure 4 is a flowchart illustrating an accelerator command processing method disclosed in another embodiment of this application.

[0015] Figure 5 is a flowchart illustrating an accelerator command processing method disclosed in another embodiment of this application.

[0016] Figure 6 is a schematic diagram of the structure of an accelerator command processing device disclosed in an embodiment of this application.

[0017] Figure 7 is a schematic diagram of the structure of an electronic device disclosed in an embodiment of this application. Detailed Implementation

[0018] To better understand the above technical solutions, exemplary embodiments of this disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0019] To improve the processing power of computationally intensive applications in Domain-Specific Architectures (DSA), chips typically adopt a heterogeneous architecture combining processors and accelerators. The processor handles control flow processing, while the accelerator handles data flow processing. Chips use Artificial Intelligence (AI) processors, Graphics Processing Units (GPUs), Digital Signal Processors (DSPs), Cryptographic Accelerators, Data Processing Units (DPUs), and stream processors as accelerators, which together with the Central Processing Unit (CPU) form the heterogeneous core of the chip. However, since the processor and accelerator each have independent control units, this often leads to resource waste and low resource utilization in heterogeneous chips.

[0020] To address the aforementioned problems, this application provides a method, apparatus, electronic device, storage medium, and computer program product for processing accelerator instructions.

[0021] The following description, with reference to the accompanying drawings, illustrates an embodiment of an accelerator command processing method and apparatus.

[0022] Figure 1 is a flowchart illustrating an accelerator instruction processing method according to an embodiment of this application.

[0023] As shown in Figure 1, the accelerator command processing method proposed in this embodiment of the application specifically includes the following steps:

[0024] S101. Dispatch accelerator instructions to a shared reservation station for the execution units of the accelerator and processor.

[0025] The Reservation Station (RS) is a component in the processor used to cache instructions to be executed until those instructions are allocated to the execution unit for processing.

[0026] It should be noted that this application does not limit the execution components, which can be selected according to the actual situation.

[0027] In some embodiments, the execution components include, but are not limited to, an instruction fetching component, a decoding component, a register renaming component, and a dispatch component.

[0028] It should be noted that for any instruction, it is possible to determine whether the instruction is an accelerator instruction based on the instruction's opcode. If the instruction is determined to be an accelerator instruction, the accelerator instruction is dispatched to the shared reservation station of the execution units of the accelerator and the processor.

[0029] In this embodiment, instructions can be read from the instruction cache, decoded to obtain the opcode of the instructions, and accelerator instructions can be determined from the read instructions based on the opcode of the instructions. The accelerator instructions are then assigned to the shared storage station of the execution units of the accelerator and the processor.

[0030] S102. Determine if there is a blank entry in the accelerator instruction data transmission unit of the processor. If there is a blank entry in the accelerator instruction data transmission unit, send the accelerator instruction from the shared reserved station to the execution unit.

[0031] In some embodiments, the physical register file may be read to determine the source operands required to execute accelerator instructions, for example, before accelerator instructions are sent from a shared reservation station to an execution unit for execution, wherein the source operands are stored in the physical register file.

[0032] In this embodiment of the application, after determining the source operands required to execute the accelerator instructions, it is determined whether there is a free entry in the accelerator instruction data transmission unit in the processor. In response to the free entry in the accelerator instruction data transmission unit, the accelerator instructions are sent from the shared reserved station to the execution unit for execution according to the priority of the accelerator instructions.

[0033] The accelerator instruction data transmission unit is located within the processor and is used for data transmission.

[0034] In some embodiments, when there are multiple accelerator instructions to be executed, the priority of the accelerator instructions can be determined, and the accelerator instructions can be sent from the shared reservation station to the execution unit according to the priority of the accelerator instructions.

[0035] S103. Listen to the write-back port of the execution unit and determine the configuration information of the execution unit, wherein the configuration information of the execution unit indicates that the execution unit exclusively uses the write-back port or the execution unit shares the write-back port.

[0036] S104. Based on the configuration information of the execution unit, write the accelerator instructions back to the reordering buffer.

[0037] In this embodiment of the application, after determining the configuration information of the execution unit, the accelerator instructions can be written back to the reordering buffer according to the configuration information of the execution unit.

[0038] In some embodiments, if the configuration information indicates that the execution unit exclusively uses the write-back port, the first number of execution units is obtained, the first number of first target accelerator instructions is determined from the accelerator instructions, and the first target accelerator instructions are simultaneously written back to the reordering buffer.

[0039] In some embodiments, if the configuration information indicates that the execution unit shares a write-back port, the write-back ports of the execution unit are arbitrated to obtain a second number of write-back ports, a second number of second target accelerator instructions are determined from the accelerator instructions, and the second target accelerator instructions are simultaneously written back to the reordering buffer.

[0040] S105. The control accelerator instruction data transmission unit sends the instruction information of the accelerator instruction to the execution unit of the accelerator in sequence. The instruction information includes the opcode and the source operand.

[0041] In some embodiments, the number of source operands is multiple.

[0042] In some embodiments, the control accelerator instruction data transmission unit sequentially sends instruction information of the accelerator instructions to the execution unit of the accelerator, including:

[0043] Write the opcode and multiple source operands of the accelerator instruction into the accelerator instruction data transmission unit; obtain the target order of the accelerator instructions in the reordering buffer, and control the accelerator instruction data transmission unit to send the opcode and multiple source operands of the accelerator instruction to the accelerator execution unit in the target order.

[0044] In some embodiments, the target order, also known as the original order, is used to write accelerator instructions (i.e., the aforementioned first target accelerator instructions or second target accelerator instructions) back to the reordering buffer in the target order.

[0045] In this embodiment, the opcode of the accelerator instruction and multiple source operands are written into the accelerator instruction data transmission unit. The accelerator instruction data transmission unit is controlled to send the opcode and multiple source operands to the execution unit of the accelerator in the original order. Accordingly, after receiving the opcode and multiple source operands, the accelerator can obtain the execution result of the execution unit of the accelerator by executing the accelerator instruction.

[0046] For example, as shown in Figure 2, the accelerator multiplexes the processor's instruction fetch unit, decode unit, register renaming unit, and dispatch unit. In these units, the accelerator instructions are executed as processor instructions, and the execution results are written back to the reordering buffer. The accelerator instructions enter the dispatch queue. The accelerator multiplexes the processor control unit's pipeline operations as follows: (1) Dispatch to the reservation station: The accelerator instructions are dispatched to the shared reservation station of the accelerator and processor's execution units. The accelerator instructions read the physical register file; (2) Issue: The accelerator instructions can multiplex any of the processor's fixed-point execution unit, floating-point execution unit, memory access execution unit, etc. An execution unit, the accelerator instruction listens to the write-back port of each execution unit, the accelerator instruction receives the value of the physical register file to determine the source operands required to execute the accelerator instruction, when the accelerator command data transmission unit (i.e. the accelerator instruction data transmission unit in the aforementioned embodiment) has an empty item, the accelerator instruction is selected for transmission; (3) Execution and write-back: the accelerator instruction writes back to the reordering buffer, writes the opcode and multiple source operands into the accelerator command data transmission unit; (4) Commit: the accelerator instruction data transmission unit is controlled to send the opcode and multiple source operands to the accelerator execution unit in the original order of the accelerator instruction.

[0047] The accelerator instruction processing method provided in this application dispatches accelerator instructions to a shared reservation station of the execution units of the accelerator and the processor. It then determines whether the accelerator instruction data transmission unit in the processor has any empty entries. If an empty entry is found, the accelerator instruction is sent from the shared reservation station to the execution unit. The method monitors the write-back port of the execution unit to determine its configuration information, which indicates whether the execution unit exclusively uses or shares the write-back port. Based on the configuration information, the accelerator instructions are written back to the reordering buffer. The method then controls the accelerator instruction data transmission unit to send the instruction information of the accelerator instructions to the execution unit of the accelerator in sequence. The instruction information includes the opcode and source operands. Therefore, the accelerator of this disclosure can reuse the execution unit of the processor, allowing the accelerator to focus on domain-specific computational tasks, avoiding resource waste and improving the resource utilization of heterogeneous chips. Simultaneously, writing the opcode and multiple source operands of the accelerator instructions into the accelerator instruction data transmission unit and controlling its transmission to the execution unit of the accelerator improves the collaborative efficiency between the processor and the accelerator.

[0048] Figure 3 is a flowchart illustrating a method for processing accelerator commands according to another embodiment of this application.

[0049] As shown in Figure 3, the accelerator command processing method proposed in this embodiment of the application specifically includes the following steps:

[0050] S301. Read the instruction from the instruction cache and decode the instruction to obtain the opcode.

[0051] S302. Determine the accelerator instruction from the instruction based on the instruction's opcode, and assign the accelerator instruction to the shared reserved station of the execution units of the accelerator and processor.

[0052] S303. Read the physical register file to determine the source operands required to execute the accelerator instructions.

[0053] S304. In response to an empty field in the accelerator command data transmission unit, the accelerator command is transmitted from the shared reserved station to the execution unit.

[0054] S305. Listen to the write-back port of the execution unit and determine the configuration information of the execution unit, wherein the configuration information of the execution unit indicates whether the execution unit exclusively uses the write-back port or the execution unit shares the write-back port.

[0055] S306. Based on the configuration information of the execution unit, write the accelerator instructions back to the reordering buffer.

[0056] In this embodiment of the application, if the configuration information indicates that the execution unit exclusively occupies the write-back port, in response to the completion of the execution of the accelerator instructions, the execution results of each execution unit are simultaneously written back to the reordering buffer in the original order of the accelerator instructions.

[0057] In this embodiment of the application, if the configuration information indicates that the execution units share write-back ports, in response to the completion of the accelerator instruction execution, the write-back ports of the execution units are arbitrated to obtain a target number of write-back ports, and the execution results of the target number of execution units are simultaneously written back to the reordering buffer according to the original order of the accelerator instructions.

[0058] S307. The control accelerator instruction data transmission unit sends the instruction information of the accelerator instruction to the execution unit of the accelerator in sequence, wherein the instruction information includes the opcode and the source operand.

[0059] For example, in the case of accelerator multiplexing processor arithmetic logic unit, there are N arithmetic logic units in the accelerator multiplexing processor, each with its own write-back port, and no write-back arbitration is required, as shown in Figure 4. The pipeline operation of the arithmetic logic unit of the accelerator multiplexing processor is as follows: (1) Dispatch to reservation station: Accelerator instructions are dispatched to the shared reservation station of the arithmetic logic units of the accelerator and the processor. The accelerator instructions read the physical register file; (2) Issue: Accelerator instructions listen to the write-back port of each execution unit. The accelerator instructions receive the value of the read physical register file to determine the source operands required to execute the accelerator instructions. When there is an empty item in the accelerator command data transmission unit, the accelerator instructions are selected for issue; (3) Execution and write-back: Accelerator instructions write back to the reordering buffer. With N arithmetic logic units, N accelerator instructions can be written simultaneously, and the opcode and multiple source operands are written to the accelerator command data transmission unit; (4) Commit: The accelerator instruction data transmission unit is controlled to send the opcode and multiple source operands to the accelerator execution unit in the original order of the accelerator instructions.

[0060] For example, regarding the register transfer unit of the accelerator multiplexed processor, there are a total of M register transfer units in the accelerator multiplexed processor. It needs to arbitrate the write-back port with other units, as shown in Figure 5. The pipeline operation of each stage of the register transfer unit of the accelerator multiplexed processor is as follows: (1) Dispatch to the reservation station: The accelerator instruction is dispatched to the shared reservation station of the register transfer units of the accelerator and the processor. The accelerator instruction reads the physical register file; (2) Issue: The accelerator instruction listens to the write-back port of each execution unit. The accelerator instruction receives the value read from the physical register file to determine the execution accelerator. (2) Source operands required by the instruction. When there are no empty entries in the accelerator command data transmission unit, the accelerator instruction is selected for transmission; (3) Execution and write-back: The accelerator instruction is arbitrated with other execution units and then written back to the reorder buffer. When there are M register transmission units in total, P write-back ports are obtained after arbitration, so that P accelerator instructions can be written at the same time, and the opcode and multiple source operands are written to the accelerator command data transmission unit; (4) Commit: The accelerator instruction data transmission unit is controlled to send the opcode and multiple source operands to the accelerator execution unit in the original order of the accelerator instructions.

[0061] The accelerator instruction processing method provided in this application reads instructions from the instruction cache, decodes the instructions to obtain their opcodes, determines the accelerator instructions from the instructions based on the opcodes, dispatches the accelerator instructions to a shared reservation station of the accelerator and processor execution units, reads the physical register file to determine the source operands required to execute the accelerator instructions, and, in response to the availability of empty entries in the accelerator instruction data transfer unit, issues the accelerator instructions from the shared reservation station to the execution units for execution according to their priority. It also listens to the write-back port of the execution units to obtain their configuration information, wherein the configuration information indicates whether the execution units exclusively use the write-back port or share the write-back port. According to the configuration information of the execution unit, in response to the completion of accelerator instruction execution, the execution result is written back to the reordering buffer according to the original order of the accelerator instructions. The accelerator instruction data transmission unit in the processor is controlled to send the instruction information of the accelerator instructions to the execution unit of the accelerator in the original order. Thus, the accelerator of this disclosure can reuse the execution unit of the processor, and the accelerator focuses on the special computing part of a specific field, avoiding the waste of resources and improving the resource utilization of heterogeneous chips. At the same time, the opcode of the accelerator instruction and multiple source operands are written into the accelerator instruction data transmission unit, and the accelerator instruction data transmission unit is controlled to send them to the execution unit of the accelerator, thereby improving the collaborative efficiency of the processor and the accelerator.

[0062] Figure 6 is a schematic diagram of the structure of an accelerator command processing device according to an embodiment of this application.

[0063] As shown in Figure 6, the accelerator command processing device 1000 includes: a dispatch module 11, a transmission module 12, a listening module 13, a write-back module 14, and a transmission module 15. Among them,

[0064] Dispatch module 11 is used to dispatch accelerator instructions to a shared reservation station of the execution units of the accelerator and the processor.

[0065] The transmitting module 12 is used to determine whether there is an empty entry in the accelerator instruction data transmission unit in the processor, and in response to the empty entry in the accelerator instruction data transmission unit, transmits the accelerator instruction from the shared reservation station to the execution unit;

[0066] The monitoring module 13 is used to monitor the write-back port of the execution unit and determine the configuration information of the execution unit, wherein the configuration information of the execution unit indicates that the execution unit exclusively uses the write-back port or the execution unit shares the write-back port;

[0067] Write-back module 14 is used to write the accelerator instructions back to the reordering buffer according to the configuration information of the execution unit;

[0068] The sending module 15 is used to control the accelerator instruction data transmission unit to send the instruction information of the accelerator instruction to the execution unit of the accelerator in sequence, wherein the instruction information includes opcode and source operand.

[0069] According to one embodiment of this application, the dispatch module 11 is further configured to: read instructions from the instruction cache, decode the instructions to obtain the opcode of the instructions; determine accelerator instructions from the instructions according to the opcode of the instructions, and dispatch the accelerator instructions to a shared reservation station of the execution units of the accelerator and the processor.

[0070] According to one embodiment of this application, the apparatus 1000 is further configured to: read the physical register file to determine the source operands required to execute the accelerator instructions. In one embodiment, the apparatus 1000 is configured to read the physical register file to determine the source operands required to execute the accelerator instructions before sending the accelerator instructions from the shared reservation station to the execution unit.

[0071] According to one embodiment of this application, the transmitting module 12 is further configured to: obtain the priority of the accelerator command, and transmit the accelerator command from the shared reservation station to the execution unit according to the priority.

[0072] According to one embodiment of this application, the write-back module 14 is further configured to: if the configuration information indicates that the execution unit exclusively occupies the write-back port, obtain a first number of the execution units; determine a first number of first target accelerator instructions from the accelerator instructions, and simultaneously write the first target accelerator instructions back to the reordering buffer.

[0073] According to one embodiment of this application, the write-back module 14 is further configured to: if the configuration information indicates that the execution unit shares a write-back port, arbitrate the write-back ports of the execution unit to obtain a second number of write-back ports; determine a second number of second target accelerator instructions from the accelerator instructions, and simultaneously write the second target accelerator instructions back to the reordering buffer.

[0074] According to one embodiment of this application, the sending module 15 is further configured to: write the opcode and multiple source operands of the accelerator instruction into the accelerator instruction data transmission unit; obtain the target order of the accelerator instructions in the reordering buffer; and control the accelerator instruction data transmission unit to send the opcode and multiple source operands of the accelerator instruction to the execution unit of the accelerator according to the target order.

[0075] This application provides an accelerator instruction processing apparatus. By dispatching accelerator instructions to a shared reservation station of the execution units of the accelerator and processor, it determines whether the accelerator instruction data transmission unit in the processor has empty entries. In response to an empty entry in the accelerator instruction data transmission unit, the accelerator instruction is sent from the shared reservation station to the execution unit. The apparatus monitors the write-back port of the execution unit to determine its configuration information. The configuration information indicates whether the execution unit exclusively uses the write-back port or shares it. Based on the configuration information, the accelerator instructions are written back to the reordering buffer. The accelerator instruction data transmission unit is controlled to send the instruction information of the accelerator instructions to the execution unit of the accelerator in sequence. The instruction information includes the opcode and source operands. Therefore, the accelerator of this disclosure can reuse the execution unit of the processor, allowing the accelerator to focus on domain-specific computing, avoiding resource waste and improving the resource utilization of heterogeneous chips. Simultaneously, by writing the opcode and multiple source operands of the accelerator instructions into the accelerator instruction data transmission unit and controlling the accelerator instruction data transmission unit to send them to the execution unit of the accelerator, the collaborative efficiency of the processor and accelerator is improved.

[0076] To implement the above embodiments, this application also proposes an electronic device 2000, as shown in FIG7, including a memory 220, a processor 210, and a computer program stored in the memory 220 and executable on the processor 210. When the processor executes the program, it implements the aforementioned accelerator instruction processing method.

[0077] To implement the above embodiments, this application also proposes a computer-readable storage medium storing a computer program thereon, wherein the program, when executed by a processor, implements the aforementioned accelerator instruction processing method.

[0078] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0079] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0080] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0081] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0082] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0083] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A method for processing accelerator instructions, executed by a processor, the method comprising: Dispatch accelerator instructions to a shared reservation station for the execution units of the accelerator and processor; Determine whether there is an empty entry in the accelerator instruction data transmission unit in the processor. In response to the empty entry in the accelerator instruction data transmission unit, send the accelerator instruction from the shared reservation station to the execution unit. Listen to the write-back port of the execution unit to determine the configuration information of the execution unit, wherein the configuration information of the execution unit indicates that the execution unit exclusively uses the write-back port or the execution unit shares the write-back port; Based on the configuration information of the execution unit, the accelerator instructions are written back to the reordering buffer; The control unit for transmitting accelerator instruction data sends the instruction information of the accelerator instruction to the execution unit of the accelerator in sequence, wherein the instruction information includes the opcode and the source operand.

2. The method according to claim 1, wherein, The shared reservation station for dispatching accelerator instructions to the execution units of the accelerator and processor includes: Read instructions from the instruction cache and decode the instructions to obtain their opcodes; The accelerator instruction is determined from the instruction based on the opcode of the instruction, and the accelerator instruction is assigned to a shared reservation station of the execution units of the accelerator and the processor.

3. The method according to claim 1 or 2, wherein, The method further includes: Read the physical register file to determine the source operands required to execute the accelerator instructions.

4. The method according to any one of claims 1-3, wherein, The step of transmitting the accelerator command from the shared reservation station to the execution unit in response to a blank entry in the accelerator command data transmission unit further includes: The priority of the accelerator command is obtained, and the accelerator command is transmitted from the shared reservation station to the execution unit according to the priority.

5. The method according to any one of claims 1-4, wherein, The step of writing the accelerator instructions back to the reordering buffer according to the configuration information of the execution unit further includes: If the configuration information indicates that the execution unit exclusively uses the write-back port, obtain the first number of the execution units; A first number of first target accelerator instructions are determined from the accelerator instructions, and the first target accelerator instructions are simultaneously written back to the reordering buffer.

6. The method according to any one of claims 1-4, wherein, The step of writing the accelerator instructions back to the reordering buffer according to the configuration information of the execution unit further includes: If the configuration information indicates that the execution unit shares the write-back port, the write-back ports of the execution unit are arbitrated to obtain a second number of write-back ports; A second number of second target accelerator instructions are determined from the accelerator instructions, and the second target accelerator instructions are simultaneously written back to the reordering buffer.

7. The method according to any one of claims 1-6, wherein, The control unit for transmitting accelerator command data sequentially to the execution unit of the accelerator also includes: The opcode of the accelerator instruction and multiple source operands are written into the accelerator instruction data transmission unit; The target order of accelerator instructions in the reordering buffer is obtained, and the accelerator instruction data transmission unit is controlled to send the opcode and multiple source operands of the accelerator instructions to the execution unit of the accelerator in the target order.

8. An accelerator instruction processing apparatus, applied to a processor, the apparatus comprising: The dispatch module is used to dispatch accelerator instructions to a shared reservation station for the execution units of the accelerator and processor. The transmission module is used to determine whether there is an empty entry in the accelerator instruction data transmission unit in the processor, and in response to the empty entry in the accelerator instruction data transmission unit, transmits the accelerator instruction from the shared reservation station to the execution unit; A monitoring module is used to monitor the write-back port of the execution unit and determine the configuration information of the execution unit, wherein the configuration information of the execution unit indicates that the execution unit exclusively uses the write-back port or the execution unit shares the write-back port; The write-back module is used to write the accelerator instructions back to the reordering buffer according to the configuration information of the execution unit; The sending module is used to control the accelerator instruction data transmission unit to send the instruction information of the accelerator instruction to the execution unit of the accelerator in sequence, wherein the instruction information includes opcode and source operand.

9. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements a method for processing accelerator instructions as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, wherein, When executed by the processor, the program implements the accelerator instruction processing method as described in any one of claims 1-7.

11. A computer program product comprising a computer program that, when executed by a processor, implements the processing method of accelerator instructions according to any one of claims 1-7.

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