Semiconductor memory device

Abstract

A card controller (22) observes the access history of accessing an SD card (20) by a host device (10). The card controller (22) uses a pattern selector (41) to determine which of a plurality of patterns the observed access history corresponds to. The card controller (22) reads, from a register (31a), a control parameter associated with the determined pattern. The card controller (22) controls writing to and reading from a NAND flash memory (23) in accordance with the control parameter read from the register (31a). The access history includes at least a data size and an address.

Description

Semiconductor memory device

[0007] ,

[0001] The present disclosure relates to a semiconductor memory device, a server device, and an information processing system.

[0002] Semiconductor memory devices such as flash memories have evolved to have higher density, capacity, and speed and are being used in an increasingly wide range of industrial fields. However, as the density, capacity, and speed of flash memories increase, the number of write cycles, i.e., the lifespan, of the flash memories decreases.

[0003] For example, Patent Document 1 discloses a device for predicting the lifespan of a NAND flash memory.

[0004] Japanese Patent No. 6386523

[0005] Instead of or in addition to predicting the lifespan of a semiconductor memory device, it is desirable to be able to actually use the semiconductor memory device over a long period of time. For this reason, there is a demand for semiconductor memory devices having a longer lifespan than conventional ones.

[0006] An object of the present disclosure is to provide a semiconductor memory device having a longer lifespan than conventional ones. Another object of the present disclosure is to provide a server device for determining control information for such a semiconductor memory device. Another object of the present disclosure is to provide an information processing system including such a semiconductor memory device and a server device.

[0007] A semiconductor memory device according to one aspect of the present disclosure is a semiconductor memory device comprising: an interface connected to an information processing device; a semiconductor memory element storing data transmitted to or received by the information processing device; and a first controller, wherein the semiconductor memory device further comprises a non-volatile memory for storing control information of the semiconductor memory device, the control information including a pattern selector for determining which of a plurality of predetermined patterns an access history of the semiconductor memory device by the information processing device corresponds to; and a plurality of sets of control parameters for writing to and reading from the semiconductor memory element, each set of control parameters associated with the plurality of patterns, the first controller observes the access history of the semiconductor memory device by the information processing device, determines which of the plurality of patterns the observed access history corresponds to using the pattern selector, reads the control parameters associated with the determined pattern from the non-volatile memory, and controls writing to and reading from the semiconductor memory element according to the control parameters read from the non-volatile memory, the access history includes at least the data size and address.

[0008] According to one aspect of this disclosure, it is possible to provide a semiconductor memory device having a longer lifespan than conventional devices.

[0009] Figure 1 is a block diagram showing an example of the configuration of a host device 10 and an SD card 20 according to the first embodiment. Figure 1 is a flowchart showing an example of card control processing performed by the card controller 22 of the SD card 20. Figure 1 shows an example of a pattern selector 41 used by the card controller 22 of the SD card 20. Figure 1 shows a first example of access history to the SD card 20 by the host device 10. Figure 1 shows a second example of access history to the SD card 20 by the host device 10. Figure 1 shows a third example of access history to the SD card 20 by the host device 10. Figure 1 shows a fourth example of access history to the SD card 20 by the host device 10. Figure 1 shows a fifth example of access history to the SD card 20 by the host device 10. Figure 1 shows the case where the SD card 20 operates according to default control parameters. Figure 1 shows the case where the SD card 20 operates according to control parameters associated with the pattern corresponding to the access history. Figure 1 is a block diagram showing an example of the configuration of an information processing system according to the second embodiment. Figure 1 is a flowchart showing an example of card preparation processing performed by the CPU 53 of the server device 50. This is a flowchart of the subroutine for the pattern selector generation process (step S12) in Figure 12. This is a flowchart of the subroutine for the control parameter generation process (step S13) in Figure 12. This is a flowchart of an example of the card update process executed by the CPU 53 of the server device 50 in Figure 11.

[0010] The embodiments will be described in detail below, with reference to the drawings as appropriate. However, unnecessarily detailed explanations may be omitted. For example, detailed explanations of already well-known matters and redundant explanations of substantially identical configurations may be omitted. This is to avoid the following explanation becoming unnecessarily verbose and to facilitate understanding for those skilled in the art.

[0011] The inventors provide the accompanying drawings and the following description so that those skilled in the art may fully understand this disclosure, and not to limit the subject matter described in the claims.

[0012] [First Embodiment] Hereinafter, a semiconductor memory device according to the first embodiment will be described with reference to Figures 1 to 10.

[0013] [Configuration of the First Embodiment] Figure 1 is a block diagram showing an example of the configuration of the host device 10 and SD card 20 according to the first embodiment.

[0014] The host device 10 comprises a host interface (I / F) 11, a host controller 12, a CPU (Central Processing Unit) 13, RAM (Random Access Memory) 14, an SSD (Solid State Drive) 15, a user input device 16, a display device 17, and a communication device 18. The host interface 11 is connected to the card interface 21 (described later) of the SD card 20, and data is transmitted to and received from the SD card 20 via the host interface 11. The host interface 11 includes, for example, a legacy SD interface and / or a PCI Express interface. The host controller 12 controls the writing and reading of data to and from the SD card 20. The host controller 12 includes a processor that executes programs. The CPU 13 executes programs such as an operating system and application programs and controls the operation of the entire host device 10. The RAM 14 temporarily stores programs and data necessary for the operation of the host device 10. The SSD 15 stores programs and data necessary for the operation of the host device 10. The user input device 16 receives user input to control the operation of the host device 10. The user input device 16 includes, for example, a keyboard and / or a pointing device. The display device 17 displays the status of the host device 10. The communication device 18 is connected to the server device via a communication line, as will be described later in relation to the second embodiment, and acquires control information for the SD card 20 from the server device.

[0015] The host device 10 is an example of an information processing device. The host device 10 includes, for example, industrial equipment such as digital signage, surveillance cameras, log recording devices, robots, machine tools, and IoT (Internet of Things) devices, as well as personal computers, tablet terminals, smartphones, digital cameras, etc.

[0016] The SD card 20 comprises a card interface (I / F) 21, a card controller 22, and NAND flash memory 23. The card interface 21 is connected to the host interface 11 of the host device 10, and data is transmitted to and received from the host device 10 via the card interface 21. The card interface 21 includes, but is not limited to, a legacy SD interface and / or a PCI Express interface. The card controller 22 controls the operation of the entire SD card 20, and in particular controls the writing and reading of data to and from the NAND flash memory 23. The NAND flash memory 23 stores the data transmitted to or received from the host device 10.

[0017] The card controller 22 comprises a processor 31, a buffer memory 32, and a NAND controller 33. The processor 31 executes programs. The buffer memory 32 temporarily stores data to be written to or read from the NAND flash memory 23. The NAND controller 33 controls the writing and reading of data to and from the NAND flash memory 23.

[0018] The card controller 22 further includes a register 31a inside or outside the processor 31. The register 31a stores control information for the SD card 20. The control information includes a pattern selector for determining which of a predetermined number of patterns the access history of the SD card 20 by the host device 10 corresponds to. The pattern selector includes, for example, a model that has been pre-machine-trained based on a plurality of access histories. In this case, the pattern selector may be stored in the register 31a as a set of weight coefficients for each node of the neural network. Alternatively, the pattern selector may be stored in the register 31a as a program that includes instructions for determining which of the plurality of patterns the access history corresponds to when executed by the processor 31. The control information also includes control parameters for writing to and reading from the NAND flash memory 23, and includes a plurality of sets of control parameters associated with each of the plurality of patterns. The control parameters include, for example, at least one of the following parameters.

[0019] - The size of the data stored in the buffer memory 32 of the SD card 20. - The unit of data written to the NAND flash memory 23. - The address of the data written to the NAND flash memory 23. - The frequency of writing data from the buffer memory 32 to the NAND flash memory 23. - The frequency of moving data written to the NAND flash memory 23 within the NAND flash memory 23.

[0020] Each of the multiple sets of control parameters is set to have improved performance with respect to a predetermined metric compared to controlling writes and reads to the NAND flash memory 23 according to other control parameters, when the access history has a pattern associated with that control parameter. The predetermined metric may include, for example, the total bytes written (TBW) of the NAND flash memory 23, and / or the write speed and read speed of the NAND flash memory 23. Each of the multiple sets of control parameters may be set to have optimized performance when the access history has a pattern associated with that control parameter.

[0021] Figure 3 shows an example of a pattern selector 41 used by the card controller 22 of the SD card 20 in Figure 1. The pattern selector 41 is configured to determine which of a predetermined number of patterns A to C the access history X to the SD card 20 by the host device 10 corresponds to, that is, which one matches or is similar to. Each of the multiple sets of control parameters A to C is set to have improved or optimized performance when the access history X has a pattern associated with that control parameter.

[0022] The SD card 20 is an example of a semiconductor memory device. The NAND flash memory 23 is an example of a semiconductor memory element. The register 31a is an example of a non-volatile memory. The pattern selector and control parameters may be stored in the NAND flash memory 23 instead of the register 31a, in which case the NAND flash memory 23 is an example of a non-volatile memory.

[0023] The functions of each component of the host device 10 and the SD card 20 are not limited to being realized by a single physical element, but may be realized by a number of elements having different locations and / or characteristics depending on the function.

[0024] [Operation of the First Embodiment] A semiconductor memory device, such as an SD card, has different access patterns (or characteristics) depending on its usage, for example, depending on the type of information processing device to which the semiconductor memory device is connected. When the access pattern changes, the degradation process of the semiconductor memory element changes. Therefore, the lifespan of the semiconductor memory device can be extended by setting different control parameters according to the access pattern.

[0025] Typically, the control parameters of semiconductor memory devices are set to operate well in general usage scenarios that do not anticipate specific access patterns; in other words, to operate in a balanced manner across multiple usage scenarios. For example, if the information processing device is a consumer device, the semiconductor memory device is used as removable media. In this case, depending on the usage, such as writing and reading data or moving data between devices, the information processing device accesses the semiconductor memory device with various access patterns, for example, with various data sizes and / or various write addresses. On the other hand, if the information processing device is industrial equipment, the semiconductor memory device is used simply as media that is not inserted or removed. In this case, the information processing device often accesses the semiconductor memory device with specific access patterns, for example, with a fixed data size and / or a nearly fixed write address. In other words, the usage of the semiconductor memory device is limited, and the semiconductor memory device often operates with specific access patterns. Therefore, as mentioned above, by setting different control parameters according to the access pattern, the lifespan of the semiconductor memory device can be extended compared to using control parameters set to operate in a balanced manner across multiple usage scenarios. However, manufacturing multiple types of semiconductor memory devices, each with customized control parameters for different types of information processing devices, is not practical from a cost and effort standpoint. Therefore, there is a need for a semiconductor memory device that can operate with a long lifespan regardless of which of the multiple types of information processing devices it is connected to.

[0026] Figure 2 is a flowchart showing an example of card control processing performed by the card controller 22 of the SD card 20 shown in Figure 1.

[0027] In step S1, the card controller 22 observes the access history of the SD card 20 by the host device 10. The access history includes at least the data size for writing and / or reading, and the addresses for writing and / or reading. The access history may further include at least one of the start and end times of writing data to the SD card 20 by the host device 10, and the start and end times of reading data from the SD card 20 by the host device 10. The card controller 22 observes the access history over a predetermined period of time.

[0028] In step S2, the card controller 22 uses the pattern selector 41 to determine which of a predetermined set of patterns the observed access history corresponds to.

[0029] In step S3, the card controller 22 reads the control parameters associated with the determined pattern from register 31a.

[0030] In step S4, the card controller 22 controls writing to and reading from the NAND flash memory 23 according to the control parameters read from the register 31a.

[0031] Next, with reference to Figures 4 to 8, some examples of access history to the SD card 20 by the host device 10 are shown.

[0032] Figure 4 shows a first example of the access history to the SD card 20 by the host device 10 in Figure 1. The host device 10 writes write data W1 to W6 to the SD card 20 and reads read data R1 to R5 from the SD card 20. The write data W1 to W6 and read data R1 to R5 have arbitrary addresses A1 to A11 and relatively small arbitrary data sizes B1 to B11.

[0033] Figure 5 shows a second example of the access history to the SD card 20 by the host device 10 in Figure 1. The host device 10 writes write data W21 to W24 to the SD card 20 and reads read data R21 to R24 from the SD card 20. The write data W21 to W24 and the read data R21 to R24 have arbitrary addresses A21 to A28. The write data W21 to W24 have a relatively large data size B21, and the read data R21 to R24 have a relatively small data size B22.

[0034] Figure 6 shows a third example of the access history to the SD card 20 by the host device 10 in Figure 1. The host device 10 writes write data W31 to W34 to the SD card 20 and reads read data R31 from the SD card 20. The write data W31 to W34 have the same address A31, and the read data R31 has address A32. The write data W31 to W34 have the same relatively large data size B31, and the read data R31 has a relatively small data size B32.

[0035] Figure 7 shows a fourth example of the access history to the SD card 20 by the host device 10 in Figure 1. The host device 10 writes the write data W41 and W42 to the SD card 20 and reads the read data R41 to R44 from the SD card 20. The write data W41 and W42 have addresses A41 and A42, and the read data R43 and R44 have the same addresses A41 and A42 as the write data W41 and W42. The read data R41 and R42 have addresses A43 and A44. The write data W41 and W42 and the read data R43 and R44 have a relatively large data size B41, while the read data R41 and R42 have a relatively small data size B42.

[0036] Figure 8 shows a fifth example of the access history to the SD card 20 by the host device 10 in Figure 1. The host device 10 writes the write data W51 to W54 to the SD card 20 and reads the read data R51 to R54 from the SD card 20. The write data W51 to W54 and the read data R51 to R54 have the same address A51 and the same data size B51.

[0037] The access history of the SD card 20 by the host device 10 may have a pattern different from those shown in Figures 4 to 8. For example, the host device 10 may write one long sequential data to the SD card 20 and then repeatedly read the same data from the SD card 20. Alternatively, the host device 10 may repeatedly write sequential data to the same address on the SD card 20. Furthermore, the host device 10 may write and read small data to and from random addresses on the SD card 20.

[0038] Next, with reference to Figures 9 to 10, the effects of changing control parameters according to the access history will be explained.

[0039] Figure 9 shows the SD card 20 in Figure 1 operating according to the default control parameters. The default control parameters are set to operate in a balanced manner under general usage conditions that do not assume a specific access history pattern. The write data W1 to W6 and read data R1 to R5 in Figure 9 (and Figure 10) are the same as those shown in Figure 4. The card controller 22 temporarily stores the data W1 to W6 written from the host device 10 to the SD card 20 in the buffer memory 32. Next, the card controller 22 writes the data W1 to W6 stored in the buffer memory 32 to the NAND flash memory 23 at a predetermined frequency. Writing to the NAND flash memory 23 is performed, for example, when the size of the data written from the host device 10 to the buffer memory 32 exceeds a threshold, or when the elapsed time since the data was written from the host device 10 to the buffer memory 32 exceeds a threshold. In the example shown in Figure 9, when data is written from the host device 10 to the SD card 20 six times, and data is written from the buffer memory 32 to the NAND flash memory 23 with a period T1, data is written from the buffer memory 32 to the NAND flash memory 23 six times.

[0040] Figure 10 shows the case where the SD card 20 in Figure 1 operates according to control parameters associated with a pattern corresponding to the access history. In the examples shown in Figures 9 and 10, the written data W1 to W6 have a relatively small data size. Therefore, by increasing the size of the data stored in the buffer memory 32 before writing the data to the NAND flash memory 23, that is, by increasing the period of writing data from the buffer memory 32 to the NAND flash memory 23, the number of rewrites of the NAND flash memory 23 can be reduced. In the example of Figure 10, when data is written from the host device 10 to the SD card 20 six times, and data is written from the buffer memory 32 to the NAND flash memory 23 with a period T2 = T1 × 2, the data is written from the buffer memory 32 to the NAND flash memory 23 four times. By reducing the number of rewrites of the NAND flash memory 23, degradation of the SD card 20 is less likely to occur, and the SD card 20 can be used for a long period of time.

[0041] The card controller 22 initially controls writing to and reading from the NAND flash memory 23 according to default control parameters. Next, the card controller 22 determines a pattern corresponding to the access history and then controls writing to and reading from the NAND flash memory 23 according to the control parameters associated with the pattern.

[0042] Instead of changing the period (or frequency) of writing data from the buffer memory 32 to the NAND flash memory 23, the card controller 22 may change other control parameters as described below.

[0043] - Increase the size of the data stored in the buffer memory 32 before writing the data to the NAND flash memory 23. - Change the unit of the data written to the NAND flash memory 23 to match the physical block size of the NAND flash memory 23. - Aggregate the data written to multiple different addresses and write it to the same physical block address. - Change the trigger for writing data from the buffer memory 32 to the NAND flash memory 23. - Change the trigger for moving the data written to the NAND flash memory 23 on the NAND flash memory 23.

[0044] Here, the "trigger" indicates the condition for generating an event. For example, it includes that the size of the data written to the buffer memory 32 or the NAND flash memory 23 exceeds the threshold value, and / or the elapsed time since the data was written to the buffer memory 32 or the NAND flash memory 23 exceeds the threshold value, etc. The card controller 22 may change the threshold value of the data size or the elapsed time as a control parameter.

[0045] The card controller 22 may change one or more of the exemplified control parameters.

[0046] According to the SD card 20 according to the present embodiment, by controlling the writing and reading to the NAND flash memory 23 according to the control parameters associated with the pattern corresponding to the access history, the life of the SD card 20 can be extended more than before. The SD card 20 can operate with a long life even when connected to any of a plurality of types of host devices 10 having different access history patterns.

[0047] For example, in NVMe adopted in SD Express, a method of efficiently accessing by setting an area for random access and an area for sequential access is provided. According to the present embodiment, since the SD card 20 can automatically execute this area setting, the design of the host device 10 can be simplified.

[0048] When the pattern of the access history to the SD card 20 by the host device 10 is known, the pattern of the access history may be specified by the user of the host device 10. In this case, the host controller 12 of the host device 10 acquires a user input for specifying one of a plurality of patterns via the user input device 16, and sends a control signal for specifying one of the plurality of patterns to the SD card 20. The card controller 22 receives a control signal for specifying one of the plurality of patterns from the host device 10. The card controller 22 reads out control parameters associated with the specified pattern from the register 31a. The card controller 22 controls writing to and reading from the NAND flash memory 23 according to the control parameters read out from the register 31a. Thereby, the control parameters can be immediately set without taking time to observe the access history, and writing to and reading from the NAND flash memory 23 can be effectively controlled.

[0049] The time taken to determine the pattern of the access history depends on the result of pre-learning and is affected by, for example, the number of patterns learned by the pattern selector 41. When using a pattern selector 41 that has learned more patterns, it takes a longer time to determine the pattern of the access history. For example, it takes a longer time to determine the pattern of the access history when using a pattern selector 41 that has learned 10 patterns than when using a pattern selector 41 that has learned 2 patterns. Similarly, when the pattern selector 41 learns more patterns, it is necessary to analyze the pattern of the access history in more detail, and thus it takes a longer time to generate the pattern selector 41. The number of patterns learned by the pattern selector 41 may be determined by the user as desired.

[0050] The control parameters may be changed gradually and stepwise from their current values ​​to the values ​​associated with the pattern determined using the pattern selector 41. If the control parameters are changed abruptly, malfunctions may occur in the operation of the SD card 20. For example, if the size of the data stored in the buffer memory 32 is reduced, there is a risk that the data stored in the buffer memory 32 before the control parameters were changed may be discarded. Therefore, the card controller 22 may set one or more intermediate values ​​between the current value of the control parameters and the target value (the value associated with the pattern determined using the pattern selector 41), and change the control parameters stepwise. This makes it less likely for malfunctions to occur in the operation of the SD card 20.

[0051] Instead of setting intermediate values ​​for the control parameters, the card controller 22 may change the control parameters after a series of write and / or read operations on the SD card 20 have been completed.

[0052] [Effects of the First Embodiment] The SD card 20 according to the first embodiment includes a card interface 21 connected to a host device 10, a NAND flash memory 23 for storing data transmitted to or received from the host device 10, and a card controller 22. The SD card 20 further includes a pattern selector 41 for determining which of a plurality of predetermined patterns the access history of the SD card 20 by the host device 10 corresponds to, and a register 31a for storing control parameters for writing to and reading from the NAND flash memory 23, each set of control parameters associated with the plurality of patterns. The card controller 22 observes the access history of the SD card 20 by the host device 10. The card controller 22 uses the pattern selector 41 to determine which of the plurality of patterns the observed access history corresponds to. The card controller 22 reads the control parameters associated with the determined pattern from the register 31a. The card controller 22 controls writing to and reading from the NAND flash memory 23 according to the control parameters read from the register 31a. The access history includes at least the data size and address.

[0053] This configuration makes it possible to provide an SD card 20 with a longer lifespan than conventional cards.

[0054] According to the SD card 20 of the first embodiment, the pattern selector 41 may include a model that has been pre-machine-trained based on a plurality of access histories.

[0055] This configuration allows the SD card 20 to support multiple types of host devices 10, each having different access history patterns, and to operate with a long lifespan regardless of which of the multiple types of host devices 10 it is connected to.

[0056] According to the SD card 20 of the first embodiment, each of the multiple sets of control parameters may be set to have improved performance with respect to a predetermined index compared to when writing to and reading from the NAND flash memory 23 is controlled according to the other control parameters, when the access history has a pattern associated with that control parameter.

[0057] This configuration makes it possible to provide an SD card 20 with improved performance compared to conventional cards.

[0058] According to the SD card 20 of the first embodiment, the set of control parameters may include at least one of the following: the size of the data stored in the buffer memory 32 of the SD card 20, the unit of data written to the NAND flash memory 23, the address of the data written to the NAND flash memory 23, the frequency of writing data from the buffer memory 32 to the NAND flash memory 23, and the frequency of moving data written to the NAND flash memory 23 on the NAND flash memory 23.

[0059] This configuration allows for improving the performance of the SD card 20 using various control parameters.

[0060] According to the SD card 20 of the first embodiment, the card controller 22 may acquire the pattern selector 41 and multiple sets of control parameters from the host device 10 and store them in the register 31a.

[0061] This configuration allows the pattern selector 41 and multiple sets of control parameters stored in the register 31a to be updated even after the SD card 20 has been shipped.

[0062] According to the SD card 20 of the first embodiment, the card controller 22 may receive a control signal from the host device 10 that specifies one of a plurality of patterns. In this case, the card controller 22 reads the control parameters associated with the specified pattern from the register 31a. The card controller 22 controls writing to and reading from the NAND flash memory 23 according to the control parameters read from the register 31a.

[0063] This configuration allows for immediate setting of control parameters without the need to spend time observing access history, and enables effective control of writing to and reading from the NAND flash memory 23.

[0064] According to the SD card 20 of the first embodiment, the access history may further include at least one of the start time and end time of writing and the start time and end time of reading.

[0065] This configuration allows the host device 10 to observe the access history to the SD card 20 with higher accuracy.

[0066] [Second Embodiment] The information processing system according to the second embodiment will be described below with reference to Figures 11 to 15. In the second embodiment, the determination of control information for the SD card 20 will be described.

[0067] [Configuration of the Second Embodiment] Figure 11 is a block diagram showing an example of the configuration of an information processing system according to the second embodiment. The information processing system in Figure 11 includes host devices 10-1 to 10-3, SD cards 20-1 to 20-3, and a server device 50, which are connected to each other via a communication line 60 such as the Internet or a local area network.

[0068] The host devices 10-1 to 10-3 and SD cards 20-1 to 20-3 are configured in the same way as the host device 10 and SD card 20 of the first embodiment. The host devices 10-1 to 10-3 have different access history patterns.

[0069] Hereafter, host devices 10-1 to 10-3 will be collectively referred to as "host device 10," and SD cards 20-1 to 20-3 will be collectively referred to as "SD card 20."

[0070] The server device 50 determines control information for the SD card 20, namely the pattern selector and multiple sets of control parameters. The server device 50 comprises at least a CPU 53, RAM 54, SSD 55, user input device 56, display device 57, and communication device 58. The CPU 53 executes programs such as the operating system and application programs and controls the operation of the entire server device 50. The RAM 54 temporarily stores programs and data necessary for the operation of the server device 50. The SSD 55 stores programs and data necessary for the operation of the server device 50. The SSD 55 stores, for example, configuration information for the SD card 20. The user input device 56 receives user input to control the operation of the server device 50. The user input device 56 includes, for example, a keyboard and / or a pointing device. The display device 57 displays the status of the server device 50. The communication device 58 is connected to host devices 10-1 to 10-3 via a communication line 60.

[0071] The server device 50 may further include a host interface (I / F) 51 and a host controller 52 similar to those of the host device 10 in Figure 1.

[0072] As will be described later, the communication device 58 and the host interface 51 are examples of data input devices for acquiring multiple access histories observed on multiple SD cards 20 from multiple host devices 10, each connected to a multiple SD card 20. At the same time, the communication device 58 and the host interface 51 are examples of data output devices for sending the generated pattern selector and the generated multiple sets of control parameters to the SD card 20.

[0073] The functions of each component of the server device 50 are not limited to being realized by a single physical element, but may be realized by a number of elements having different locations and / or characteristics depending on the function.

[0074] [Operation of the Second Embodiment] Figure 12 is a flowchart showing an example of a card preparation process performed by the CPU 53 of the server device 50 in Figure 11.

[0075] In step S11, the CPU 53 determines a plurality of host devices 10 to which the SD card 20 may be connected. The plurality of host devices 10 have different access history patterns from each other.

[0076] In step S12, the CPU 53 generates a pattern selector by executing a pattern selector generation process.

[0077] In step S13, the CPU 53 generates multiple sets of control parameters by executing a control parameter generation process.

[0078] In step S14, the CPU 53 sends the generated pattern selector and generated control parameters to the SD card 20. The CPU 53 sends the pattern selector and control parameters to the host device 10 via the communication device 58 and the communication line 60, and the host device 10 writes the pattern selector and control parameters to the SD card 20. The card controller 22 retrieves the pattern selector and multiple sets of control parameters from the host device 10 and stores them in the register 31a. The SD card 20 has an application programming interface (API) that can be used by the host device 10 to write the pattern selector and multiple sets of control parameters to the register 31a.

[0079] Furthermore, if the SD card 20 is connected to the host interface 51 of the server device 50, the CPU 53 may write the pattern selector and control parameters to the SD card 20 via the host controller 52 and the host interface 51. Also, when a new SD card is manufactured, the CPU 53 may send the pattern selector and control parameters to the manufacturing equipment, and the manufacturing equipment may write the pattern selector and control parameters to the SD card 20.

[0080] Figure 13 is a flowchart showing the subroutine for the pattern selector generation process (step S12) in Figure 12.

[0081] In step S21, the CPU 53 selects one of the multiple host devices 10.

[0082] In step S22, the CPU 53 obtains multiple observed access histories to the SD card 20 from the selected host device 10. At this time, the SD card 20 is operating according to default control parameters. The card controller 22 observes the access history to the SD card 20 by the host device 10 for a predetermined time period and a predetermined number of times. The host device 10 obtains the observed access history from the SD card 20. The SD card 20 has APIs available to the host device 10 for starting access history observation, ending access history observation, and obtaining the observed access history. The CPU 53 obtains the access history from the host device 10 via the communication line 60 and the communication device 58.

[0083] Alternatively, after observing the access history of the SD card 20 by the host device 10, the SD card 20 may be connected to the host interface 51 of the server device 50. In this case, the CPU 53 obtains the access history from the SD card 20 via the host controller 52 and the host interface 51.

[0084] In step S23, the CPU 53 performs machine learning based on the observed access history and trains a model. The machine learning may include training a convolutional neural network or a recurrent neural network based on images of the access history, such as those shown in Figures 4 to 8. Alternatively, the machine learning may include training a model based on text data representing the access history. The CPU 53 may generate multiple trained models based on the same access history. In this case, the CPU 53 calculates the accuracy of the models along with their accuracy.

[0085] In step S24, the CPU 53 determines whether or not the model has been trained for all host devices. If the answer is YES, the process proceeds to step S26; otherwise, it proceeds to step S25.

[0086] In step S25, the CPU 53 selects another host device 10 and returns to step S22.

[0087] In step S26, the CPU 53 determines the model with the highest accuracy rate as the pattern selector based on the accuracy rates of the trained models.

[0088] According to the pattern selector generation process shown in Figure 13, the CPU 53 generates a pattern selector by performing machine learning based on multiple access histories. The pattern selector can identify multiple patterns corresponding to multiple host devices 10.

[0089] Figure 14 is a flowchart showing the subroutine for the control parameter generation process (step S13) in Figure 12.

[0090] In step S31, the CPU 53 acquires a plurality of patterns included in the pattern selector generated in step S12 (i.e., identified by the pattern selector).

[0091] In step S32, the CPU 53 obtains configuration information for the SD card 20 from the SSD 55 or from another external storage device. The configuration information for the SD card 20 includes, for example, at least some of the following:

[0092] - Cell type (SLC (single memory cell), MLC (multilevel cell), TLC (triple memory cell), QLC (quad-level cell), etc.) - Number of layers, page size, erase block size, ECC (error-correcting code) function level, and write time (programming time) if the NAND flash memory 23 has a 3D structure

[0093] In step S33, the CPU 53 generates multiple sets of control parameters, each containing various combinations of values ​​within the configurable range of the control parameters, based on the configuration information of the SD card 20.

[0094] In step S34, the CPU 53 selects one of several patterns.

[0095] In step S35, the CPU 53 selects one set of control parameters from among multiple sets of control parameters.

[0096] In step S36, the CPU 53 performs a simulation of the SD card's behavior according to the control parameters and estimates the TBW of the SD card 20. Alternatively or additionally, the CPU 53 may estimate other performance indicators of the SD card 20, such as the write and read speeds of the NAND flash memory 23.

[0097] In step S37, the CPU 53 determines whether or not it has performed a simulation for all control parameters. If the answer is YES, it proceeds to step S39; otherwise, it proceeds to step S38.

[0098] In step S38, the CPU 53 selects another set of control parameters and returns to step S36. The CPU 53 may gradually change the control parameters in order to find the optimal set of control parameters.

[0099] In step S39, the CPU 53 determines the optimal control parameters. If one indicator is estimated in step S36, the control parameters corresponding to the minimum TBW, or the control parameters corresponding to the fastest write and read speeds, are determined as the optimal values. If multiple indicators are estimated in step S36, for example, the control parameters that result in TBW being less than or equal to a first threshold, and the write and read speeds being greater than or equal to a second threshold, are determined as the optimal values.

[0100] In step S40, the CPU 53 determines whether or not it has calculated the control parameters for all access history. If the answer is YES, it proceeds to step S14 in Figure 12; otherwise, it proceeds to step S41 in Figure 14.

[0101] In step S41, the CPU 53 selects another pattern and returns to step S35.

[0102] According to the control parameter generation process shown in Figure 14, the CPU 53 generates multiple sets of control parameters by simulating the behavior of the SD card 20 based on the multiple patterns included in the generated pattern selector and the configuration information of the SD card 20.

[0103] As explained with reference to Figures 12 to 14, according to this embodiment, control information for the SD card 20, namely the pattern selector and multiple sets of control parameters, can be determined. The CPU 53 generates the pattern selector and multiple sets of control parameters based on multiple access histories to the SD card 20 by multiple types of host devices 10. By writing the control information determined in this way to the SD card 20, an SD card 20 with a longer lifespan than conventional cards can be provided.

[0104] The generated pattern selector and multiple sets of control parameters may be sent to the SD card 20 used to observe the access history acquired in step S22 of Figure 13, or alternatively, to another SD card 20.

[0105] The control information of the SD card 20 may be updated while the SD card 20 is in use. In this case, the information processing system includes at least one host device 10, at least one SD card 20, and a server device 50, and the CPU 53 of the server device 50 performs the card update process shown in Figure 15.

[0106] Figure 15 is a flowchart showing an example of a card update process executed by the CPU 53 of the server device 50 in Figure 11.

[0107] Steps S51 to S53 in Figure 15 are the same as steps S22, S23, and S26 in Figure 13. Steps S54 to S60 in Figure 15 are the same as steps S32, S33, and S35 to S39 in Figure 14. Step S61 in Figure 15 is the same as step S14 in Figure 12.

[0108] According to the card update process in Figure 15, the server device 50 operates as follows: The communication device 58 obtains the current access history observed on the SD card 20 from the host device 10. The CPU 53 regenerates the pattern selector and multiple sets of control parameters based on the current access history. The communication device 58 sends the regenerated pattern selector and multiple sets of control parameters to the SD card 20. This allows the control information of the SD card 20 to be updated while the SD card 20 is in use. For example, even if the operation of the host device 10 changes during use and the access history pattern changes, the lifespan of the SD card 20 can be extended compared to conventional methods.

[0109] [Effects of the Second Embodiment] The server device 50 according to the second embodiment determines the control information of the SD card 20. The server device 50 includes a data input device that acquires multiple access histories observed on each of the multiple SD cards 20 from multiple host devices 10 each connected to the multiple SD cards 20, a CPU 53 that generates a pattern selector 41 and multiple sets of control parameters based on the multiple access histories, and a data output device that sends the generated pattern selector 41 and the generated multiple sets of control parameters to the SD card 20.

[0110] This configuration allows for the determination of control information for the SD card 20.

[0111] According to the server device 50 of the second embodiment, the CPU 53 may generate a pattern selector 41 by performing machine learning based on a plurality of access histories.

[0112] This configuration makes it possible to generate a pattern selector 41 that identifies multiple patterns corresponding to multiple host devices 10.

[0113] According to the server device 50 of the second embodiment, the CPU 53 may generate multiple sets of control parameters by performing a simulation of the behavior of the SD card 20 based on the multiple patterns included in the generated pattern selector 41 and the configuration information of the SD card 20.

[0114] This configuration allows for the generation of multiple sets of control parameters, each corresponding to a different pattern.

[0115] The information processing system according to the second embodiment includes an SD card 20, a host device 10, and a server device 50. The communication device 58 obtains the current access history observed on the SD card 20 from the host device 10. The CPU 53 regenerates the pattern selector 41 and multiple sets of control parameters based on the current access history. The communication device 58 sends the regenerated pattern selector 41 and multiple sets of control parameters to the SD card 20.

[0116] This configuration allows the control information of the SD card 20 to be updated while the SD card 20 is in use.

[0117] [Other Embodiments] As described above, the first and second embodiments have been explained as examples of the technology disclosed in this application. However, the technology in this disclosure is not limited thereto and can be applied to embodiments that are modified, replaced, added, or omitted as appropriate.

[0118] Furthermore, attached drawings and a detailed description are provided to illustrate the embodiments. Therefore, the components described in the attached drawings and detailed description may include not only components essential for solving the problem, but also components that are not essential for solving the problem, in order to illustrate the above technology. For this reason, the mere presence of such non-essential components in the attached drawings or detailed description should not be immediately assumed to mean that those non-essential components are essential.

[0119] Furthermore, since the embodiments described above are for illustrative purposes of the technology described herein, various modifications, substitutions, additions, omissions, etc., can be made within the scope of the claims or equivalents thereof.

[0120] If the control information of the SD card 20 is not updated after the SD card 20 is shipped, the card controller 22 does not need to have an API available to the host device 10 to start observing the access history, end the observation of the access history, and acquire the observed access history.

[0121] The embodiments described above are not limited to SD cards and corresponding host devices, but are applicable to any semiconductor storage device and corresponding information processing device.

[0122] [Summary of Embodiments] A semiconductor memory device according to a first aspect of the present disclosure is a semiconductor memory device comprising: an interface connected to an information processing device; a semiconductor memory element storing data transmitted to or received by the information processing device; and a first controller, wherein the semiconductor memory device further comprises a non-volatile memory for storing control information of the semiconductor memory device, the control information includes: a pattern selector for determining which of a plurality of predetermined patterns the access history of the semiconductor memory device by the information processing device corresponds to; and a plurality of sets of control parameters for writing to and reading from the semiconductor memory element, each set of control parameters associated with the plurality of patterns, the first controller observes the access history of the semiconductor memory device by the information processing device, determines which of the plurality of patterns the observed access history corresponds to using the pattern selector, reads the control parameters associated with the determined pattern from the non-volatile memory, and controls writing to and reading from the semiconductor memory element according to the control parameters read from the non-volatile memory, the access history includes at least the data size and address.

[0123] According to a semiconductor memory device according to a second aspect of the present disclosure, in the semiconductor memory device according to the first aspect, the pattern selector includes a model that has been pre-machine-trained based on a plurality of access histories.

[0124] According to a semiconductor memory device of a third aspect of the present disclosure, in a semiconductor memory device of a first or second aspect, each of the plurality of control parameters is set to have improved performance with respect to a predetermined index compared to when writing to and reading from the semiconductor memory element is controlled according to other control parameters, when the access history has a pattern associated with the control parameter.

[0125] According to a semiconductor memory device according to a fourth aspect of the present disclosure, in a semiconductor memory device according to one of the first to third aspects, the plurality of control parameters include at least one of the following: the size of data stored in the buffer memory of the semiconductor memory device; the unit of data written to the semiconductor memory element; the address of the data written to the semiconductor memory element; the frequency of writing data from the buffer memory to the semiconductor memory element; and the frequency of moving data written to the semiconductor memory element on the semiconductor memory element.

[0126] According to a semiconductor memory device according to a fifth aspect of the present disclosure, in a semiconductor memory device according to one of the first to fourth aspects, the first controller acquires the pattern selector and the plurality of control parameters from the information processing device and stores them in the non-volatile memory.

[0127] According to a semiconductor memory device according to a sixth aspect of the present disclosure, in a semiconductor memory device according to one of the first to fifth aspects, the first controller receives a control signal from the information processing device that specifies one of the plurality of patterns, reads control parameters associated with the specified pattern from the non-volatile memory, and controls writing to and reading from the semiconductor memory element according to the control parameters read from the non-volatile memory.

[0128] According to the seventh aspect of this disclosure, in the semiconductor memory device according to one of the first to sixth aspects, the semiconductor memory device is an SD card.

[0129] According to the eighth aspect of the present disclosure, in a semiconductor memory device according to one of the first to seventh aspects, the access history further includes at least one of the start and end times of writing and the start and end times of reading.

[0130] According to the ninth aspect of the present disclosure, the server device is for determining control information for a semiconductor memory device according to one of the first to eighth aspects, and comprises: a data input device that acquires a plurality of access histories observed in a plurality of semiconductor memory devices from a plurality of information processing devices each connected to a plurality of semiconductor memory devices; a second controller that generates the pattern selector and the plurality of sets of control parameters based on the plurality of access histories; and a data output device that sends the generated pattern selector and the generated plurality of sets of control parameters to the semiconductor memory device.

[0131] According to the semiconductor memory device according to the tenth aspect of the present disclosure, in the server device according to the ninth aspect, the second controller generates the pattern selector by performing machine learning based on the plurality of access histories.

[0132] According to the semiconductor memory device according to the eleventh aspect of the present disclosure, in a server device according to the ninth or tenth aspect, the second controller generates the plurality of control parameters by performing a simulation of the behavior of the semiconductor memory device based on the plurality of patterns included in the generated pattern selector and the configuration information of the semiconductor memory device.

[0133] An information processing system according to a twelfth aspect of the present disclosure is an information processing system comprising: a semiconductor memory device according to one of the first to eighth aspects; an information processing device connected to the semiconductor memory device and for writing and reading data to and from the semiconductor memory device; and a server device according to one of the ninth to eleventh aspects, wherein the data input device obtains the current access history observed in the semiconductor memory device from the information processing device; the second controller regenerates the pattern selector and the multiple sets of control parameters based on the current access history; and the data output device sends the regenerated pattern selector and the regenerated multiple sets of control parameters to the semiconductor memory device.

[0134] This disclosure is applicable to consumer devices using semiconductor memory devices such as SD cards, and is also applicable to industrial equipment, including robot control equipment and industrial machinery.

[0135] 10, 10-1 to 10-3 Host device 11 Host interface (I / F) 12 Host controller 13 CPU (Central Processing Unit) 14 RAM (Random Access Memory) 15 SSD (Solid State Drive) 16 User input device 17 Display device 18 Communication device 20, 20-1 to 20-3 SD card 21 Card interface (I / F) 22 Card controller 23 NAND flash memory 31 Processor 31a Register 32 Buffer memory 33 NAND controller 41 Pattern selector 50 Server device 51 Host interface (I / F) 52 Host controller 53 CPU (Central Processing Unit) 54 RAM (Random Access Memory) 55 SSD (Solid State Drive) 56 User input device 57 Display device 58 Communication device 60 Communication line

Claims

1. A semiconductor memory device comprising: an interface connected to an information processing device; a semiconductor memory element for storing data transmitted to or received by the information processing device; and a first controller, wherein the semiconductor memory device further comprises a non-volatile memory for storing control information of the semiconductor memory device, the control information including a pattern selector for determining which of a plurality of predetermined patterns the access history of the semiconductor memory device by the information processing device corresponds to; and a plurality of sets of control parameters for writing to and reading from the semiconductor memory element, each set of control parameters associated with the plurality of patterns, wherein the first controller observes the access history of the semiconductor memory device by the information processing device, determines which of the plurality of patterns the observed access history corresponds to using the pattern selector, reads the control parameters associated with the determined pattern from the non-volatile memory, and controls writing to and reading from the semiconductor memory element according to the control parameters read from the non-volatile memory, the access history including at least the data size and address.

2. The semiconductor memory device according to claim 1, wherein the pattern selector includes a model that has been pre-machine-trained based on a plurality of access histories.

3. The semiconductor memory device according to claim 1, wherein each of the plurality of control parameters is set to have improved performance with respect to a predetermined index compared to when writing to and reading from the semiconductor memory element is controlled according to the other control parameters, when the access history has a pattern associated with the control parameter.

4. The semiconductor memory device according to claim 1, wherein the plurality of control parameters include at least one of the following: the size of data stored in the buffer memory of the semiconductor memory device; the unit of data written to the semiconductor memory element; the address of data written to the semiconductor memory element; the frequency at which data is written from the buffer memory to the semiconductor memory element; and the frequency at which data written to the semiconductor memory element is moved on the semiconductor memory element.

5. The semiconductor memory device according to claim 1, wherein the first controller acquires the pattern selector and the plurality of control parameters from the information processing device and stores them in the non-volatile memory.

6. The semiconductor memory device according to claim 1, wherein the first controller receives a control signal from the information processing device to specify one of the plurality of patterns, reads control parameters associated with the specified pattern from the non-volatile memory, and controls writing to and reading from the semiconductor memory element according to the control parameters read from the non-volatile memory.

7. The semiconductor memory device according to claim 1, wherein the access history further includes at least one of the start time and end time of writing and the start time and end time of reading.

8. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is an SD card.

9. A server device for determining control information of a semiconductor memory device according to one of claims 1 to 8, comprising: a data input device that acquires a plurality of access histories observed in each of the plurality of semiconductor memory devices from a plurality of information processing devices each connected to the plurality of semiconductor memory devices; a second controller that generates the pattern selector and the plurality of sets of control parameters based on the plurality of access histories; and a data output device that sends the generated pattern selector and the generated plurality of sets of control parameters to the semiconductor memory device.

10. The server device according to claim 9, wherein the second controller generates the pattern selector by performing machine learning based on the plurality of access histories.

11. The server device according to claim 9, wherein the second controller generates the plurality of control parameters by performing a simulation of the behavior of the semiconductor memory device based on the plurality of patterns included in the generated pattern selector and the configuration information of the semiconductor memory device.

12. An information processing system comprising: a semiconductor memory device according to claim 1; an information processing device connected to the semiconductor memory device and for writing and reading data to and from the semiconductor memory device; and a server device according to claim 9, wherein the data input device obtains the current access history observed in the semiconductor memory device from the information processing device; the second controller regenerates the pattern selector and the multiple sets of control parameters based on the current access history; and the data output device sends the regenerated pattern selector and the regenerated multiple sets of control parameters to the semiconductor memory device.

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