Method for manufacturing indium-based composite oxide semiconductor layer having preferentially oriented crystallinity, and thin-film transistor including in- based composite oxide semiconductor layer

Abstract

Provided are a method for manufacturing an In-based composite oxide semiconductor layer having preferentially oriented crystallinity, and a thin-film transistor including the In-based composite oxide semiconductor layer. A method of crystallizing an In-based composite oxide semiconductor layer comprises forming an In-based composite oxide semiconductor layer on a substrate, and performing a first heat treatment on the substrate. The first heat treatment breaks metal–oxygen bonds in the In-based composite oxide semiconductor layer while maintaining an amorphous state of the In-based composite oxide semiconductor layer after the first heat treatment. In-based oxide conductor patterns are formed at both ends of the In-based composite oxide semiconductor layer, and a second heat treatment is performed on the substrate to crystallize the In-based oxide conductor patterns so as to have a bixbyite crystal structure. A third heat treatment is performed on the substrate to induce crystallization of the In-based composite oxide semiconductor layer by the crystallized indium-based oxide conductor patterns, thereby crystallizing the In-based composite oxide semiconductor layer so as to be preferentially oriented in a [222] direction.

Description

Method for manufacturing an indium-based composite oxide semiconductor layer having preferentially oriented crystals and a thin-film transistor including an IN-based composite oxide semiconductor layer

[0001] The present invention relates to a semiconductor device, and more specifically, to a transistor having an oxide semiconductor film.

[0002] As for the silicon film used as a semiconductor film for a transistor, either an amorphous silicon film or a polycrystalline silicon film is used depending on the purpose. For example, in the case of transistors included in large display devices, it is preferable to use an amorphous silicon film, which can form relatively uniform characteristics even when formed over a large area. On the other hand, in the case of devices including driving circuits, it is preferable to use a polycrystalline silicon film, which can exhibit high field-effect mobility. As a method for forming the polycrystalline silicon film, methods are known to involve high-temperature heat treatment of the amorphous silicon film or treatment with laser light.

[0003] Recently, research has been conducted on using oxide semiconductors as the channel layer of transistors (JP Publication 2006-165528). However, oxide semiconductor layers are mostly amorphous layers, are known to be electrically and chemically unstable, and are known to be difficult to exhibit sufficient field-effect mobility.

[0004] The problem that the present invention aims to solve is to provide a metal oxide semiconductor layer exhibiting high field-effect mobility and a thin-film transistor having the same.

[0005] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0006] To achieve the above objective, one aspect of the present invention provides a method for crystallizing an In-based composite oxide semiconductor layer. First, an Indium-based composite oxide semiconductor layer is formed on a substrate, and the substrate is subjected to a first heat treatment. The first heat treatment destroys the metal-oxygen bonds within the In-based composite oxide semiconductor layer, but maintains the amorphous state of the In-based composite oxide semiconductor layer after the first heat treatment. In-based oxide conductor patterns are formed on both ends of the In-based composite oxide semiconductor layer, and the substrate is subjected to a second heat treatment to crystallize the In-based oxide conductor patterns to form Bixbyite crystals. The substrate is subjected to a third heat treatment to induce crystallization of the In-based composite oxide semiconductor layer by the crystallized In-based oxide conductor patterns, thereby crystallizing the In-based composite oxide semiconductor layer to be preferentially oriented in the

[0222] direction.

[0007] The above In-based composite oxide semiconductor layer may be a ternary oxide or a quaternary oxide containing other metal elements in addition to indium. The ternary oxide may be In-Ga-O (IGO) or In-Zn-O (IZO). The quaternary oxide may be In-Ga-Zn-O (IGZO) or In-Zn-Sn-O (IZTO).

[0008] The first heat treatment may be performed at a temperature greater than 300°C and less than 500°C. Specifically, the first heat treatment may be performed at a temperature of 350°C to 450°C. The first heat treatment may be performed in an oxygen atmosphere for 0.5 to 2 hours.

[0009] The above In-based oxide conductor patterns may be In-Sn-O (ITO) or In-Zn-O (IZO). The second heat treatment may be performed at a temperature of 180 to 220°C. Even after the second heat treatment, the In-based composite oxide semiconductor layer may maintain an amorphous state.

[0010] Before subjecting the substrate to a third heat treatment, a passivation film covering the crystallized In-based oxide conductor patterns can be formed. The passivation film may be a silicon oxide film.

[0011] The crystallized In-based composite oxide semiconductor layer may have a ratio of the (222) peak intensity to the (400) peak intensity in an XRD (X-ray diffraction) spectrum of 6 to 8. The crystallized In-based oxide conductor pattern and the In-based composite oxide semiconductor layer induced by it may have a lattice mismatch degree of less than 2.5%. The crystallized In-based composite oxide semiconductor layer may have a lower degree of crystallization from the ends in contact with the In-based oxide conductor patterns toward the center. The crystallized In-based composite oxide semiconductor layer may have the outer part of the exposed region between the In-based oxide conductor patterns crystallized first, while the center may remain in an amorphous state.

[0012] To achieve the above objective, one aspect of the present invention provides a method for manufacturing a thin-film transistor. First, a gate electrode is formed on a substrate, and a gate insulating film is formed on the gate electrode. A channel layer, which is an indium-based composite oxide semiconductor layer, is formed on the gate insulating film, and the substrate is subjected to a first heat treatment to break the metal-oxygen bonds within the indium-based composite oxide semiconductor layer while maintaining an amorphous state. Indium-based oxide conductor patterns are formed on both ends of the indium-based composite oxide semiconductor layer, and the substrate is subjected to a second heat treatment to crystallize the indium-based oxide conductor patterns to form Bixbyite crystals. The substrate is subjected to a third heat treatment to induce crystallization of the indium-based composite oxide semiconductor layer by the crystallized indium-based oxide conductor patterns, thereby crystallizing the indium-based composite oxide semiconductor layer to be preferentially oriented in the

[0222] direction.

[0013] The crystallized In-based oxide conductor patterns above may be source / drain electrodes.

[0014] To achieve the above objective, one aspect of the present invention provides a thin-film transistor. The thin-film transistor comprises a gate electrode. An In-based composite oxide semiconductor layer is disposed overlapping the gate electrode, having a Bixbyite crystal, and preferentially oriented in the

[0222] direction. A gate insulating film is disposed between the gate electrode and the In-based composite oxide semiconductor layer. Source and drain electrodes are electrically connected to each other at both ends of the In-based composite oxide semiconductor layer.

[0015] The degree of crystallization of the above In-based composite oxide semiconductor layer may decrease from both ends toward the center. The outer part of the channel region of the above In-based composite oxide semiconductor layer may be crystallized, while the center may remain in an amorphous state.

[0016] The above In-based composite oxide semiconductor layer may have a ratio of the (222) peak intensity to the (400) peak intensity in an XRD (X-ray diffraction) spectrum of 6 to 8. The source / drain electrodes may be In-based oxide conductor patterns crystallized to have Bixbyite crystals. The In-based composite oxide semiconductor layer may be induced crystallized by the crystallized In-based oxide conductor patterns. The crystallized In-based oxide conductor patterns and the In-based composite oxide semiconductor layer induced crystallized by them may have a lattice mismatch degree of less than 2.5%.

[0017] According to embodiments of the present invention, an In-based composite oxide semiconductor layer having a single-crystal-like crystalline structure that is preferentially oriented, and a thin-film transistor including this as a channel layer that exhibits excellent characteristics such as high field-effect mobility can be provided.

[0018] However, the effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below.

[0019] FIGS. 1 to 3 are cross-sectional views illustrating a method for manufacturing a thin-film transistor according to an embodiment of the present invention.

[0020] FIGS. 4a and FIGS. 4b are a cross-sectional view and a top view, respectively, showing that the semiconductor layer is induced crystallized by crystallized In-based oxide conductor patterns.

[0021] FIG. 5 is a perspective view showing a TFT manufactured in any one of the TFT manufacturing examples.

[0022] FIG. 6 is a perspective view showing a specimen prepared in any one of the IGO layer crystallinity evaluation examples.

[0023] FIG. 7 shows XRD (X-ray diffraction) spectra for IGO layers prepared by the methods according to IGO layer crystallinity evaluation examples 1 to 5.

[0024] Figure 8 shows XRD spectra for the IGO layers of TFTs prepared by the methods according to TFT preparation examples 1, 3, and 6.

[0025] Figure 9 shows XRD spectra for the IGO layers of TFTs prepared by the methods according to TFT preparation examples 2, 3, 4, and 5.

[0026] Figure 10 shows scanning electron microscope images of the IGO layers of TFTs according to TFT manufacturing examples 2, 3, 4, and 5, separated by the third heat treatment temperature.

[0027] FIG. 11 shows XRD spectra for IGO layers prepared by the methods according to IGO layer crystallinity evaluation examples 6 to 8.

[0028] FIG. 12 shows a TEM (transmission electron microscopy) image of a cross-sectional plane (AA′) of a TFT (a) obtained in TFT Manufacturing Example 3, a HAADF-STEM (high-angle annular dark field scanning transmission electron microscopy) image, and an FFT (fast Fourier transform) pattern (b) inserted therein.

[0029] Figure 13 is a TEM image of another part of the cross-sectional plane (AA′) of the TFT obtained in TFT Manufacturing Example 3.

[0030] FIG. 14 shows EBSD (electron back scattering diffraction) images (a, b) of an IGO layer obtained according to TFT manufacturing example 3 (with ITO) and IGO layer crystallinity evaluation example 7 (without ITO), and a graph (c) showing the distribution of grain boundaries with respect to the difference in grain orientation (rotation angle) obtained therefrom.

[0031] FIG. 15 is a series of photographs confirming crystallization of samples prepared by performing TFT Manufacturing Example 3, with different third heat treatment times: before (a), 1 minute (b), 30 minutes (c), 1 hour (d), 5 hours (e), and 10 hours (f).

[0032] FIG. 16 is a graph (I) showing the transfer characteristics of the TFT obtained in TFT Manufacturing Example 1. DS -V GS )(a) and graph showing output characteristics (I D -V D )(d), graph showing the transfer characteristics of the TFT obtained in TFT Manufacturing Example 3 (I DS -V GS )(b) and graph showing output characteristics (I D -V D )(e), and a graph showing the transfer characteristics of the TFT obtained in TFT Manufacturing Example 6 (I DS -V GS )(c) and graph showing output characteristics (I D -V D Shows )(f).

[0033] Figure 17 is a graph showing the reliability characteristics of TFTs obtained in TFT manufacturing examples 1, 3, and 6, showing the change in threshold voltage according to stress time in (a) PBS (Positive-Bias Stress), (b) PBTS (Positive-Bias Temperature Stress), (c) NBS (Negative-Bias Stress), and (d) NBTS (Negative-Bias Temperature Stress).

[0034] FIG. 18 shows graphs comparing the mobility (a), SS (b), and threshold voltage (c) of TFTs obtained in TFT manufacturing examples 2, 3, 4, and 5.

[0035] Figure 19 shows XRD graphs of the IGO layers of the TFTs obtained in TFT Manufacturing Example 3, TFT Comparative Example 1, and TFT Comparative Example 2.

[0036] FIG. 20 shows an SEM image showing a cross-section of a portion where a source electrode is stacked on an IGO layer of TFTs obtained in TFT Manufacturing Example 3(a), TFT Comparative Example 1(b), and TFT Comparative Example 2(c), and an FFT (fast Fourier transform) pattern inserted therein.

[0037] Figure 21 shows graphs comparing the mobility (a), SS (b), and threshold voltage (c) of TFTs obtained in TFT Manufacturing Example 3, TFT Comparative Example 1, and TFT Comparative Example 2.

[0038] FIG. 22 shows X-ray diffraction (XRD) spectra for IGZO layers prepared by the methods according to IGZO layer crystallinity evaluation examples 1 to 3.

[0039] FIG. 23 shows XRD spectra for the IGZO layers of TFTs prepared by the methods according to TFT preparation examples 7, 8, and 9.

[0040] Hereinafter, preferred embodiments according to the present invention will be described in more detail with reference to the accompanying drawings in order to explain the present invention more specifically. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. In the drawings, where a layer is referred to as being "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed between them. In these embodiments, "first," "second," or "third" are not intended to impose any limitations on the components, but should be understood merely as terms to distinguish the components.

[0041] In this specification, "preferred orientation" means that most of the thin film has the same crystal plane; in other words, the crystals have grown in the same direction. Specifically, even if the preferentially oriented thin film has multiple crystals, these multiple crystals may have the same crystal plane out of the surface direction of the thin film, and in the cross-sectional direction (in-plane), they may have crystal planes that are different from the surface direction but have the same direction in the cross-sectional direction.

[0042]

[0043] FIGS. 1 to 3 are cross-sectional views illustrating a method for manufacturing a thin-film transistor according to an embodiment of the present invention.

[0044] Referring to FIG. 1, a substrate (10) may be provided. The substrate (10) may be a semiconductor, metal, glass, or polymer substrate. A lower insulating film (20) may be disposed on the substrate (10). The lower insulating film (20) may serve to prevent the inflow of impurities from the substrate (10) or may be an insulating film covering other elements formed on the substrate (10).

[0045] A gate electrode (30) extending in one direction can be formed on the substrate (10). The gate electrode (30) can be formed using Al, Cr, Cu, Ta, Ti, Mo, W, Si, or an alloy thereof. A gate insulating film (40) can be formed on the gate electrode (30). The gate insulating film (40) may be a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or a composite film thereof.

[0046] A semiconductor layer (50) superimposed with the gate electrode (30) can be formed on the gate insulating film (40). The semiconductor layer (50) may be in an amorphous state as deposited as an Indium-based composite oxide layer.

[0047] The In-based composite oxide semiconductor layer may be a ternary oxide or quaternary oxide containing other metal elements in addition to indium, and may be an oxide layer having semiconductor properties by containing In at a concentration of 70 to 85 at%, specifically 75 to 80 at%, relative to the total number of atoms of metal elements. The ternary In-based composite oxide layer may be an In-Ga-O (IGO) layer or an In-Zn-O (IZO) layer, and the quaternary In-based composite oxide layer may be an In-Ga-Zn-O (IGZO) layer or an In-Zn-Sn-O (IZTO) layer.

[0048] The semiconductor layer (50) can be formed using various methods used in the field of technology, for example, by using a physical vapor deposition method such as sputtering or a chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition, and can also be patterned using various methods used in the field of technology. The semiconductor layer (50) can be formed with a thickness of several to tens of nm, for example, a thickness of 5 to 50 nm, for example, a thickness of 10 to 30 nm.

[0049] The semiconductor layer (50) can be heat-treated by performing a first heat treatment on the substrate. The first heat treatment can be performed in an oxygen atmosphere, specifically in air, for 0.5 to 2 hours. Through the first heat treatment, the metal-oxygen bonds within the semiconductor layer (50) are sufficiently destroyed, but the amorphous state in which crystallization does not occur can be maintained. To this end, the temperature of the first heat treatment may be greater than 300 and less than 500°C, specifically 350 to 450°C, more specifically 380 to 420°C, and as an example, 400°C.

[0050] Referring to FIG. 2, In-based oxide conductor patterns (60S, 60D) are formed on both ends of the semiconductor layer (50) to expose a portion of the surface of the semiconductor layer (50) between the In-based oxide conductor patterns (60S, 60D), specifically a channel region, which is an area where the semiconductor layer (50) overlaps with the gate electrode (20). The In-based oxide conductor patterns (60S, 60D) are patterns that are not semiconducting but metallic, and may be a layer containing 88 to 100 at%, specifically 89 to 91 at%, of In relative to the total number of atoms of metal elements. The metallic In-based oxide conductor patterns (60S, 60D) may be an In-Sn-O (ITO) layer or an In-Zn-O (IZO) layer. The above In-based oxide conductor patterns (60S, 60D) may be in an amorphous state as deposited.

[0051] After depositing the above In-based oxide conductor patterns (60S, 60D), the substrate may be subjected to a second heat treatment to crystallize the above In-based oxide conductor patterns (60S, 60D). The second heat treatment may be performed in an oxygen atmosphere, specifically in air, for 0.5 to 2 hours, and the second heat treatment temperature may be 180 to 220°C, specifically 200°C.

[0052] The crystallized In-based oxide conductor patterns (60S, 60D) may have Bixbyite crystals having a {111} crystal plane. Specifically, the crystallized In-based oxide conductor patterns (60S, 60D) may have preferential orientation in the

[0222] direction. Specifically, the source / drain electrodes (60S, 60D), which are metallic In-based composite oxide layers, may have a (222) peak intensity greater than the (400) peak intensity in the XRD (X-ray diffraction) spectrum.

[0053] Even in the second heat treatment process above, the semiconductor layer (50) may remain in an amorphous state without crystallizing.

[0054] Referring to FIG. 3, a passivation film (not shown) can be formed covering the crystallized In-based oxide conductor patterns (60S, 60D) and the semiconductor layer (50 in FIG. 2) exposed between them. The passivation film may be a silicon oxide film. The silicon oxide film can be formed by various methods such as chemical vapor deposition and atomic layer deposition, but as an example, it can be formed using the PEALD (Plasma Enhanced Atomic Layer Deposition) method. The passivation film can be formed to a size of several nm, for example, about 3 to 10 nm.

[0055] After forming the passivation film, the substrate may be subjected to a third heat treatment. The third heat treatment may be performed in an oxygen atmosphere, specifically in air, for 0.5 to 2 hours. During the third heat treatment process, the semiconductor layer (50 in FIG. 2) may be induced to crystallize by the crystallized In-based oxide conductor patterns (60S, 60D) and transformed into a crystallized semiconductor layer (50′).

[0056] FIGS. 4a and FIGS. 4b are a cross-sectional view and a top view, respectively, showing that the semiconductor layer is induced crystallized by crystallized In-based oxide conductor patterns.

[0057] Referring simultaneously to FIG. 3, FIG. 4a and FIG. 4b, the semiconductor layer (50′) induced by these, similar to the crystallized In-based oxide conductor patterns (60S, 60D), may have a Bixbyite crystal having a {111} crystal plane. Specifically, the crystallized semiconductor layer (50′) may have a single-crystal-like crystal structure with preferential orientation in the

[0222] direction. Specifically, the crystallized semiconductor layer (50′) may have a very large ratio of the (222) peak intensity to the (400) peak intensity in the XRD (X-ray diffraction) spectrum ((222) / (400) intensity ratio) of 6 to 8, specifically 7 to 7.5.

[0058] In addition, the crystallized In-based oxide conductor patterns (60S, 60D) and the semiconductor layer (50′) induced by them have a lattice mismatch degree of less than about 2.5%, so the crystallized In-based oxide conductor patterns (60S, 60D) and the crystallized semiconductor layer (50′) can be considered to be in a lattice-matched state.

[0059] Specifically, prior to the third heat treatment, the semiconductor layer (50 in FIG. 2) is in an amorphous state in which the metal-oxygen bonds are sufficiently destroyed. However, during the third heat treatment process, the metal-oxygen bonds within the semiconductor layer (50 in FIG. 2) are rearranged starting from the region adjacent to the crystallized In-based oxide conductor patterns (60S, 60D), and as this rearrangement propagates horizontally into the semiconductor layer, the entire semiconductor layer (50) can be converted into a crystalline, specifically a single-crystal-like crystalline structure having preferential orientation, even at a relatively low temperature. This process may imply that the semiconductor layer (50′) is induced crystallized or epitaxially crystallized in the horizontal direction by the crystallized In-based oxide conductor patterns (60S, 60D). In this way, the induced crystallized semiconductor layer (50′) undergoes crystallization from both ends in contact with the In-based oxide conductor patterns (60S, 60D) toward the center of the semiconductor layer (50′), so the degree of crystallization can be reduced from both ends in contact with the In-based oxide conductor patterns (60S, 60D) toward the center of the semiconductor layer (50′). Additionally, the outer part of the region of the semiconductor layer (50′) exposed between the In-based oxide conductor patterns (60S, 60D), i.e., the channel region, may crystallize first, while the center may remain in an amorphous state.

[0060] In the above third heat treatment process, the semiconductor layer (50′) can be ohmic-bonded to In-based oxide conductor patterns (60S, 60D).

[0061] In-based oxide conductor patterns (60S, 60D) may be source / drain electrodes. However, in another example, after the third heat treatment, the passivation layer and the In-based oxide conductor patterns (60S, 60D) may be removed, and a metal pattern, specifically a metal pattern such as Ta, Ti, W, Mo, etc., may be formed on both ends of the semiconductor layer (50′) to form source / drain electrodes.

[0062] In the example above, a thin-film transistor with a bottom-gate / top-contact structure was described, but it is not limited thereto and can be applied to thin-film transistors with bottom-gate / bottom-contact structures, top-gate / top-contact structures, or top-gate / bottom-contact structures. Here, a top-gate structure refers to a structure in which a metal oxide channel layer overlaps below the gate electrode, and a bottom-gate structure refers to a structure in which source and drain electrodes are electrically connected below the metal oxide channel layer.

[0063]

[0064] Hereinafter, preferred experimental examples are presented to aid in understanding the present invention. However, the following experimental examples are intended only to aid in understanding the present invention, and the present invention is not limited by the following experimental examples.

[0065]

[0066] TFT Manufacturing Examples 1-6

[0067] FIG. 5 is a perspective view showing a TFT manufactured in any one of the TFT manufacturing examples.

[0068] Referring to FIG. 5, a p-type Si wafer (P ++ A 100 nm SiO2 layer was grown on a p-type Si wafer by thermal oxidation of Si. On the SiO2 layer, RF sputtering was performed in an argon atmosphere and a-In was used with a shadow mask. 0.76 Ga 0.24 An IGO semiconductor layer having the composition of O was deposited to a thickness of 20 nm. At this time, the sputtering targets were In2O3 and Ga2O3, the RF power and DC power were 50 W and 70 W, respectively, and the chamber pressure was 3 mTorr. Afterwards, the IGO semiconductor layer was heat-treated in air at the first heat treatment temperature listed in Table 1 below for 1 hour.

[0069] A shadow mask was placed on the heat-treated IGO semiconductor layer, and ITO was deposited using DC sputtering under an Ar atmosphere to form ITO source / drain electrodes with a thickness of 100 nm on both ends of the IGO semiconductor layer. At this time, the DC power was 50 W and the operating pressure was 5 mTorr. The width of the IGO semiconductor layer was 1000 μm, and the length of the IGO semiconductor layer exposed between the source / drain electrodes, i.e., the channel length, was 300 μm. Subsequently, a second heat treatment was performed at 200°C for 1 hour in an air atmosphere to crystallize the ITO source / drain electrodes.

[0070] A 5 nm SiO2 passivation layer was formed on the crystallized ITO source / drain electrodes using the PEALD (Plasma Enhanced Atomic Layer Deposition) method, which involves performing a unit cycle comprising a DIPAS (Di-isopropyl amino Silane) supply / purge / O2 plasma / purge step multiple times. Subsequently, the IGO semiconductor layer was crystallized in an air atmosphere for 1 hour at the third heat treatment temperature listed in Table 1 below.

[0071]

[0072] Examples of IGO layer crystallinity evaluation 1-5

[0073] p-type Si wafer (P ++ A 100 nm SiO2 layer was grown on a p-type Si wafer by thermal oxidation of Si. a-In was grown on the SiO2 layer using RF sputtering in an argon atmosphere. 0.76 Ga 0.24 An IGO layer having the composition of O was deposited to a thickness of 20 nm. At this time, the sputtering targets were In2O3 and Ga2O3, the RF power and DC power were 50 W and 70 W, respectively, and the chamber pressure was 3 mTorr. Afterwards, the IGO layer was heat-treated in air at the first heat treatment temperature listed in Table 1 below for 1 hour.

[0074]

[0075] Examples of IGO layer crystallinity evaluation 6-8

[0076] FIG. 6 is a perspective view showing a specimen prepared in any one of the IGO semiconductor layer crystallinity evaluation examples.

[0077] Referring to FIG. 6, a p-type Si wafer (P ++ A 100 nm SiO2 layer was grown on a p-type Si wafer by thermal oxidation of Si. a-In was grown on the SiO2 layer using RF sputtering in an argon atmosphere. 0.76 Ga 0.24 An IGO layer having the composition of O was deposited to a thickness of 20 nm. At this time, the sputtering targets were In2O3 and Ga2O3, the RF power and DC power were 50 W and 70 W, respectively, and the chamber pressure was 3 mTorr. Subsequently, the IGO layer was heat-treated in air at the first heat treatment temperature listed in Table 1 below for 1 hour. The heat-treated IGO layer was then heat-treated a second time at 200°C for 1 hour in an air atmosphere.

[0078] A 5 nm SiO2 passivation layer was formed on the second heat-treated IGO layer using the PEALD (Plasma Enhanced Atomic Layer Deposition) method, which involves performing a unit cycle comprising the steps of DIPAS (Di-isopropyl amino Silane) supply / purging / O2 plasma / purging multiple times. Subsequently, a third heat treatment was performed at 400°C for 1 hour in an air atmosphere.

[0079] First heat treatment (in air, 1 hour) Second heat treatment (in air, 1 hour) Third heat treatment (in air, 1 hour) IGO layer state TFT Manufacturing Example 1 300 ℃ 200 ℃ 400 ℃ Amorphous TFT Manufacturing Example 2 400 ℃ 200 ℃ 300 ℃ Amorphous TFT Manufacturing Example 3 400 ℃ 200 ℃ 400 ℃ Polycrystalline, (222) Preferential orientation TFT Manufacturing Example 4 400 ℃ 200 ℃ 500 ℃ Polycrystalline, Random orientation TFT Manufacturing Example 5 400 ℃ 200 ℃ 600 ℃ Polycrystalline, Random orientation TFT Manufacturing Example 6 500 ℃ 200 ℃ 400 ℃ Polycrystalline, Random orientation IGO layer crystallinity evaluation example 1 300 ℃ -- Amorphous IGO layer crystallinity evaluation example 2 400 ℃--Amorphous IGO layer crystallinity evaluation example 3450 ℃--Polycrystalline, (222) preferentially oriented IGO layer crystallinity evaluation example 4500 ℃--Polycrystalline, (222) preferentially oriented IGO layer crystallinity evaluation example 5600 ℃--Polycrystalline, randomly oriented IGO layer crystallinity evaluation example 6300 ℃ 200 ℃ 400 ℃ Amorphous IGO layer crystallinity evaluation example 7400 ℃ 200 ℃ 400 ℃ Amorphous IGO layer crystallinity evaluation example 8500 ℃ 200 ℃ 400 ℃ Polycrystalline, randomly oriented

[0080] FIG. 7 shows X-ray diffraction (XRD) spectra for IGO layers prepared by the methods according to IGO layer crystallinity evaluation examples 1 to 5, FIG. 8 shows XRD spectra for IGO layers of TFTs prepared by the methods according to TFT manufacturing examples 1, 3, and 6, FIG. 9 shows XRD spectra for IGO layers of TFTs prepared by the methods according to TFT manufacturing examples 2, 3, 4, and 5, and FIG. 11 shows XRD spectra for IGO layers prepared by the methods according to IGO layer crystallinity evaluation examples 6 to 8. In addition, Table 2 below summarizes the characteristics of the IGO layers obtained from the XRD spectra of the IGO layers of TFTs prepared by the methods according to TFT manufacturing examples 1 to 6 and the IGO layers prepared by the methods according to IGO layer crystallinity evaluation examples 1 to 8.

[0081] IGO Layer State Intensity (222) / (400)(222) Peak Area Percentage (%) Texture Coefficient (TC222) Vertical Grain Size (nm) TFT Manufacturing Example 1 Amorphous----TFT Manufacturing Example 2 Amorphous----TFT Manufacturing Example 3 Polycrystalline, (222) Preferred Orientation 7.048 3.72 % 2.88 16.03 nm TFT Manufacturing Example 4 Polycrystalline, Random Orientation 1.1945 % 1.22 10.13 nm TFT Manufacturing Example 5 Polycrystalline, Random Orientation 3.055 0.97 % 1.98 13.03 nm TFT Manufacturing Example 6 Polycrystalline, Random Orientation 1.245 % 1.23 10.13 nm IGO Layer Crystallinity Evaluation Example 1 Amorphous----IGO Layer Crystallinity Evaluation Example 2 Amorphous----IGO Layer Crystallinity Evaluation Example 3 Polycrystalline, (222) preferred orientation 10.766 1.4 % 2.52 13.28 IGO layer crystallinity evaluation example 4 Polycrystalline, (222) preferred orientation 6.747 9.82 % 2.73 12.71 IGO layer crystallinity evaluation example 5 Polycrystalline, random orientation 1.524 7.63 % 1.53 11.53 IGO layer crystallinity evaluation example 6 Amorphous----IGO layer crystallinity evaluation example 7 Amorphous----IGO layer crystallinity evaluation example 8 Polycrystalline, random orientation 1.24 49 % 1.35 12.65 nm

[0082] Referring to FIG. 7, when the first heat treatment temperature, which is the heat treatment immediately after forming the IGO layer, is 450 degrees or higher (IGO layer crystallinity evaluation examples 3 to 5), crystal peaks are observed in the IGO layer, so it can be seen that the IGO layer crystallizes when the first heat treatment temperature is 450 degrees or higher. On the other hand, when the first heat treatment temperature is 400 degrees or lower (IGO layer crystallinity evaluation examples 1 and 2), crystal peaks are not observed in the IGO layer, so it can be seen that the IGO layer is in an amorphous state when the first heat treatment temperature is less than 450 degrees, specifically 400 degrees or lower. Referring to FIG. 8 and Table 2, when a first heat treatment at 300, 400, or 500°C, a second heat treatment at 200°C, and a third heat treatment at 400°C are performed as in TFT Manufacturing Examples 1, 3, and 6, it can be seen that when the first heat treatment is at 300°C (TFT Manufacturing Example 1), no crystal peaks are observed in the IGO layer, indicating that it is in an amorphous state. On the other hand, when the first heat treatment is at 400°C (TFT Manufacturing Example 3), crystal peaks are observed in the IGO layer, indicating that it is crystallized, and the peak of the (222) plane appears very strongly, indicating that it is preferentially oriented in the

[0222] direction. On the other hand, when the first heat treatment is at 500°C (TFT Manufacturing Example 6), various crystal planes are detected, indicating that the IGO layer is in a randomly oriented polycrystalline state having crystals arranged in random crystal directions.

[0083] Referring simultaneously to FIGS. 7 and FIGS. 8, immediately after the first heat treatment in TFT Manufacturing Examples 1 and 3 is performed at 300°C or 400°C, the IGO layer is in an amorphous state, as with reference to IGO layer crystallinity evaluation Examples 1 and 2. After the second heat treatment at 200°C and the third heat treatment at 400°C are performed, the IGO layer in TFT Manufacturing Example 1, where the first heat treatment was performed at 300°C, remains in an amorphous state, whereas in TFT Manufacturing Example 3, where the first heat treatment was performed at 400°C, the peak of the (222) plane appears very strongly, indicating preferential orientation in the

[0222] direction. Meanwhile, immediately after the first heat treatment in TFT Manufacturing Example 6 is performed at 500°C, the IGO layer is in a crystalline state preferentially oriented in the

[0222] direction, as with reference to IGO layer crystallinity evaluation Example 4. However, it can be seen that after the second heat treatment at 200°C and the third heat treatment at 400°C are performed, the IGO layer changes into a randomly oriented polycrystalline state.

[0084] From this, in order for the IGO layer to become a crystalline state with preferential orientation, it may be desirable to perform a heat treatment immediately after forming the IGO layer at a temperature greater than 300°C and less than 500°C, specifically at 350°C to 450°C, more specifically at 320°C to 430°C, so that the IGO layer remains in an amorphous state while being sufficiently heat-treated.

[0085]

[0086] Referring to Figure 9 and Table 3, when a first heat treatment at 400°C, a second heat treatment at 200°C, and a third heat treatment at 300, 400, 500, or 600°C are performed as in TFT manufacturing examples 2, 3, 4, and 5, it can be seen that when the third heat treatment is at 300°C (TFT manufacturing example 2), no crystal peak is observed in the IGO layer, indicating that it is in an amorphous state. Meanwhile, when the third heat treatment is at 400, 500, or 600°C (TFT Manufacturing Examples 3, 4, and 5), crystal peaks are observed in the IGO layer, indicating crystallization. When the third heat treatment is at 400°C (TFT Manufacturing Example 3), the peak of the (222) plane appears very strongly, and the (222) / (400) peak ratio appears to be 5 or more, specifically 7 or more, indicating preferential orientation in the

[0222] direction. When the third heat treatment is at 500 or 600°C (TFT Manufacturing Examples 4 and 5), the peak of the (222) plane is relatively weak, that is to say, the (222) / (400) peak ratio is lower than 5, so it can be understood that it has a randomly oriented polycrystalline structure.

[0087] FIG. 10 shows scanning electron microscope images of the IGO layers of TFTs according to TFT manufacturing examples 2, 3, 4, and 5, classified by the third heat treatment temperature. In FIG. 10, SE means secondary electron image, and BSE means backscattered electron image.

[0088] Referring to FIG. 10, in the case of TFT Manufacturing Example 2 (third heat treatment temperature 300 °C), no crystal peaks were observed in the IGO layer, indicating an amorphous state, and in the case of TFT Manufacturing Examples 3, 4, and 5 (third heat treatment temperature 400, 500, or 600 °C), grain boundaries were confirmed on the surface of the IGO layer, indicating a polycrystalline state. However, referring to FIG. 9, it was estimated that the IGO layer of TFT Manufacturing Example 3 had a number of crystals preferentially oriented in the (222) direction, and the IGO layers of TFT Manufacturing Examples 4 and 5 had a number of crystals randomly oriented.

[0089]

[0090] Referring simultaneously to FIG. 8 and FIG. 11, in the case where the first heat treatment at 300°C, the second heat treatment at 200°C, and the third heat treatment at 400°C were performed without ITO stacking in IGO layer crystallinity evaluation example 6, the IGO layer appears to be in an amorphous state, similar to the case where the first heat treatment at 300°C, the second heat treatment at 200°C, and the third heat treatment at 400°C were performed with ITO stacking in TFT manufacturing example 1; and in the case where the first heat treatment at 500°C, the second heat treatment at 200°C, and the third heat treatment at 400°C were performed without ITO stacking in IGO layer crystallinity evaluation example 8, the IGO layer appears to be in a randomly oriented polycrystalline state, similar to the case where the first heat treatment at 500°C, the second heat treatment at 200°C, and the third heat treatment at 400°C were performed with ITO stacking in TFT manufacturing example 6, etc., the first heat treatment When heat-treated at 300 or 500°C, a similar state of the IGO layer was exhibited regardless of whether the ITO layer was stacked.

[0091] Meanwhile, in the case of the first heat treatment at 400°C in Evaluation Example 7, the second heat treatment at 200°C without stacking ITO, and the third heat treatment at 400°C were performed, and no crystal peaks appeared other than the crystal peaks of the Si substrate, indicating an amorphous state. On the other hand, in the case of the first heat treatment at 400°C, the second heat treatment at 200°C without stacking ITO, and the third heat treatment at 400°C were performed, as previously observed, crystal peaks were observed in the IGO layer, indicating crystallization, and the peaks of the (222) plane appeared very strongly, indicating preferential orientation in the

[0222] direction. Compared to Evaluation Example 7 of the IGO layer crystallization, in TFT Manufacturing Example 3, the crystallization of IGO was promoted due to the ITO that was crystallized at a temperature of 200°C during the third heat treatment at 400°C; specifically, it can be seen that the crystallization of IGO was induced by the crystallized ITO.

[0092]

[0093] FIG. 12 shows a TEM (transmission electron microscopy) image of a cross-section (AA′) of a TFT (a) obtained in TFT Manufacturing Example 3, a HAADF-STEM (high-angle annular dark field scanning transmission electron microscopy) image, and an FFT (fast Fourier transform) pattern (b) inserted therein. FIG. 13 is a TEM image of another part of the cross-section (AA′) of a TFT obtained in TFT Manufacturing Example 3.

[0094] Referring to FIGS. 12 and 13, it can be seen that both the ITO layer and the IGO layer have an indium bixbyite crystal structure and are preferentially oriented in the (222) direction. Additionally, the IGO layer has the same crystal lattice and crystallographic orientation as the ITO layer and has nearly identical lattice constants, indicating that the IGO layer is lattice-matched to the ITO layer. This suggests that the crystallized ITO layer acts as a template layer to induce crystallization or epitaxial crystallization of the IGO layer.

[0095]

[0096] FIG. 14 shows EBSD (electron back scattering diffraction) images (a, b) of an IGO layer obtained according to TFT manufacturing example 3 (with ITO) and IGO layer crystallinity evaluation example 7 (without ITO), and a graph (c) showing the distribution of grain boundaries with respect to the difference in grain orientation (rotation angle) obtained therefrom.

[0097] Referring to Fig. 14, it can be seen that the grain size of the IGO layer is larger when crystallization of IGO is induced by crystallized ITO (with ITO) compared to when it is not, and that it is equipped with low angle grain boundaries (LAGBs) in which the difference in orientation between grains is mainly distributed at 2-5 degrees and overall distributed at 15 degrees or less.

[0098] FIG. 15 shows photographs confirming crystals of samples prepared by performing TFT Manufacturing Example 3, with different times for the third heat treatment (a), 1 minute (b), 30 minutes (c), 1 hour (d), 5 hours (e), and 10 hours (f). Here, crystal growth was confirmed by etching the samples using Secco etchant (HF: K2Cr2O7 = 2:1), and crystals grown within the channel region were indicated in a bright color.

[0099] Referring to FIG. 15, it can be seen that as the third heat treatment time increases, crystals within the IGO layer grow from the portion overlapping with ITO towards the center of the channel region. From this, it can be seen that the IGO layer is induced to crystallize horizontally by the ITO layer. In addition, when the third heat treatment is performed for 1 hour as in TFT Manufacturing Example 3, it can be seen that the outer part of the channel region crystallizes first, while the center remains in an amorphous state.

[0100]

[0101] Table 3 below shows the characteristics of the TFTs obtained in TFT manufacturing examples 1 to 6.

[0102] IGO layer state μFEμSATSSVTHTFT Preparation Example 1 Amorphous 50.8 ± 848.1 ± 11.90.1 ± 0.02-1.22 ± 0.14TFT Preparation Example 2 Amorphous metallic metallic metallic metallicTFT Preparation Example 3 Polycrystalline, (222) preferred orientation 152.9 ± 23.8149.4 ± 27.30.1 ± 0.01-1.18 ± 0.25TFT Preparation Example 4 Polycrystalline, random orientation 36.232.720.85-1.84TFT Preparation Example 5 Polycrystalline, random orientation 42.0841.241.09-14.72TFT Preparation Example 6 Polycrystalline, random orientation 36.7 ± 1.111.8 ± 0.250.6 ± 0.040.96 ± 0.1

[0103] FIG. 16 is a graph (I) showing the transfer characteristics of the TFT obtained in TFT Manufacturing Example 1. DS -VGS )(a) and graph showing output characteristics (I D -V D )(d), graph showing the transfer characteristics of the TFT obtained in TFT Manufacturing Example 3 (I DS -V GS )(b) and graph showing output characteristics (I D -V D )(e), and a graph showing the transfer characteristics of the TFT obtained in TFT Manufacturing Example 6 (I DS -V GS )(c) and graph showing output characteristics (I D -V D Figure 17 shows the reliability characteristics of TFTs obtained in TFT manufacturing examples 1, 3, and 6, and shows the change in threshold voltage according to stress time in (a) PBS (Positive-Bias Stress), (b) PBTS (Positive-Bias Temperature Stress), (c) NBS (Negative-Bias Stress), and (d) NBTS (Negative-Bias Temperature Stress).

[0104] Referring to FIG. 16 and Table 3, the TFT according to TFT Manufacturing Example 3, in which the first heat treatment was performed at 400 ℃, has an IGO layer that is induced crystallized in the third heat treatment and is 152.9 cm 2 It exhibits excellent characteristics, such as high mobility of / Vs and SS characteristics of 0.1 V / decade. However, the TFT according to TFT Manufacturing Example 1, in which the first heat treatment was performed at 300 ℃, has an IGO layer in an amorphous state, and the TFT according to TFT Manufacturing Example 6, in which the first heat treatment was performed at 500 ℃, has an IGO layer that is crystallized by simple thermal energy and exhibits a randomly oriented polycrystalline structure, thus exhibiting inferior characteristics compared to the TFT according to TFT Manufacturing Example 3.

[0105] Referring to Fig. 17, the TFT according to TFT Manufacturing Example 3 exhibits excellent reliability characteristics, and it was found that the reliability characteristics are also improved when the channel layer is crystallized by induced crystallization.

[0106] FIG. 18 shows graphs comparing the mobility (a), SS (b), and threshold voltage (c) of TFTs obtained in TFT manufacturing examples 2, 3, 4, and 5.

[0107] Referring to Fig. 18, it can be seen that the TFT according to TFT Manufacturing Example 3, when the third heat treatment time is 400 ℃, exhibits the best electrical characteristics, and that as the third heat treatment time increases, the deterioration of the characteristics occurs.

[0108]

[0109] TFT Comparative Example 1

[0110] A TFT was manufactured using the same method as in TFT Manufacturing Example 3, except that a shadow mask was placed on an IGO semiconductor layer that was heat-treated at 400 ℃ and tungsten (W) was deposited using DC sputtering under an Ar atmosphere to form tungsten (W) source / drain instead of ITO source / drain.

[0111]

[0112] TFT Comparative Example 2

[0113] A TFT was manufactured using the same method as in TFT Manufacturing Example 3, except that a shadow mask was placed on an IGO semiconductor layer that was heat-treated at 400 ℃ and molybdenum (Mo) was deposited using DC sputtering under an Ar atmosphere to form molybdenum (Mo) source / drain instead of ITO source / drain.

[0114]

[0115] Figure 19 shows XRD graphs of the IGO layers of the TFTs obtained in TFT Manufacturing Example 3, TFT Comparative Example 1, and TFT Comparative Example 2.

[0116] Referring to FIG. 19, it can be seen that the IGO layer of the TFT obtained in TFT Manufacturing Example 3 exhibits an indium bixviite crystal structure preferentially oriented in the (222) direction, and the IGO layer of the TFTs obtained in TFT Comparative Example 1 and TFT Comparative Example 2 exhibits an amorphous structure.

[0117]

[0118] FIG. 20 shows an SEM image showing a cross-section of a portion where a source electrode is stacked on an IGO layer of TFTs obtained in TFT Manufacturing Example 3(a), TFT Comparative Example 1(b), and TFT Comparative Example 2(c), and an FFT (fast Fourier transform) pattern inserted therein.

[0119] Referring to FIG. 20, the IGO layer of TFT Manufacturing Example 3 exhibits an indium bixviite crystal structure preferentially oriented in the (222) direction, whereas the IGO layer of TFT Comparative Example 1 and TFT Comparative Example 2 exhibits an amorphous structure.

[0120] Referring to Figures 19 and 20 simultaneously, it can be seen that the IGO layer of TFT Manufacturing Example 3 is induced crystallized by the crystallized ITO layer. The degree of lattice mismatch of the IGO layer with respect to the ITO layer is very small at 2.35%, so it can be understood that the IGO layer is epitaxially crystallized with respect to the ITO layer and lattice-matched.

[0121]

[0122] Figure 21 shows graphs comparing the mobility (a), SS (b), and threshold voltage (c) of TFTs obtained in TFT Manufacturing Example 3, TFT Comparative Example 1, and TFT Comparative Example 2.

[0123] Referring to FIG. 21, it can be seen that the TFT according to TFT Manufacturing Example 3, which applies ITO source / drain, exhibits the best electrical characteristics.

[0124]

[0125] TFT Manufacturing Examples 7-9

[0126] p-type Si wafer (P ++ A 100 nm SiO2 layer was grown on a p-type Si wafer by thermal oxidation of Si. On the SiO2 layer, RF sputtering was performed in an argon atmosphere and a-In was used with a shadow mask. 0.77 Ga 0.13 Zn 0.1 An IGZO channel layer having the composition of O was deposited to a thickness of 20 nm. At this time, the sputtering targets were In2O3, Ga2O3, and ZnO2, the RF, DC1, and DC2 powers were 50 W, 30 W, and 10 W, respectively, and the chamber pressure was 3 mTorr. Afterward, the IGZO channel layer was heat-treated in air for 1 hour at the first heat treatment temperature listed in Table 4 below. In this way, a TFT was manufactured using the same method as TFT Manufacturing Example 3, except that an IGZO channel layer was formed instead of an IGO semiconductor layer and the first heat treatment temperature was different.

[0127]

[0128] Examples of IGZO layer crystallinity evaluation 1-3

[0129] p-type Si wafer (P ++ A 100 nm SiO2 layer was grown on a p-type Si wafer by thermal oxidation of Si. a-In was grown on the SiO2 layer using RF sputtering in an argon atmosphere. 0.77 Ga 0.13 Zn 0.1 An IGZO channel layer having the composition of O was deposited to a thickness of 20 nm. At this time, the sputtering targets were In2O3, Ga2O3, and ZnO2, the RF, DC1, and DC2 powers were 50 W, 30 W, and 10 W, respectively, and the chamber pressure was 3 mTorr. Afterwards, the IGZO channel layer was heat-treated in air at the first heat treatment temperature listed in Table 4 below for 1 hour.

[0130]

[0131] 1st heat treatment (in air, 1 hour) 2nd heat treatment (in air, 1 hour) 3rd heat treatment (in air, 1 hour) IGZO layer state TFT Manufacturing Example 7 300 ℃ 200 ℃ 400 ℃ Polycrystalline, (222) preferential orientation TFT Manufacturing Example 8 400 ℃ 200 ℃ 400 ℃ Polycrystalline, (222) preferential orientation TFT Manufacturing Example 6 500 ℃ 200 ℃ 400 ℃ Polycrystalline, (222) preferential orientation IGO layer Crystallinity Evaluation Example 1 300 ℃ -- Amorphous IGO layer Crystallinity Evaluation Example 2 400 ℃ -- Amorphous IGO layer Crystallinity Evaluation Example 3 500 ℃ -- Polycrystalline, (222) preferential orientation

[0132] FIG. 22 shows X-ray diffraction (XRD) spectra for IGZO layers prepared by the methods according to IGZO layer crystallinity evaluation examples 1 to 3, and FIG. 23 shows XRD spectra for IGZO layers of TFTs prepared by the methods according to TFT preparation examples 7, 8, and 9. Referring to FIG. 22, it can be seen that the IGZO layer crystallizes to have an indium bixbyite structure only at temperatures above 500 degrees.

[0133] However, referring to FIG. 23, it can be seen that even if the IGZO layer is heat-treated for the first time at 300 or 400 degrees, the IGZO layer is induced to crystallize to have an indium bixviite structure by the ITO layer crystallized at 200 degrees.

[0134] This study was conducted as a result of the research project for the Information and Communications Broadcasting Innovation Talent Development (Artificial Intelligence Semiconductor Advanced Talent Development) of the Ministry of Science and ICT and the Institute of Information and Communications Planning and Evaluation (IITP-(2025)-RS-2023-00253914).

[0135]

[0136] Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and changes are possible by those skilled in the art within the technical spirit and scope of the present invention.

Claims

1. A step of forming an indium-based composite oxide semiconductor layer on a substrate, and performing a first heat treatment on the substrate to destroy metal-oxygen bonds within the indium-based composite oxide semiconductor layer while maintaining an amorphous state; A step of forming In-based oxide conductor patterns on both ends of the above In-based composite oxide semiconductor layer, and crystallizing the In-based oxide conductor patterns to have Bixbyite crystals by performing a second heat treatment on the substrate; and A method for crystallizing an In-based composite oxide semiconductor layer, comprising the step of induced crystallization of the In-based composite oxide semiconductor layer by the crystallized In-based oxide conductor patterns by heat-treating the substrate a third time, thereby crystallizing the In-based composite oxide semiconductor layer so as to preferentially orient it in the [222] direction.

2. In Paragraph 1, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the above In-based composite oxide semiconductor layer is a ternary oxide or quaternary oxide containing other metal elements in addition to indium.

3. In Paragraph 2, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the above-mentioned ternary oxide is In-Ga-O (IGO) or In-Zn-O (IZO).

4. In Paragraph 2, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the above-mentioned quaternary oxide is In-Ga-Zn-O (IGZO) or In-Zn-Sn-O (IZTO).

5. In Paragraph 1, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the first heat treatment is performed at a temperature greater than 300°C and less than 500°C.

6. In Paragraph 5, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the first heat treatment is performed at a temperature of 350 to 450°C.

7. In Paragraph 1, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the first heat treatment is performed in an oxygen atmosphere for 0.5 to 2 hours.

8. In Paragraph 1, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the above In-based oxide conductor patterns are In-Sn-O (ITO) or In-Zn-O (IZO).

9. In Paragraph 1, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the second heat treatment is performed at a temperature of 180 to 220°C.

10. In Paragraph 1, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the In-based composite oxide semiconductor layer maintains an amorphous state even after the second heat treatment.

11. In Paragraph 1, A method for crystallizing an In-based composite oxide semiconductor layer, further comprising the step of forming a passivation film covering the crystallized In-based oxide conductor patterns before performing a third heat treatment on the substrate.

12. In Paragraph 11, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the above passivation film is a silicon oxide film.

13. In Paragraph 1, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the crystallized In-based composite oxide semiconductor layer has a ratio of the (222) peak intensity to the (400) peak intensity in an XRD (X-ray diffraction) spectrum of 6 to 8.

14. In Paragraph 1, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the crystallized In-based oxide conductor pattern and the In-based composite oxide semiconductor layer induced by the same have a lattice mismatch degree of less than 2.5%.

15. In Paragraph 1, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the crystallization degree of the crystallized In-based composite oxide semiconductor layer decreases from the two ends in contact with the In-based oxide conductor patterns toward the center.

16. In Paragraph 1, A method for crystallizing an In-based composite oxide semiconductor layer, wherein the outer portion of the region exposed between the In-based oxide conductor patterns is crystallized first and the center remains in an amorphous state.

17. A step of forming a gate electrode on a substrate and forming a gate insulating film on the gate electrode; A step of forming an indium-based composite oxide semiconductor layer on the gate insulating film, and performing a first heat treatment on the substrate to destroy the metal-oxygen bonds within the indium-based composite oxide semiconductor layer while maintaining an amorphous state; A step of forming In-based oxide conductor patterns on both ends of the above In-based composite oxide semiconductor layer, and crystallizing the In-based oxide conductor patterns to have Bixbyite crystals by performing a second heat treatment on the substrate; and A method for manufacturing a thin film transistor, comprising the step of performing a third heat treatment on the substrate to induce crystallization of the In-based composite oxide semiconductor layer by the crystallized In-based oxide conductor patterns, thereby crystallizing the In-based composite oxide semiconductor layer so as to preferentially orient it in the [222] direction.

18. In Paragraph 17, A method for manufacturing a thin-film transistor in which the crystallized In-based oxide conductor patterns are source / drain electrodes.

19. Gate electrode; An In-based composite oxide semiconductor layer that overlaps with the gate electrode and has a Bixbyite crystal and is preferentially oriented in the [222] direction; A gate insulating film disposed between the gate electrode and the In-based composite oxide semiconductor layer; and A thin-film transistor comprising source and drain electrodes electrically connected to each of the two ends of the above-mentioned In-based composite oxide semiconductor layer.

20. In Paragraph 19, The above In-based composite oxide semiconductor layer is a thin-film transistor in which the degree of crystallinity decreases from both ends toward the center.

21. In Paragraph 19, The above In-based composite oxide semiconductor layer is a thin-film transistor in which the outer portion of the channel region between the above In-based oxide conductor patterns is crystallized and the center remains in an amorphous state.

22. In Paragraph 19, The above In-based composite oxide semiconductor layer is a thin-film transistor in which the ratio of the (222) peak intensity to the (400) peak intensity in the XRD (X-ray diffraction) spectrum is 6 to 8.

23. In Paragraph 19, The above source / drain electrodes are thin-film transistors in which In-based oxide conductor patterns crystallized to have Bixbyite crystals.

24. In Paragraph 23, The In-based composite oxide semiconductor layer is induced crystallized by the crystallized In-based oxide conductor patterns above, forming a thin-film transistor.

25. In Paragraph 24, A thin-film transistor having a crystallized In-based oxide conductor pattern and an In-based composite oxide semiconductor layer induced by the same, wherein the lattice mismatch degree is less than 2.5%.

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