Semiconductor package and manufacturing method therefor

Abstract

The present invention relates to a semiconductor package, which comprises: a substrate including a first build-up substrate layer and a second build-up substrate layer stacked from at least a portion of the upper surface of the first build-up substrate layer; at least one connecting structure disposed on the first build-up substrate layer; and a plurality of semiconductor chips disposed on the second build-up substrate layer and the connecting structure.

Description

Semiconductor package and method of manufacturing the same

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same, and more specifically, to a semiconductor package and a method for manufacturing the same that can simplify the manufacturing process and reduce manufacturing costs.

[0002] A semiconductor chip refers to an integrated circuit composed of semiconductors, which have electrical conductivity higher than insulators but lower than conductors.

[0003] Typically, after a semiconductor chip is separated from a wafer, which is a single-crystal substrate, a type of packaging process is required. This is intended to protect the chip from physical shock and to mitigate the difference in integration density between the chip and the substrate on which it will be mounted, thereby increasing ease of mounting. The resulting packaged semiconductor chip is called a semiconductor package.

[0004] Multiple semiconductor chips can be mounted in such semiconductor packages, and depending on the arrangement of the mounted semiconductor chips, they can be classified into 2D, 2.5D, 3D, etc. Among these, a 2.5D semiconductor package refers to a package in which logic chips are arranged horizontally and memory chips are stacked vertically.

[0005] In addition, in a 2.5D semiconductor package, an interposer or a bridge die may be placed between the substrate and the semiconductor chip to increase the connection rate between the substrate and the semiconductor chip (i.e., the die). In such a case, the semiconductor chip is electrically connected to the substrate through the interposer or the bridge die.

[0006] However, conventional interposers or bridge dies have the problem of being somewhat complex to manufacture and disadvantageous in terms of miniaturization of semiconductor packages. Therefore, a method to solve these problems is required.

[0007] The present invention aims to solve the aforementioned problems and other problems. Another objective is to provide a semiconductor package with improved power supply characteristics and signal transmission characteristics, and a method for manufacturing the same.

[0008] Another objective is to provide a semiconductor package and a method for manufacturing the same that can simplify the manufacturing process.

[0009] Another objective is to provide a semiconductor package and a method for manufacturing the same that can reduce manufacturing costs.

[0010] According to one aspect of the present invention to achieve the above or other objectives, a semiconductor package is provided comprising: a substrate including a first build-up substrate layer and a second build-up substrate layer laminated from at least one portion of the upper surface of the first build-up substrate layer; one or more connecting structures disposed on the first build-up substrate layer; and a plurality of semiconductor chips disposed on the second build-up substrate layer and the connecting structures.

[0011] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, comprising the steps of: creating a first build-up substrate layer through a first build-up manufacturing process; creating a second build-up substrate layer on at least one portion of the upper surface of the first build-up substrate layer through a second build-up manufacturing process; arranging a plurality of connecting structures on the first build-up substrate layer; coating a molding member on the first build-up substrate layer, the second build-up substrate layer, and the connecting structures; removing a portion of the molding member so that the second build-up substrate layer and the connecting structures are exposed to the outside; and mounting a plurality of semiconductor chips on the second build-up substrate layer and the connecting structures.

[0012] The effects of the semiconductor package and the method for manufacturing the same according to the embodiments of the present invention are described as follows.

[0013] According to at least one of the embodiments of the present invention, by replacing a plurality of fillers formed on a substrate of a conventional semiconductor package with a part of the substrate, it is possible to achieve miniaturization of the semiconductor package and, furthermore, to reduce manufacturing costs by simplifying the manufacturing process of the semiconductor package.

[0014] In addition, according to at least one of the embodiments of the present invention, by stacking a second build-up substrate layer on the upper surface of a first build-up substrate layer through a partial build-up manufacturing process, the power supply characteristics and signal transmission characteristics of the semiconductor package can be improved, and the manufacturing process of the semiconductor package can be simplified to reduce manufacturing costs.

[0015] The technical effects achieved through the present invention are not limited to those mentioned above, and other technical effects not mentioned will be clearly understood by those skilled in the art to which the present invention belongs from the description below.

[0016] FIG. 1 is a drawing showing the structure of a semiconductor package according to a first embodiment of the present invention;

[0017] FIG. 2 is a drawing illustrating the upper surface pad structure of the second build-up substrate layer illustrated in FIG. 1;

[0018] FIG. 3 is a drawing showing the structure of the connecting structure illustrated in FIG. 1;

[0019] FIG. 4 is a flowchart illustrating a method for manufacturing a semiconductor package according to a first embodiment of the present invention;

[0020] FIGS. 5a to 5h are drawings referenced to explain a method for manufacturing a semiconductor package according to a first embodiment of the present invention;

[0021] FIG. 6 is a drawing showing the structure of a semiconductor package according to a second embodiment of the present invention;

[0022] FIG. 7 is a drawing showing the structure of a semiconductor package according to a third embodiment of the present invention;

[0023] FIG. 8 is a diagram showing the structure of a semiconductor package according to a fourth embodiment of the present invention.

[0024] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Identical or similar components regardless of drawing symbols are assigned the same reference number, and redundant descriptions thereof will be omitted. In the following description of embodiments according to the present invention, where each layer (film), region, pattern, or structure is described as being formed "on" or "under" of a substrate, each layer (film), region, pad, or pattern, "on" and "under" include both being formed "directly" and "indirectly" through another layer. Furthermore, the reference for the "on" or "under" of each layer is described based on the drawings. In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically depicted for convenience and clarity of explanation. Also, the size of each component does not entirely reflect its actual size. Identical drawing symbols refer to identical components.

[0025] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them. Furthermore, in this specification, terms such as "comprising" or "having" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0026] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0027] In addition, when describing the embodiments disclosed in this specification, if it is determined that a detailed description of related prior art may obscure the essence of the embodiments disclosed in this specification, such detailed description is omitted. Furthermore, the attached drawings are intended only to facilitate understanding of the embodiments disclosed in this specification, and the technical concept disclosed in this specification is not limited by the attached drawings; it should be understood that the drawings include all modifications, equivalents, and substitutions that fall within the spirit and technical scope of the invention.

[0028] The present invention proposes a semiconductor package with improved power supply characteristics and signal transmission characteristics, and a method for manufacturing the same. Furthermore, the present invention proposes a semiconductor package and a method for manufacturing the same that can simplify the manufacturing process. Additionally, the present invention proposes a semiconductor package and a method for manufacturing the same that can reduce manufacturing costs.

[0029]

[0030] Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings.

[0031] FIG. 1 is a drawing showing the structure of a semiconductor package according to a first embodiment of the present invention, FIG. 2 is a drawing illustrating the upper surface pad structure of a second build-up substrate layer shown in FIG. 1, and FIG. 3 is a drawing showing the structure of a connecting structure shown in FIG. 1.

[0032] Referring to FIGS. 1 to 3, a semiconductor package (100) according to a first embodiment of the present invention may include a substrate (110), a connecting structure (120), a molding member (130), a reinforcing plate (140), a semiconductor chip (150), and an external connection member (160). Since the components illustrated in FIG. 1 are not essential for implementing the semiconductor package, the semiconductor package described herein may have more or fewer components than those listed above.

[0033] The substrate (110) can perform the role of mounting various electronic components. The substrate (110) may be a printed circuit board (PCB), a flexible PCB substrate, an IC substrate, etc., but is not necessarily limited thereto. In the following embodiment, the use of a PCB substrate as the substrate (110) will be described as an example.

[0034] The printed circuit board (110) may be formed from an organic PCB, a glass PCB, or a plastic PCB. The printed circuit board (110) may include a wiring circuit for electrical connection between electronic components.

[0035] Electronic components such as integrated circuits, passive components, active components, or switches may be mounted or embedded in the printed circuit board (110). For example, resistors, integrated passive devices (IPDs), power management integrated circuits (PMICs), etc. may be mounted or embedded in the printed circuit board (110).

[0036] A printed circuit board (110) can be produced through a plurality of build-up manufacturing processes. Here, the build-up manufacturing process is a manufacturing process that processes as many layers as are required by repeating the process of forming a circuit after laminating and compressing a layer of copper foil and an insulator on a double-sided board, and then laminating and compressing a copper foil and an insulator on top of it to form a circuit.

[0037] The printed circuit board (110) may include a first build-up substrate layer (basic build-up substrate layer, 111) and a second build-up substrate layer (partial build-up substrate layer, 112).

[0038] The first build-up substrate layer (111) may include a plurality of first sublayers generated through a first build-up manufacturing process (i.e., a general build-up manufacturing process). A second build-up substrate layer (112), a connecting structure (120), and a molding member (130) may be disposed on the upper portion of the first build-up substrate layer (111).

[0039] Each first sublayer may include a first wiring circuit and a first insulating material coated on the first wiring circuit. Here, the first wiring circuit may be formed of a conductive metal material such as copper (Cu), silver (Ag), gold (Au), or aluminum (Al).

[0040] The first insulating material may be formed from an insulating material different from that of the molding member (130). Additionally, the first insulating material may be formed from an insulating material different from that of the insulating materials of the connecting structure (120). For example, glass, plastic, organic material, polymer material, PI (Polyimide), etc. may be used as the first insulating material, but are not necessarily limited thereto.

[0041] The first build-up substrate layer (111) can be electrically connected to a semiconductor chip (150) located on top of the connecting structure (120) through the connecting structure (120). Power and signals can be transmitted between the first build-up substrate layer (111) and the semiconductor chip (150).

[0042] The first build-up substrate layer (111) can be electrically connected to a semiconductor chip (150) located on top of the second build-up substrate layer (112) through the second build-up substrate layer (112). Power and signals can be transmitted between the first build-up substrate layer (111) and the semiconductor chip (150).

[0043] The second build-up substrate layer (112) may be partially formed in at least a portion of the upper surface of the first build-up substrate layer (111). The second build-up substrate layer (112) may be formed to extend vertically from the upper surface of the first build-up substrate layer (111). The second build-up substrate layer (112) may be formed integrally with the first build-up substrate layer (111).

[0044] The second build-up substrate layer (112) may be disposed between connecting structures (120) arranged in a horizontal direction. The height of the second build-up substrate layer (112) may be formed to be equal to or slightly lower than the height of the connecting structure (120). The upper surface of the second build-up substrate layer (112) and the upper surface of the connecting structure (120) may be formed to be located on the same plane.

[0045] The second build-up substrate layer (112) may include a plurality of second sublayers generated through a second build-up manufacturing process (i.e., a partial build-up manufacturing process). Here, the number of stacked second sublayers may vary depending on the height of the connecting structure (120).

[0046] A semiconductor chip (150) may be disposed on the upper portion of the second build-up substrate layer (112). At this time, the cross-sectional area of ​​the second build-up substrate layer (112) may be formed to have a width smaller than the cross-sectional area of ​​the semiconductor chip (150).

[0047] Each second sublayer may include a second wiring circuit and a second insulating material coated on the second wiring circuit. Here, the second wiring circuit may be formed of the same material as the first wiring circuit of the first build-up substrate layer (111). Additionally, the second insulating material may be formed of the same material as the first insulating material of the first build-up substrate layer (111).

[0048] The second wiring circuit can electrically connect the first build-up substrate layer (111) and the semiconductor chip (150). To this end, the second wiring circuit may include a plurality of conductive structures extending vertically from the upper surface of the first build-up substrate layer (111). The cross-sections of the conductive structures may be formed in a predetermined shape (e.g., circular, elliptical, square, rectangular, etc.). The conductive structures may be formed to have the same width.

[0049] A plurality of connection pads (115) electrically connected to the second wiring circuit may be formed on the upper portion of the second build-up substrate layer (112). A solder ball or a solder bump may be additionally formed on the connection pads (115).

[0050] A plurality of connection pads (115) formed on the upper surface of the second build-up substrate layer (112) may have a uniform shape, size, and spacing between pads. For example, as shown in FIG. 2 (a) and (b), a plurality of connection pads (115) may be formed as circular shapes of the same size, and each pad may be arranged at a uniform interval. In this case, each connection pad (115) is connected one-to-one with a conductive structure.

[0051] Meanwhile, the plurality of connection pads (115) may be formed with different pad sizes and spacing between pads in two or more different ways. For example, as shown in (c) of FIG. 2, the plurality of connection pads (115) may be formed in different sizes and arranged with different spacing between each pad.

[0052] Additionally, the plurality of connection pads (115) may be formed with different shapes, sizes, and spacing between pads in two or more different ways. For example, as shown in (d) of FIG. 2, the plurality of connection pads (115) may be formed with different shapes and sizes, such as circular, elliptical, rectangular, straight, or L-shaped, and each pad may be arranged at different spacings. In this case, some of the plurality of connection pads (115) are connected one-to-one with one conductive structure, and the rest are connected one-to-many with two or more conductive structures.

[0053] By supplying power through at least two of a plurality of conductive structures, power can be supplied through another conductive structure even if one conductive structure is defective. Additionally, by transmitting the same signal through at least two of a plurality of conductive structures, the corresponding signal can be transmitted through another conductive structure even if one conductive structure is defective. Through this, power supply characteristics and signal transmission characteristics can be improved.

[0054] A connecting structure (120) may be disposed on one side of the first build-up substrate layer (111). A single or multiple connecting structures (120) may be disposed within the semiconductor package (100).

[0055] The connecting structure (120) may be positioned adjacent to the second build-up substrate layer (112). At this time, the connecting structure (120) may be arranged horizontally parallel to the second build-up substrate layer (112). The height of the connecting structure (120) may be formed to be the same as or slightly higher than the height of the second build-up substrate layer (112).

[0056] The connecting structure (120) can be formed from a silicon wafer, a capacitor, an active die, a memory die, or an integrated passive device (IPD), etc.

[0057] The connecting structure (120) can be mounted on the first build-up substrate layer (111) in a flip-chip structure. After the connecting structure (120) is mounted on the first build-up substrate layer (111), an underfill may be filled.

[0058] The connecting structure (120) can be formed to enable electrical connection in the horizontal direction. Additionally, the connecting structure (120) can be formed to enable electrical connection in the vertical direction.

[0059] For example, the connecting structure (120) may include a wiring layer (30), a conductive layer (20) disposed on top of the wiring layer (30), and a plurality of connecting members (i.e., bumps, 40) disposed on the bottom of the wiring layer (30).

[0060] The conductive layer (20) may include a plurality of spaced-apart fillers (21) and a first insulating material (22) coated between the plurality of fillers (21). The wiring layer (30) may include a wiring circuit (31) and a second insulating material (32) coated on the wiring circuit (31). A plurality of connecting members (40) may be configured in the form of metal balls or metal bumps.

[0061] Each filler (21) may be formed from a conductive metal material such as copper (Cu), silver (Ag), gold (Au), or aluminum (Al). The filler (21) may be positioned to be in contact with the semiconductor chip (150) and may be electrically connected to the semiconductor chip (150).

[0062] Each filler (21) may be formed to have a constant height. Additionally, the filler (21) may be formed to have a constant cross-sectional width or to have a cross-sectional width that gradually increases toward the upper direction. For example, the filler (21) may be formed to have a diameter of 5 µm to 100 µm, a height of 10 µm to 50 µm, and a pitch of 10 µm to 150 µm.

[0063] The first and second insulating materials (22, 32) may be formed from dielectric or polymer materials. The polymer materials may include EMC (Epoxy Molding Compound), PI (Polyimide), ABF (Ajinomoto Build-up Film), etc., but are not necessarily limited thereto.

[0064] The wiring circuit (31) can be configured with a higher density than the wiring circuit of the substrate (110). The line / space of the wiring layer (30) can be formed to be 2 µm / 2 µm or less.

[0065] The connecting structure (120) can electrically connect multiple different semiconductor chips (150). At this time, the connecting structure (120) can electrically connect semiconductor chips of the same type or semiconductor chips of different types. To this end, the upper surface of the connecting structure (120) can be formed to be in contact with the multiple semiconductor chips (150). The connecting structure (120) can be electrically connected to the multiple semiconductor chips (150).

[0066] The connecting structure (120) can electrically connect the first build-up substrate layer (111) and the semiconductor chip (150). To this end, the upper surface of the connecting structure (120) may be formed to be in contact with the semiconductor chip (150), and the lower surface of the connecting structure (120) may be formed to be in contact with the first build-up substrate layer (111).

[0067] The structure can be formed to perform direct electrical connection without placing a separate circuit layer or a separate redistribution layer between the lower surface of the semiconductor chip (150) and the upper surface of the connecting structure (120), and between the lower surface of the connecting structure (120) and the upper surface of the first build-up substrate layer (111).

[0068] Meanwhile, although not shown in the drawing, an underfill or a molded underfill (MUF) may be filled under the semiconductor chip (150) mounted on the connecting structure (120).

[0069] The connecting structure (120) is not required to be installed over the entire upper surface of the first build-up substrate layer (111), and it is sufficient to be installed in at least one part of the overlapping area between the first build-up substrate layer (111) and the semiconductor chips (150). In the illustrated embodiment, the total area of ​​the connecting structure (120) may be formed to be smaller than the sum of the areas of the semiconductor chips (150) combined with the connecting structure (120). Accordingly, the installation area of ​​the connecting structure (120) may be further reduced, which has the effect of reducing the manufacturing cost of the connecting structure (120) and the semiconductor package (100).

[0070] In addition, since the installation area of ​​the connecting structure (120) is further reduced, it is advantageous in terms of miniaturization of the connecting structure (120). Therefore, as the space occupied by the connecting structure (120) is reduced, the entire semiconductor package can be miniaturized in a high-performance semiconductor package.

[0071] The molding member (130) is applied to one side of the substrate (110) and can perform the function of electrically insulating components mounted on the substrate (110).

[0072] The molding member (130) may be formed from an insulating material. For example, the molding member (130) may be formed from a dielectric or polymer material. The polymer material may include EMC, PI, ABF, etc., but is not necessarily limited thereto.

[0073] A stiffener (140) may be placed in the edge area of ​​the molding member (130) to improve the mechanical stability of the semiconductor package (100). Meanwhile, although not shown in the drawing, the stiffener (140) may be placed in the edge area of ​​the substrate (110) rather than the edge area of ​​the molding member (130) to improve the mechanical stability of the semiconductor package (100).

[0074] A semiconductor chip (150) may be placed on top of a substrate (110) and a connecting structure (120). More specifically, the semiconductor chip (150) may be placed on top of a second build-up substrate layer (112) and a connecting structure (120).

[0075] A plurality of semiconductor chips (150) may be provided within a semiconductor package (100). The plurality of semiconductor chips (150) have a structure arranged in a horizontal and / or vertical direction. The plurality of semiconductor chips (150) may include one or more logic chips and one or more memory chips. Here, one or more logic chips may be arranged in a horizontal direction, and one or more memory chips may be arranged in a vertical direction.

[0076] A chip connection member (not shown) for electrical connection with a second build-up substrate layer (112) and / or a connecting structure (120) may be formed on the lower surface of the semiconductor chip (150). The upper portion of the chip connection member may be formed by a grinding process.

[0077] Meanwhile, although not shown in the drawing, a first connecting member may be disposed between the semiconductor chip (150) and the connecting structure (120), and a second connecting member may be disposed between the semiconductor chip (150) and the second build-up substrate layer (112). The first and second connecting members may be formed of a conductive metal material. The first and second connecting members may be formed in the shape of a bump. The first and second connecting members serve simply as passages for electrical connection, such as bumps or fillers, and their structure and function differ from those of the wiring layer in which the circuit is formed.

[0078] Additionally, although not shown in the drawing, a heat dissipation die or an active die may be additionally stacked on the upper side of the semiconductor chip (150). When an active die is stacked on the upper side of the semiconductor chip (150), a conductive connection means for electrical connection between the semiconductor chip (150) and the active die may be additionally configured.

[0079] Additionally, although not shown in the drawing, a thermal interface material (TIM) may be additionally laminated on the upper side of the semiconductor chip (150). In this case, the thermal interface material (TIM) may be placed between the semiconductor chip (150) and the heat dissipation die (or active die). Alternatively, the thermal interface material (TIM) may be placed on the upper surface of the heat dissipation die (or active die).

[0080] A heat transfer material (TIM) is placed on top of a semiconductor chip (150) to release heat generated from the semiconductor chip (150) to the outside. To this end, the heat transfer material (TIM) may be formed from a material with high thermal conductivity.

[0081] Through a heat dissipation die and / or a heat transfer material (TIM) placed on the upper side of the semiconductor chip (150), heat generated from the semiconductor chip (150) can be dissipated more easily, and overheating of the semiconductor chip (150) can be prevented. Furthermore, damage to the semiconductor package (100) due to overheating can be prevented, and maintenance costs incurred in the event of semiconductor package damage can also be reduced.

[0082] In addition, as illustrated in the drawing, since multiple semiconductor chips are individually controlled and mounted, there is no need to include a structure and process for wrapping the semiconductor chips with a molding layer or other insulating materials, thereby simplifying the overall process and reducing costs. Furthermore, since the semiconductor chips are handled individually, warpage control is very easy. This is a structural difference and effect resulting from the fact that the package of the present invention handles the semiconductor chips individually, whereas processes such as wafer-level fan-out or TBDB (Temporary Bonding and Debonding), which are widely used in advanced packaging processes, necessarily involve wrapping multiple semiconductor chips at once with EMC (Epoxy Molding Compound).

[0083] Meanwhile, although not illustrated in the drawing, an additional process of wrapping the spaces between and around the semiconductor chips with a specific material can be optionally performed after arranging multiple semiconductor chips. The specific material may be used without limitation and may include EMC, PI (Polyimide), and other insulating materials, as well as materials with high or low thermal conductivity and mixtures thereof. Alternatively, the semiconductor chips may be exposed to the atmosphere without being wrapped with a specific material. In particular, the material to be filled in the space around or between the semiconductor chips can be freely selected according to the thermal characteristics of the semiconductor chips, thereby increasing the freedom of the process and easily improving the thermal characteristics of the entire package.

[0084] The external connection member (160) is attached to the lower surface of the substrate (110) and can perform the function of electrically connecting the substrate (110) and an external member (not shown). The external connection member (160) may be formed in the shape of a solder ball or a metal ball.

[0085] As described above, the semiconductor package (100) according to the first embodiment of the present invention can not only achieve miniaturization of the semiconductor package by replacing a plurality of fillers formed on a substrate of a conventional semiconductor package with a part of the substrate, but also reduce manufacturing costs by simplifying the manufacturing process of the semiconductor package. In addition, the semiconductor package (100) can improve power supply characteristics and signal transmission characteristics of the semiconductor package by stacking a second build-up substrate layer on the upper surface of a first build-up substrate layer through a partial build-up manufacturing process, and also reduce manufacturing costs by simplifying the manufacturing process of the semiconductor package.

[0086]

[0087] FIG. 4 is a flowchart illustrating a method for manufacturing a semiconductor package according to a first embodiment of the present invention, and FIGS. 5a to 5h are drawings referenced to explain a method for manufacturing a semiconductor package according to a first embodiment of the present invention. Although the semiconductor package manufacturing method is described in the illustrated flowchart by dividing it into a plurality of steps, at least some of the steps may be performed in a different order, combined with other steps and performed together, omitted, divided into detailed steps, or performed with one or more steps not illustrated added.

[0088] Referring to FIGS. 4 to 5h, a first build-up substrate layer (111) is created through a first build-up manufacturing process (S410).

[0089] A second build-up manufacturing process (i.e., a partial build-up manufacturing process) is performed on a predetermined area of ​​the upper surface of the first build-up substrate layer (111) to create a second build-up substrate layer (112) (S420). Here, the second build-up substrate layer (112) can be formed integrally with the first build-up substrate layer (111).

[0090] The first and second build-up substrate layers (111, 112) form a single substrate (110). A PCB substrate or an F-PCB substrate may be used as the substrate (110).

[0091] A plurality of connection pads (115) electrically connected to a second wiring circuit can be formed on the upper part of the second build-up substrate layer (112). A solder ball or a solder bump may be additionally formed on the connection pads (115).

[0092] A plurality of connecting structures (120) are mounted on the first build-up substrate layer (111) (S430). At this time, the plurality of connecting structures (120) may be arranged adjacent to the second build-up substrate layer (112). Additionally, the plurality of connecting structures (120) may be arranged side by side in a horizontal direction with respect to the second build-up substrate layer (112).

[0093] A molding member (130) is placed (coated) on the upper portion of the substrate (110) and the plurality of connecting structures (120) (S440). At this time, the molding member (130) is coated to cover the entire substrate (110) and the connecting structures (120).

[0094] When this coating process is completed, a portion of the molding member (130) is removed so that the upper portion of the second build-up substrate layer (112) and the plurality of connecting structures (120) is exposed to the outside (S450). The removal process may be performed through a grinding process and is not necessarily limited thereto.

[0095] A plurality of semiconductor chips (150) are mounted on a second build-up substrate layer (112) and a plurality of connecting structures (120) (S460). The semiconductor chips (150) may be arranged in a horizontal direction and / or a vertical direction.

[0096] A plurality of bumps may be formed on the lower surface of the semiconductor chips (150). The bumps may be formed as irregular bumps to correspond, respectively, to the plurality of connecting members (115) mounted on the second build-up substrate layer (112) and the fillers (21) of the connecting structure (120). More specifically, the plurality of bumps may include high-density bumps directly connected to the conductive layer (20) of the connecting structure (120) and low-density bumps directly connected to the connecting members (115) of the second build-up substrate layer (112).

[0097] Afterwards, a plurality of external connection members (160) are attached to the lower surface of the substrate (110) (S470).

[0098] A semiconductor package (100) according to the first embodiment of the present invention can be formed through the processes described above.

[0099] As described above, the semiconductor package manufacturing method according to the first embodiment of the present invention can not only achieve miniaturization of the semiconductor package by replacing a plurality of fillers formed on a substrate of an existing semiconductor package with a part of the substrate, but also reduce manufacturing costs by simplifying the manufacturing process of the semiconductor package. In addition, the semiconductor package manufacturing method can improve the power supply characteristics and signal transmission characteristics of the semiconductor package by stacking a second build-up substrate layer on the upper surface of a first build-up substrate layer through a partial build-up manufacturing process, and also reduce manufacturing costs by simplifying the manufacturing process of the semiconductor package.

[0100]

[0101]

[0102] FIG. 6 is a diagram showing the structure of a semiconductor package according to a second embodiment of the present invention.

[0103] Referring to FIG. 6, a semiconductor package (600) according to a second embodiment of the present invention may include a substrate (610), a connecting structure (620), a molding member (630), a reinforcing plate (640), a semiconductor chip (650), and an external connection member (660). Since the components illustrated in FIG. 6 are not essential for implementing the semiconductor package, the semiconductor package described herein may have more or fewer components than those listed above.

[0104] The semiconductor package (600) according to the present embodiment may include a second build-up substrate layer (612) having a structure different from the second build-up substrate layer (112) of the semiconductor package (100) according to the first embodiment described above.

[0105] The connecting structure (620), molding member (630), reinforcing plate (640), semiconductor chip (650), and external connection member (660) of the semiconductor package (600) according to the present embodiment are identical to the connecting structure (120), molding member (130), reinforcing plate (140), semiconductor chip (150), and external connection member (160) of the semiconductor package (100) according to the first embodiment described above, so a detailed description thereof is omitted.

[0106] The substrate (610) can be produced through a plurality of build-up manufacturing processes. Here, the build-up manufacturing process is a manufacturing process that processes as many layers as are required by repeating the process of forming a circuit after laminating and compressing a layer of copper foil and an insulator on a double-sided plate, and then laminating and compressing a copper foil and an insulator on top of it to form a circuit.

[0107] The substrate (610) may include a first build-up substrate layer (basic build-up substrate layer, 611) and a second build-up substrate layer (partial build-up substrate layer, 612).

[0108] The first build-up substrate layer (611) may include a plurality of first sublayers generated through a first build-up manufacturing process. Each first sublayer may include a first wiring circuit and a first insulating material coated on the first wiring circuit.

[0109] The first build-up substrate layer (611) can be electrically connected to a semiconductor chip (650) located on top of the connecting structure (620) through a connecting structure (620). Additionally, the first build-up substrate layer (611) can be electrically connected to a semiconductor chip (650) located on top of the second build-up substrate layer (612) through a second build-up substrate layer (612).

[0110] The second build-up substrate layer (612) may be partially formed in at least a portion of the upper surface of the first build-up substrate layer (611). The second build-up substrate layer (612) may be formed to extend vertically from the upper surface of the first build-up substrate layer (611). The second build-up substrate layer (612) may be formed integrally with the first build-up substrate layer (611).

[0111] The second build-up substrate layer (612) may be placed between connecting structures (620) arranged in a horizontal direction. The height of the second build-up substrate layer (612) may be formed to be equal to or slightly lower than the height of the connecting structures (620).

[0112] The second build-up substrate layer (612) may include a plurality of second sublayers generated through a second build-up manufacturing process (i.e., a partial build-up manufacturing process). Here, the number of stacked second sublayers may vary depending on the height of the connecting structure (620).

[0113] A semiconductor chip (650) may be disposed on the upper portion of the second build-up substrate layer (612). At this time, the cross-sectional area of ​​the second build-up substrate layer (612) may be formed to have a width smaller than the cross-sectional area of ​​the semiconductor chip (650).

[0114] The second build-up substrate layer (612) may include a second wiring circuit and a second insulating material coated on the second wiring circuit. Here, the second wiring circuit may be formed of the same material as the first wiring circuit of the first build-up substrate layer (611). Additionally, the second insulating material may be formed of the same material as the first insulating material of the first build-up substrate layer (611).

[0115] The second wiring circuit can electrically connect the first build-up substrate layer (611) and the semiconductor chip (650). To this end, the second wiring circuit may include a plurality of conductive structures extending in a vertical direction. The cross-sections of the conductive structures may be formed in a predetermined shape (e.g., circular, elliptical, square, rectangular, etc.). The conductive structures may be formed to have different widths.

[0116] A plurality of connection pads (615) electrically connected to the second wiring circuit may be formed on the upper portion of the second build-up substrate layer (612). A solder ball or a solder bump may be additionally formed on the connection pads (615).

[0117] As described above, the semiconductor package (600) according to the second embodiment of the present invention can not only achieve miniaturization of the semiconductor package by replacing a plurality of fillers formed on the substrate of a conventional semiconductor package with a part of the substrate, but also reduce manufacturing costs by simplifying the manufacturing process of the semiconductor package. In addition, the semiconductor package (600) can improve power supply characteristics and signal transmission characteristics of the semiconductor package by stacking a second build-up substrate layer on the upper surface of a first build-up substrate layer through a partial build-up manufacturing process, and also reduce manufacturing costs by simplifying the manufacturing process of the semiconductor package.

[0118]

[0119] FIG. 7 is a diagram showing the structure of a semiconductor package according to a third embodiment of the present invention.

[0120] Referring to FIG. 7, a semiconductor package (700) according to a third embodiment of the present invention may include a substrate (710), a connecting structure (720), a molding member (730), a reinforcing plate (740), a semiconductor chip (750), and an external connection member (760). Since the components illustrated in FIG. 7 are not essential for implementing the semiconductor package, the semiconductor package described herein may have more or fewer components than those listed above.

[0121] The semiconductor package (700) according to the present embodiment may include a second build-up substrate layer (712) having a structure different from the second build-up substrate layer (112) of the semiconductor package (100) according to the first embodiment described above.

[0122] The connecting structure (720), molding member (730), reinforcing plate (740), semiconductor chip (750), and external connection member (760) of the semiconductor package (700) according to the present embodiment are identical to the connecting structure (120), molding member (130), reinforcing plate (140), semiconductor chip (150), and external connection member (160) of the semiconductor package (100) according to the first embodiment described above, so a detailed description thereof is omitted.

[0123] The substrate (710) can be produced through a plurality of build-up manufacturing processes. Here, the build-up manufacturing process is a manufacturing process that processes as many layers as are required by repeating the process of forming a circuit after laminating and compressing a layer of copper foil and an insulator on a double-sided plate, and then laminating and compressing a layer of copper foil and an insulator on top of it to form a circuit.

[0124] The substrate (710) may include a first build-up substrate layer (basic build-up substrate layer, 711) and a second build-up substrate layer (partial build-up substrate layer, 712).

[0125] The first build-up substrate layer (711) may include a plurality of first sublayers generated through a first build-up manufacturing process. Each first sublayer may include a first wiring circuit and a first insulating material coated on the first wiring circuit.

[0126] The first build-up substrate layer (711) can be electrically connected to a semiconductor chip (750) located on top of the connecting structure (720) through a connecting structure (720). Additionally, the first build-up substrate layer (711) can be electrically connected to a semiconductor chip (750) located on top of the second build-up substrate layer (712) through a second build-up substrate layer (712).

[0127] The second build-up substrate layer (712) may be partially formed in at least a portion of the upper surface of the first build-up substrate layer (711). The second build-up substrate layer (712) may be formed to extend vertically from the upper surface of the first build-up substrate layer (711). The second build-up substrate layer (712) may be formed integrally with the first build-up substrate layer (711).

[0128] The second build-up substrate layer (712) may be placed between connecting structures (720) arranged in a horizontal direction. The height of the second build-up substrate layer (712) may be formed to be equal to or slightly lower than the height of the connecting structures (720).

[0129] The second build-up substrate layer (712) may include a plurality of second sublayers generated through a second build-up manufacturing process (i.e., a partial build-up manufacturing process). Here, the number of stacked second sublayers may vary depending on the height of the connecting structure (720).

[0130] A semiconductor chip (750) may be disposed on the upper portion of the second build-up substrate layer (712). At this time, the cross-sectional area of ​​the second build-up substrate layer (712) may be formed to have a width smaller than the cross-sectional area of ​​the semiconductor chip (750).

[0131] The second build-up substrate layer (712) may include a second wiring circuit and a second insulating material coated on the second wiring circuit. Here, the second wiring circuit may be formed of the same material as the first wiring circuit of the first build-up substrate layer (711). Additionally, the second insulating material may be formed of the same material as the first insulating material of the first build-up substrate layer (711).

[0132] The second wiring circuit can electrically connect the first build-up substrate layer (711) and the semiconductor chip (750). To this end, the second wiring circuit may include a plurality of conductive structures extending in the vertical and horizontal directions. Accordingly, it can electrically connect connection pads arranged in a straight line in the vertical direction, as well as electrically connect connection pads not arranged in a straight line in the vertical direction.

[0133] A plurality of connection pads (715) electrically connected to the second wiring circuit may be formed on the upper portion of the second build-up substrate layer (712). A solder ball or a solder bump may be additionally formed on the connection pads (715).

[0134] As described above, the semiconductor package (700) according to the third embodiment of the present invention can not only achieve miniaturization of the semiconductor package by replacing a plurality of fillers formed on the substrate of a conventional semiconductor package with a part of the substrate, but also reduce manufacturing costs by simplifying the manufacturing process of the semiconductor package. In addition, the semiconductor package (700) can improve power supply characteristics and signal transmission characteristics of the semiconductor package by stacking a second build-up substrate layer on the upper surface of a first build-up substrate layer through a partial build-up manufacturing process, and also reduce manufacturing costs by simplifying the manufacturing process of the semiconductor package.

[0135]

[0136] FIG. 8 is a diagram showing the structure of a semiconductor package according to a fourth embodiment of the present invention.

[0137] Referring to FIG. 8, a semiconductor package (800) according to a fourth embodiment of the present invention may include a substrate (810), a connecting structure (820), a molding member (830), a reinforcing plate (840), a semiconductor chip (850), and an external connection member (860). Since the components illustrated in FIG. 8 are not essential for implementing the semiconductor package, the semiconductor package described herein may have more or fewer components than those listed above.

[0138] Unlike the semiconductor package (100) according to the first embodiment described above, the semiconductor package (800) according to the present embodiment may include a plurality of second build-up substrate layers (812, 813, 814).

[0139] The connecting structure (820), molding member (830), reinforcing plate (840), semiconductor chip (850), and external connection member (860) of the semiconductor package (800) according to the present embodiment are identical to the connecting structure (120), molding member (130), reinforcing plate (140), semiconductor chip (150), and external connection member (160) of the semiconductor package (100) according to the first embodiment described above, so a detailed description thereof is omitted.

[0140] The substrate (810) can be produced through a plurality of build-up manufacturing processes. Here, the build-up manufacturing process is a manufacturing process that processes as many layers as are required by repeating the process of forming a circuit after laminating and compressing a layer of copper foil and an insulator on a double-sided plate, and then laminating and compressing a layer of copper foil and an insulator on top of it to form a circuit.

[0141] The substrate (810) may include a first build-up substrate layer (basic build-up substrate layer, 811) and a plurality of second build-up substrate layers (partial build-up substrate layers, 812, 813, 814).

[0142] The first build-up substrate layer (811) may include a plurality of first sublayers generated through a first build-up manufacturing process. Each first sublayer may include a first wiring circuit and a first insulating material coated on the first wiring circuit.

[0143] The first build-up substrate layer (811) can be electrically connected to a semiconductor chip (850) located on top of the connecting structure (820) through a connecting structure (820). Additionally, the first build-up substrate layer (811) can be electrically connected to a semiconductor chip (850) located on top of the second build-up substrate layers (812, 813, 814) through a plurality of second build-up substrate layers (812, 813, 814).

[0144] A plurality of second build-up substrate layers (812, 813, 814) may be partially formed in at least a portion of the upper surface of the first build-up substrate layer (811). The second build-up substrate layers (812, 813, 814) may be formed to extend vertically from the upper surface of the first build-up substrate layer (811). The second build-up substrate layers (812, 813, 814) may be formed integrally with the first build-up substrate layer (811).

[0145] A plurality of second build-up substrate layers (812, 813, 814) may be arranged side by side in a horizontal direction with the connecting structure (820). Additionally, the height of the second build-up substrate layers (812, 813, 814) may be formed to be the same as or slightly lower than the height of the connecting structure (820).

[0146] Each of the second build-up substrate layers (812, 813, 814) may include a plurality of second sublayers generated through a second build-up manufacturing process (i.e., a partial build-up manufacturing process). Here, the number of stacked second sublayers may vary depending on the height of the connecting structure (820).

[0147] A semiconductor chip (850) may be disposed on the upper portion of each second build-up substrate layer (812, 813, 814). At this time, the cross-sectional area of ​​the second build-up substrate layer (812, 813, 814) may be formed to have a width smaller than the cross-sectional area of ​​the semiconductor chip (850).

[0148] Each of the second build-up substrate layers (812, 813, 814) may include a second wiring circuit and a second insulating material coated on the second wiring circuit. Here, the second wiring circuit may be formed of the same material as the first wiring circuit of the first build-up substrate layer (811). Additionally, the second insulating material may be formed of the same material as the first insulating material of the first build-up substrate layer (811).

[0149] The second wiring circuit can electrically connect the first build-up substrate layer (811) and the semiconductor chip (850). To this end, the second wiring circuit may include a plurality of conductive structures extending in a vertical direction. The cross-sections of the conductive structures may be formed in a predetermined shape (e.g., circular, elliptical, square, rectangular, etc.). The conductive structures may be formed to have the same width.

[0150] Meanwhile, as illustrated in the drawing, the conductive structures of one layer (812) among the plurality of second build-up substrate layers (812, 813, 814) may be formed to have a wider width than the conductive structures of the other layers (813, 814).

[0151] A plurality of connection pads (815) electrically connected to the second wiring circuit may be formed on the upper portion of the second build-up substrate layer (812). A solder ball or a solder bump may be additionally formed on the connection pads (815).

[0152] As described above, the semiconductor package (800) according to the fourth embodiment of the present invention can not only achieve miniaturization of the semiconductor package by replacing a plurality of fillers formed on the substrate of a conventional semiconductor package with a part of the substrate, but also reduce manufacturing costs by simplifying the manufacturing process of the semiconductor package. In addition, the semiconductor package (800) can improve power supply characteristics and signal transmission characteristics of the semiconductor package by stacking a plurality of second build-up substrate layers on the upper surface of a first build-up substrate layer through a partial build-up manufacturing process, and also reduce manufacturing costs by simplifying the manufacturing process of the semiconductor package.

[0153] Meanwhile, although specific embodiments of the present invention have been described above, it is understood that various modifications are possible within the scope of the present invention. Therefore, the scope of the present invention is not limited to the described embodiments, but should be defined by the claims set forth below as well as equivalents thereof.

Claims

1. A substrate comprising a first build-up substrate layer and a second build-up substrate layer laminated from at least one portion of the upper surface of the first build-up substrate layer; One or more connecting structures disposed on the first build-up substrate layer; and A semiconductor package comprising a plurality of semiconductor chips disposed on the upper portion of the second build-up substrate layer and the connecting structure.

2. In Paragraph 1, A semiconductor package characterized in that the first build-up substrate layer comprises a plurality of first sublayers generated through a general build-up manufacturing process.

3. In Paragraph 1, A semiconductor package characterized in that the second build-up substrate layer comprises a plurality of second sublayers generated through a partial build-up manufacturing process.

4. In Paragraph 1, A semiconductor package characterized in that the height of the second build-up substrate layer is formed to be the same as the height of the connecting structure.

5. In Paragraph 1, A semiconductor package characterized in that the cross-sectional area of ​​the second build-up substrate layer is formed to have a width smaller than the cross-sectional area of ​​a semiconductor chip located on top of the second build-up substrate layer.

6. In Paragraph 1, A semiconductor package characterized in that the second build-up substrate layer electrically connects the first build-up substrate layer and a semiconductor chip located on top of the second build-up substrate layer.

7. In Paragraph 3, A semiconductor package characterized in that the second sublayer comprises a wiring circuit and an insulating material coated on the wiring circuit.

8. In Paragraph 7, A semiconductor package characterized in that the wiring circuit comprises a plurality of conductive structures extending in a vertical direction from the upper surface of the first build-up substrate layer.

9. In Paragraph 7, A semiconductor package characterized in that the insulating material is formed of an insulating material different from the insulating material of the connecting structure.

10. In Paragraph 1, A semiconductor package further comprising a plurality of connection pads disposed on the upper portion of the second build-up substrate layer.

11. In Paragraph 10, A semiconductor package characterized in that at least one of the shape, size, and spacing between the above-mentioned connection pads is formed differently from each other.

12. In Paragraph 1, A semiconductor package further comprising a molding member surrounding the above-mentioned connecting structure.

13. In Paragraph 12, A semiconductor package further comprising a reinforcing material disposed in the edge region of the molding member.

14. In Paragraph 1, A semiconductor package characterized by the above connecting structure being formed to electrically connect semiconductor chips arranged in a horizontal direction.

15. In Paragraph 1, A semiconductor package characterized in that the connecting structure is formed to electrically connect the first build-up substrate layer and a semiconductor chip located on top of the connecting structure.

16. In Paragraph 1, A semiconductor package characterized in that the above connecting structure is mounted as a flip-chip structure on the first build-up substrate layer.

17. In Paragraph 1, A semiconductor package characterized in that the above connecting structure is arranged horizontally parallel to the above second build-up substrate layer.

18. In Paragraph 1, A semiconductor package characterized by the fact that the upper surface of the connecting structure and the upper surface of the second build-up substrate layer are formed to be located on the same plane.

19. In Paragraph 1, A semiconductor package further comprising a plurality of external connection members attached to the lower surface of the substrate.

20. A step of generating a first build-up substrate layer through a first build-up manufacturing process; A step of creating a second build-up substrate layer on at least one portion of the upper surface of the first build-up substrate layer through a second build-up manufacturing process; A step of arranging a plurality of connecting structures on the first build-up substrate layer; A step of coating a molding member on the first build-up substrate layer, the second build-up substrate layer, and the connecting structures; A step of removing a portion of the molding member so that the second build-up substrate layer and the connecting structures are exposed to the outside; and A method for manufacturing a semiconductor package comprising the step of mounting a plurality of semiconductor chips on the second build-up substrate layer and the connecting structures.

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