Semiconductor devices including memory elements and threshold switches, and methods of forming same

Abstract

Semiconductor devices are disclosed. The devices include a substrate, and a metallization layer disposed over the substrate, where the metallization layer includes a plurality of interconnects. The devices also include a threshold switch formed over a first interconnect of the plurality of interconnects. The threshold switch includes a bottom electrode disposed directly over the first interconnect, a threshold switching layer disposed over the bottom electrode, and a top electrode disposed directly over the threshold switching layer. The devices also include a memory element formed over the threshold switch. The memory element includes a memory stack disposed over the top electrode of the threshold switch, and a memory top electrode disposed directly over the memory stack.

Description

Attorney Docket No. 011-2318W001SEMICONDUCTOR DEVICES INCLUDING MEMORY ELEMENTS ANDTHRESHOLD SWITCHES. AND METHODS OF FORMING SAMECROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 707,973, filed October 16, 2024. the entirety of which is hereby incorporated herein by this reference.BACKGROUND

[0002] The disclosure relates generally to semiconductor devices, and more particularly, to semiconductor devices including memory elements and threshold switches, and methods of forming the semiconductor devices.

[0003] Metal-insulator-metal (MIM) devices play a critical role in modem semiconductor memory technology due to their simple structure, scalability7, and general compatibility with standard CMOS processes. A typical MIM device consists of two metal electrodes separated by an insulating layer, often a transition metal oxide that may or may not be a high-k dielectric. This configuration enables a range of electronic behaviors, including resistive switching, which is the core principle behind resistive random-access memory7(ReRAM). In ReRAM, the resistance state of the insulating layer can be modulated by applying voltage pulses, allowing data to be stored as high or low resistance states (representing binary I s and 0s). These devices are particularly attractive for non-volatile memory applications due to their fast-switching speed, low power consumption, and excellent scalability7down to the nanometer scale.

[0004] In memory applications. MIM structures benefit from the ability to engineer the insulator properties and interface characteristics, which directly impact device performance and reliability. MIM-based ReRAM is considered a leading candidate for nextgeneration non-volatile memory7, offering the potential to overcome limitations of flash memory while supporting high-density7integration and neuromorphic computing applications.BRIEF DESCRIPTION

[0005] A first aspect of the disclosure provides a semiconductor device including a substrate; a metallization layer disposed over the substrate, the metallization layer including a plurality of interconnects; a first threshold switch formed over a first interconnect of the plurality of interconnects, the first threshold switch including: a first bottom electrodeAttorney Docket No. 011-2318W001 disposed directly over the first interconnect; a first threshold switching layer disposed over the first bottom electrode; and a first top electrode disposed directly over the first threshold switching layer; a memory element formed over the first threshold switch, the memory element including: a memory stack disposed over the first top electrode of the first threshold switch; and a memory7top electrode disposed directly over the memory stack; and a second threshold switch formed over a second interconnect of the plurality7of interconnects, the second threshold switch including: a second bottom electrode disposed directly over the second interconnect; a second threshold switching layer disposed directly over the second bottom electrode; and a second top electrode disposed directly over the second threshold switching layer.

[0006] A second aspect of the disclosure provides a semiconductor device including a substrate; a metallization layer disposed over the substrate, the metallization layer including a plurality of interconnects; a threshold switch formed over a first interconnect of the plurality of interconnects, the threshold switch including: a bottom electrode disposed directly over the first interconnect; a threshold switching layer disposed over the bottom electrode; and a top electrode disposed directly over the threshold switching layer; and a memory7element formed over the threshold switch, the memory element including: a memory stack disposed over the top electrode of the threshold switch; and a memory top electrode disposed directly over the memory7stack.

[0007] A third aspect of the disclosure provides a method of manufacturing a semiconductor device. The method includes depositing a bottom electrode layer over a metallization layer including a plurality of interconnects; depositing a switching layer over the bottom electrode layer; depositing a top electrode layer over the switching layer; depositing a dielectric material over the top electrode layer; patterning the dielectric material, the top electrode layer, the threshold switching layer, and the bottom electrode layer over an interconnect of the plurality of interconnects to form: a bottom electrode disposed over the interconnect, a threshold switching layer disposed over the bottom electrode, and a top electrode disposed over the threshold switch; depositing the dielectric material over the metallization layer, the bottom electrode, the threshold switching layer, and the top electrode; exposing the top electrode within the dielectnc material; depositing a memory stack layer over the top electrode and the dielectric material; depositing a memory' top electrode layer over the memory' stack layer; depositing the dielectric material over the memory7top electrode layer; patterning the dielectric material, the memory top electrode layer, and the memory stack layer over the top electrode to form: a memory stack disposed over the top electrode, and a memory top electrode disposed over the memory stack; and encapsulating the memory stack and theAttorney Docket No. 011-2318W001 memory' top electrode with the dielectric material to form an inter-layer dielectric (ILD).

[0008] The illustrative aspects of the present disclosure are designed to solve the problems herein described and / or other problems not discussed.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure, in which:

[0010] FIG. 1 shows a cross-sectional view of a semiconductor device including a memory element and a plurality of threshold switches, according to embodiments of the disclosure.

[0011] FIGS. 2-12 show cross-sectional views of a semiconductor device undergoing various processes for forming a memory element and a plurality of threshold switch therein, according to embodiments of the disclosure.

[0012] FIG. 13 shows a cross-sectional view of a semiconductor device including a memory element and a threshold switch, according to additional embodiments of the disclosure.

[0013] FIG. 14 shows a cross-sectional view of a semiconductor device including a memory element and a threshold switch, according to another embodiment of the disclosure.

[0014] FIG. 15 shows a cross-sectional view of a semiconductor device including a memory' element and a threshold switch, according to an additional embodiment of the disclosure.

[0015] FIGS. 16A and 16B sho \?flow charts illustrating processes for forming a semiconductor device including a memory' element and a plurality of threshold switches, according to embodiments of the disclosure.

[0016] It is noted that the drawings of the disclosure are not to scale. The drawings are intended to depict only typical aspects of the disclosure and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.DETAILED DESCRIPTIONAttorney Docket No. 011-2318W001

[0017] As an initial matter, in order to clearly describe the current disclosure it will become necessary to select certain terminology when referring to and describing relevant components within the disclosure. When doing this, if possible, common industry terminology will be used and employed in a manner consistent with its accepted meaning. Unless otherwise stated, such terminology should be given a broad interpretation consistent with the context of the present application and the scope of the appended claims. Those of ordinary skill in the art will appreciate that often a particular component may be referred to using several different or overlapping terms. What may be described herein as being a single part may include and be referenced in another context as consisting of multiple components. Alternatively, what may be described herein as including multiple components may be referred to elsewhere as a single part.

[0018] As discussed herein, the disclosure relates generally to semiconductor devices, and more particularly, to semiconductor devices including memory' elements and threshold switches, as well as methods of forming semiconductor devices.

[0019] These and other embodiments are discussed below with reference to FIGS. 1-16B. However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these Figures is for explanatory purposes only and should not be construed as limiting.

[0020] FIG. 1 show s cross-sectional view of a semiconductor module or device including a memory element and a plurality of threshold switches formed therein. In the exemplary embodiment, semiconductor device 100 includes a portion of a larger semiconductor structure. Additionally, semiconductor device 100 may include a substrate 102. Substrate 102 may include or form a base layer or layers of semiconductor device 100 that may be formed from semiconducting material(s) and / or may be formed from any suitable module, material or material compositions that includes semiconducting properties / characteristic. In the exemplary embodiment shown in FIG. 1, substrate 102 is formed from a plurality of layers that may be patterned and / or materials disposed over one another. Specifically, substrate 102 includes a silicon (Si) base layer 104, a silicon dioxide (SiCh) layer 106 disposed and / or formed directly over base layer 104. Additionally in the exemplary embodiment, substrate 102 includes a silicon nitride (SiN) layer 108 disposed and / or formed directly over SiO2 layer 106.

[0021] In other exemplary embodiments, substrate 102 is formed from indium phosphide (InP) or Indium gallium arsenide (InGaAs), or any other suitable materials or compositions consisting essentially of one or more compound semiconductors. For example, substrate 102 can be provided as a bulk substrate or as part of a silicon-on-insulator (SOI)Attorney Docket No. 011-2318W001 wafer. Additionally, or alternatively, substrate 102 may be formed from, for example, silicon (Si), silicon carbide (SiC), germanium (Ge), germanium oxide (GeO), cadmium zinc telluride (CdZnTe), gallium nitride (GaN), or gallium arsenide (GaAs). Furthermore, substrate 102 may be fabricated as a layer or multiple layers of semiconductor material, substances or materials consisting essentially of one or more compound semiconductors having a composition defined by the formula AlXlGaX2InX3AsYlPY2NY3SbY4, where XI, X2, X3. Yl, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substances can include II-VI compound semiconductors having a composition ZnAlCdA2SeBlTeB2, where Al, A2, Bl, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity).

[0022] Semiconductor device 100 also includes a metallization layer 110 disposed over substrate 102. In the exemplary' embodiment shown in FIG. 1, metallization layer 110 is disposed and / or formed directly over SiN layer 108 of substrate 102. Metallization layer 110 is disposed, deposited, patterned, and / or formed over substrate 102 using any suitable material deposition technique and / or process including, but not limited to, lithography, reactive ion etch (RIE), chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like. Additionally, metallization layer 110 is formed from any suitable, dielectric material included within semiconductor device 100. For example, and as shown in FIG. 1, metallization layer 1 10 is formed from silicon dioxide (SiCh).

[0023] Metallization layer 110 included in semiconductor device 100 also includes a plurality of interconnects 112 formed therein. More specifically, and in the exemplary embodiment where semiconductor module 100 includes a memory component and a switching component, semiconductor device 100 includes a first interconnect 112A, a second interconnect 112B, and a third interconnect 112C formed within metallization layer 110. Interconnects 112 included in metallization layer 110 are formed from any suitable conductive material to facilitate the electrical connection and / or communication with various components (e.g, vias, memory component, switching component) included within semiconductor device 100. In exemplary embodiments, interconnects 112 are formed from a material or material compound including, but not limited to, Copper (Cu), aluminum (Al), tungsten (T), and the like. Additionally, interconnects 112 are fonned within metallization layer 110 using any suitable material removal and / or deposition techniques.

[0024] In the exemplary embodiment shown in FIG. 1, semiconductor deviceAttorney Docket No. 011-2318W001100 also includes a first threshold switch 118A formed over first interconnect 112A of the plurality of interconnects formed in metallization layer 110. As discussed herein, first threshold switch 1 18A is formed from a plurality of distinct portions and / or materials. As shown in FIG. 1, and as discussed herein, first threshold switch 118A, and the plurality of distinct portions and / or materials forming first threshold switch 118A, is approximately 200 nanometers (nm) or less in width and / or diameter.

[0025] As shown in FIG. 1, first threshold switch 118A of semiconductor device 100 includes a first bottom electrode 120 disposed over first interconnect 112A formed in metallization layer 110. More specifically, and in the exemplary embodiment, first bottom electrode 120 is disposed directly over, is formed directly on, and / or covers at least a portion first interconnect 112A formed in metallization layer 110. As shown, and as discussed herein, at least a portion of first interconnect 112A is exposed and / or remains uncovered by bottom electrode 120 forming first threshold switch 118A. Additionally, bottom electrode 120 of first threshold switch 118A is substantially aligned with first interconnect 112A. Bottom electrode 120 is formed and / or disposed directly over at least a portion of first interconnect 112A using any suitable material deposition and / or material removal processes, as discussed herein (see e.g., FIGS. 3-5). Additionally in the exemplary embodiments, bottom electrode 120 is formed from any suitable electrically conductive material including or a combination thereof, but not limited to, titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, etchable materials.

[0026] First threshold switch 1 18A of semiconductor device 1 0 also includes a threshold switching layer 122 disposed over bottom electrode 120. More specifically, and in the exemplary' embodiment shown in FIG. 1, threshold switching layer 122 is disposed directly over, is formed directly on. and / or covers bottom electrode 120. As shown, threshold switching layer 122 of threshold switch 118A is also substantially aligned with first interconnect 112A. Threshold switching layer 122 is formed and / or disposed directly over bottom electrode 120 using any suitable material deposition and / or material removal processes, as discussed herein. Additionally in the exemplary embodiments, threshold switching layer 122 is formed from any suitable electrically conductive material exhibiting an electrically induced volatile resistance change including, but not limited to, niobium dioxide (NbCh), vanadium oxides (VOx), samarium nickelate (SmNiO3), or the like. As shown, threshold switching layer 122 includes a thickness and / or height less than approximately 50 nanometers (nm), and in non-limiting examples is formed to include a width and / or diameter less than approximately 200 nm.

[0027] In the exemplary embodiment shown in FIG. 1, first threshold switchAttorney Docket No. 011-2318W001118A of semiconductor device 100 further includes a top electrode 124 disposed over threshold switching layer 122. More specifically, top electrode 124 is disposed directly over, is formed directly on, and / or covers threshold switching layer 122. As shown in FIG. 1, top electrode 124 of threshold switch 118A is substantially aligned with first interconnect 112A. Similar to bottom electrode 120, and as discussed herein (see e.g., FIGS. 3-5), top electrode 124 is formed and / or disposed directly over threshold switching layer 122 using any suitable material deposition and / or material removal processes. Moreover, top electrode 124 is formed from any suitable electrically conductive material or a combination thereof including, but not limited to, titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, etchable materials in exemplary embodiments discussed herein.

[0028] Additionally in the exemplary embodiment, semiconductor device 100 includes a memory element 126 formed over first threshold switch 118A. In non-limiting examples, and as discussed herein, memory element 126 is formed as a ReRAM device within semiconductor device 100. In other non-limiting examples, memory7element 126 can be formed as phase change memory7(PCM), ferroelectric random- access memory (FeRAM), magnetic random-access memory (MRAM), or similar elements. Similar to first threshold switch 118A, and as discussed herein, memory element 126 is formed from a plurality of distinct portions and / or materials. Additionally as discussed herein, memory7element 126, and the plurality of distinct portions and / or materials forming memory element 126, is approximately 1 micrometer (pm) or less in width and / or diameter.

[0029] Memory element 126 included in semiconductor device 100 also includes a memory7stack 128 disposed over top electrode 124 of first threshold switch 118A. In the exemplary embodiment shown in FIG. 1, memory7stack 128 is disposed directly over, is formed directly on, and / or covers top electrode 124. At least a portion of memory stack 128 extends beyond, overhangs, and / or is positioned adjacent top electrode 124 of first threshold switch 118A. As discussed herein, additional portions (e.g., ILD) of semiconductor device 100 support memory stack 128 of memory7element 126. Additionally, and as shown in FIG. 1, memory stack 128 of memory element 126 is substantially aligned with first interconnect 112A and / or top electrode 124. As discussed herein (see e.g, FIGS. 3-5), memory stack 128 is formed and / or disposed directly over top electrode 124 using any suitable material deposition and / or material removal processes. In exemplary7embodiments, memory stack 128 is formed from any suitable material exhibiting an electrically induced volatile resistance including, but not limited to, niobium dioxide (NbCh), vanadium oxides (VOx), samarium nickelate (SmNiO3), titanium oxide (Ti2O3), and the like.Attorney Docket No. 011-2318W001

[0030] Additionally, and as shown in FIG. 1, memory' element 126 includes a memory top electrode 130 disposed over memory’ stack 128. In the exemplary embodiment, memory top electrode 130 is disposed directly over, is formed directly on, and / or covers memory stack 128. Similar to memory stack 128, at least a portion of memory top electrode 130 extends beyond, overhangs, and / or is positioned adjacent top electrode 124. Moreover, memory top electrode 130 is also formed and / or sized to be substantially aligned with memory stack 128. As discussed herein, additional portions (e.g., ILD) of semiconductor device 100 support and / or surround memory top electrode 130. In the exemplary embodiment shown in FIG. 1, memory top electrode 130 of memory' element 126is also substantially aligned yvith first interconnect 112A and / or top electrode 124. As discussed herein (see e.g., FIGS. 3-5), memory top electrode 130 is formed and / or disposed directly over memory stack 128 using any suitable material deposition and / or material removal processes. In exemplary embodiments, memory' top electrode 130 is formed from any suitable electrically conductive material or a combination thereof including, but not limited to, titanium (Ti), hafnium (Hf), titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, etchable materials in exemplary embodiments discussed herein.

[0031] Top electrode 124 of first threshold switch 118A is formed between memory' stack 128 of memory' element 126 and threshold switching layer 122 and facilitates electrical connection and / or communication through and / or between first threshold switch 118A and memory element 126. In exemplary embodiments, top electrode 124 of threshold switch 118A also acts as a bottom electrode for memory element 126. That is, and as discussed herein, top electrode 124 operates as a “top electrode” for threshold switch 118A including top electrode 124, threshold switching layer 122, and bottom electrode 120, and top electrode 124 operates as a “bottom electrode” for memory element 126 including memory stack 128 and memory top electrode 130. In exemplary embodiments, the combination of first threshold switch 1 18A and memory element 126 are referred to as “1-TS, 1-M” portions and / or components of semiconductor device 100, where “1-TS" refers to a single semiconductor threshold switch, and “1-M” refers to a single memory component. In other exemplary embodiments, the combination of first threshold switch 118A and memory element 126 are referred to as “1-S, 1-R” portions and / or components of semiconductor device 100, where “1- S" refers to a single semiconductor switch or selector, and “1-R” refers to a single semiconductor resistor component.

[0032] In exemplary embodiments shown in FIG. 1. semiconductor device 100 also includes a second or distinct threshold switch 1 18B formed adjacent first threshold switchAttorney Docket No. 011-2318W001118A. More specifically, threshold switch 118B is formed within semiconductor device 100 adjacent to threshold switch 118A and over second interconnect 112B of the plurality of interconnects included in metallization layer 110. As discussed herein, second threshold switch 118B is spaced apart from and / or separated from first threshold switch 118A via an inter-layer dielectric (ILD). Additionally as discussed herein, second threshold switch 118B, and the plurality of distinct portions and / or materials forming second threshold switch 118B, is approximately 200 nanometers (nm) or less in width and / or diameter.

[0033] As shown in FIG. 1, second threshold switch 118B of semiconductor device 100 includes a distinct bottom electrode 132 disposed over second interconnect 112B formed in metallization layer 110. More specifically, and in the exemplary' embodiment, distinct bottom electrode 132 is disposed directly over, is formed directly on, and / or covers at least a portion second interconnect 112B formed in metallization layer 110. As shown, and as discussed herein, at least a portion of second interconnect 112B is exposed and / or remains uncovered by distinct bottom electrode 132 forming threshold switch 118B. Additionally, distinct bottom electrode 132 of threshold switch 118B is substantially aligned with second interconnect 112B. Distinct bottom electrode 132 is formed and / or disposed directly over at least a portion of second interconnect 112B using any suitable material deposition and / or material removal processes, as discussed herein (see e.g., FIGS. 3-5). Additionally in the exemplary embodiments, and similar to bottom electrode 120, distinct bottom electrode 132 is formed from any suitable electrically conductive material including, but not limited to, titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, etchable materials.

[0034] Second threshold switch 118B of semiconductor device 100 also includes a distinct threshold switching layer 134 disposed over distinct bottom electrode 132. More specifically, and in the exemplary embodiment shown in FIG. 1. distinct threshold switching layer 134 is disposed directly over, is formed directly on, and / or covers distinct bottom electrode 132. As shown, threshold switching layer 134 of threshold switch 118B is also substantially aligned with second interconnect 112B. Distinct threshold switching layer 134 is formed and / or disposed directly over distinct bottom electrode 132 using any suitable material deposition and / or material removal processes, as discussed herein. Additionally in the exemplary embodiments, threshold switching layer 134 is formed from any suitable electrically conductive material including, but not limited to, niobium dioxide (NbO2), vanadium oxides (VOx), samarium nickelate (SmNiO3), or the like. As shown, threshold switching layer 134 includes a thickness and / or height of less than approximately 50 nanometers (nm), and in nonlimiting examples is formed to include a width and / or diameter less than approximately 200Attorney Docket No. 011-2318W001 nm.

[0035] In the exemplary embodiment shown in FIG. 1, threshold switch 118B of semiconductor device 100 further includes a distinct top electrode 136 disposed over distinct threshold switching layer 134. More specifically, distinct top electrode 136 is disposed directly over, is formed directly on, and / or covers threshold switching layer 134. As shown in FIG. 1, distinct top electrode 136 of second threshold switch 118B is substantially aligned with second interconnect 112B. Similar to distinct bottom electrode 132, and as discussed herein (see e.g. , FIGS. 3-5), distinct top electrode 136 is formed and / or disposed directly over distinct threshold switching layer 134 using any suitable material deposition and / or material removal processes. Moreover, top electrode 136 is formed from any suitable electrically conductive material including, but not limited to, titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, etchable materials in exemplary embodiments discussed herein.

[0036] In the exemplary embodiment shown in FIG. 1, second threshold switch 118B of semiconductor device 100 form synapse and neuron devices, respectively. More specifically, threshold switch 118A and memory element 126, collectively, form, represent, and / or define a synapse device within semiconductor device 100, while second threshold switch 118B forms, represents, and / or defines a neuron device for semiconductor device 100. As such, semiconductor device 100 including threshold switches 118A, 118B and memory element 126 can be utilized within and / or in conjunction with neuro-multi-computing systems and / or devices.

[0037] Semiconductor device 100 also includes an inter-later dielectric (ILD) 138 disposed over metallization layer 110. More specifically, ILD 138 is disposed directly over, is formed directly on, and / or covers at least a portion of metallization layer 110, and at least a portion of interconnects 112A, 112B, 112C formed within metallization layer 110. In the exemplary embodiment, ILD 138 is disposed over portions of first interconnect 112A adjacent to and / or uncovered by first threshold switch 118A, as well as being disposed over portions of second interconnect 112B adjacent to and / or uncovered by second threshold switch 118B. Moreover, and as discussed herein, ILD 138 also covers a portion of third interconnect 112C uncovered and / or formed within metallization layer 110 adjacent to a via extending through semiconductor device 100.

[0038] As shown in FIG. 1, ILD 138 also substantially surrounds first threshold switch 118A, second threshold switch 118B, and memory element 126, respectively. In the exemplary embodiment. ILD 138 substantially surrounds, encapsulates, and / or is disposed around at least a portion of bottom electrode 120, threshold switching layer 122, top electrodeAttorney Docket No. 011-2318W001124, memory' stack 128, and memory top electrode 130 forming threshold switch 118A and memory element 126, respectively. As shown, ILD 138 is also disposed and / or formed over the top of memory top electrode 130 of memory element 126, and is disposed below, formed adjacent to, and / or supports a portion of memory stack 128 that extends beyond top electrode 124 within threshold switch 118A. Additionally, ILD 138 substantially surrounds, encapsulates, and / or is disposed around at least a portion of distinct bottom electrode 132, distinct threshold switching layer 134, and distinct top electrode 136 forming second threshold switch 118B. ILD 138 is formed and / or disposed within semiconductor device 100 using any suitable material deposition and / or material removal processes, as discussed herein (see e.g., FIGS. 3-9). Additionally in the exemplary embodiments, ILD 138 is fonned from any suitable material having dielectric properties and / or characteristics including, but not limited to. silicon nitride (SiN), silicon dioxide (SiC>2), and the like.

[0039] In the exemplary embodiment, semiconductor device 100 also includes a dielectric layer 140 disposed over ILD 138. More specifically, and as shown in FIG. 1, dielectric layer 140 is disposed directly over, is formed directly on, and / or covers ILD 138 formed within semiconductor device 100. Dielectric layer 140 is formed and / or disposed within semiconductor device 100 using any suitable material deposition and / or material removal processes, as discussed herein (see e.g., FIGS. 10-12). Additionally in the exemplary' embodiments, dielectric layer 140 is formed from any suitable material having dielectric properties and / or characteristics including, but not limited to, silicon nitride (SiN), low-k dielectric (low-k), or silicon dioxide (SiO2). In non-limiting examples, dielectric layer 140 is formed from a substantially similar material as ILD 138.

[0040] Semiconductor device 100 also includes a plurality of distinct interconnects 142 formed within dielectric layer 140. More specifically, and in the exemplary embodiment shown in FIG. 1, semiconductor device 100 includes a first distinct interconnect 142 A, a second distinct interconnect 142B, and a third distinct interconnect 142C formed within dielectric layer 140. In the exemplary embodiment, first distinct interconnect 142A is substantially aligned with threshold switch 118A, memory element 126, and first interconnect 112A formed in metallization layer 110, respectively. Additionally, and as discussed herein, first distinct interconnect 142A is formed on, disposed over, and / or contacts a portion of ILD 138 that separates memory' element 126 and dielectric layer 140. Second distinct interconnect 142B is substantially aligned with second threshold switch 118B and second interconnect 112B, respectively, while third distinct interconnect 142C is substantially aligned with third interconnect 112C. Distinct interconnects 142 included in dielectric layer 140 are formed fromAttorney Docket No. 011-2318W001 any suitable conductive material to facilitate the electrical connection and / or communication with various components (e.g, vias, threshold switch 118A, 118B, memory’ element 126) included within semiconductor device 100. In exemplary embodiments, interconnects 142 are formed from a material or material compound including, but not limited to, copper (Cu), aluminum (Al), or any other suitable material having similar conductive characteristics and / or properties. Additionally, distinct interconnect 142 are formed within dielectric layer 140 using any suitable material removal and / or deposition techniques.

[0041] In the exemplary embodiment shown in FIG. 1, semiconductor device 100 also includes a plurality of vias 144. That is, semiconductor device 100 includes a first via 144A, a second via 144B, and a third via 144C extending and / or disposed through at least a portion of ILD 138 and / or dielectric layer 140. First via 144A is disposed and / or extends through at least a portion of ILD 138, between first distinct interconnect 142A and memory element 126. More specifically, first via 144A extends through a portion of ILD 138 formed above and / or substantially encapsulating memory' element 126 to contact and / or electrically couple memory’ top electrode 130 of memory element 126 and first distinct interconnect 142A. Second via 144B is disposed and / or extends through at least a portion of ILD 138 and dielectric layer 140, respectively, between second distinct interconnect 142B and memory top electrode 130. As shown in FIG. 1, second via 144B extends through a portion of ILD 138 formed above memory top electrode 130, as well as a portion of dielectric layer 140 disposed and / or formed below second distinct interconnect 142B. Additionally, second via 144B contacts and / or electrically couples distinct top electrode 136 of memory top electrode 130 and second distinct interconnect 142B. Third via 144C is disposed and / or extends through at least a portion of ILD 138 and dielectric layer 140, respectively, and contacts and / or electrically couples third interconnect 112C and third distinct interconnect 142C within semiconductor device 100. Vias 144 extending through ILD 138 and / or dielectric layer 140 are formed from any suitable conductive material to facilitate the electrical connection and / or communication with various components (e.g., interconnect 142, threshold switch 118A, 118B, memory element 126) included within semiconductor device 100. In exemplary’ embodiments, vias 144 are formed from a material or material compound including, but not limited to, copper (Cu), aluminum (Al), or any other suitable material having similar conductive characteristics and / or properties. Additionally, vias 144 are formed within semiconductor device 100 using any suitable material removal and / or deposition techniques.

[0042] FIGS. 2-12 show various processes for forming semiconductor device 100 therein. More specifically, FIGS. 2-12 show cross-sectional views of semiconductorAttorney Docket No. 011-2318W001 device 100 undergoing various processes to form semiconductor device 100 including threshold switch 118A, 118B and memory element 126 therein. It is understood that similarly numbered and / or named components may function in a substantially similar fashion. Redundant explanation of these components has been omitted for brevity.

[0043] FIG. 2 shows a cross-sectional view of substrate 102, and metallization layer 110. In the exemplary embodiment, metallization layer 110 is disposed directly over and / or on top of SiN layer 108 included within substrate 102. Additionally, as shown, metallization layer 110 includes a plurality of interconnects 112A, 1 12B, 112C disposed and / or formed therein. The plurality’ of interconnects 112A, 112B, 112C are formed within metallization layer 110 using any suitable material removal and / or deposition techniques. For example, after depositing material forming metallization layer 110 over SiN layer 108 of substrate 102, a portion of the material is removed (e.g, via an etching process), and material forming the plurality of interconnects 112A, 112B, 112C is subsequently deposited into metallization layer 110.

[0044] FIG. 3 shows various layers being deposited over metallization layer 110 and / or interconnects 112A, 112B, 112C. In the exemplary embodiment, a bottom electrode layer 150 is deposited directly over metallization layer 110 including interconnects 112A, 112B, 112C. That is, bottom electrode layer 150 is deposited, disposed, and / or formed directly over metallization layer 110 and each of the plurality of interconnects 112A, 112B, 112C formed therein. Bottom electrode layer 150 is formed from any suitable electrically conductive material including, but not limited to, titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, etchable materials. Additionally, bottom electrode layer 150 is deposited over metallization layer 110 / interconnects 112A, 112B, 112C using any suitable material deposition processes including, but not limited to. chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.

[0045] Additionally, and as shown in FIG. 3, a switching layer 152 is deposited directly over bottom electrode layer 150. More specifically, switching layer 152 is deposited, disposed, and / or formed directly over bottom electrode layer 150. Switching layer 152 is formed from any suitable electrically conductive material including, but not limited to, niobium dioxide (NbO2). Additionally, switching layer 152 is deposited over bottom electrode layer 150 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD). physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.Attorney Docket No. 011-2318W001

[0046] A top electrode layer 154 is deposited directly switching layer 152. In the exemplary embodiment shown in FIG. 3. top electrode layer 154 is deposited, disposed, and / or formed directly over switching layer 152. Top electrode layer 154 is formed from any suitable electrically conductive material including, but not limited to, titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, etchable materials. Additionally, top electrode layer 154 is deposited over switching layer 152 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), a chemical mechanical planarization (CMP), and the like.

[0047] Furthermore, and as shown in FIG. 3, a dielectric material 156 is deposited over top electrode layer 154. More specifically, dielectric material 156 is deposited, disposed, and / or formed directly over top electrode layer 154. In exemplary embodiments, dielectric material 156 includes any suitable material having dielectric properties and / or characteristics including, but not limited to, silicon nitride (SiN). Additionally, dielectric material 156 is deposited over top electrode layer 154 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.

[0048] FIG. 4 shows various layers being patterned over metallization layer 110. In the exemplary embodiment, each of bottom electrode layer 150. switching layer 152, top electrode layer 154, and dielectric material 156 (see, FIG. 3) are patterned to remove at least a portion of the materials forming each layer. In exemplary embodiments, at least one patterning and / or material removal process is performed on bottom electrode layer 150, switching layer 152, top electrode layer 154, and dielectric material 156 to remove at least a portion of the material. The patterning and / or material removal processes include any suitable processes capable of structuring the material including, but not limited to, lithography, reactive ion etch (RIE), ion milling, wet etching, and the like.

[0049] The patterning of bottom electrode layer 150, switching layer 152, top electrode layer 154, and dielectric material 156 results in the formation of various distinct components and / or portions utilized within semiconductor device 100 (see, FIG. 12). For example, patterning the layers forms bottom electrode 120 directly over first interconnect 112A. That is, patterning bottom electrode layer 150 results in the formation of bottom electrode 120 being disposed directly over first interconnect 112A. As shown in the exemplary embodiment, bottom electrode 120 is smaller in size (e.g., width) than first interconnect 112A.Attorney Docket No. 011-2318W001As such, forming bottom electrode 120 also results in a portion of first interconnect 112A formed in metallization layer 110 being exposed subsequent to the patterning.

[0050] Additionally, patterning the layers forms threshold switching layer 122 directly over bottom electrode 120, as well as forming top electrode 124 directly over threshold switching layer 122. In the exemplary embodiment shown in FIG. 4, patterning switching layer 152 results in the formation of threshold switching layer 122 being disposed directly over bottom electrode 120. Additionally, patterning top electrode layer 154 results in the formation of top electrode 124 being disposed directly over threshold switching layer 122. As shown in FIG. 4, each of threshold switching layer 122 and top electrode 124 are sized and / or include a geometry that is substantially similar to bottom electrode 120.

[0051] In the exemplary embodiment shown in FIG. 4. the patterning of bottom electrode layer 150, switching layer 152, top electrode layer 154, and dielectric material 156 results in the formation of various distinct components and / or portions utilized within semiconductor device 100 (see, FIG. 12). For example, patterning the layers results in the formation of a first threshold switch 118A including bottom electrode 120, threshold switching layer 122, and top electrode 124, respectively. Additionally, patterning the layers results in the formation of second or distinct threshold switch 118B over second interconnect 112B included within metallization layer 110. More specifically, patterning bottom electrode layer 150 results in the formation of distinct bottom electrode 132 being disposed directly over second interconnect 112B. As shown, distinct bottom electrode 132 is smaller in size (e.g.. width) than second interconnect 1 12B. As such, forming distinct bottom electrode 132 also results in a portion of second interconnect 112B being exposed subsequent to the patterning.

[0052] Moreover, patterning the layers forms distinct threshold switching layer 134 directly over distinct bottom electrode 132, as well as forming distinct top electrode 136 directly over distinct threshold switching layer 134. In the exemplary embodiment shown in FIG. 4, patterning switching layer 152 results in the formation of distinct threshold switching layer 134 being disposed directly over distinct bottom electrode 132. Additionally, patterning top electrode layer 154 results in the formation of distinct top electrode 136 being disposed directly over distinct threshold switching layer 134. As shown in FIG. 4, each of distinct threshold switching layer 134 and distinct top electrode 136 are sized and / or include a geometry that is substantially similar to distinct bottom electrode 132. Distinct threshold switch 118B included in semiconductor device 100 is formed from distinct bottom electrode 132, distinct threshold switching layer 134, and distinct top electrode 136.

[0053] Additionally, the layers are patterned such that distinct bottom electrodeAttorney Docket No. 011-2318W001132, distinct threshold switching layer 134, and distinct top electrode 136 are spaced apart from and / or separated from bottom electrode 120, threshold switching layer 122, and top electrode 124. In the exemplary embodiment shown in FIG. 4, dielectric material 156 is patterned and / or removed such that only two distinct portions 1 8, 160 remain after performing the patterning process. More specifically, a first portion 158 of dielectric material 156 is disposed and / or formed directly over top electrode 124, while a second portion 160 of dielectric material 156 is disposed and / or formed directly over distinct top electrode 136. All remaining dielectric material 156 previously deposited over top electrode layer 154 (see, FIG. 3) is removed during the patterning process. As a result of the patterning process as shown in FIG. 4, at least a portion of first interconnect 112A, and second interconnect 112B are exposed. Additionally, and subsequent to the patterning process, the entirety of third interconnect 112C, as well as the remainder of metallization layer 110 are also exposed.

[0054] FIG. 5 shows the deposition of additional dielectric material 156. More specifically, and subsequent to the patterning, additional dielectric material 156 is disposed, encapsulates, and / or is deposited over metallization layer 110, the exposed portions of first interconnect 112A and second interconnect 112B, and the entirety of third interconnect 112C. Additionally, additional dielectric material 156 is deposited over at least a portion of bottom electrode 120, threshold switching layer 122, and top electrode 124 to substantially encapsulate the same. Also as shown in FIG. 5, depositing dielectric material 156 includes depositing dielectric material 156 over at least a portion of distinct bottom electrode 132, distinct threshold switching layer 134, and distinct top electrode 136 forming memory top electrode 130. As similarly discussed herein, dielectric material 156 includes any suitable material having dielectric properties and / or characteristics including, but not limited to, silicon nitride (SiN). Additionally, dielectric material 156 is deposited as shown in FIG. 5 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.

[0055] FIG. 6 shows a portion of dielectric material 156 being removed to expose various layers and / or portions including within semiconductor device 100. In the exemplary embodiment, material removal processes are performed to remove at least a portion of dielectric material 156 to expose top electrode 124 formed over first interconnect 112A and distinct top electrode 136 formed over second interconnect 112B. In exemplary' embodiments, the material removal processes include any suitable processes capable of removing dielectric material 156 and exposing top electrodes 124, 136, including, but not limited to, chemicalAttorney Docket No. 011-2318W001 mechanical polishing (CMP), selective deposition, lithography, reactive ion etch (RIE), ion milling, wet etching, and the like.

[0056] FIG. 7 shows various layers being deposited over dielectric material 156 as well as exposed top electrode 124 and distinct top electrode 136. In the exemplary embodiment, a memory stack layer 162 is deposited directly over dielectric material 156, exposed top electrode 124, and exposed, distinct top electrode 136, respectively. That is, memory stack layer 162 is deposited, disposed, and / or formed directly over dielectric material 156, and top electrodes 124, 136 exposed therein. Memory stack layer 162 is formed from any suitable electrically conductive material including, but not limited to, niobium dioxide (NbCh), vanadium oxides (VOX), alloyed niobium dioxide (NbCh), doped niobium dioxide (NbCh), and volatile resistive switching materials. Additionally, memory stack layer 162 is deposited over dielectric material 156 and exposed electrodes 124, 136 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), and the like.

[0057] Additionally, and as shown in FIG. 7, a memory top electrode layer 164 is deposited directly memory stack layer 162. More specifically, memory top electrode layer 164 is deposited, disposed, and / or formed directly over memory stack layer 162. Memory top electrode layer 164 is formed from any suitable electrically conductive material including, but not limited to, titanium nitride (TiN). ruthenium (Ru), iridium (Ir), and other suitable inert, etchable materials. Additionally, memory top electrode layer 164 is deposited over memory stack layer 162 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), and the like.

[0058] A layer 166 of dielectric material 156 is also deposited over memory top electrode layer 164. More specifically, layer 166 of dielectric material 156 is deposited, disposed, and / or formed directly7over memory' top electrode layer 164. As similarly discussed herein, layer 166 of dielectric material 156 includes any suitable material having dielectric properties and / or characteristics including, but not limited to. silicon nitride (SiN). Additionally, layer 166 of dielectric material 156 is deposited over memory top electrode layer 164 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), and the like.

[0059] FIG. 8 shows various layers being patterned over dielectric material 156 and top electrodes 124, 136. In the exemplary7embodiment, each of layer 166 of dielectricAttorney Docket No. 011-2318W001 material 156, memory top electrode layer 164, and memory stack layer 162 are patterned to remove at least a portion of the materials forming each layer. In exemplary embodiments, at least one patterning and / or material removal process is performed on layer 166 of dielectric material 156, memory top electrode layer 164, and memory stack layer 162 to remove at least a portion of the material. The patterning and / or material removal processes include any suitable processes capable of removing material including, but not limited to, lithography, reactive ion etch (RIE), ion milling, and / or, wet etching, and the like.

[0060] The patterning of layer 166 of dielectric material 156, memory top electrode layer 164, and memory7stack layer 162 results in the formation of various distinct components and / or portions utilized within semiconductor device 100 (see, FIG. 12). For example, patterning the layers forms memory stack 128 directly over top electrode 124 of threshold switch 118A. That is, patterning memory stack layer 162 results in the formation of memory stack 128 being disposed directly over top electrode 124 and at least a portion of remaining dielectric material 156 surrounding top electrode 124. As shown in the exemplary embodiment, memory stack 128 is larger in size (e.g, width) than top electrode 124. As such, forming memory stack 128 also results in a portion of memory stack 128 extending beyond top electrode 124 and / or being disposed over at least a portion of remaining dielectric material 156 subsequent to the patterning. In the exemplary' embodiment shown in FIG. 8, patterning memory stack layer 162 also results in the exposure of distinct top electrode 136, as well as at least a portion of dielectric material 156 previously deposited over metallization layer 110 and at least a portion of interconnects 1 12A, 1 12B, 112C, respectively.

[0061] Additionally, patterning the layers forms memory top electrode 130 directly over memory' stack 128. In the exemplary embodiment shown in FIG. 8, patterning memory top electrode layer 164 results in the formation of memory top electrode 130 being disposed directly over memory stack 128. As shown, memory top electrode 130 is sized and / or includes a geometry that is substantially7similar to memory stack 128.

[0062] Layer 166 of dielectric material 156 is also patterned and / or removed such that only a single portion of layer 166 remains after performing the patterning process on layer 166 of dielectric material 156, memory top electrode layer 164, and memory stack layer 162. More specifically, a single portion of layer 166 of dielectric material 156 is disposed and / or formed directly over memory' top electrode 130 subsequent to performing the patterning process. All remaining portions of layer 166 of dielectric material 156 previously deposited over memory top electrode layer 164 (see, FIG. 7) are removed during the patterning process. As discussed herein, at least a portion of previously deposited dielectric material 156 disposedAttorney Docket No. 011-2318W001 over metallization layer 110 and at least a portion of interconnects 112A, 112B, 112C remains and / or is exposed, along with distinct top electrode 136.

[0063] Patterning memory top electrode layer 164 and memory stack layer 162 to form memory top electrode 130 and memory stack 128, respectively, also forms memory element 126 included in semiconductor device 100. More specifically, and subsequent to the patterning of layer 166 of dielectric material 156, memory top electrode layer 164. and memory stack layer 162, memory element 126 is formed directly over threshold switch 118A and / or is formed over / aligned with first interconnect 112A included in metallization layer 110. In the exemplary embodiment shown in FIG. 8, memory element 126 formed over threshold switch 118A includes memory stack 128 disposed over top electrode 124 of first threshold switch 118A, and memory top electrode 130 disposed over memory stack 128.

[0064] FIG. 9 shows the deposition of additional dielectric material 156. More specifically, and subsequent to the patterning, additional dielectric material 156 is disposed, encapsulates, and / or is deposited over previously deposited dielectric material 156, exposed distinct top electrode 136, at least the exposed portions of memory stack 128 and memory top electrode 130, and the remaining portion of layer 166 of dielectric material 156. The depositing of additional dielectric material 156 as shown in FIG. 9, results in the formation of an interlayer dielectric (ILD) 138 andthe encapsulation of threshold switches 118A, 118B and memory element 126 within ILD 138. More specifically, ILD 138 formed from additionally deposited dielectric material 156, the remaining portion of layer 166, and previously deposited dielectric material 156 (see, FIGS. 5 and 6), respectively, encapsulates exposed portion of memory stack 128 and memory top electrode 130. Additionally, ILD 138 encapsulates distinct top electrode 136 included in threshold switch 118B formed over second interconnect 112B. As similarly discussed herein, dielectric material 156 forming ILD 138 includes any suitable material having dielectric properties and / or characteristics including, but not limited to, silicon nitride (SiN). Additionally, dielectric material 156 is deposited as shown in FIG. 9 to form ILD 138 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), and the like.

[0065] FIG. 10 shows the deposition of a distinct dielectric layer over ILD 138 to form dielectric layer 140. That is, and subsequent to formation of ILD 138 encapsulating threshold switches 118A, 118B and memory element 126, distinct dielectric material is deposited, disposed, and / or formed over ILD 138 to form dielectric layer 140. Dielectric layer 140 is formed and / or disposed over ILD 138 using any suitable material deposition and / orAttorney Docket No. 011-2318W001 material removal processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), and the like. Additionally in the exemplary embodiments, dielectric layer 140 is formed from any suitable material having dielectric properties and / or characteristics including, but not limited to, silicon dioxide (SiO2).

[0066] FIG. 11 shows the patterning and / or material removal of distinct portions of semiconductor device 100 to form distinct interconnects 142 and vias 144 (see, FIG. 12) therein. That is, distinct portions and / or layers of semiconductor device 100 are patterned and / or undergo material removal processes to form openings 168. In the exemplary embodiment, first opening 168A is formed through dielectric layer 140 and at least a portion of ILD 138, adjacent to and / or above memory element 126. More specifically, first opening 168 A extends through dielectric layer 140 and ILD 138 and exposes a portion of memory top electrode 130 of memory element 126. Additionally, second opening 168B extends through dielectric layer 140 and at least a portion of ILD 138 to expose distinct top electrode 136 of threshold switch 118B. Finally, third opening 168C extends through dielectric layer 140 and the entirety of ILD 138 to expose a portion of third interconnect 112C formed in metallization layer 110. The patterning and / or material removal processes to forming openings 168A, 168B, 168C include any suitable processes capable of removing material including, but not limited to, lithography, reactive ion etch (RIE), ion milling, and / or, wet etching, and the like.

[0067] FIG. 12 shows the deposition of materials within openings 168A, 168B, 168C to form distinct interconnects 142 and vias 144, respectively. In the exemplary embodiments, material is deposited, disposed, and / or formed within each of the distinct openings 168A, 168B, 168C to first forms distinct vias 144A, 144B, 144C within semiconductor device 100. Subsequent to the deposition of materials and formation of vias 144A, 144B, 144C, additional material is deposited within the remainer of openings 168A, 168B, 168C, over vias 144A, 144B, 144C, to form distinct interconnects 142A, 142B, 142C. In exemplary embodiments, the material deposited within respective openings 168A, 168B, 168C to form vias 144 is distinct from or identical to the material forming distinct interconnects 142.

[0068] As shown in FIG. 12, first via 144A extends through a portion of ILD 138 formed above and / or substantially encapsulating threshold switch 118A and memory element 126, respectively, to contact memory top electrode 130 of memory element 126. Second via 144B extends through a portion of ILD 138 formed above distinct threshold switch 1 18B, as well as a portion of dielectric layer 140 to contact distinct top electrode 136 ofAttorney Docket No. 011-2318W001 threshold switch 118B. Third via 144C is disposed and / or extends through at least a portion of ILD 138 and dielectric layer 140, respectively, and contacts third interconnect 112C. Vias 144 extending through ILD 138 and / or dielectric layer 140 are formed from any suitable conductive material to facilitate the electrical connection and / or communication with various components (e.g, interconnects 142, threshold switch 118A, 118B, memory element 126) included within semiconductor device 100. In exemplary embodiments, vias 144 are formed from a material or material compound including, but not limited to, copper (Cu), aluminum (Al), or any other suitable material having similar conductive characteristics and / or properties. Additionally, vias 144 are formed within semiconductor device 100 using any suitable material deposition techniques or processes, as discussed herein.

[0069] In the exemplary embodiment shown in FIG. 12. first distinct interconnect 142A is formed in dielectric layer 140 and is substantially aligned with threshold switch 118A, memory element 126, and first interconnect 112A formed in metallization layer 110, respectively. Additionally, first distinct interconnect 142A is formed on, disposed over, and / or contacts a portion of ILD 138 that separates memory element 126 and dielectric layer 140. Second distinct interconnect 142B is substantially aligned with second or distinct threshold switch 118B and second interconnect 112B, respectively, while third distinct interconnect 142C is substantially aligned with third interconnect 112C. Each of the respective distinct interconnects 142A, 142B, 142C are electrically coupled to and / or in electrical communication with respective components (e.g.. threshold switch 118A, 118B. memory element 126) and / or interconnects (e.g, third interconnect 1 12C) by corresponding vias 144A, 144B, 144C, as discussed herein. Distinct interconnects 142 included in dielectric layer 140 are formed from any suitable conductive material to facilitate the electrical connection and / or communication with various components (e.g. vias, threshold switch 118A, 118B. memory element 126) included within semiconductor device 100. In exemplary embodiments, interconnects 142 are formed from a material or material compound including, but not limited to, copper (Cu), aluminum (Al), or any other suitable material having similar conductive characteristics and / or properties. Additionally, distinct interconnects 142 are formed within dielectric layer 140 using any suitable material deposition techniques and / or processes, as discussed herein.

[0070] FIG. 13 shows cross-sectional view of an additional exemplary embodiment of semiconductor device 200 including threshold switch 218 and memory element 226 formed therein. In the exemplary embodiment, and as similarly discussed herein with respect to FIG. 1, semiconductor device 200 shown and discussed herein with respect to FIG.Attorney Docket No. 011-2318W00113 is included within and / or formed in a portion of a larger semiconductor structure. It is understood that similarly numbered and / or named components may function in a substantially similar fashion. Redundant explanation of these components has been omitted for brevity.

[0071] In the exemplary embodiment shown in FIG. 13, semiconductor device 200 includes a single threshold switch 218 and memory element 226. More specifically, and distinct from semiconductor device 100 shown and discussed herein with respect to FIG. 1, semiconductor device 200 includes a single threshold switch 218 and memory element 226, but does not include a second or distinct threshold switch formed therein (see, FIG. 1). As show n, threshold switch 218 includes bottom electrode 220 disposed directly over interconnect 212A formed in metallization layer 210, threshold switching layer 222 disposed directly over bottom electrode 220, and top electrode 224 disposed directly over threshold switching layer 222. Additionally as show n in FIG. 13, memory element 226, formed directly over threshold switch 218, includes memory stack 228 disposed directly over top electrode 224 of threshold switch 218 and memory top electrode 230 disposed directly over memory' stack 228. As similarly discussed herein threshold switch 218 and memory element 226 are encapsulated by ILD 238. Adjacent threshold switch 218 and memory element 226 in semiconductor device 200 is via 244B contacting, electrically coupling, and / or electrically connecting interconnect 212B formed in metallization layer 210 and distinct interconnect 242B formed in dielectric layer 240.

[0072] FIG. 14 shows cross-sectional view of a portion of another exemplary embodiment of semiconductor device 300. In the exemplary embodiment, semiconductor device 300 includes threshold switch 318 and memory element 326. As discussed herein, the portion of semiconductor device 300 shown in FIG. 14 can be implemented and / or included in semiconductor device 100 shown and discussed herein with respect to FIG. 1, or alternatively with semiconductor device 200 shown and discussed herein with respect to FIG. 13.

[0073] In the exemplary embodiment, top electrode 324 included in threshold switch 318 is formed from two distinct portion and / or materials 370, 372. More specifically, top electrode 324 of threshold switch 318 includes a first material 370 disposed directly over threshold switching layer 322 of threshold switch 318, and a second, distinct material 372 disposed directly over first material 370. Second material 372 of top electrode 324 is disposed, formed, and / or positioned between first material 370 and memory stack 328 of memory element 326. That is, and as shown in FIG. 14, memory' stack 328 is disposed, formed, and / or deposited directly over second material 372 of top electrode 324. First material 370 and second material 372 collectively forming top electrode 324 of threshold switch 318 are formed fromAttorney Docket No. 011-2318W001 any suitable electrically conductive material including, but not limited to, titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, etchable or pattemable materials. Additionally, each of first material 370 and second material 372 are formed from distinct materials. For example, first material 370 of top electrode 324 is formed from ruthenium (Ru), while second material 372 is formed from titanium nitride (TiN). Top electrode 324 including first material 370 and second material 372 is formed using any suitable material deposition and / or removal technique or process, as similarly discussed herein.

[0074] FIG. 15 shows cross-sectional view of a portion of an additional exemplary embodiment of semiconductor device 300. In the exemplary embodiment, semiconductor device 300 includes threshold switch 318 and memory element 326. As discussed herein, the portion of semiconductor device 300 shown in FIG. 15 can be implemented and / or included in semiconductor device 100 shown and discussed herein with respect to FIG. 1, or alternatively with semiconductor device 200 shown and discussed herein with respect to FIG. 13.

[0075] In the exemplary embodiment, and similar to top electrode 324 discussed herein with respect to FIG. 14, bottom electrode 320 included in threshold switch 318 is formed from two distinct portion and / or materials 374, 376. More specifically, bottom electrode 320 of threshold switch 318 includes a third material 374 disposed directly over interconnect 312A. and afourth, distinct material 376 disposed directly over third material 374. Fourth material 376 of bottom electrode 320 is disposed, formed, and / or positioned between third material 374 and threshold switching layer 322 of threshold switch 318. That is, and as shown in FIG. 15, threshold switching layer 322 is disposed, formed, and / or deposited directly over fourth material 376 of bottom electrode 320. Third material 374 and fourth material 376 collectively forming bottom electrode 320 of threshold switch 318 are formed from any suitable electrically conductive material including, but not limited to, titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, etchable or pattemable materials. Additionally, each of third material 374 and fourth material 376 are formed from distinct materials. For example, third material 374 of bottom electrode 320 is formed from ruthenium (Ru), while fourth material 376 is formed from titanium nitride (TiN). Bottom electrode 320 including materials 374, 376 is formed using any suitable material deposition and / or removal technique or process, as similarly discussed herein.

[0076] Additionally, or alternatively, memory top electrode 330 included in memory element 326 is formed from two distinct portion and / or materials 378, 380. That is, memory top electrode 330 of memory element 326 includes a fifth material 378 disposedAttorney Docket No. 011-2318W001 directly over memory stack 328. and a sixth, distinct material 380 disposed directly over fifth material 378. In the exemplary embodiment, sixth material 380 of memory top electrode 330 is disposed, formed, and / or positioned between fifth material 378 and via 344A and ILD 338, respectively. That is, and as shown in FIG. 15, via 334A and ILD 338, collectively, are disposed, formed, and / or deposited directly over sixth material 380 of memory7top electrode 330. Fifth material 378 and sixth material 380 collectively forming memory top electrode 330 of memory element 326 are formed from any suitable electrically conductive material including, but not limited to, titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, etchable or pattemable materials. Additionally, each of fifth material 378 and sixth material 380 are formed from distinct materials. Memory top electrode 330 including materials 378, 380 is formed using any suitable material deposition and / or removal technique or process, as similarly discussed herein.

[0077] Although shown in FIG. 15 as including distinct materials included in each of bottom electrode 320, top electrode 324, and memory7top electrode 330, it is understood that semiconductor device 300 can include any combination of distinct portions that include distinct materials. That is, and in other exemplary embodiments, bottom electrode 320, top electrode 324, and / or memory top electrode 330 included in semiconductor device 300 can and / or be formed from distinct materials, as discussed herein.

[0078] FIGS. 16A and 16B show flowcharts illustrating example processes 400 for manufacturing a semiconductor device. More specifically, FIGS. 16A and 16B show nonlimiting examples of processes for manufacturing semiconductor devices including a memory element and at least one threshold switch therein. The semiconductor device manufactured using the processes shown and discussed herein with respect to FIGS. 16A and 16B may be substantially similar to semiconductor device 100, 200, 300, shown and discussed herein with respect to FIGS. 1-15.

[0079] In process 402 (see, FIG. 16 A), a bottom electrode layer is deposited over a metallization layer including a plurality of interconnects formed therein. In process 404, a switching layer is deposited over the bottom electrode layer. In process 406, a top electrode layer is deposited over the switching layer. In process 408, a dielectric material is deposited over the top electrode layer. In process 410, the dielectric material, the top electrode layer, and the switching layer are patterned over a first interconnect of the plurality of interconnects formed in the metallization layer. Patterning the dielectric material, the top electrode layer, and the switching layer in process 410 includes forming a bottom electrode disposed over the first interconnect, a threshold switching layer disposed over the bottom electrode, and a topAttorney Docket No. 011-2318W001 electrode disposed over the threshold switch. The patterning in process 410 also forms a first threshold switch over the first interconnect including the bottom electrode, the threshold switching layer, and the top electrode, respectively. Patterning the dielectric material, the bottom electrode layer, the top electrode layer, and the switching layer in process 410 also includes patterning the dielectric material, the bottom electrode layer, the top electrode layer, and the switching layer over a second, distinct interconnect formed in the metallization layer to form a second or distinct threshold switch over the second, distinct interconnect. The distinct threshold switch includes a distinct bottom electrode disposed over the distinct, second interconnect, a distinct threshold switching layer disposed over the distinct bottom electrode, and a distinct top electrode disposed over the distinct threshold switching layer.

[0080] In process 412, dielectric material is deposited over at least a portion of the metallization layer, the bottom electrode, the threshold switch, the top electrode, the distinct bottom electrode, the distinct threshold switch, and the distinct top electrode. In process 414, the top electrode of the first threshold switch formed over the first interconnect and the distinct top electrode of the distinct threshold switch formed over the distinct, second interconnect are exposed. In process 416, a memory stack layer is deposited over the exposed top electrode formed over the first interconnect, the distinct top electrode formed over the distinct, second interconnect, and the dielectric material. In process 418 (see, FIG. 16B) a memory top electrode layer is deposited over the memory stack layer. In process 420 dielectric material is deposited over the memory top electrode layer. In process 422, the dielectric material, the memory top electrode layer, and the memory stack layer are patterned. Patterning the dielectric material, the memory top electrode layer, and the memory stack layer in process 422 includes forming a memory stack disposed over the top electrode of the first threshold switch formed over the first interconnect, and a memory top electrode disposed over the memory’ stack. Patterning the dielectric material, the memory top electrode layer, and the memory stack layer in process 422 also includes patterning the dielectric material, the memory top electrode layer, and the memory’ stack layer to expose the distinct top electrode of the distinct threshold switch formed over the distinct, second interconnect. Additionally, the patterning in process 422 forms a memory element over the first threshold switch, aligned with the first interconnect. In the exemplary embodiment, the memory element includes the memory stack disposed over the top electrode of the first threshold switch, and the memory top electrode disposed over the memory stack.

[0081] In process 424. the formed memory element and the formed threshold switches are encapsulated. For example, in process 424 dielectric material is deposited overAttorney Docket No. 011-2318W001 the memory' stack and the memory top electrode of the memory' element, as well as the exposed distinct top electrode of the distinct threshold switch, to form an inter-layer dielectric (ILD) that encapsulates the memory element and the threshold switches. In process 426, distinct dielectric material is deposited over the ILD to form a dielectric layer over the ILD. In process 428, distinct interconnects and vias are formed in the dielectric layer and the ILD, respectively. For example, a first via extends through at least a portion of the ILD and contacts the memory top electrode of the memory element. The first via electrically couples and / or connects an interconnect formed in the dielectric layer, above and / or aligned with the memory element, the first threshold switch, and the first interconnect formed in the metallization layer, respectively. Additionally, a second via extends through at least a portion of the dielectric layer and the ILD to contact the distinct top electrode of the distinct threshold switch. The second via electrically couples and / or connects a distinct interconnect formed in the dielectric layer, above and / or aligned with the distinct threshold switch and the second contact formed in the metallization layer, respectively. Furthermore, a third via extends through at least a portion of the dielectric layer and the ILD to contact and electrically couple an interconnect formed in the dielectric layer to a third interconnect formed in the metallization layer.

[0082] The foregoing drawings show some of the processing associated according to several embodiments of this disclosure. In this regard, each drawing or block within a flow diagram of the drawings represents a process associated with embodiments of the method described. It should also be noted that in some alternative implementations, the acts noted in the drawings or blocks may occur out of the order noted in the figure or, for example, may in fact be executed substantially concurrently or in the reverse order, depending upon the act involved. Also, one of ordinary skill in the art w ill recognize that additional blocks that describe the processing may be added.

[0083] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.Attorney Docket No. 011-2318W001

[0084] Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as ’‘about,” “approximately” and “substantially,” are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and / or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” and / or “substantially” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate + / - 10% of the stated value(s).

[0085] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

Attorney Docket No. 011-2318W001CLAIMSWhat is claimed is:

1. A semiconductor device, comprising: a substrate; a metallization layer disposed over the substrate, the metallization layer including a plurality of interconnects; a first threshold switch formed over a first interconnect of the plurality of interconnects, the first threshold switch including: a first bottom electrode disposed directly over the first interconnect; a first threshold switching layer disposed over the first bottom electrode; and a first top electrode disposed directly over the first threshold switching layer; a memory element formed over the first threshold switch, the memory element including: a memory stack disposed over the first top electrode of the first threshold switch; and a memory top electrode disposed directly over the memory stack; and a second threshold switch formed over a second interconnect of the plurality of interconnects, the second threshold switch including: a second bottom electrode disposed directly over the second interconnect; a second threshold switching layer disposed directly over the second bottom electrode; and a second top electrode disposed directly over the second threshold switching layer.

2. The semiconductor device of claim 1, further comprising: an inter-layer dielectric (ILD) disposed over the metallization layer, the ILD disposed substantially around the memory element, the first threshold switch, and the second threshold switch; a first via disposed through the ILD, the first via in contact with the memory top electrode of the memory7element; and a second via disposed through the ILD, the second via in contact with the second top electrode of the second threshold switch.Attorney Docket No. 011-2318W0013. The semiconductor device of claim 2, further comprising: a dielectric layer disposed over the ILD; and a plurality of distinct interconnects formed in the dielectric layer, the plurality of distinct interconnects including: a third interconnect disposed over and directly connected to the first via; and a fourth interconnect disposed over and directly connected to the second via, wherein the second via is disposed through a portion of the dielectric layer.

4. The semiconductor device of claim 1, wherein the first top electrode of the first threshold switch further includes: a first material disposed directly over the first threshold switching layer of the first threshold switch; and a second material disposed directly over the first material, the second material disposed between the first material and the memory stack of the memory element, wherein the second material is distinct from the first material.

5. The semiconductor device of claim 1, wherein at least one of: the first bottom electrode of the of the first threshold switch further includes: a first material disposed directly over the first interconnect of the plurality of interconnects, and a second material disposed directly over the first material, the second material distinct from the first material; or the niemon' top electrode of the memory element further includes: a third material disposed directly over the memory stack of the memory element, and a fourth material disposed directly over the third material, the fourth material distinct from the third material.

6. The semiconductor device of claim 1, wherein the first bottom electrode of the first threshold switch and the second bottom electrode of the second threshold switch are formed from a material selected from the group consisting of: titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, etchable materials.Attorney Docket No. 011-2318W0017. The semiconductor device of claim 1, wherein the first top electrode of the first threshold switch and the second top electrode of the second threshold switch are formed from a material selected from the group consisting of: titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, pattemable materials.

8. The semiconductor device of claim 1, wherein the first threshold switching layer of the first threshold switch and the second threshold switching layer of the second threshold switch are formed from a material selected from the group consisting of: niobium dioxide (NbCh), vanadium oxides (VOx), alloyed niobium dioxide (NbCh), doped niobium dioxide (NbCh), and volatile resistive switching materials.

9. A semiconductor device, comprising: a substrate; a metallization layer disposed over the substrate, the metallization layer including a plurality of interconnects; a threshold switch formed over a first interconnect of the plurality of interconnects, the threshold switch including: a bottom electrode disposed directly over the first interconnect; a threshold switching layer disposed over the bottom electrode; and a top electrode disposed directly over the threshold switching layer; and a memory element formed over the threshold switch, the memory element including: a memory’ stack disposed over the top electrode of the threshold switch; and a memory top electrode disposed directly over the memory' stack.

10. The semiconductor device of claim 9, further comprising: an inter-layer dielectric (ILD) disposed over the metallization layer and disposed substantially around the threshold switch and the memory element; a via disposed through the ILD, the via in contact with the memory top electrode of the memory element; and a distinct via disposed through the ILD, adjacent the memory element, the distinct via in contact with a second interconnect of the plurality7of interconnects included in the metallization layer.1 1. The semiconductor device of claim 10, further comprising:Attorney Docket No. 011-2318W001 a dielectric layer disposed over the ILD; and a plurality of distinct interconnects formed in the dielectric layer, the plurality of distinct interconnects including: a third interconnect disposed over and directly connected to the via; and a fourth interconnect disposed over and directly connected to the distinct via, wherein the distinct via is disposed through a portion of the dielectric layer.

12. The semiconductor device of claim 9, wherein the top electrode of the threshold switch further includes: a first material disposed directly over the threshold switching layer; and a second material disposed directly over the first material, the second material disposed between the first material and the memory stack of the memory element, wherein the second material is distinct from the first material.

13. The semiconductor device of claim 12, wherein at least one of: the bottom electrode of the threshold switch further includes: a third material disposed directly over the first interconnect of the plurality of interconnects, and a fourth material disposed directly over the third material, the fourth material distinct from the third material; or the memory top electrode of the memory element further includes: a fifth material disposed directly over the memory stack of the memory element, and a sixth material disposed directly over the fifth material, the sixth material distinct from the fifth material.

14. The semiconductor device of claim 9, wherein the bottom electrode and the top electrode of the threshold switch are formed from a material selected from the group consisting of: titanium nitride (TiN), ruthenium (Ru), iridium (Ir), and other suitable inert, pattemable materials.

15. The semiconductor device of claim 9, wherein the threshold switch of the threshold switch is formed from a material selected from the group consisting of: niobium dioxideAttorney Docket No. 011-2318W001(NbCh), vanadium oxides (VOx), alloyed niobium dioxide (NbCh), doped niobium dioxide (NbCh), and volatile resistive switching materials.

16. A method of manufacturing a semiconductor device, the method comprising: depositing a bottom electrode layer over a metallization layer including a plurality7of interconnects; depositing a switching layer over the bottom electrode layer; depositing a top electrode layer over the switching layer; depositing a dielectric material over the top electrode layer; patterning the dielectric material, the top electrode layer, the switching layer, and the bottom electrode layer over an interconnect of the plurality of interconnects to form: a bottom electrode disposed over the interconnect, a threshold switching layer disposed over the bottom electrode, and a top electrode disposed over the threshold switch; depositing the dielectric material over the metallization layer, the bottom electrode, the threshold switching layer, and the top electrode; exposing the top electrode within the dielectric material; depositing a memory7stack layer over the top electrode and the dielectric material; depositing a memory top electrode layer over the memory stack layer; depositing the dielectric material over the memory top electrode layer; patterning the dielectric material, the memory top electrode layer, and the memory stack layer over the top electrode to form: a memory stack disposed over the top electrode, and a memory top electrode disposed over the memory stack; and encapsulating the memory stack and the memory top electrode with the dielectric material to form an inter-layer dielectric (ILD).

17. The method of claim 16 further comprising depositing a distinct dielectric material over the ILD to form a dielectric layer.

18. The method of claim 17, further comprising: forming a threshold switch over the interconnect of the plurality of interconnects, the threshold switch including: the bottom electrode disposed over the interconnect;Attorney Docket No. 011-2318W001 the threshold switching layer disposed over the bottom electrode; and the top electrode disposed over the threshold switch: and forming a memory element over the threshold switch, the formed memory element including: the memory stack disposed over the top electrode of the threshold switch; and the memory top electrode disposed over the memor\rstack.

19. The method of claim 18, wherein the patterning of the dielectric material, the top electrode layer, the switching layer, and the bottom electrode layer further includes: forming a distinct threshold switch over a distinct interconnect of the plurality of interconnects, the distinct threshold switch including: a distinct bottom electrode disposed over the distinct interconnect, a distinct threshold switching layer disposed over the distinct bottom electrode; and a distinct top electrode disposed over the distinct threshold switch.

20. The method of claim 19, wherein the encapsulating of the memory stack and the memory top electrode to form the ILD further includes: encapsulating the distinct threshold switch formed over the distinct interconnect within the ILD.

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