Semiconductor devices including electrodes and plurality of pillars, and methods of forming same

Abstract

Semiconductor devices are disclosed. The devices include an interconnect layer disposed over a substrate, an interconnect disposed within the interconnect layer, and a bottom electrode stack disposed directly over a portion of the interconnect. Additionally, the devices include a plurality of pillars disposed over at least one of the interconnect layer or the interconnect. The plurality of pillars includes a pillar encapsulating the bottom electrode stack, where the pillar is formed over the interconnect. The plurality of pillars also include at least one distinct pillar formed over at least one of the interconnect layer or the interconnect, adjacent to and spaced apart from the pillar encapsulating the bottom electrode stack. Moreover, the plurality of pillars are formed from a dielectric material..

Description

011-2326W001SEMICONDUCTOR DEVICES INCLUDING ELECTRODES AND PLURALITY OF PILLARS, AND METHODS OF FORMING SAMECROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 708,835, filed October 18, 2024, the entirety of which is hereby incorporated herein by this reference.BACKGROUND

[0002] The disclosure relates generally to semiconductor devices, and more particularly, to semiconductor devices including electrodes and a plurali ty of pillars, and methods of forming the semiconductor devices including the electrodes and the plurality of pillars.

[0003] Semiconductor devices are essential components in modem electronics, enabling the functionality of integrated circuits, transistors, diodes, and various optoelectronic systems. These devices are built on semiconductor materials — primarily silicon — using intricate layering and doping processes that create p-n junctions and active regions necessary for controlling electrical conductivity. Electrodes, typically made of metals like aluminum or copper, are deposited onto these semiconductor layers to provide electrical contact, allowing current to flow into and out of the device. Their precise placement and integrity are critical for ensuring device performance, as any irregularity in electrode formation can impact electrical behavior, signal integrity, and overall reliability.

[0004] One key manufacturing challenge in semiconductor devices is center height variation across layers, which refers to non-uniform thickness or elevation differences between the central region and edges of a layer. These variations can occur during processes such as chemical vapor deposition (CVD). etching, or chemical mechanical planarization (CMP), and they can lead to misalignment issues, defective layer stacking, or inconsistent electrical properties. In particular, when center height variation affects the interface between electrodes and active semiconductor regions, it may cause increased contact resistance or incomplete connections, leading to degraded device performance or outright failure. Controlling such variations through improved process calibration and metrology is essential for ensuring high yield and long-term reliability in semiconductor fabrication.BRIEF DESCRIPTION

[0005] A first aspect of the disclosure provides a semiconductor device including011-2326W001 an interconnect layer disposed over a substrate; an interconnect disposed within the interconnect layer; a bottom electrode stack disposed directly over a portion of the interconnect; and a plurality of pillars disposed over at least one of the interconnect layer or the interconnect, the plurality of pillars including: a pillar encapsulating the bottom electrode stack, the pillar formed over the interconnect; and at least one distinct pillar formed over at least one of the interconnect layer or the interconnect, adjacent to and spaced apart from the pillar encapsulating the bottom electrode stack, wherein the plurality of pillars are formed from a dielectric material.

[0006] A second aspect of the disclosure provides a method of manufacturing a semiconductor device. The method includes depositing a dielectric material directly over: an interconnect layer; an interconnect formed within the interconnect layer; and a bottom electrode stack disposed directly over the interconnect; depositing a lithography stack directly over the dielectric material; and etching the lithography stack and the dielectric material to form a plurality of pillars over at least one of the interconnect layer or the interconnect, the plurality of pillars formed from the dielectric material and including: a pillar encapsulating the bottom electrode stack; and at least one distinct pillar disposed over at least one of the interconnect layer or the interconnect, adjacent to and spaced apart from the pillar encapsulating the bottom electrode stack.

[0007] The illustrative aspects of the present disclosure are designed to solve the problems herein described and / or other problems not discussed.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure, in which:

[0009] FIG. 1 shows a cross-sectional view of a semiconductor device including a bottom electrode and a plurality of pillars, according to embodiments of the disclosure.

[0010] FIGS. 2-9 show cross-sectional views of a semiconductor device undergoing various processes for forming a bottom electrode and a plurality of pillars, according to embodiments of the disclosure.

[0011] FIG. 10 shows a flow chart illustrating processes for forming a semiconductor device including a bottom electrode and a plurality of pillars, according to embodiments of the disclosure.

[0012] It is noted that the drawings of the disclosure are not to scale. The drawings011-2326W001 are intended to depict only ty pical aspects of the disclosure and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.DETAILED DESCRIPTION

[0013] As an initial matter, in order to clearly describe the current disclosure it will become necessary to select certain terminology when referring to and describing relevant components within the disclosure. When doing this, if possible, common industry terminology will be used and employed in a manner consistent with its accepted meaning. Unless otherw ise stated, such terminology should be given a broad interpretation consistent with the context of the present application and the scope of the appended claims. Those of ordinary’ skill in the art will appreciate that often a particular component may be referred to using several different or overlapping terms. What may be described herein as being a single part may’ include and be referenced in another context as consisting of multiple components. Alternatively, what may be described herein as including multiple components may be referred to elsewhere as a single part.

[0014] As discussed herein, the disclosure relates generally to semiconductor devices, and more particularly, to semiconductor devices including electrodes and a plurality of pillars, and methods of forming the semiconductor devices including the electrodes and the plurality7of pillars.

[0015] These and other embodiments are discussed below with reference to FIGS. 1-10. However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these Figures is for explanatory’ purposes only and should not be construed as limiting.

[0016] FIG. 1 shows cross-sectional view of a semiconductor module or device. In the exemplary embodiment, semiconductor device 100 includes a portion of a larger semiconductor structure. Semiconductor device 100 shown in FIG. 1 (see also, FIG. 7) includes a semiconductor device having undergone some, but not all processes, for forming complete elements and / or components to be included with the larger semiconductor structure. As discussed herein, semiconductor device 100 includes electrode(s) formed over an interconnect and a plurality of the plurality of pillars.

[0017] Semiconductor device 100 includes a substrate 102. Substrate 102 includes or forms a base layer or layers of semiconductor device 100 that are formed from semiconducting material(s) and / or are formed from any suitable module, material, or material compositions that011-2326W001 includes semiconducting properties / characteristic. In the exemplary embodiment show n in FIG. 1, substrate 102 is formed from a plurality of layers that may be patterned and / or materials disposed over one another. Specifically, substrate 102 includes a silicon (Si) base layer 104, a silicon dioxide (SiCh) layer 106 disposed and / or formed directly over base layer 104. Additionally in the exemplary' embodiment, substrate 102 includes a silicon nitride (SiN) layer 108 disposed and / or formed directly over SiO2 layer 106.

[0018] In other exemplary embodiments, substrate 102 is formed from indium phosphide (InP) or Indium gallium arsenide (InGaAs), or any other suitable materials or compositions consisting essentially of one or more compound semiconductors. For example, substrate 102 can be provided as a bulk substrate, as part of a silicon-on-insulator (SOI) w afer, or as a partially fabricated CMOS device wafer. Additionally, or alternatively, substrate 102 may be formed from, for example, silicon (Si), silicon carbide (SiC), germanium (Ge), germanium oxide (GeO), cadmium zinc telluride (CdZnTe), gallium nitride (GaN), or gallium arsenide (GaAs). Furthermore, substrate 102 may be fabricated as a layer or multiple layers of semiconductor material, substances or materials consisting essentially of one or more compound semiconductors having a composition defined by the formula AlXlGaX2InX3AsYlPY2NY3SbY4, where XI, X2, X3, Yl, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substances can include II-VI compound semiconductors having a composition ZnAlCdA2SeBlTeB2, where Al, A2, Bl, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity).

[0019] Semiconductor device 100 also includes an interconnect layer 110 disposed over substrate 102. In the exemplary' embodiment shown in FIG. 1, interconnect layer 110 is disposed and / or formed directly over SiN layer 108 of substrate 102. Interconnect layer 110 is disposed, deposited, patterned, and / or formed over substrate 102 using any suitable material deposition technique and / or process including, but not limited to, lithography, reactive ion etch (RIE), chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like. Additionally, interconnect layer 110 is formed from any suitable, dielectric material included within semiconductor device 100. For example, as shown in FIG. 1, interconnect layer 110 is formed from silicon dioxide (SiCh).

[0020] Interconnect layer 110 included in semiconductor device 100 also includes at least one interconnect 112 formed therein. More specifically, and in the exemplary embodiment011-2326W001 interconnect 112 extends through interconnect layer 110, as well as silicon nitride (SiN) layer 108 and at least a portion of silicon dioxide (SiCh) layer 106 of substrate 102. In other exemplary embodiments, interconnect 112 extends through interconnect layer 110 and ends at, contacts, and / or is disposed over silicon nitride (SiN) layer 108 of substrate 102. Interconnect 112 included in interconnect layer 110 is formed from any suitable conductive material to facilitate the electrical connection and / or communication with various components (e.g, vias, memory component, threshold switches) included within semiconductor device 100. In exemplary embodiments, interconnect 112 formed from a material or material compound including, but not limited to, Copper (Cu), cobalt (Co), iron (Fe), nickel (Ni), silver (Ag), and the like. Additionally, interconnect 112 is formed within interconnect layer 110 using any suitable material removal and / or deposition techniques. Although a single interconnect 112 is shown in FIG. 1. it is to be understood that semiconductor device 100 can include more interconnects formed therein.

[0021] As shown in FIG. 1, semiconductor device 100 also includes a bottom electrode stack 118 positioned over interconnect 112. More specifically, and in the exemplary embodiment, bottom electrode stack 118 is disposed directly over, is formed directly on, contacts, and / or covers at least a portion of interconnect 112 formed in interconnect layer 110. As discussed herein, at least a portion of interconnect 1 12 is exposed and / or remains uncovered by bottom electrode stack 118 and distinct elements of semiconductor device 100. Additionally, bottom electrode stack 118 is substantially aligned with and / or positioned over interconnect 112 included in interconnect layer 110. Bottom electrode stack 118 is formed and / or disposed directly over at least a portion of interconnect 112 using any suitable material deposition and / or material removal processes, as discussed herein (see e.g., FIGS. 2-4).

[0022] Bottom electrode stack 118 is formed from and / or includes at least one distinct conductive material positioned over interconnect 112. In exemplary embodiments, the at least one distinct conductive material positioned over interconnect 112 includes two distinct conductive materials 120, 122. That is, at least one of the distinct conductive materials 120, 122 are distinct from interconnect 112. In a non-limiting example, at least first distinct conductive material 120 is distinct from interconnect 112, while second distinct conductive material 122 is distinct from or the same as interconnect 112. As shown in FIG. 1, the first distinct conductive material 120 forming bottom electrode stack 118 includes a titanium (Ti) layer disposed directly over a portion of interconnect 112, and a second distinct conductive material 122 includes a titanium nitride (TiN) layer disposed directly over the first distinct conductive material 120 formed from titanium (Ti) layer. As such, the titanium (Ti) layer forming the first distinct011-2326W001 conductive material 120 is disposed, formed, and / or positioned between interconnect 112 and the second conductive material 122 (e.g, titanium nitride (TiN)) forming bottom electrode stack 118. In the example, the titanium (Ti) layer and the titanium nitride (TiN) layer forming the distinct conductive material 120, 122 collectively form bottom electrode stack 1 18 within semiconductor device 100. It is to be understood that the conductive material(s) forming bottom electrode stack 118 can be formed from additional suitable materials and / or combinations of materials.

[0023] Semiconductor device 100 also may include a hard mask layer 124 disposed over bottom electrode stack 118. More specifically, and in the exemplary embodiment shown in FIG. 1, hard mask layer 124 is disposed directly over, is formed directly on, and / or covers titanium nitride (TiN) forming second distinct conductive material 122 of bottom electrode stack 118. As shown, hard mask layer 124 is also substantially aligned with interconnect 112. Hard mask layer 124 is formed and / or disposed directly over bottom electrode stack 118 using any suitable material deposition and / or material removal processes, as discussed herein. Additionally in the exemplary embodiments, hard mask layer 124 is formed from any suitable electrically conductive material exhibiting an electrically induced volatile resistance change including, but not limited to, silicon nitride (SiN). silicon dioxide (SiCh). aluminum oxide (A12O3), or the like.

[0024] Although shown and discussed herein as including hard mask layer 124, it is to be understood that semiconductor device 100 can include a distinct material or layer disposed over bottom electrode stack 118. For example, in place of hard mask layer 124, semiconductor device 100 may include at least one layer of a conductive material disposed directly over titanium nitride (TiN) forming second distinct conductive material 122 of bottom electrode stack 118. Alternatively, semiconductor device 100 may be formed without the use of hard mask layer 124 or conductive material(s). As such, it is to be understood that any materials and / or elements discussed herein as being disposed or formed over hard mask layer 124 may similarly be formed directly over second distinct conductive material 122 of bottom electrode stack 1 18.

[0025] In the exemplary embodiments, semiconductor device 100 also includes a plurality of pillars 126. More specifically, semiconductor device 100 includes aplurality of pillars 126 formed, disposed, and / or positioned over at least a portion of interconnect layer 110 and / or interconnect 112. As shown in FIG. 1, a pillar 126A of the plurality of pillars is formed directly over interconnect 112 and substantially encapsulates bottom electrode stack 118 and hard mask layer 124 (when applicable), respectively. That is, pillar 126A substantially surrounds, encapsulates, and / or encloses bottom electrode stack 118 and hard mask layer 124 in the phase of011-2326W001 processing and / or manufacturing of semiconductor device 100, as show n.

[0026] Additionally, semiconductor device 100 also includes at least one other distinct pillar 126 formed over at least a portion of interconnect layer 110 and / or interconnect 112, adjacent pillar 126A. For example, and as shown in FIG. 1 , semiconductor device 100 also includes a second, distinct pillar 126B disposed directly over interconnect 112, adjacent to and / or spaced apart from pillar 126 A. In the exemplary' embodiment, semiconductor device 100 also includes a third pillar 126C. a fourth pillar 126D, and a fifth pillar 126E. Third pillar 126C is disposed directly over interconnect layer 110, adjacent to pillar 126 A, and opposite second pillar 126B. Fourth pillar 126D is disposed directly over interconnect 112, adjacent to second pillar 126B, and fifth pillar 126E is disposed directly over a portion of interconnect layer 110 and a portion of interconnect 112, respectively. As shown in FIG. 1, fifth pillar 126E is formed adjacent to fourth pillar 126D.

[0027] Although five (5) pillars are shown and discussed herein, it is to be understood that semiconductor device 100 can include more or less pillars. That is, FIG. 1 depicts a side cross-sectional view- of a portion of semiconductor device 100. As such, semiconductor device 100 can include thousands, millions, or even billions of pillars 126 included therein. The number of pillars 126 included in semiconductor device 100 is dependent, at least in part, on the number of elements (e.g., electrodes, interconnects) included in semiconductor device 100, the size of each element, the size of interconnect 112, the size of semiconductor device 100, and the like. Additionally, although shown as being substantially similar in size (e.g, height, width), it is to be understood that the size of pillars 126 may vary within semiconductor device 100. The size of each pillar 126 is dependent, at least in part, on the number of elements (e.g., electrodes, interconnects) included in semiconductor device 100, the size of each element, the size of interconnect 112, the size of semiconductor device 100, the functionality within semiconductor device 100, and the like.

[0028] In the exemplary embodiment shown, each of the respective plurality of pillars 126 are spaced apart from one another within semiconductor device 100 at a predetermined distance (D). For example, second pillar 126B is spaced apart from pillar 126 A at the predetermined distance (D). and third pillar 126C is also spaced apart from pillar 126A at the predetermined distance (D). Each of the other pillars 126D, 126E are also spaced apart from adjacent, corresponding pillars at the predetermined distance (D). The distance (D) in which each pillar 126 are separated w ithin semiconductor device 100 is based upon, at least in part, the number of elements (e.g., electrodes, interconnects) included in semiconductor device 100, the size ofPage ? of 22011-2326W001 each element, the size of interconnect 112, the size of semiconductor device 100, and the like. In other exemplary embodiments, the distance separating each pillar 126 varies and / or is non- uniform.

[0029] As a result of separating and / or spacing pillars 126 apart from one another within semiconductor device 100, portions of interconnect 112 are exposed between distinct pillars 126. In the exemplary embodiment shown in FIG. 1, portions of interconnect 112 are uncovered, exposed, and / or revealed between at least a portion of the plurality of pillars 126A- 126E.

[0030] Each of the plurality of pillars 126 included within semiconductor device 100 are formed from an insulative, non-conductive, and / or dielectric material using various material deposition and / or removal processes, as discussed herein with respect to FIGS. 5-7. In exemplary embodiments, the plurality of pillars 126 are formed from non-conductive, dielectnc material including, but not limited to, silicon nitride (Si3N4), silicon dioxide (SiCh), aluminum oxide (A12O3), or the like.

[0031] As discussed herein, the inclusion of the plurality of pillars 126A-126E within semiconductor device 100 provides more uniform density within semiconductor device 100 during additional processing. That is, and as discussed herein, the inclusion of pillars 126A- 126E facilitates and / or ensures improved density within certain layers of material forming semiconductor device 100, which in turn improves process control when forming semiconductor device 100. In an exemplary embodiment, the improved density reduces or substantially eliminates center height variations for semiconductor device 100 when forming the same.

[0032] It is to be understood that semiconductor device 100 can include additional and / or distinct components and / or elements formed over and in electrical communication with interconnect 112 via bottom electrode stack 118. For example, and after additional processing, semiconductor device 100 can include, but is not limited to. through vias, memory elements (e.g., ReRAM, PCM, FeRAM, MRAM), threshold switches, and similar elements formed over and in electrical communication with interconnect 112 via bottom electrode stack 118.

[0033] FIGS. 2-9 show- various processes for forming semiconductor device 100 therein. More specifically, FIGS. 2-9 show cross-sectional views of semiconductor device 100 undergoing various processes to form semiconductor device 100 including interconnect 112, bottom electrode stack 118 over interconnect 112, and pillars 126 over interconnect layer 110 / interconnect 112. It is understood that similarly numbered and / or named components may function in a substantially similar fashion. Redundant explanation of these components has been011-2326W001 omitted for brevity.

[0034] FIG. 2 shows a cross-sectional view of substrate 102, and interconnect layer 110. In the exemplary embodiment, interconnect layer 110 is disposed directly over and / or on top of SiN layer 108 included within substrate 102. Additionally, as shown, interconnect layer 1 10 includes interconnect 112 disposed and / or formed therein. Interconnect 112 is formed within interconnect layer 110 using any suitable material removal and / or deposition techniques. For example, after depositing material forming interconnect layer 110 over SiN layer 108 of substrate 102, a portion of the material is removed from interconnect layer 110 and at least a portion of substrate 102 (e.g., via an etching process), and copper (cu) material forming interconnect 112 is subsequently deposited into interconnect layer 110.

[0035] FIG. 3 shows various layers being deposited over interconnect layer 110, and interconnect 112, respectively. In the exemplary embodiment, a first bottom electrode layer 128 is deposited directly over interconnect layer 110 and interconnect 112. That is, first bottom electrode layer 128 is deposited, disposed, and / or formed directly over the entirety' of exposed surfaces of interconnect layer 110 and interconnect 112, respectively. First bottom electrode layer 128 is formed from any suitable electrically conductive material. In the exemplary embodiment shown in FIG. 3, depositing first bottom electrode layer 128 includes depositing first distinct conductive material 120 directly over interconnect layer 110 and / or interconnect 112. Additionally, first bottom electrode layer 128 is deposited over interconnect layer 110 and interconnect 112 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.

[0036] Additionally, as shown in FIG. 3, a second, distinct bottom electrode layer 130 is deposited over first bottom electrode layer 128. More specifically, and subsequent to depositing first bottom electrode layer 128 over interconnect layer 110 and interconnect 112, second bottom electrode layer 130 is disposed, deposited, and / or formed directly over first bottom electrode layer 128. The depositing of second bottom electrode layer 130 also includes depositing second distinct conductive material 122 directly over first distinct conductive material 120 forming first bottom electrode layer 128. Similar to first bottom electrode layer 128, second bottom electrode layer 130 is formed from any suitable electrically conductive material (e.g., second distinct conductive material 122) that is distinct from first bottom electrode layer 128 (e.g., first distinct conductive material 120). In the exemplary embodiment shown in FIG. 3, second bottom electrode layer 130 / second distinct conductive material 122 is formed from titanium011-2326W001 nitride (TiN), such that second bottom electrode layer 130 includes a layer of titanium nitride (TiN) material deposited directly over the layer of titanium (Ti) forming the first bottom electrode layer 128 / first distinct conductive material 120. Second bottom electrode layer 130 is deposited over first bottom electrode layer 128 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.

[0037] A hard mask layer 124 is deposited directly over second bottom electrode layer 130. More specifically, hard mask layer 124 is deposited, disposed, and / or formed directly over second bottom electrode layer 130. Hard mask layer 124 is formed from any suitable mask material including, but not limited to, silicon nitride (SiN), silicon dioxide (SiCh), aluminum oxide (A12O3), or the like. Additionally, hard mask layer 124 is deposited over second bottom electrode layer 130 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like. As discussed herein, hard mask layer 124 may be optional within semiconductor device 100, or may be replaced by at least one layer of conductive material (not shown).

[0038] Subsequent to depositing the hard mask layer 124 over second bottom electrode layer 130, a lithography stack 132 is deposited directly over hard mask layer 124. In exemplary embodiments, lithography stack 132 includes an organic planarization layer (OPL) 134 deposited directly over hard mask layer 124. As shown in FIG. 3, OPL 134 is deposited, disposed, and / or formed directly over hard mask layer 124. OPL 134 is formed from any suitable organic material used in material removal processes, as discussed herein. Additionally, OPL 134 is deposited over hard mask layer 124 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), a chemical mechanical planarization (CMP), and the like.

[0039] Furthermore, and as shown in FIG. 3, lithography stack 132 includes an antireflective coating (ARC) layer 136 deposited over OPL 134. More specifically, ARC layer 136 is deposited, disposed, and / or formed directly over OPL 134. ARC layer 136 is deposited over OPL 134 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical plating (ECP), chemical mechanical planarization (CMP), and the like.

[0040] Additionally, a resist mask 138 included in lithography stack 132 is formed over ARC layer 136. That is, and as shown in FIG. 3, resist mask 138 is formed over a portion of011-2326W001ARC layer 136. Resist mask 138 is substantially aligned with interconnect 112 formed in interconnect layer 110. In exemplary embodiments, resist mask 138 is aligned with interconnect 112 using an alignment trench (not shown). Resist mask 138 is formed from any suitable material capable of facilitating the patterning of the various layers of material. Additionally, resist mask 138 is disposed and / or formed over the portion of ARC layer 136 using any suitable technique including, but not limited to, spin coating.

[0041] FIG. 4 shows various layers being patterned, etched, and / or removed to form bottom electrode stack 118 and hard mask layer 124, respectively. That is, and subsequent to forming resist mask 138 of lithography stack 132 over ARC layer 136, at least a portion of ARC layer 136, OPL 134, hard mask layer 124, second bottom electrode layer 130, and first bottom electrode layer 128 are etched, patterned, and / or at least partially removed to form bottom electrode stack 118 and hard mask layer 124. In exemplary embodiments, at least one patterning, etching, and / or material removal process is performed on ARC layer 136, OPL 134, hard mask layer 124, second bottom electrode layer 130, and first bottom electrode layer 128 to remove at least a portion of the material. The patterning, etching, and / or material removal processes include any suitable processes capable of structuring the material including, but not limited to, lithography, reactive ion etch (RIE), ion milling, wet etching, and the like.

[0042] In FIG. 5, a dielectric material layer 140 is deposited over various portions of semiconductor device 100. More specifically, dielectric material layer 140, formed from the dielectric material discussed herein, is deposited over exposed portions of interconnect layer 110, exposed portions of interconnect 112, bottom electrode stack 1 18 disposed directly over interconnect 112, and hard mask layer 124 disposed directly over bottom electrode stack 118, respectively. Dielectric material layer 140 is formed from any suitable dielectric material to subsequently form pillars 126 (see, FIG. 6) within semiconductor device 100, as discussed herein. For example, the dielectric material forming dielectric material layer 140 is formed from a materials including, but not limited to silicon nitride (Si3N4), silicon dioxide (SiCh), aluminum oxide (A12O3), or the like. Additionally, dielectric material layer 140 is deposited over interconnect layer 110, interconnect 112, bottom electrode stack 118, and hard mask layer 124 using any suitable material deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), chemical mechanical planarization (CMP), and the like.

[0043] In exemplary embodiments show n in FIG. 6, a distinct lithography stack 132A is formed over dielectric material layer 140. As shown, distinct lithography stack 132A011-2326W001 includes OPL 134A. As shown in FIG. 6, OPL 134A is deposited, disposed, and / or formed directly over dielectric material layer 140. OPL 134A is formed from any suitable organic material used in material removal processes, as similarly discussed herein with respect to OPL 134 of lithography stack 132 (see, FIG. 3). Distinct lithography stack 132A also includes ARC layer 136A deposited over OPL 134A. More specifically, ARC layer 136A is deposited, disposed, and / or formed directly over OPL 134A. Finally, distinct lithography stack 132A includes resist mask 138A formed over ARC layer 136A. That is. and as shown in FIG. 6, resist mask 138A is formed over various portions of ARC layer 136A. In the exemplary embodiment, resist mask 138A includes four (4) distinct portions formed over ARC layer 136A. Additionally in the embodiment, no portions of resist mask 138A are substantially aligned with bottom electrode stack 118 and hard mask layer 124 encapsulated within dielectric material layer 140.

[0044] As shown in FIG. 7, various layers of distinct lithography stack 132 A and dielectric material layer 140 are patterned, etched, and / or removed to form the plurality of pillars 126A-126E within semiconductor device 100. That is, and subsequent to forming resist mask 138A of distinct lithography stack 132A over ARC layer 136A, at least a portion of ARC layer 136A, OPL 134A, and dielectric material layer 140 are etched, patterned, and / or at least partially removed to form the plurality of pillars 126A-126E over interconnect layer 110 and / or interconnect 112. As similarly discussed herein, at least one patterning, etching, and / or material removal process is performed on ARC layer 136A, OPL 134A, and dielectric material layer 140 to remove at least a portion of the material and / or form pillars 126A-126E. The patterning, etching, and / or material removal processes include any suitable processes capable of structuring the material including, but not limited to, lithography, reactive ion etch (RIE), ion milling, wet etching, and the like.

[0045] In exemplary embodiments, etching distinct lithography stack 132A to form the plurality of pillars 126A-126E includes forming pillar 126A over interconnect 112. where pillar 126A encapsulates bottom electrode stack 118 and hard mask layer 124, respectively. Additionally, forming the plurality of pillars 126A-126E by etching distinct lithography stack 132A includes forming second pillar 126B disposed over interconnect 112, adjacent to and spaced apart from pillar 126 A. Furthermore in exemplary embodiments, forming the plurality of pillars 126A-126E by etching distinct lithography stack 132A includes forming third pillar 126C over interconnect layer 110, adjacent to pillar 126A and opposite second pillar 126B, forming fourth pillar 126D directly over interconnect 112, adjacent to second pillar 126B, and forming fifth pillar 126E over a portion of interconnect 112 and interconnect layer 110, respectively, adjacent fourth011-2326W001 pillar 126D. As shown in FIG. 7, each of the plurality of pillars 126A-126E formed over interconnect layer 110 and / or interconnect 112 are spaced apart from one another at an equal, predetermined distance (D). For example, etching distinct lithography stack 132A to form the plurality of pillars 126A-126E also results in forming second pillar 126B to be spaced apart from pillar 126A at predetermined distance (D). Distinct lithography stack 132A and the processes used to form the plurality of pillars 126A-126E facilitate forming pillars 126A-126E at the predetermined distance (D) from one another. As discussed herein, although five (5) distinct pillars 126A-126E are shown in FIG. 7, it is understood that semiconductor device 100 may include more pillars therein.

[0046] Additionally, as shown in FIG. 7, etching distinct lithography stack 132A and dielectric material layer 140 also includes exposing portions of interconnect 112 within semiconductor device 100. More specifically, etching distinct lithography stack 132A and dielectric material layer 140 to form the plurality of pillars 126A-126E therein, results in the exposure of interconnect 112 between at least a portion of the plurality of pillars 126A-126E. For example, and as show n in FIG. 7, interconnect 112 is exposed between at least (a) pillar 126 A and second pillar 126B, (b) second pillar 126B and fourth pillar 126D, and (c) fourth pillar 126D and fifth pillar 126E, respectively.

[0047] In FIG. 8, additional dielectric material 140A is deposited over semiconductor device 100. More specifically, additional dielectric material 140A is disposed, covers, and / or is deposited directly over each of the plurality of pillars 126A-126E (shown in phantom), exposed portions of interconnect layer 110, and exposed portions of interconnect 112, respectively. As shown, the additional dielectric material 140A substantially encapsulates the plurality7of pillars 126A-126E previously formed in semiconductor device 100. In the exemplary embodiment shown, depositing the additional dielectric material 140A also forms bumps, ridges, and / or protrusions 142 (hereafter, "‘protrusions 142”) within semiconductor device 100. Each protrusion 142 formed by additional dielectric material 140 A corresponds to and / or is aligned with one of the plurality of pillars 126A-126E formed in semiconductor device 100.

[0048] In exemplary embodiments, each of the plurality of pillars 126A-126E formed in semiconductor device 100 at least partially oxidize subsequent to formation. More specifically, prior to, or in conjunction with, the deposition of additional dielectric material 140A over the plurality of pillars 126A-126E (shown in phantom), exposed portions of interconnect layer 110, and exposed portions of interconnect 112, pillars 126A-126E at least partially oxidize. The oxidation of pillars 126A-126E is detectable using suitable techniques and / or instrumentation011-2326W001 including, but not limited to, transmission electron microscopy (TEM).

[0049] As shown in FIG. 9, the additional dielectric material 140A and hard mask layer 124 are etched to remove at least a portion of each material. In the exemplars’ embodiment, portions of additional dielectric material 140A including protrusions 142, as well as mask layer 124 disposed over bottom electrode stack 118 are patterned, etched, and / or removed to expose bottom electrode stack 118 within semiconductor device 100. Second distinct conductive material 122 of bottom electrode stack 118 is exposed subsequent to the etching of additional dielectric material 140A and hard mask layer 124, respectively. Etching additional dielectric material 140A and hard mask layer 124 includes the formation of an intermediary layer 144 over interconnect layer 110 and interconnect 112, respectively. Intermediary layer 144 is formed adjacent to and / or substantially surrounds bottom electrode stack 118. Additionally, intermediary layer 144 includes a top surface 146 that is substantially planar, in-plane, and / or even with the exposed surface of second distinct conductive material 122 of bottom electrode stack 118. That is, and based on the inclusion of pillars 126A-126E within semiconductor device 100 which improves the density dielectric material 140, 140A forming semiconductor device 100, top surface 146 of intermediary layer 144 is substantially even and / or planar with the exposed surface of bottom electrode stack 1 18. As such, intermediary’ layer 144 and bottom electrode stack 118 include a substantially uniform height (H) across semiconductor device 100, as a result of pillars 126A-126E facilitating the reduction or elimination of density dependent height variations across within semiconductor device 100 when performing the processes shown and discussed herein with respect to FIGS. 2- 9. Additionally, process-induced height variations can be countered by controlling the patterning induced center to edge width variation (e.g., RIE bias) of pillars 126.

[0050] FIG. 10 shows a flowchart illustrating example processes 200 for manufacturing a semiconductor device. More specifically, FIG. 10 shows non-limiting examples of processes for manufacturing semiconductor devices including electrodes formed over interconnects and a plurality of sacrificial pillars formed therein. The semiconductor device manufactured using the processes shown and discussed herein with respect to FIG. 10 may be substantially similar to semiconductor devices 100 shown and discussed herein with respect to FIGS. 1-9.

[0051] In process 202, a first bottom electrode layer is deposited directly over a surface of an interconnect layer and an interconnect formed within the interconnect layer. In process 204, a second bottom electrode layer is deposited over the first bottom electrode layer. In exemplary embodiments, the second bottom electrode layer is formed from a material distinctfrom the first bottom electrode layer. In process 206, show n in phantom as optional, a hard mask layer is deposited directly over the second bottom electrode layer. In process 208. a lithographystack is deposited over the hard mask layer, where applicable, or alternatively over the second bottom electrode layer. Depositing the lithography stack in process 208 can include depositing an optical planarization layer (OPL) directly over the hard mask layer or second bottom electrode layer, depositing an anti-reflection coating (ARC) layer directly over the OPL and forming a resist mask over a portion of the ARC layer. The resist mask is formed over the ARC layer and is aligned with the interconnect.

[0052] In process 210 the lithography stack, the hard mask layer (where applicable), the second bottom electrode layer, and the first bottom electrode layer are etched, patterned, and / or have at least a portion of the material removed. In exemplary embodiments, the etching of the various layers in process 210 also includes exposing the surface of the interconnect layer and at least a portion of the interconnect. In process 212, and subsequent to the etching in process 210, a bottom electrode stack is formed directly over the interconnect, and forming a mask layer directly over the bottom electrode stack.

[0053] In process 214, a dielectric material is deposited over the bottom electrode stack, the hard mask layer (where applicable), the exposed interconnect layer, and the exposed interconnect. The dielectric material is formed from any suitable material including, but not limited to, silicon nitride (Si3N4), silicon dioxide (SiCh), aluminum oxide (A12O3), or the like. In process 216, a distinct lithography stack is deposited over the dielectric material. Depositing the distinct lithography stack in process 214 can include depositing an optical planarization layer (OPL) directly over the dielectric material, depositing an anti-reflection coating (ARC) layer directly over the OPL. and forming a resist mask over a plurality- of distinct portions of the ARC layer.

[0054] In process 218, the distinct lithography stack and the dielectric material is etched to form pillars over at least one of the interconnect layer or the interconnect. The plurality of pillars formed during the etching in process 218 includes a pillar encapsulating the bottom electrode stack and the hard mask layer (where applicable) and at least one distinct pillar disposed over the interconnect and / or interconnect layer, adjacent to and spaced apart from the pillar. The etching in process 218 also includes forming at least one distinct pillar disposed over the interconnect layer, adjacent to the pillar encapsulating the bottom electrode stack, forming at least one distinct pillar directly over the interconnect, and forming at least one other pillar disposed over a portion of the interconnect and the interconnect layer, respectively. In exemplary-011-2326W001 embodiments, the pillars are formed from the dielectric material deposited over the bottom electrode stack, the mask layer (where applicable), the interconnect layer, and the interconnect, respectively. Additionally, process 218 includes forming the pillars to be spaced apart from one another at a predetermined distance (D).

[0055] In process 220, additional dielectric material is deposited directly over the plurality of pillars formed in process 218, the exposed interconnect, and the interconnect layer. Depositing the additional dielectric material in process 220 also forms a plurality of protrusions in the dielectric material. Each protrusion is substantially aligned with a corresponding pillar formed within the semiconductor device. In process 222, a portion of the additional dielectric material and the hard mask layer (where applicable) are etched to expose the bottom electrode stack. The etching in process 222 also includes forming an intermediary layer over the interconnect and the interconnect layer from the additional dielectric material deposited in process 220. The intermediary layer is formed adjacent to the bottom electrode stack and includes a top surface substantially in plane, planar, and / or even with a top, exposed surface of the bottom electrode stack.

[0056] The foregoing drawings show some of the processing associated according to several embodiments of this disclosure. In this regard, each drawing or block within a flow diagram of the drawings represents a process associated with embodiments of the method described. It should also be noted that in some alternative implementations, the acts noted in the drawings or blocks may occur out of the order noted in the figure or, for example, may in fact be executed substantially concurrently or in the reverse order, depending upon the act involved. Also, one of ordinary skill in the art will recognize that additional blocks that describe the processing may be added.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.

[0058] Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” “approximately” and “substantially,” are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and / or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherw ise. “Approximately” and / or “substantially” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate + / - 10% of the stated value(s).

[0059] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below' are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment w as chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

CLAIMSWhat is claimed is:1 . A semiconductor device, comprising: an interconnect layer disposed over a substrate; an interconnect disposed within the interconnect layer; a bottom electrode stack disposed directly over a portion of the interconnect; and a plurality of pillars disposed over at least one of the interconnect layer or the interconnect, the plurality of pillars including: a pillar encapsulating the bottom electrode stack, the pillar formed over the interconnect; and at least one distinct pillar formed over at least one of the interconnect layer or the interconnect, adjacent to and spaced apart from the pillar encapsulating the bottom electrode stack, wherein the plurality of pillars are formed from a dielectric material.

2. The semiconductor device of claim 1, wherein the at least one distinct pillar further includes: at least one pillar disposed directly over the interconnect and positioned directly adjacent the pillar encapsulating the bottom electrode stack; at least one pillar disposed over the interconnect layer, directly adjacent to the pillar encapsulating the bottom electrode stack; and at least one pillar disposed over a portion of the interconnect and a portion of the interconnect layer.

3. The semiconductor device of claim 2, wherein each of the plurality of pillars are spaced apart from one another at a predetermined distance (D).

4. The semiconductor device of claim 1, wherein the interconnect is exposed between at least a portion of the plurality of pillars disposed over at least one of the interconnect layer or the interconnect.

5. The semiconductor device of claim 1, further comprising one of: a hard mask layer disposed directly over the bottom electrode stack, wherein the pillar of the plurality of pillars encapsulates the hard mask layer, or at least one conductive material layer disposed directly over the bottom electrode stack, wherein the pillar of the plurality of pillars encapsulates the at least one conductive material layer.

6. The semiconductor device of claim 1, wherein the dielectric material forming the pillar and the at least one distinct pillar is formed from a material selected from the group consisting of: silicon nitride (Si3N4), silicon dioxide (SiN), and aluminum oxide (A12O3).

7. A method of manufacturing a semiconductor device, the method comprising: depositing a dielectric material directly over: an interconnect layer; an interconnect formed within the interconnect layer; and a bottom electrode stack disposed directly over the interconnect; depositing a lithography stack directly over the dielectric material; and etching the lithography stack and the dielectric material to form a plurality of pillars over at least one of the interconnect layer or the interconnect, the plurality of pillars formed from the dielectric material and including: a pillar encapsulating the bottom electrode stack; and at least one distinct pillar disposed over at least one of the interconnect layer or the interconnect, adj acent to and spaced apart from the pillar encapsulating the bottom electrode stack.

8. The method of claim 7, wherein the etching of the lithography stack and the dielectric material further includes: forming at least one pillar disposed directly over the interconnect and positioned directly adjacent the pillar encapsulating the bottom electrode stack; forming at least one pillar disposed over the interconnect layer, directly adjacent to the pillar encapsulating the bottom electrode stack; and forming at least one pillar disposed over a portion of the interconnect and a portion of the interconnect layer.

9. The method of claim 7, wherein the etching of the lithography stack and the dielectric material further includes: exposing the interconnect betw een at least a portion of the plurality of pillars disposed over at least one of the interconnect layer or the interconnect.

10. The method of claim 9, further comprising depositing additional, dielectric material directly over: the plurality of pillars; the exposed interconnect; and the interconnect layer.

11. The method of claim 10, further comprising etching the additional, dielectric material to expose the bottom electrode stack.

12. The method of claim 11, wherein the etching of the additional, dielectric material further includes: forming an intermediary layer over the interconnect and the interconnect layer, the intermediary layer formed adj acent to the bottom electrode stack and including a top surface substantially in plane with an exposed surface of the bottom electrode stack.

13. The method of claim 7, wherein the etching of the lithography stack and the dielectric material further includes: forming each of the plurality of pillars to be spaced apart from one another at a predetermined distance (D).

14. The method of claim 7, further comprising one of: forming a hard mask layer directly over the bottom electrode stack prior to the depositing of the dielectric material, wherein the pillar of the plurality of pillars encapsulates the hard mask layer; or forming at least one conductive material layer directly over the bottom electrode stack prior to the depositing of the dielectric material, w herein the pillar of the plurality' of pillars encapsulates the at least one conductive material layer.

15. The method of claim 8, wherein the dielectric material forming the plurality of pillars is formed from a material selected from the group consisting of: silicon nitride (Si3N4), silicon dioxide (SiN), and aluminum oxide (A12O3).

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