Circuit board and semiconductor package

Abstract

This circuit board comprises: a core part including an upper surface and a lower surface; a core via electrode passing through the upper surface of the core part and the lower surface of the core part; and a wiring layer disposed on the lower surface of the core via electrode, wherein the wiring layer includes a seed layer disposed on the lower surface of the core via electrode and a metal layer disposed on the seed layer, and the width of the seed layer in the horizontal direction is greater than the width of the lower surface of the core via electrode in the horizontal direction.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, technologies related to electronic products, such as AI and servers, are progressing toward multifunctionality and high speed, and to respond to this trend, semiconductor chip manufacturing technology is also developing rapidly.

[0004] In particular, as the density of transistors and wiring within semiconductor chips increases, the number of I / O terminals on the chips is growing. To meet this trend, not only are the wiring densities, lengths, and widths of circuit boards becoming finer, but there is also a trend toward high-layer, large-area designs.

[0005] Furthermore, from the perspective of miniaturizing finished electronic products, the thickness of the applied circuit boards is also decreasing, and technologies related to multilayer circuit boards, which configure more circuit layers within a circuit board of the same thickness, are being actively researched. In addition, as the pitch of semiconductor chips narrows and the size of chips increases, chiplet technology for separating semiconductor chips by function is being researched. Moreover, technologies for connecting separated chiplets on circuit boards are being actively researched. Furthermore, by connecting semiconductor chips with different functions on circuit boards, technologies regarding the connection relationship between circuit boards and semiconductor chips are being actively researched, such as the circuit board connecting semiconductor chips to each other, which was previously considered only from the perspective of conventional semiconductor packaging.

[0006] A circuit board is a device in which circuit line patterns are arranged using a conductive material, such as copper, on an electrically insulating substrate; it is a general term for the package board immediately before mounting electronic components. To densely mount many different types of electronic components on a flat surface, the mounting positions of each component are determined, and circuit patterns connecting the components are printed and fixed onto the surface.

[0007] A circuit board includes a core layer and a build-up layer disposed on the surface of the core layer. The core layer and the build-up layer each include one or more insulating layers, and a wiring layer and a via electrode connecting different wiring layers in a vertical direction are disposed on each insulating layer. The via electrode is disposed within a via hole penetrating the insulating layer.

[0008] In the case of the core layer, the width of the via electrode may be larger than that of the insulating layer of the build-up layer. However, when the width of the via hole increases, defects in plating solution deposition occur due to differences in internal current density in different regions within the via hole, making it difficult to ensure the quality of the via electrode.

[0009]

[0010] The present invention provides a circuit board and a semiconductor package that can improve the quality of via electrodes within a core layer and improve reliability by minimizing warpage.

[0011]

[0012] A circuit board according to an embodiment includes a core portion including an upper surface and a lower surface; a core via electrode penetrating the upper surface of the core portion and the lower surface of the core portion; and a wiring layer disposed on the lower surface of the core via electrode, wherein the wiring layer includes a seed layer disposed on the lower surface of the core via electrode and a metal layer disposed on the seed layer, and the horizontal width of the seed layer is greater than the horizontal width of the lower surface of the core via electrode.

[0013] The size of the crystal grains constituting the seed layer above may be smaller than the size of the crystal grains constituting the metal layer above.

[0014] The vertical thickness of the seed layer may be smaller than the vertical thickness of the metal layer.

[0015] The vertical length of the above core via electrode may be 50 µm or more.

[0016] The size of the crystal grains constituting the seed layer above may be smaller than the size of the crystal grains constituting the core via electrode above.

[0017] The core portion comprises a plurality of glass fibers arranged in a vertical direction, and the vertical length between the plurality of glass fibers may be shorter than the length between the uppermost glass fiber among the plurality of glass fibers and the upper surface of the core layer.

[0018] It includes a second seed layer disposed on the upper surface of the core portion, and the second seed layer can be separated through the seed layer and the core via electrode.

[0019] It includes a first wiring layer disposed on the core, and the size of the crystal grains of the first wiring layer may be smaller than the size of the crystal grains of the core via electrode.

[0020] It includes a polished surface disposed between the core via electrode and the seed layer, and the horizontal width of the polished surface may be greater than the horizontal width of the seed layer.

[0021] A semiconductor package according to an embodiment comprises: a core portion including an upper surface and a lower surface; a first build-up layer disposed on the upper surface of the core portion; a second build-up layer disposed on the lower surface of the core portion; a semiconductor chip disposed on the first build-up layer or the second build-up layer; a core via electrode penetrating the upper surface of the core portion and the lower surface of the core portion; and a wiring layer disposed on the lower surface of the core via electrode, wherein the wiring layer comprises a seed layer disposed on the lower surface of the core via electrode and a metal layer disposed on the seed layer, and the horizontal width of the seed layer is greater than the horizontal width of the lower surface of the core via electrode.

[0022]

[0023] Through this embodiment, even if the width of the hole in the core layer is increased, a uniform core via electrode can be stably implemented. In particular, as the electrical resistance of the core via electrode decreases with increasing the width of the core via electrode, the electrical conductivity of the circuit board can be improved.

[0024] In addition, since the width of the core via electrode can be easily increased, there is an advantage in that the heat dissipation efficiency of the circuit board through the core layer can be improved. Accordingly, the occurrence of warping of the circuit board can be minimized due to the improvement in thermal stress resulting from the increase in the thermal capacity of the core layer itself.

[0025] In addition, since components such as the filling material within the core via electrode are omitted compared to conventional methods, quality defects caused by the difference in the coefficient of thermal expansion between the filling material and the core via electrode can be prevented in advance, and there is an advantage of improving production efficiency through process simplification.

[0026]

[0027] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0028] FIGS. 2 to 10 are drawings illustrating the process of forming a core via electrode in a circuit board according to an embodiment of the present invention.

[0029] FIG. 11 is an enlarged view of one side of a core layer according to an embodiment of the present invention.

[0030] FIG. 12 is a drawing illustrating the arrangement structure of glass fibers within a core layer according to an embodiment of the present invention.

[0031] FIGS. 13 and 14 are drawings showing the formation process of a core via electrode and a cross-section of the core via electrode according to a comparative example.

[0032] FIGS. 15 and 16 are drawings showing the formation process of a core via electrode and a cross-section of the core via electrode according to an embodiment of the present invention.

[0033] FIG. 17 is a drawing illustrating a semiconductor package according to an embodiment of the present invention.

[0034]

[0035]

[0036] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0037] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0038] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0039] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) shall be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, shall be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it shall be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it shall not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0040] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0041] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0042] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0043] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0044] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0045] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0046] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0047] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0048] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0049] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0050] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0051] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 to FIG. 10 are drawings illustrating the process of forming a core via electrode in a circuit board according to an embodiment of the present invention, FIG. 11 is an enlarged view of one side of a core layer according to an embodiment of the present invention, and FIG. 12 is a drawing illustrating the arrangement structure of glass fibers in a core layer according to an embodiment of the present invention.

[0052] Referring to FIGS. 1 to 12, a circuit board (10) according to an embodiment of the present invention may include a core portion (100), a first build-up layer (200), a second build-up layer (300), a plurality of wiring layers, a plurality of via portions, and a protection layer.

[0053] The circuit board (10) may include a core portion (100). The core portion (100) may be a component forming the base of the circuit board (10). Based on the vertical direction of the circuit board (10), the core portion (100) may be positioned in the center. The material of the core portion (100) may include at least one selected from the group consisting of glass, resin, plastic, and metal.

[0054] The core portion (100) may include a first core layer (101) and a second core layer (500) arranged in a vertical direction.

[0055] The first core layer (101) may include a plurality of insulating layers stacked in a vertical direction. When the first core layer (101) is implemented with a plurality of insulating layers, compared to a structure in which the core layer is implemented with a single layer, via holes in each insulating layer constituting the first core layer (101) can be formed using a laser as well as a mechanical drill, thereby lowering the manufacturing cost and making it easy to fill the entire via holes of the first core layer (101) with metal. In addition, according to the structure in which a plurality of insulating layers are stacked vertically, the degree of design freedom regarding the formation of pads and via electrodes is increased, and accordingly, there is an advantage that production efficiency can be improved. Furthermore, the first core layer (101) may have a structure in which a plurality of reinforcing members are stacked along the vertical direction within the insulating layer. In addition, at least two of the reinforcing members may be provided with different materials.

[0056] However, this is not limited to this, and the first core layer (101) may be implemented as a single layer structure.

[0057] As illustrated in FIG. 12, the insulating layer constituting the first core layer (101) may be a prepreg (PPG) containing glass fibers (180) within the resin. When the first core layer (101) is composed of multiple insulating layers, the glass fibers (180) within the first core layer (101) may also be provided in multiple numbers and arranged along the vertical direction.

[0058] In order to suppress warpage of the circuit board (10), the vertical thickness of the core portion (100) may differ from the vertical thickness of the first build-up layer (200) or the vertical thickness of the second build-up layer (300) to be described later. In the circuit board (10) according to the present embodiment, the vertical thickness of the core portion (100) is depicted as being thicker than the vertical thickness of the first build-up layer (200) and / or the vertical thickness of the second build-up layer (200), but it may be freely provided without being limited thereto depending on the area of ​​the circuit board (10) and the design of the circuit.

[0059] The first build-up layer (200) may be disposed on one side of the core portion (100). The first build-up layer (200) may be disposed on the upper surface of the core portion (100). The second build-up layer (300) may be disposed on the other side of the core portion (100). The second build-up layer (300) may be disposed on the lower surface of the core portion (100). The first build-up layer (100) and the second build-up layer (300) may be disposed facing each other with respect to the core portion (100). The first build-up layer (200) and the second build-up layer (300) may each include a plurality of insulating layers disposed in a vertical direction. The number of insulating layers of the first build-up layer (200) and the number of insulating layers of the second build-up layer (300) may be the same. Accordingly, the occurrence of bending of the circuit board (10) based on the core part (100) can be minimized. However, this is not limited to the number of insulating layers in the first build-up layer (200) and the number of insulating layers in the second build-up layer (300) may differ from each other.

[0060] For example, the first build-up layer (200) may include a first insulating layer (211), a second insulating layer (212), a third insulating layer (213), a fourth insulating layer (214), and a fifth insulating layer (215) arranged in a vertical direction. The first insulating layer (211) may be placed on the upper surface of the core portion (100). The second insulating layer (212) may be placed on the upper surface of the first insulating layer (211). The third insulating layer (213) may be placed on the upper surface of the second insulating layer (212). The fourth insulating layer (214) may be placed on the third insulating layer (213). The fifth insulating layer (215) may be placed on the fourth insulating layer (214).

[0061] The second build-up layer (300) may include a sixth insulating layer (311), a seventh insulating layer (312), an eighth insulating layer (313), a ninth insulating layer (314), and a tenth insulating layer (315) arranged in a vertical direction. The sixth insulating layer (311) may be placed on the lower surface of the core portion (100). The seventh insulating layer (312) may be placed on the lower surface of the sixth insulating layer (311). The eighth insulating layer (313) may be placed on the lower surface of the seventh insulating layer (312). The ninth insulating layer (314) may be placed on the lower surface of the eighth insulating layer (313). The tenth insulating layer (315) may be placed on the lower surface of the ninth insulating layer (314).

[0062] The number of insulating layers constituting the first build-up layer (200) and the number of insulating layers constituting the second build-up layer (300) shown in FIG. 1 are exemplary, and the circuit board (10) may have a greater number of insulating layers stacked vertically to form the first build-up layer (200) and the second build-up layer (300), respectively.

[0063] The first to tenth insulating layers (211, 212, 213, 214, 215, 311, 312, 313, 314, 315) may each be any insulating material, such as photocurable and / or thermosetting materials. As thermosetting insulating materials, insulating materials in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and prepregs (PPG) containing glass fibers within a resin may be used. In addition, the resins described above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. When the first to tenth insulating layers (211, 212, 213, 214, 215, 311, 312, 313, 314, 315) are photocurable insulators, the first to tenth insulating layers (211, 212, 213, 214, 215, 311, 312, 313, 314, 315) may each be a PID (Photo Imageable Dielectric).

[0064] The vertical thickness of each of the first to tenth insulating layers (211, 212, 213, 214, 215, 311, 312, 313, 314, 315) may be thinner than the vertical thickness of each layer constituting the core portion (100).

[0065] The circuit board (10) may include a protective layer. The protective layer may include a first protective layer (410) disposed on the surface of the first build-up layer (200) and a second protective layer (420) disposed on the surface of the second build-up layer (200). The first protective layer (410) and the second protective layer (420) can perform the function of preventing short circuits between solders due to low wettability with the solder when semiconductor devices are disposed on the surface of the circuit board (10) with a material such as solder, and can prevent problems that reduce reliability by preventing external contaminants from penetrating into the build-up structure. The first protective layer (410) and the second protective layer (420) may each utilize a photocurable insulating material. Accordingly, the first protective layer (410) and the second protective layer (420) are provided with a solder resist other than the aforementioned ABF, PPG, BT resin, and PID. However, it is not limited to this, and can be provided with various materials capable of performing low wettability with solder and the resulting short-circuit prevention function between solders as described above.

[0066] The first protective layer (410) may include a hole (412) for exposing upward a wiring layer (225) disposed on the surface of the first build-up layer (200). The second protective layer (420) may include a hole (422) for exposing downward a wiring layer (325) disposed on the surface of the second build-up layer (300) to the circuit board (10).

[0067] The circuit board (10) may include a circuit pattern for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The circuit pattern may include a plurality of wiring layers and a plurality of vias.

[0068] A plurality of wiring layers may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of wiring layers is embedded within each of the plurality of insulating layers or protective layers and exposed to the outside from the surface. A wiring layer may also be referred to as a metal layer. Furthermore, the surface of the plurality of insulating layers includes a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of a wiring layer being disposed on the surface is that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be formed in which a wiring layer is disposed on the first surface and the second surface of some of the insulating layers, respectively, and a wiring layer is disposed on only the first surface or the second surface of other parts of the plurality of insulating layers.

[0069] A plurality of wiring layers include a first wiring layer (120) disposed on the upper surface of the core portion (100), a second wiring layer (130) disposed on the lower surface of the core portion (100), a third wiring layer (221) disposed on the upper surface of the first insulating layer (211), a fourth wiring layer (222) disposed on the upper surface of the second insulating layer (212), a fifth wiring layer (223) disposed on the upper surface of the third insulating layer (213), a sixth wiring layer (224) disposed on the upper surface of the fourth insulating layer (214), a seventh wiring layer (225) disposed on the upper surface of the fifth insulating layer (215), an eighth wiring layer (321) disposed on the lower surface of the sixth insulating layer (311), and a ninth wiring layer (322) disposed on the lower surface of the seventh insulating layer (312). It may include a 10th wiring layer (323) disposed on the lower surface of the 8th insulation layer (313), an 11th wiring layer (324) disposed on the lower surface of the 9th insulation layer (314), and a 12th wiring layer (325) disposed on the lower surface of the 10th insulation layer (315).

[0070] Each of the above plurality of wiring layers can also be named as a pad portion.

[0071] The via portion may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring layers facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and the via portion may be disposed within the via hole.

[0072] The via section comprises a first via section (231) penetrating at least a portion of the first insulating layer (211), a second via section (232) penetrating at least a portion of the second insulating layer (212), a third via section (233) penetrating at least a portion of the third insulating layer (213), a fourth via section (234) penetrating at least a portion of the fourth insulating layer (214), a fifth via section (235) penetrating at least a portion of the fifth insulating layer (215), a sixth via section (331) penetrating at least a portion of the sixth insulating layer (311), a seventh via section (332) penetrating at least a portion of the seventh insulating layer (312), an eighth via section (333) penetrating at least a portion of the eighth insulating layer (313), and a ninth via section (334) penetrating at least a portion of the ninth insulating layer (314). It may include a 10th via (335) that penetrates at least a portion of the 10th insulating layer (315).

[0073] The first via section (231) can electrically connect the first wiring layer (120) and the third wiring layer (221). The second via section (232) can electrically connect the third wiring layer (221) and the fourth wiring layer (222). The third via section (233) can electrically connect the fourth wiring layer (222) and the fifth wiring layer (223). The fourth via section (234) can electrically connect the fifth wiring layer (223) and the sixth wiring layer (224). The fifth via section (235) can electrically connect the sixth wiring layer (224) and the seventh wiring layer (225). The sixth via section (331) can electrically connect the second wiring layer (130) and the eighth wiring layer (321). The 7th via (332) can electrically connect the 8th wiring layer (321) and the 9th wiring layer (322). The 8th via (333) can electrically connect the 9th wiring layer (322) and the 10th wiring layer (323). The 9th via (334) can electrically connect the 10th wiring layer (323) and the 11th wiring layer (324). The 10th via (335) can electrically connect the 11th wiring layer (324) and the 12th wiring layer (325).

[0074] A plurality of wiring layers and a plurality of vias can each be implemented through a seed layer disposed on the surface of an insulating layer or the inner wall of a via hole and an electroplated layer formed on the surface of the seed layer by an electroplating method.

[0075] The first to fifth via sections (231, 232, 233, 234, 235) disposed in the first build-up layer (200) may each have a shape in which the horizontal width gradually decreases as it faces the core section (100). The sixth to tenth via sections (331, 332, 333, 334, 335) disposed in the second build-up layer (300) may each have a shape in which the horizontal width gradually decreases as it faces the core section (100). Accordingly, with respect to the core section (100), the shapes of the via sections within the first build-up layer (200) and the via sections within the second build-up layer (300) may be formed to be symmetrical to each other.

[0076] The circuit board (10) may include a core via electrode (150). The core via electrode (150) may have a shape that penetrates the upper surface of the core portion (100) and the lower surface of the core portion (100). The core via electrode (150) may be a portion that overlaps horizontally with the core portion (100). Through the core via electrode (150), the first wiring layer (120) and the second wiring layer (130) may be electrically connected to each other.

[0077] The core via electrode (150) may have a polygonal shape including a circular or square cross section.

[0078] The core portion (100) may include a hole (110) in which a core via electrode (150) is disposed. The hole (110) may have a shape that penetrates from the upper surface to the lower surface of the core portion (100). The core via electrode (150) may be a metal material plated within the hole (110) in the core portion (100). In this embodiment, the core via electrode (150) may be provided in multiple numbers and disposed along the horizontal direction of the core portion (100), and in this case, the hole (110) in the core portion (100) may also be provided in multiple numbers.

[0079] The horizontal width (D1) of the hole (110) of the core via electrode (150) or the core part (100) may be larger than the horizontal width of each of the plurality of via parts disposed in the first build-up layer (200) or the second build-up layer (300). In the embodiment, the horizontal width (D1) of the hole (110) of the core part (100) may be 50 µm or more. When processing the hole (110) for forming the core via electrode (150) within the core part (100) due to the vertical length of the core part (100) itself, if the width of the hole (110) is less than 50 µm, there is a problem of reduced productivity due to the difficulty of the hole processing operation. In addition, in a structure connecting a plurality of wiring layers in the vertical direction, if the width of the hole (110) is less than 50 µm, the bonding force with the wiring layer may not be sufficient.

[0080] However, as the width of the hole (110) increases, the plating process for forming the core via electrode (150) within the hole (110) may not be easy. Additionally, due to the non-uniformity of the plating area within the hole (110), problems such as voids, short circuits, and burrs may occur.

[0081] Below, we will explain the process of forming a core via electrode (150) to solve the problem caused by the increase in the width of the hole (110).

[0082] FIGS. 2 to 10 illustrate the process of forming a core via electrode in a circuit board according to an embodiment of the present invention. Referring to FIGS. 2 and FIGS. 3, a second core layer (500) may be bonded to one side of a first core layer (101) in which a hole (110) is not formed. The second core layer (500) may have a material different from that of the first core layer (101). The second core layer (500) may have adhesive properties on one or both sides. For example, the material of the second core layer (500) may be epoxy or acrylic. The second core layer (500) may also be called an adhesive layer in that it has adhesive properties.

[0083] As illustrated in FIG. 4, a hole (110) can be machined in the first core layer (101) to which the second core layer (500) is combined. The hole (110) can be formed within the first core layer (101) by mechanical or laser drilling. As previously mentioned, there may be multiple holes (110). Accordingly, a hole can be formed in the second core layer (500) along with the first core layer (101).

[0084] As illustrated in FIG. 5, a first metal layer (600) may be bonded to a first core layer (101) and a second core layer (500) in which a hole (110) is formed. The first metal layer (600) may function as a seed layer for forming a core via electrode (150). The first metal layer (600) may be a Cu foil. A portion of the first metal layer (600) may be arranged to overlap the hole (110) in a vertical direction.

[0085] As illustrated in FIGS. 6 and 7, plating for forming a core via electrode (150) can be performed in a hole (110) within a first core layer (101) to which a first metal layer (600) is bonded. The plating of the hole (110) can be performed by an electrolytic copper plating method. Accordingly, a plating layer (700) for forming a core via electrode (150) can be formed downward from one side of the first metal layer (600).

[0086] As illustrated in FIG. 8, a core via electrode (150) can be formed by the growth of a plating layer (700) through plating in a hole (110) within the first core layer (101). Afterward, a seed layer (800) can be formed on the other side of the first core layer (101) opposite to the side to which the second core layer (500) is bonded. The seed layer (800) is intended to form a second metal layer (900, see FIG. 9) on the other side of the first core layer (101) and can be formed on the other side of the first core layer (101) by a chemical copper plating method. The seed layer (800) does not exist in the hole (110) within the first core layer (101). The seed layer (800) can be arranged so as to be offset in a horizontal direction from the first core layer (101).

[0087] The seed layer (800) can be positioned to overlap perpendicularly with one side of the core via electrode (150). The seed layer (800) and the core via electrode (150) can be in direct contact.

[0088] Meanwhile, as illustrated in FIG. 11, a polished surface (170) may be disposed on the other side of the first core layer (101) to facilitate bonding with the seed layer (800) and the second metal layer (900), and to process the end region of the plating layer (700) protruding from the other side of the first core layer (101) during the formation process of the core via electrode (150). The polished surface (170) may be a surface formed on the lower surface of the core via electrode (150) and on the lower surface of the first core layer (101) disposed along the perimeter of the core via electrode (150) by polishing the lower end of the plating portion (700) protruding from the other side of the first core layer (101). The area where the polished surface (170) is formed on the lower surface of the first core layer (101) may have a groove shape that is concave upward from the other area. However, this is exemplary, and the polished surface (170) may be a plane that forms a plane with the lower surface of the first core layer (101). Additionally, the polished surface (170) may be formed over the entire lower surface of the first core layer (101). The horizontal width of the polished surface (170) may be longer than the horizontal width of the core via electrode (150) or the first and second wiring layers (120, 130).

[0089] Subsequently, as illustrated in FIG. 9, a second metal layer (900) may be formed on the surface of the seed layer (800) by an electrolytic method. The second metal layer (900) is intended for forming the first wiring layer (120) or the second wiring layer (130) and may be positioned to cover the seed layer (800) on the lower surface of the first core layer (101). A portion of the second metal layer (900) may be removed by etching, and the remaining portion may form a portion of the first wiring layer (120) or the second wiring layer (130) on the surface of the first core layer (101). During the patterning process through etching the second metal layer (900), a portion of the seed layer (800) may also be removed by etching in correspondence with the formation area of ​​the first wiring layer (120) and the second wiring layer (130).

[0090] Accordingly, as illustrated in FIG. 11, the first wiring layer (120) or the second wiring layer (130) may include a seed layer (800) disposed on one side of the core via electrode (150) and a metal layer (810) disposed on the seed layer (800). As the wiring layer is formed on the surface of the first core layer (101) through the seed layer (800), the horizontal width of the seed layer (800) and the metal layer (810) disposed on the lower surface of the first core layer (101) may be greater than the horizontal width of the lower surface of the core via electrode (150). Additionally, the seed layer (800) may be disposed to overlap the core via electrode (150) in the horizontal direction.

[0091] Due to differences in the plating method, the size of the crystal grains constituting the seed layer (800) may be smaller than the size of the crystal grains constituting the metal layer (810). Accordingly, the first wiring layer (120) or the second wiring layer (130) may include multiple regions with different crystal grains, and when the region with small crystal grains is called the first region and the region with large crystal grains is called the second region, the first region may be positioned closer to the first core layer (101) or the core via electrode (150) than the second region. The vertical thickness of the first region may be shorter than the vertical thickness of the second region.

[0092] The size of the crystal grains constituting the seed layer (800) may be smaller than the size of the crystal grains constituting the core via electrode (150).

[0093] As illustrated in FIG. 10, after forming a first metal layer (600) and a second metal layer (900) on one side and the other side, respectively, of the first core layer (101), the second core layer (500) can be cured. Accordingly, as the second core layer (500) is cured under conditions above a certain temperature, the second core layer (500) can form a core portion (100) together with the first core layer (101). Due to the cured area of ​​the second core layer (500), the vertical thickness of the core portion (100) can be increased by a predetermined length. Accordingly, as the vertical thickness of the core portion (100) increases through the second core layer (500) in addition to the first core layer (101), warpage of the circuit board (10) can be minimized.

[0094] As illustrated in FIG. 12, based on the glass fibers (180) arranged within the core portion (100), the vertical distance (L1) between adjacent glass fibers (180) may be shorter than the distance (L2) between the upper surface of the first core layer (101) combined with the second core layer (500) and the glass fibers (180) arranged at the top. Accordingly, the glass fibers (180) within the first core layer (101) may be prevented from protruding from the resin forming the core portion (100), and the glass fibers (180) may be concentrated in the vertical central area within the core portion (100) to minimize the bending phenomenon of the circuit board (10).

[0095] Meanwhile, the first metal layer (600) combined for plating of the plating portion (700) for forming the core via electrode (150) can form a first wiring layer (120) or a second wiring layer (130) by patterning. In this case, the size of the crystal grains constituting the core via electrode (150) may be larger than the size of the crystal grains constituting the first wiring layer (120) or the second wiring layer (130) formed by the patterning of the first metal layer (600). That is, when a first metal layer (600) is disposed on the upper surface of the first core layer (101) and a second wiring layer (130) is formed on the lower surface of the first core layer (101), the size of the crystal grains of the first wiring layer (120) formed through the first metal layer (600) in the circuit board (10) and the size of the crystal grains of the second wiring layer (130) may be different from each other.

[0096] However, this is not limited thereto, and the first metal layer (600) may be removed after the formation of the core via electrode (150). Afterward, a plating process for forming a first wiring layer (120) or a second wiring layer (130) through the core via electrode (150) may be added to one side of the first core layer (101) on which the core via electrode (150) is formed. When the second metal layer (900) is disposed on the lower surface of the core via electrode (150), a seed layer may be disposed on the upper surface of the core via electrode (150) and the upper surface of the core part (100) after the removal of the first metal layer (600), and the first wiring layer (120) may be formed through the seed layer. In this case, the circuit board (10) may include a plurality of seed layers facing each other in a vertical direction with respect to the core via electrode (150), and the plurality of seed layers may be spaced apart in a vertical direction through the core via electrode (150). The plurality of seed layers may be separated in a vertical direction through the core via electrode (150). A seed layer disposed on the upper surface of the core portion (100) may be named a second seed layer.

[0097] In addition, in this embodiment, a core via electrode (150) is formed by arranging a single metal layer through the second core layer (500) only on one side of the first core layer (101), but this is not limited thereto. The core via electrode (150) may also be realized through plating by arranging the second core layer (500) and a plurality of metal layers on both sides of the first core layer (101) and then processing holes in either one of the metal layers and the second core layer.

[0098] FIGS. 13 and 14 are drawings showing the formation process of a core via electrode and a cross-section of the core via electrode according to a comparative example, and FIGS. 15 and 16 are drawings showing the formation process of a core via electrode and a cross-section of the core via electrode according to an embodiment of the present invention.

[0099] Referring to FIG. 13, in the core layer according to the comparative example, a core via electrode is formed by a plating method through a seed layer (30) within a hole (20) in the core layer. The seed layer (30) is composed of an upper surface portion (32) disposed on the upper surface of the core layer, a lower surface portion (34) disposed on the lower surface of the core layer, and a connecting portion (36) disposed on the inner wall of a hole (20) in the core layer. Accordingly, the structure is such that a core via electrode is realized by an electroplating method through the seed layer (30).

[0100] The graph on the left side of FIG. 13 indicates the intensity of the charge amount of Cl by region of the hole (20) according to color, and the graph on the right side of FIG. 13 indicates the current density by region of the hole (20) according to color. Accordingly, the plating for forming the core via electrode according to the comparative example is a structure in which the plating region (40) grows in both directions from the vertical center region of the hole (20), which has a low current density and a high charge amount.

[0101] Accordingly, as illustrated in FIG. 14, the core via electrode according to the comparative example may have a boundary (50) or uneven plating areas such as voids and burrs due to differences in charge amount or plating density by region. Accordingly, the core via electrode according to the comparative example has a problem in that the durability of the core via electrode is reduced and the electrical conductivity is also low due to the occurrence of uneven areas such as the boundary (50), resulting in reduced signal transmission efficiency.

[0102] According to the present embodiment, as shown in FIG. 15, the plating layer (700) for forming the core via electrode (150) grows in one direction, that is, in a unidirectional manner, based on the first metal layer (600), so that the core via electrode (150) can be densely formed within the hole (110) of the core part (100) as shown in FIG. 16, and the plating density can be uniform for each region.

[0103] According to the above structure, even if the width of the hole (110) within the core part (100) increases, there is an advantage that a uniform core via electrode (150) within the hole (110) can be stably implemented. In particular, as the electrical resistance of the core via electrode (150) decreases with increasing the width of the core via electrode (150), the electrical conductivity of the circuit board (10) can be improved.

[0104] In addition, as the width of the core via electrode (150) increases, there is an advantage in that the heat dissipation efficiency of the circuit board (10) through the core portion (100) can be improved. Accordingly, the occurrence of warping of the circuit board (10) can be minimized due to the improvement in thermal stress resulting from the increase in the thermal capacity of the core portion (100) itself.

[0105] In addition, since components such as the filling material within the core via electrode (150) are omitted compared to conventional methods, quality defects caused by the difference in the coefficient of thermal expansion between the filling material and the core via electrode can be prevented in advance, and there is an advantage of improving production efficiency through process simplification. In other words, as the thickness of the core part (100) increases, it becomes difficult to fill the via holes within the core part (100) with plating. For example, referring to FIG. 14, the core via electrode can be implemented by a process of plating a first layer, polishing it, and then plating a second layer within the core layer; however, in this case, production efficiency or yield may decrease as the polishing process and plating control process become complex. Referring to FIG. 14, it can be seen that the upper surface of the second layer is not uniform, which is due to an uneven plating thickness caused by height deviation during plating; this part may also require polishing again for flattening when placing another build-up insulating layer on the core part (100). In addition, if the boundary surface between the first layer and the second layer acts as an electrical resistance, it may be disadvantageous for power transmission and may cause problems such as delamination between the first layer and the second layer. However, referring to FIG. 16, in the case of the core via electrode (700) according to the present invention, the phenomenon of uneven plating thickness due to height variation does not occur. Also, the above-mentioned problems can be improved as the first layer and the second layer are not plated separately.

[0106] FIG. 17 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0107] Referring to FIG. 17, a first semiconductor chip (1000) and a second semiconductor chip (2000) may be included on a circuit board (10), the first semiconductor chip (1000) may be coupled to a first build-up layer (200) through a first connection part (430), and the second semiconductor chip (2000) may be coupled to a second build-up layer (300) through a second connection part (440). Here, the first connection part (430) and the second connection part (440) may each be solder balls.

[0108] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0109] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0110] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0111] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. Core part including upper and lower surfaces; A core via electrode penetrating the upper surface of the core portion and the lower surface of the core portion; and It includes a wiring layer disposed on the lower surface of the core via electrode, and The wiring layer comprises a seed layer disposed on the lower surface of the core via electrode and a metal layer disposed on the seed layer, and A circuit board in which the horizontal width of the seed layer is larger than the horizontal width of the lower surface of the core via electrode.

2. In Paragraph 1, A circuit board in which the size of the crystal grains constituting the seed layer is smaller than the size of the crystal grains constituting the metal layer.

3. In Paragraph 1, A circuit board in which the vertical thickness of the seed layer is smaller than the vertical thickness of the metal layer.

4. In Paragraph 1, A circuit board in which the vertical length of the core via electrode is 50 µm or more.

5. In Paragraph 1, A circuit board in which the size of the crystal grains constituting the seed layer is smaller than the size of the crystal grains constituting the core via electrode.

6. In Paragraph 1, The above core portion includes a plurality of glass fibers arranged in a vertical direction, and A circuit board in which the vertical length between the plurality of glass fibers is shorter than the length between the uppermost glass fiber among the plurality of glass fibers and the upper surface of the core layer.

7. In Paragraph 1, It includes a second seed layer disposed on the upper surface of the core portion, and The second seed layer is a circuit board separated from the seed layer through the core via electrode.

8. In Paragraph 1, It includes a first wiring layer disposed on the above-mentioned core, and A circuit board in which the size of the crystal grains of the first wiring layer is smaller than the size of the crystal grains of the core via electrode.

9. In Paragraph 1, It includes a polished surface disposed between the core via electrode and the seed layer, A circuit board in which the horizontal width of the polished surface is greater than the horizontal width of the seed layer.

10. Core part including upper and lower surfaces; A first build-up layer disposed on the upper surface of the core portion; A second build-up layer disposed on the lower surface of the above-mentioned core portion; A semiconductor chip disposed on the first build-up layer or the second build-up layer; A core via electrode penetrating the upper surface of the core portion and the lower surface of the core portion; and It includes a wiring layer disposed on the lower surface of the core via electrode, and The wiring layer comprises a seed layer disposed on the lower surface of the core via electrode and a metal layer disposed on the seed layer, and A semiconductor package in which the horizontal width of the seed layer is greater than the horizontal width of the lower surface of the core via electrode.

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