Adjustment module, adjustment method, and display apparatus

Abstract

An adjustment module (51), an adjustment method, and a display apparatus. The adjustment module (51) is used for a display apparatus, the display apparatus comprising at least one driving module (50) and a plurality of pixel circuits (60), and the driving module (50) being used for providing corresponding driving signals to the pixel circuits (60). The driving module (50) is electrically connected to a start of frame end (STV), and is used for receiving a start of frame signal from the start of frame end (STV). The adjustment module (51) comprises an adjustment unit (11). The adjustment unit (11) is electrically connected to the start of frame end (STV), and is used for providing the start of frame signal and adjusting the frequencies of the driving signals by means of adjusting the frequency of the start of frame signal. By means of adjusting the frequency of the start of frame signal provided to the driving module (50), the frequencies of the driving signals can be adjusted, so that a refresh rate can be adjusted.

Description

Adjustment module, adjustment method and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an adjustment module, adjustment method and display device. Background Technology

[0002] In related technologies, the application scenarios for displays are becoming increasingly diverse. For example, there is a demand for high-frequency refresh rate solutions in gaming and esports. A single refresh rate is no longer sufficient to meet people's display needs, especially in gaming and esports applications where insufficient refresh rates can lead to slow response times and stuttering. In scenarios requiring lower refresh rates, reducing power consumption and extending product lifespan can be achieved.

[0003] Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide an adjustment module applied to a display device, the display device including at least one driving module and a plurality of pixel circuits, the driving module being used to provide corresponding driving signals to the pixel circuits; the driving module being electrically connected to a frame start end and being used to receive a frame start signal from the frame start end; the adjustment module including an adjustment module;

[0005] The adjustment module is electrically connected to the frame start terminal and is used to provide the frame start signal. By adjusting the frequency of the frame start signal, the frequency of the drive signal is adjusted.

[0006] In at least one embodiment of this disclosure, the driving module includes a multi-stage driving circuit; the driving circuit is electrically connected to a clock signal terminal and is used to receive a clock signal provided by the clock signal terminal and provide the driving signal according to the clock signal;

[0007] The adjustment module is also electrically connected to the clock signal terminal to provide the clock signal and adjust the frequency of the drive signal by adjusting the frequency of the clock signal.

[0008] In at least one embodiment of this disclosure, the frequency of the clock signal is greater than or equal to the frequency of the frame start signal.

[0009] In at least one embodiment of this disclosure, the adjustment module is further configured to adjust the pulse width of the drive signal by adjusting at least one of the pulse width of the frame start signal and the pulse width of the clock signal;

[0010] The pulse width of the frame start signal is the width of the effective pulse of the frame start signal, the pulse width of the output clock signal is the width of the effective pulse of the output clock signal, and the pulse width of the drive signal is the width of the effective pulse of the drive signal.

[0011] In at least one embodiment of this disclosure, the pulse width of the frame start signal is greater than or equal to the pulse width of the clock signal.

[0012] In at least one embodiment of this disclosure, at a first refresh rate, the frequency of the frame start signal is a first frequency, and the frequency of the clock signal is a second frequency; at a second refresh rate, the frequency of the frame start signal is a third frequency, and the frequency of the clock signal is a fourth frequency; the second refresh rate is greater than the first refresh rate.

[0013] The third frequency is greater than or equal to the first frequency, and the fourth frequency is greater than or equal to the second frequency.

[0014] In at least one embodiment of this disclosure, the second frequency is greater than or equal to the first frequency, and the fourth frequency is greater than or equal to the third frequency.

[0015] In at least one embodiment of this disclosure, at a third refresh rate, the frequency of the frame start signal is a fifth frequency;

[0016] The second refresh rate is equal to the third refresh rate, and the fifth frequency is greater than or equal to the third frequency.

[0017] In at least one embodiment of this disclosure, at a first refresh rate, the pulse width of the frame start signal is a first pulse width, and the pulse width of the clock signal is a second pulse width; at a second refresh rate, the pulse width of the frame start signal is a third pulse width, and the pulse width of the clock signal is a fourth pulse width; the second refresh rate is greater than the first refresh rate.

[0018] The first pulse width is greater than the third pulse width, and the second pulse width is greater than the fourth pulse width.

[0019] In at least one embodiment of this disclosure, at the second refresh rate, the pulse width of the frame start signal is a third pulse width; at the third refresh rate, the pulse width of the frame start signal is a fifth pulse width; and the second refresh rate is equal to the third refresh rate.

[0020] The third pulse width is greater than the fifth pulse width;

[0021] At the second refresh rate, the frequency of the frame start signal is less than the frequency of the frame start signal at the third refresh rate.

[0022] In a second aspect, embodiments of this disclosure provide an adjustment method applied to a display device, the display device including at least one driving module and a plurality of pixel circuits, the driving module being used to provide corresponding driving signals to the pixel circuits; the driving module being electrically connected to a frame start end; the adjustment method comprising:

[0023] The adjustment module adjusts the frequency of the drive signal by adjusting the frequency of the frame start signal provided by the frame start terminal.

[0024] In a third aspect, embodiments of this disclosure provide a display device including at least one driving module and a plurality of pixel circuits, the display device further including the aforementioned adjustment module;

[0025] The driving module is used to provide corresponding driving signals to the pixel circuit;

[0026] The driving module is electrically connected to the frame start end.

[0027] The display device according to at least one embodiment of this disclosure includes a first driving module and a second driving module; the first driving module is used to provide a first reset control signal to the pixel circuit, and the second driving module is used to provide a light emission control signal to the pixel circuit;

[0028] The first driving module is electrically connected to the first frame start terminal, and the first driving module includes a multi-stage first driving circuit, which is electrically connected to the first clock signal terminal.

[0029] The second driving module is electrically connected to the start end of the second frame. The second driving module includes a multi-stage second driving circuit, and the second driving circuit is electrically connected to the second clock signal terminal.

[0030] The adjustment module includes an adjustment module for adjusting the first frame start signal provided by the first frame start terminal and / or the first clock signal provided by the first clock signal terminal, adjusting the second frame start signal provided by the second frame start terminal and / or the second clock signal provided by the second clock signal terminal, and controlling the frequency of the first reset control signal to be greater than or equal to the frequency of the light emission control signal.

[0031] In at least one embodiment of this disclosure, the adjustment module is used to control the frequency of the first reset control signal to be a sixth frequency and the frequency of the light emission control signal to be a seventh frequency at a first refresh rate; to control the frequency of the first reset control signal to be an eighth frequency and the frequency of the light emission control signal to be a ninth frequency at a second refresh rate; and to control the frequency of the first reset control signal to be a tenth frequency and the frequency of the light emission control signal to be an eleventh frequency at a third refresh rate.

[0032] The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0033] The eighth frequency is greater than the sixth frequency, the ninth frequency is greater than the seventh frequency, the tenth frequency is greater than the eleventh frequency; the tenth frequency is greater than the eighth frequency.

[0034] In at least one embodiment of this disclosure, the adjustment module is further configured to control the pulse width of the first reset control signal and the pulse width of the light emission control signal by adjusting the first frame start signal and / or the first clock signal, adjusting the second frame start signal and / or the second clock signal;

[0035] The adjustment module is used to control the pulse width of the first reset control signal to be the sixth pulse width and the pulse width of the light emission control signal to be the seventh pulse width at the first refresh rate; to control the pulse width of the first reset control signal to be the eighth pulse width and the pulse width of the light emission control signal to be the ninth pulse width at the second refresh rate; and to control the pulse width of the first reset control signal to be the tenth pulse width and the pulse width of the light emission control signal to be the eleventh pulse width at the third refresh rate.

[0036] The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0037] The sixth pulse width is greater than the eighth pulse width, the seventh pulse width is greater than the ninth pulse width, and the eighth pulse width is greater than the tenth pulse width;

[0038] The adjustment module is used to control the frequency of the first reset control signal at the second refresh rate to be less than the frequency of the first reset control signal at the third refresh rate.

[0039] The display device according to at least one embodiment of this disclosure includes a second driving module and a third driving module; the second driving module is used to provide a light emission control signal to the pixel circuit; the third driving module is used to provide a second reset control signal to the pixel circuit;

[0040] The adjustment module includes an adjustment module for adjusting the second frame start signal provided by the second frame start terminal and / or the second clock signal provided by the second clock signal terminal, and adjusting the third frame start signal provided by the third frame start terminal and / or the third clock signal provided by the third clock signal terminal, thereby controlling the frequency of the second reset control signal to be greater than or equal to the frequency of the light emission control signal.

[0041] In at least one embodiment of this disclosure, the adjustment module is used to control the frequency of the second reset control signal to be the twelfth frequency and the frequency of the light emission control signal to be the seventh frequency at the first refresh rate; to control the frequency of the second reset control signal to be the thirteenth frequency and the frequency of the light emission control signal to be the ninth frequency at the second refresh rate; and to control the frequency of the second reset control signal to be the fourteenth frequency and the frequency of the light emission control signal to be the eleventh frequency at the third refresh rate.

[0042] The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0043] The thirteenth frequency is greater than the twelfth frequency, the ninth frequency is greater than the seventh frequency, the fourteenth frequency is greater than the thirteenth frequency, and the fourteenth frequency is greater than the eleventh frequency.

[0044] In at least one embodiment of this disclosure, the adjustment module is further configured to control the pulse width of the second reset control signal and the pulse width of the light emission control signal by adjusting the second frame start signal and / or the second clock signal, and adjusting the third frame start signal and / or the third clock signal;

[0045] The adjustment module is used to control the pulse width of the second reset control signal to be the twelfth pulse width and the pulse width of the light emission control signal to be the seventh pulse width at the first refresh rate; to control the pulse width of the second reset control signal to be the thirteenth pulse width and the pulse width of the light emission control signal to be the ninth pulse width at the second refresh rate; and to control the pulse width of the second reset control signal to be the fourteenth pulse width and the pulse width of the light emission control signal to be the eleventh pulse width at the third refresh rate.

[0046] The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0047] The twelfth pulse width is greater than the thirteenth pulse width, the seventh pulse width is greater than the ninth pulse width, and the thirteenth pulse width is greater than the fourteenth pulse width;

[0048] The adjustment module is used to control the frequency of the second reset control signal at the second refresh rate to be less than the frequency of the second reset control signal at the third refresh rate.

[0049] The display device according to at least one embodiment of this disclosure includes a fourth driving module and a fifth driving module; the fourth driving module is used to provide a scanning signal for the pixel circuit, and the fifth driving module is used to provide a compensation control signal for the pixel circuit;

[0050] The fourth driving module is electrically connected to the fourth frame start terminal. The fourth driving module includes a multi-stage fourth driving circuit, and the fourth driving circuit is electrically connected to the fourth clock signal terminal.

[0051] The fifth driving module is electrically connected to the fifth frame start terminal. The fifth driving module includes a multi-stage fifth driving circuit, and the fifth driving circuit is electrically connected to the fifth clock signal terminal.

[0052] The adjustment module in the adjustment module is used to adjust the fourth frame start signal provided by the fourth frame start terminal and / or the fourth clock signal provided by the fourth clock signal terminal, and adjust the fifth frame start signal provided by the fifth frame start terminal and / or the fifth clock signal provided by the fifth clock signal terminal, so as to control the frequency of the scanning signal to be greater than or equal to the frequency of the compensation control signal.

[0053] In at least one embodiment of this disclosure, the adjustment module is used to control the frequency of the scanning signal to the fifteenth frequency and the frequency of the compensation control signal to the sixteenth frequency at a first refresh rate, and to control the frequency of the scanning signal to the seventeenth frequency and the frequency of the compensation control signal to the eighteenth frequency at a second refresh rate.

[0054] The second refresh rate is greater than the first refresh rate;

[0055] The eighteenth frequency is greater than the sixteenth frequency, the fifteenth frequency is greater than or equal to the sixteenth frequency, and the seventeenth frequency is greater than or equal to the eighteenth frequency.

[0056] In at least one embodiment of this disclosure, the pixel circuit includes a light-emitting element, a driving transistor, a first light-emitting control circuit, and a first reset circuit; the first light-emitting control circuit is electrically connected to a light-emitting control terminal, the first electrode of the driving transistor, and the first electrode of the light-emitting element; the first reset circuit is electrically connected to a first reset control terminal, a first initial voltage terminal, and the first electrode of the light-emitting element; the second electrode of the light-emitting element is electrically connected to the first voltage terminal; the display cycle of the pixel circuit includes a stop-light-emitting phase; the stop-light-emitting phase includes at least one first reset phase;

[0057] The first driving module is used to provide the first reset control signal to the first reset control terminal, and the second driving module is used to provide the light emission control signal to the light emission control terminal, so that in the stop light emission phase, the first light emission control circuit controls the first electrode of the driving transistor to disconnect from the first electrode of the light emission element under the control of the light emission control signal. In the first reset phase, the first reset circuit writes the first initial voltage provided by the first initial voltage terminal to the first electrode of the light emission element under the control of the first reset control signal.

[0058] In at least one embodiment of this disclosure, the pixel circuit further includes a second reset circuit; the second reset circuit is electrically connected to a second reset control terminal, a second initial voltage terminal, and the second electrode of the driving transistor; the display device includes a third driving module; the display cycle of the pixel circuit includes a stop-light-emitting phase; the stop-light-emitting phase includes at least one second reset phase;

[0059] The third driving module is used to provide the second reset control signal to the second reset control terminal, so that during the second reset phase, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the second terminal of the driving transistor.

[0060] In at least one embodiment of this disclosure, the pixel circuit further includes a data writing circuit; the data writing circuit is electrically connected to the scanning terminal, the data line, and the second electrode of the driving transistor; the display cycle of the pixel circuit includes a stop-light-emitting phase; the first stop-light-emitting phase in the display cycle includes at least one writing phase;

[0061] The fourth driving module is used to provide a first scanning signal to the scanning end, so that during the writing stage, the data writing circuit, under the control of the first scanning signal, writes the data voltage provided by the data line into the second terminal of the driving transistor.

[0062] The pixel circuit further includes a compensation control circuit; the compensation control circuit is electrically connected to the compensation control terminal, the gate of the driving transistor, and the first electrode of the driving transistor; the first stop-light-emitting stage in the display cycle includes a compensation stage;

[0063] The fifth driving module is used to provide a second scanning signal to the compensation control terminal, so that during the compensation stage, the compensation control circuit controls the gate of the driving transistor to be connected to the first terminal of the driving transistor under the control of the second scanning signal.

[0064] In at least one embodiment of this disclosure, at least one light-stopping phase in the display cycle, in addition to the first light-stopping phase, also includes a conduction phase;

[0065] The fifth driving module is used to provide a second scanning signal to the compensation control terminal, so that during the conduction phase, the compensation control circuit controls the gate of the driving transistor to connect with the first electrode of the driving transistor under the control of the second scanning signal.

[0066] In at least one embodiment of this disclosure, the driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a first energy storage circuit, and an output circuit;

[0067] The first node control circuit is electrically connected to the first node, the cascade input terminal, the second node, the second voltage terminal, the first control clock signal terminal, and the second control clock signal terminal, respectively. It is used to write the cascade input signal provided by the cascade input terminal into the first node under the control of the first control clock signal provided by the first control clock signal terminal, and to write the second voltage signal provided by the second voltage terminal into the first node under the control of the potential of the second node and the second control clock signal provided by the second control clock signal terminal.

[0068] The second node control circuit is electrically connected to the third control clock signal terminal, the third voltage terminal, the first node, and the second node, respectively. Under the control of the third control clock signal provided by the third control clock signal terminal, the third voltage signal provided by the third voltage terminal is written into the second node. Under the control of the potential of the first node, the third control clock signal is written into the second node.

[0069] The third node control circuit is electrically connected to the third voltage terminal, the first node, and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the third voltage signal provided by the third voltage terminal;

[0070] The first energy storage circuit is electrically connected to the second node, the third node and the drive signal output terminal respectively, and is used to maintain the potential of the second node and control the potential of the third node according to the drive signal provided by the drive signal output terminal.

[0071] The output circuit is electrically connected to the second node, the third node, the second voltage terminal, the output clock signal terminal, and the drive signal output terminal, respectively. It is used to control the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node, and to control the connection or disconnection between the drive signal output terminal and the output clock signal terminal under the control of the potential of the third node.

[0072] The clock signal terminal includes at least one of the first control clock signal terminal, the second control clock signal terminal, the third control clock signal terminal, and the output clock signal terminal.

[0073] In at least one embodiment of this disclosure, the driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a first energy storage circuit, and an output circuit;

[0074] The first node control circuit is electrically connected to the first node, the cascade input terminal, the second node, the second voltage terminal, the first control clock signal terminal, and the second control clock signal terminal, respectively. It is used to write the cascade input signal provided by the cascade input terminal into the first node under the control of the first control clock signal provided by the first control clock signal terminal, and to write the second voltage signal provided by the second voltage terminal into the first node under the control of the potential of the second node and the second control clock signal provided by the second control clock signal terminal.

[0075] The second node control circuit is electrically connected to the first control clock signal terminal, the third voltage terminal, the first node, and the second node, respectively. Under the control of the first control clock signal provided by the first control clock signal terminal, the third voltage signal provided by the third voltage terminal is written into the second node. Under the control of the potential of the first node, the first control clock signal is written into the second node.

[0076] The third node control circuit is electrically connected to the third voltage terminal, the first node, and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the third voltage signal provided by the third voltage terminal;

[0077] The first energy storage circuit is electrically connected to the second node, the third node and the drive signal output terminal respectively, and is used to maintain the potential of the second node and control the potential of the third node according to the drive signal provided by the drive signal output terminal.

[0078] The output circuit is electrically connected to the second node, the third node, the second voltage terminal, the output clock signal terminal, and the drive signal output terminal, respectively. It is used to control the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node, and to control the connection or disconnection between the drive signal output terminal and the output clock signal terminal under the control of the potential of the third node.

[0079] The clock signal terminal includes at least one of the first control clock signal terminal, the second control clock signal terminal, and the output clock signal terminal.

[0080] In at least one embodiment of this disclosure, the driving circuit includes a carry signal output circuit, a selection control circuit, a first on / off control circuit, a second on / off control circuit, a first energy storage circuit, a second energy storage circuit, and an output circuit.

[0081] The carry signal output circuit is electrically connected to the cascade input terminal, the control clock signal terminal, the second node, the third node, the output clock signal terminal, and the carry signal output terminal, respectively. It is used to control the potential of the second node and the potential of the third node under the control of the cascade input signal provided by the cascade input terminal and the control clock signal provided by the control clock signal terminal. Under the control of the potential of the second node and the potential of the third node, the carry signal is provided through the carry signal output terminal according to the output clock signal provided by the output clock signal terminal.

[0082] The selection control circuit is electrically connected to the first control terminal, the second control terminal, the selection control terminal and the fourth node respectively, and is used to write the selection control signal provided by the selection control terminal into the fourth node under the control of the first control signal provided by the first control terminal and the second control signal provided by the second control terminal;

[0083] The first on / off control circuit is electrically connected to the fourth node, the second node and the first output control node respectively, and is used to control the connection or disconnection between the second node and the first output control node under the control of the potential of the fourth node;

[0084] The second on / off control circuit is electrically connected to the fourth node, the third node and the second output control node respectively, and is used to control the connection or disconnection between the third node and the second output control node under the control of the potential of the fourth node;

[0085] The first energy storage circuit is electrically connected to the first output control node, the second output control node and the drive signal output terminal respectively, and is used to maintain the potential of the first output control node and control the potential of the second output control node according to the drive signal provided by the drive signal output terminal.

[0086] The second energy storage circuit is electrically connected to the fourth node and the second output control node respectively, and is used to control the potential of the second output control node according to the potential of the fourth node;

[0087] The output circuit is electrically connected to the first output control node, the second output control node, the second voltage terminal, the drive signal output terminal, and the output clock signal terminal, respectively. It is used to control the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the first output control node, and to control the connection or disconnection between the drive signal output terminal and the output clock signal terminal under the control of the potential of the second output control node.

[0088] The clock signal terminal includes at least one of the control clock signal terminal and the output clock signal terminal. Attached Figure Description

[0089] Figure 1 is a structural diagram of the adjustment module according to at least one embodiment of the present disclosure;

[0090] Figure 2 is a structural diagram of the adjustment module according to at least one embodiment of the present disclosure;

[0091] Figure 3A is a timing diagram of the operation of the adjustment module according to at least one embodiment of the present disclosure;

[0092] Figure 3B is a timing diagram of the operation of the adjustment module according to at least one embodiment of the present disclosure;

[0093] Figure 3C is a timing diagram of the operation of the adjustment module according to at least one embodiment of the present disclosure;

[0094] Figure 4A is a timing diagram of the operation of the adjustment module according to at least one embodiment of the present disclosure;

[0095] Figure 4B is a timing diagram of the operation of the adjustment module according to at least one embodiment of the present disclosure;

[0096] Figure 4C is a timing diagram of the operation of the adjustment module according to at least one embodiment of the present disclosure;

[0097] Figure 5 is a structural diagram of a display device according to at least one embodiment of the present disclosure;

[0098] Figure 6 is a structural diagram of a display device according to at least one embodiment of the present disclosure;

[0099] Figure 7A is a timing diagram of at least one embodiment of the display device shown in Figure 6;

[0100] Figure 7B is a timing diagram of at least one embodiment of the display device shown in Figure 6;

[0101] Figure 7C is a timing diagram of at least one embodiment of the display device shown in Figure 6;

[0102] Figure 8 is a structural diagram of a display device according to at least one embodiment of the present disclosure;

[0103] Figure 9A is a timing diagram of at least one embodiment of the display device shown in Figure 8;

[0104] Figure 9B is a timing diagram of at least one embodiment of the display device shown in Figure 8;

[0105] Figure 9C is a timing diagram of at least one embodiment of the display device shown in Figure 8;

[0106] Figure 10 is a structural diagram of a display device according to at least one embodiment of the present disclosure;

[0107] Figure 11A is a timing diagram of the operation of a display device according to at least one embodiment of the present disclosure;

[0108] Figure 11B is a timing diagram of the operation of a display device according to at least one embodiment of the present disclosure;

[0109] Figure 11C is a timing diagram of the operation of a display device according to at least one embodiment of the present disclosure;

[0110] Figure 12A is a timing diagram of the operation of a display device according to at least one embodiment of the present disclosure;

[0111] Figure 12B is a timing diagram of the operation of a display device according to at least one embodiment of the present disclosure;

[0112] Figure 12C is a timing diagram of the operation of a display device according to at least one embodiment of the present disclosure;

[0113] Figure 13 is a structural diagram of at least one embodiment of the pixel circuit;

[0114] Figure 14 is a structural diagram of at least one embodiment of the pixel circuit;

[0115] Figure 15 is a timing diagram of at least one embodiment of the pixel circuit;

[0116] Figure 16 is a structural diagram of at least one embodiment of the pixel circuit;

[0117] Figure 17 is a structural diagram of at least one embodiment of the pixel circuit;

[0118] Figure 18 is a circuit diagram of at least one embodiment of the pixel circuit;

[0119] Figure 19 is a structural diagram of at least one embodiment of the driving circuit;

[0120] Figure 20 is a circuit diagram of at least one embodiment of the driving circuit;

[0121] Figure 21 is a structural diagram of at least one embodiment of the driving circuit;

[0122] Figure 22 is a circuit diagram of at least one embodiment of the driving circuit;

[0123] Figure 23 is a structural diagram of at least one embodiment of the driving circuit;

[0124] Figure 24 is a circuit diagram of at least one embodiment of the driving circuit;

[0125] Figure 25 is a circuit diagram of at least one embodiment of the driving circuit;

[0126] Figure 26 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 25. Detailed Implementation

[0127] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0128] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0129] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0130] The adjustment module described in this embodiment is applied to a display device, which includes at least one driving module and multiple pixel circuits. The driving module is used to provide corresponding driving signals to the pixel circuits. The driving module is electrically connected to a frame start end and is used to receive a frame start signal from the frame start end. As shown in FIG1, the adjustment module includes an adjustment module 11.

[0131] The adjustment module 11 is electrically connected to the frame start terminal STV and is used to output the frame start signal to the frame start terminal STV. By adjusting the frequency of the frame start signal, the frequency of the drive signal is adjusted.

[0132] The refresh rate can be adjusted by adjusting the frequency of the drive signal through the adjustment of the frequency of the frame start signal.

[0133] In related technologies, the application scenarios for displays present diverse demands. For example, there is a need for high-frequency refresh rates greater than 120Hz for applications such as gaming and esports, and a need for partitioned frequency conversion solutions for partitioned refresh rates. A single refresh rate is no longer sufficient to meet people's display needs, especially in applications requiring high refresh rates, where insufficient refresh rates can lead to slow response times and stuttering. In scenarios requiring low refresh rates, reducing the refresh rate can reduce power consumption and extend product lifespan. Based on this, embodiments of this disclosure provide an adjustment module that, by adjusting the frequency of the frame start signal provided to the drive module, can adjust the frequency of the drive signal to achieve refresh rate adjustment.

[0134] In at least one embodiment of this disclosure, the adjustment module may be included in the display device, or the adjustment module may be independent of the display device.

[0135] In a specific implementation, the display device may include a display driver IC (Integrated Circuit), and the adjustment module may be included in the display driver IC.

[0136] In at least one embodiment of this disclosure, the driving module may include multi-stage driving circuits;

[0137] The cascaded input terminals of the first n stages of the driving module can be electrically connected to the frame start terminal, where n is a positive integer;

[0138] The cascaded input terminal of the m-th stage drive circuit included in the drive module can be electrically connected to the drive signal output terminal or the carry signal output terminal of the ma-th stage drive circuit, where m is a positive integer, greater than n, and a is a positive integer. For example, m is greater than a; a is greater than or equal to 1, and n is greater than or equal to 1.

[0139] In at least one embodiment of this disclosure, the driving module includes a multi-stage driving circuit; the driving circuit is electrically connected to a clock signal terminal and is used to receive a clock signal provided by the clock signal terminal and provide the driving signal according to the clock signal;

[0140] The adjustment module is also electrically connected to the clock signal terminal to provide the clock signal and adjust the frequency of the drive signal by adjusting the frequency of the clock signal.

[0141] In a specific implementation, the driving module may include multiple cascaded driving circuits. The driving circuit is electrically connected to the clock signal terminal and provides a driving signal to the pixel circuit according to the clock signal. The adjustment module can adjust the frequency of the driving signal by adjusting the frequency of the clock signal, thereby adjusting the refresh rate.

[0142] As shown in Figure 2, based on at least one embodiment of the adjustment module shown in Figure 1, the adjustment module can be electrically connected to the clock signal terminal CK to provide a clock signal to the clock signal terminal CK, and adjust the frequency of the drive signal by adjusting the frequency of the clock signal.

[0143] In a specific implementation, the driving circuit may include an output circuit;

[0144] The output circuit can be electrically connected to the second node, the third node, the second voltage terminal, the output clock signal terminal, and the drive signal output terminal respectively. It is used to control the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node, and to control the connection or disconnection between the drive signal output terminal and the output clock signal terminal under the control of the potential of the third node.

[0145] The driving circuit may include circuitry for controlling the second node and circuitry for controlling the third node.

[0146] At least one of the circuits for controlling the second node and the circuits for controlling the third node is electrically connected to at least one control clock signal terminal, and is used to control the potential of the second node and the potential of the third node according to the control clock signal provided by the control clock signal terminal.

[0147] The clock signal terminal electrically connected to the adjustment module may include at least one of the output clock signal terminal and the at least one control clock signal terminal.

[0148] Optionally, the frequency of the clock signal is greater than or equal to the frequency of the frame start signal.

[0149] In practical implementation, the frequency of the clock signal can be set to be greater than or equal to the frequency of the frame start signal to provide more timing combinations.

[0150] In at least one embodiment of this disclosure, the adjustment module is further configured to adjust the pulse width of the drive signal by adjusting at least one of the pulse width of the frame start signal and the pulse width of the clock signal;

[0151] The pulse width of the frame start signal is the width of the effective pulse of the frame start signal, the pulse width of the output clock signal is the width of the effective pulse of the output clock signal, and the pulse width of the drive signal is the width of the effective pulse of the drive signal.

[0152] In a specific implementation, the adjustment module can also adjust the pulse width of the drive signal by adjusting the pulse width of the frame start signal and / or the pulse width of the clock signal.

[0153] Optionally, the pulse width of the frame start signal is greater than or equal to the pulse width of the clock signal.

[0154] In specific implementation, the pulse width of the frame start signal can be set to be greater than or equal to the pulse width of the clock signal. When increasing the refresh rate, the pulse width of the clock signal can be reduced while the pulse width of the frame start signal remains unchanged. Alternatively, the pulse widths of the clock signal and the frame start signal can be reduced simultaneously. Thus, the pulse width of the frame start signal can be greater than or equal to the pulse width of the clock signal.

[0155] In at least one embodiment of this disclosure, at a first refresh rate, the frequency of the frame start signal is a first frequency, and the frequency of the clock signal is a second frequency; at a second refresh rate, the frequency of the frame start signal is a third frequency, and the frequency of the clock signal is a fourth frequency; the second refresh rate is greater than the first refresh rate.

[0156] The third frequency is greater than or equal to the first frequency, and the fourth frequency is greater than or equal to the second frequency.

[0157] Optionally, the second frequency is greater than or equal to the first frequency, and the fourth frequency is greater than or equal to the third frequency.

[0158] In at least one embodiment of this disclosure, at a first refresh rate, the pulse width of the frame start signal is a first pulse width, and the pulse width of the clock signal is a second pulse width; at a second refresh rate, the pulse width of the frame start signal is a third pulse width, and the pulse width of the clock signal is a fourth pulse width; the second refresh rate is greater than the first refresh rate.

[0159] The first pulse width is greater than the third pulse width, and the second pulse width is greater than the fourth pulse width.

[0160] As shown in Figure 3A, at the first refresh rate, the frame start signal provided by the frame start terminal STV has a first frequency, and the clock signal provided by the clock signal terminal CK has a second frequency; the pulse width of the frame start signal is the first pulse width, and the pulse width of the clock signal is the second pulse width.

[0161] As shown in Figure 3B, at the second refresh rate, the frequency of the frame start signal provided by STV is the third frequency, and the frequency of the clock signal provided by the clock signal terminal CK is the fourth frequency; the pulse width of the frame start signal is the third pulse width, and the pulse width of the clock signal is the fourth pulse width.

[0162] As shown in Figure 3C, at the fourth refresh rate, the frequency of the frame start signal provided by STV is greater than the third frequency, the frequency of the clock signal provided by the clock signal terminal CK is greater than the fourth frequency, and the frequency of the clock signal provided by the clock signal terminal CK is greater than the frequency of the frame start signal provided by STV.

[0163] In at least one embodiment corresponding to Figures 3A-3C, the first refresh rate is less than the second refresh rate, and the fourth refresh rate is greater than the second refresh rate; for example, the first refresh rate can be 120Hz, the second refresh rate can be 180Hz, and the fourth refresh rate can be 240Hz.

[0164] The third frequency is greater than the first frequency, the fourth frequency is greater than the second frequency, the second frequency is greater than the first frequency, and the fourth frequency is greater than the third frequency;

[0165] The first pulse width is greater than the third pulse width, and the second pulse width is greater than the fourth pulse width.

[0166] In at least one embodiment shown in Figures 3A-3C, at the fourth refresh rate, the pulse width of the frame start signal is smaller than the pulse width of the frame start signal at the second refresh rate.

[0167] At the fourth refresh rate, the pulse width of the clock signal is smaller than that at the second refresh rate.

[0168] As shown in Figures 3A-3C, when the frequency of the driving signal provided by the driving circuit is increased, the frequency of the clock signal can be increased, and the frequency of the frame start signal can be increased at the same time, while the pulse width of the clock signal and the pulse width of the frame start signal can be decreased at the same time.

[0169] When the refresh rate is the normal refresh rate, such as 120Hz, the waveforms of the frame start signal and the clock signal are shown in Figure 3A.

[0170] As shown in Figure 3B, when the refresh rate increases to 180Hz, the frequency of the frame start signal increases accordingly, the pulse width of the frame start signal narrows, the frequency of the clock signal increases, and the pulse width of the clock signal narrows.

[0171] As shown in Figure 3C, when the refresh rate increases to 240Hz, the frequency of the frame start signal increases accordingly, the pulse width of the frame start signal narrows, the frequency of the clock signal increases, and the pulse width of the clock signal narrows.

[0172] The increase in the frequency of the frame start signal can be the same as or different from the increase in the frequency of the clock signal.

[0173] The narrowing degree of the pulse width of the frame start signal can be the same as or different from the narrowing degree of the pulse width of the clock signal. For example, the ratio of the frequency of the frame start signal to the frequency of the clock signal can be greater than or equal to 0.6 and less than or equal to 0.8, but is not limited thereto.

[0174] In at least one embodiment of this disclosure, when it is necessary to increase the refresh rate, one approach is to increase the frequency and pulse width of the clock signal while keeping the frequency and pulse width of the frame start signal unchanged; another approach is to increase the frequency and pulse width of the clock signal while correspondingly increasing the frequency and pulse width of the frame start signal.

[0175] In at least one embodiment of this disclosure, at a third refresh rate, the frequency of the frame start signal is a fifth frequency;

[0176] The second refresh rate is equal to the third refresh rate, and the fifth frequency is greater than or equal to the third frequency.

[0177] In at least one embodiment of this disclosure, at the second refresh rate, the pulse width of the frame start signal is a third pulse width; at the third refresh rate, the pulse width of the frame start signal is a fifth pulse width; and the second refresh rate is equal to the third refresh rate.

[0178] The third pulse width is greater than the fifth pulse width;

[0179] At the second refresh rate, the frequency of the frame start signal is less than the frequency of the frame start signal at the third refresh rate.

[0180] As shown in Figure 4A, at the first refresh rate, the frequency of the frame start signal provided by the frame start terminal STV is the first frequency, and the pulse width of the frame start signal is the first pulse width.

[0181] As shown in Figure 4B, at the second refresh rate, the frequency of the frame start signal provided by the frame start terminal STV is the second frequency, and the pulse width of the frame start signal is the third pulse width.

[0182] As shown in Figure 4C, at the third refresh rate, the frequency of the frame start signal provided by the frame start terminal STV is the fifth frequency, and the pulse width of the frame start signal is the fifth pulse width.

[0183] The first refresh rate is less than the second refresh rate, and the second refresh rate is equal to the third refresh rate; for example, the first refresh rate can be 120Hz, and the second refresh rate and the third refresh rate can be 180Hz.

[0184] The fifth frequency is greater than the third frequency, the second frequency is greater than the first frequency, and the third pulse width is greater than the fifth pulse width.

[0185] As shown in Figure 4C, during high-frequency driving (high-frequency driving can refer to a refresh rate greater than 120Hz), the number of effective low pulses of the frame start signal can be increased, and the number of effective low pulses output by the frame start terminal STV at one time is more than one. When the driving signal provided by the driving circuit is the first reset control signal that controls the anode reset of the light-emitting element, multiple and sufficient resets of the anode of the light-emitting element can be achieved during the non-light-emitting stage. Especially in high-frequency applications, multiple effective resets can promptly reduce the aging degree of the light-emitting element.

[0186] The adjustment method described in this disclosure is applied to a display device, which includes at least one driving module and multiple pixel circuits. The driving module is used to provide corresponding driving signals to the pixel circuits. The driving module is electrically connected to a frame start end. The adjustment method includes:

[0187] The adjustment module adjusts the frequency of the drive signal by adjusting the frequency of the frame start signal provided by the frame start terminal.

[0188] Optionally, the frequency of the clock signal is greater than or equal to the frequency of the frame start signal.

[0189] In at least one embodiment of this disclosure, the driving method may further include:

[0190] The adjustment module adjusts the pulse width of the drive signal by adjusting at least one of the pulse width of the frame start signal and the pulse width of the clock signal;

[0191] The pulse width of the frame start signal is the width of the effective pulse of the frame start signal, the pulse width of the output clock signal is the width of the effective pulse of the output clock signal, and the pulse width of the drive signal is the width of the effective pulse of the drive signal.

[0192] Optionally, the pulse width of the frame start signal is greater than or equal to the pulse width of the clock signal.

[0193] The display device described in this disclosure includes at least one driving module and multiple pixel circuits, and the display device further includes the aforementioned adjustment module;

[0194] The driving module is used to provide corresponding driving signals to the pixel circuit;

[0195] The driving module is electrically connected to the frame start end.

[0196] As shown in FIG5, the display device according to at least one embodiment of the present disclosure may include a driving module 50 and an adjustment module 51;

[0197] The drive module 50 is electrically connected to the frame start terminal STV and is used to receive the frame start signal from the frame start terminal STV and output multi-level drive signals under the control of the frame start signal.

[0198] The adjustment module 51 is electrically connected to the frame start terminal STV and is used to provide the frame start signal. By adjusting the frequency of the frame start signal, the frequency of the drive signal provided by the drive module 50 is adjusted.

[0199] As shown in Figure 6, the display device according to at least one embodiment of this disclosure includes a first driving module 61 and a second driving module 62; the pixel circuit 60 is electrically connected to the first reset control terminal RST1 and the light emission control terminal EM, respectively.

[0200] The first driving module 61 is electrically connected to the pixel circuit 60 and is used to provide a first reset control signal to the first reset control terminal RST1;

[0201] The second driving module 62 is electrically connected to the pixel circuit 60 and is used to provide a light emission control signal to the light emission control terminal EM;

[0202] The first driving module 61 is electrically connected to the first frame start terminal STV1. The first driving module 61 includes a multi-stage first driving circuit, and the first driving circuit is electrically connected to the first clock signal terminal CLK1.

[0203] The second driving module 62 is electrically connected to the second frame start terminal STV2. The second driving module 62 includes a multi-stage second driving circuit, and the second driving circuit is electrically connected to the second clock signal terminal CLK2.

[0204] The adjustment module 51 can be electrically connected to the frame start end and the clock signal end, and is used to provide a frame start signal to the frame start end and a clock signal to the clock signal end. In at least one embodiment shown in FIG6, the frame start end may include a first frame start end STV1 and a second frame start end STV2, and the clock signal end may include a first clock signal end CLK1 and a second clock signal end CLK2.

[0205] The adjustment module 51 includes an adjustment module 11 electrically connected to the first frame start terminal STV1, the first clock signal terminal CLK1, the second frame start terminal STV2, and the second clock signal terminal CLK2, respectively. It is used to provide a first frame start signal to the first frame start terminal STV1, a second frame start signal to the second frame start terminal STV2, a first clock signal to the first clock signal terminal CLK1, and a second clock signal to the second clock signal terminal CLK2. By adjusting the first frame start signal provided by the first frame start terminal STV1 and / or the first clock signal provided by the first clock signal terminal CLK1, and adjusting the second frame start signal provided by the second frame start terminal STV2 and / or the second clock signal provided by the second clock signal terminal CLK2, the frequency of the first reset control signal is controlled to be greater than or equal to the frequency of the light emission control signal.

[0206] In at least one embodiment of this disclosure, the adjustment module is used to control the frequency of the first reset control signal to be a sixth frequency and the frequency of the light emission control signal to be a seventh frequency at a first refresh rate; to control the frequency of the first reset control signal to be an eighth frequency and the frequency of the light emission control signal to be a ninth frequency at a second refresh rate; and to control the frequency of the first reset control signal to be a tenth frequency and the frequency of the light emission control signal to be an eleventh frequency at a third refresh rate.

[0207] The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0208] The eighth frequency is greater than the sixth frequency, the ninth frequency is greater than the seventh frequency, the tenth frequency is greater than the eleventh frequency; the tenth frequency is greater than the eighth frequency.

[0209] As shown in Figure 7A, at the first refresh rate, the frequency of the first reset control signal provided by RST1 is the sixth frequency, and the frequency of the light emission control signal provided by EM is the seventh frequency.

[0210] As shown in Figure 7B, at the second refresh rate, the frequency of the first reset control signal provided by RST1 is the eighth frequency, and the frequency of the light emission control signal provided by EM is the ninth frequency.

[0211] As shown in Figure 7C, at the third refresh rate, the frequency of the first reset control signal provided by RST1 is the tenth frequency, and the frequency of the light emission control signal provided by EM is the eleventh frequency.

[0212] For example, the first refresh rate can be 120Hz, and the second and third refresh rates can be 180Hz.

[0213] In at least one embodiment shown in Figures 7A-7C, the second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0214] The eighth frequency is greater than the sixth frequency, the ninth frequency is greater than the seventh frequency, the tenth frequency is greater than the eleventh frequency; the tenth frequency is greater than the eighth frequency.

[0215] In at least one embodiment of this disclosure, in a high refresh rate operating state, for example, when the refresh rate is 180Hz, increasing the reset frequency of the anode of the light-emitting element can control the frequency of the first reset control signal and the frequency of the light-emitting control signal to increase synchronously, or control the frequency of the first reset control signal to be greater than the frequency of the light-emitting control signal.

[0216] Specifically, for the first method of increasing frequency, as shown in Figure 7B, the frequency of the light emission control signal and the frequency of the first reset control signal are increased simultaneously. That is, the light emission frequency of the control pixel circuit is increased, and simultaneously, the frequency of the anode reset of the light emission element is also increased.

[0217] As shown in Figure 7C, the frequency of the first reset control signal is greater than the frequency of the light emission control signal. During the non-light emission stage, the anode of the light emission element is reset multiple times to ensure that the anode of the light emission element will not form a bias voltage with the low voltage under the high brush operating state, which would cause false light emission.

[0218] By comparing Figures 7B and 7C, the following results are obtained: In Figures 7B and 7C, the frequencies of the first light emission control signals provided by the EM are equal;

[0219] In Figure 7C, the frequency of the first reset control signal provided by RST1 is greater than that in Figure 7B.

[0220] In at least one embodiment of this disclosure, the adjustment module is further configured to control the pulse width of the first reset control signal and the pulse width of the light emission control signal by adjusting the first frame start signal and / or the first clock signal, adjusting the second frame start signal and / or the second clock signal;

[0221] The adjustment module is used to control the pulse width of the first reset control signal to be the sixth pulse width and the pulse width of the light emission control signal to be the seventh pulse width at the first refresh rate; to control the pulse width of the first reset control signal to be the eighth pulse width and the pulse width of the light emission control signal to be the ninth pulse width at the second refresh rate; and to control the pulse width of the first reset control signal to be the tenth pulse width and the pulse width of the light emission control signal to be the eleventh pulse width at the third refresh rate.

[0222] The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0223] The sixth pulse width is greater than the eighth pulse width, the seventh pulse width is greater than the ninth pulse width, and the eighth pulse width is greater than the tenth pulse width;

[0224] The adjustment module is used to control the frequency of the first reset control signal at the second refresh rate to be less than the frequency of the first reset control signal at the third refresh rate.

[0225] As shown in Figure 7A, at the first refresh rate, the pulse width of the first reset control signal provided by RST1 is the sixth pulse width, and the pulse width of the light emission control signal provided by EM is the seventh pulse width.

[0226] As shown in Figure 7B, at the second refresh rate, the pulse width of the first reset control signal provided by RST1 is the eighth pulse width, and the pulse width of the light emission control signal provided by EM is the ninth pulse width.

[0227] As shown in Figure 7C, at the third refresh rate, the pulse width of the first reset control signal provided by RST1 is the tenth pulse width, and the frequency of the light emission control signal provided by EM is the eleventh pulse width.

[0228] For example, the first refresh rate can be 120Hz, and the second and third refresh rates can be 180Hz.

[0229] In at least one embodiment shown in Figures 7A-7C, the second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0230] The sixth pulse width is greater than the eighth pulse width, the seventh pulse width is greater than the ninth pulse width, and the eighth pulse width is greater than the tenth pulse width;

[0231] At the second refresh rate, the frequency of the first reset control signal is less than the frequency of the first reset control signal at the third refresh rate.

[0232] The display device according to at least one embodiment of this disclosure includes a second driving module and a third driving module; the second driving module is used to provide a light emission control signal to the pixel circuit; the third driving module is used to provide a second reset control signal to the pixel circuit;

[0233] The adjustment module includes an adjustment module for adjusting the second frame start signal provided by the second frame start terminal and / or the second clock signal provided by the second clock signal terminal, and adjusting the third frame start signal provided by the third frame start terminal and / or the third clock signal provided by the third clock signal terminal, thereby controlling the frequency of the second reset control signal to be greater than or equal to the frequency of the light emission control signal.

[0234] As shown in Figure 8, the display device according to at least one embodiment of the present disclosure includes a second driving module 62 and a third driving module 63; the pixel circuit 60 is electrically connected to the second reset control terminal RST2 and the light emission control terminal EM, respectively;

[0235] The second driving module 62 is electrically connected to the light-emitting control terminal EM and is used to provide light-emitting control signals to the light-emitting control terminal EM;

[0236] The third drive module 63 is electrically connected to the second reset control terminal RST2 and is used to provide a second reset control signal to the second reset control terminal RST2.

[0237] The adjustment module 51 includes an adjustment module 11 that is electrically connected to the second frame start terminal STV2, the second clock signal terminal CLK2, the third frame start terminal STV3, and the third clock signal terminal CLK3, respectively. It is used to adjust the second frame start signal provided by the second frame start terminal STV2 and / or the second clock signal provided by the second clock signal terminal CLK2, and adjust the third frame start signal provided by the third frame start terminal STV3 and / or the third clock signal provided by the third clock signal terminal CLK3, so as to control the frequency of the second reset control signal to be greater than or equal to the frequency of the light emission control signal.

[0238] In at least one embodiment of this disclosure, the pixel circuit, under the control of a second reset control signal, resets the potential of the second electrode of the driving transistor included in the pixel circuit, so as to improve the hysteresis phenomenon of the driving transistor.

[0239] In at least one embodiment of this disclosure, the adjustment module is used to control the frequency of the second reset control signal to be the twelfth frequency and the frequency of the light emission control signal to be the seventh frequency at the first refresh rate; to control the frequency of the second reset control signal to be the thirteenth frequency and the frequency of the light emission control signal to be the ninth frequency at the second refresh rate; and to control the frequency of the second reset control signal to be the fourteenth frequency and the frequency of the light emission control signal to be the eleventh frequency at the third refresh rate.

[0240] The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0241] The thirteenth frequency is greater than the twelfth frequency, the ninth frequency is greater than the seventh frequency, the fourteenth frequency is greater than the thirteenth frequency, and the fourteenth frequency is greater than the eleventh frequency.

[0242] As shown in Figure 9A, at the first refresh rate, the frequency of the second reset control signal provided by RST2 is the twelfth frequency, and the frequency of the light emission control signal provided by EM is the seventh frequency.

[0243] As shown in Figure 9B, at the second refresh rate, the frequency of the second reset control signal provided by RST2 is the thirteenth frequency, and the frequency of the light emission control signal provided by EM is the ninth frequency.

[0244] As shown in Figure 9C, at the third refresh rate, the frequency of the second reset control signal provided by RST2 is the fourteenth frequency, and the frequency of the light emission control signal provided by EM is the eleventh frequency.

[0245] For example, the first refresh rate can be 120Hz, and the second and third refresh rates can be 180Hz.

[0246] In at least one embodiment shown in Figures 9A-9C, the second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0247] The thirteenth frequency is greater than the twelfth frequency, the ninth frequency is greater than the seventh frequency, the fourteenth frequency is greater than the thirteenth frequency, and the fourteenth frequency is greater than the eleventh frequency.

[0248] In at least one embodiment of this disclosure, in a high refresh rate operating state, for example, when the refresh rate is 180Hz, increasing the reset frequency of the second electrode of the driving transistor can control the frequency of the second reset control signal and the frequency of the light emission control signal to increase synchronously, or control the frequency of the second reset control signal to be greater than the frequency of the light emission control signal.

[0249] Specifically, for the first method of increasing frequency, as shown in Figure 9B, the frequency of the light emission control signal and the frequency of the second reset control signal are increased simultaneously. That is, the light emission frequency of the control pixel circuit is increased, and simultaneously, the reset frequency of the second electrode of the driving transistor is also increased.

[0250] As shown in Figure 9C, for the second method of increasing the frequency, the frequency of the second reset control signal is greater than the frequency of the light emission control signal. During the non-light emission stage, the second electrode of the driving transistor is reset multiple times to ensure that the hysteresis phenomenon of the driving transistor can be improved in the high-brush operating state.

[0251] In at least one embodiment of this disclosure, the adjustment module is further configured to control the pulse width of the second reset control signal and the pulse width of the light emission control signal by adjusting the second frame start signal and / or the second clock signal, and adjusting the third frame start signal and / or the third clock signal;

[0252] The adjustment module is used to control the pulse width of the second reset control signal to be the twelfth pulse width and the pulse width of the light emission control signal to be the seventh pulse width at the first refresh rate; to control the pulse width of the second reset control signal to be the thirteenth pulse width and the pulse width of the light emission control signal to be the ninth pulse width at the second refresh rate; and to control the pulse width of the second reset control signal to be the fourteenth pulse width and the pulse width of the light emission control signal to be the eleventh pulse width at the third refresh rate.

[0253] The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0254] The twelfth pulse width is greater than the thirteenth pulse width, the seventh pulse width is greater than the ninth pulse width, and the thirteenth pulse width is greater than the fourteenth pulse width;

[0255] The adjustment module is used to control the frequency of the second reset control signal at the second refresh rate to be less than the frequency of the second reset control signal at the third refresh rate.

[0256] As shown in Figure 9A, at the first refresh rate, the pulse width of the second reset control signal provided by RST2 is the twelfth pulse width, and the pulse width of the light emission control signal provided by EM is the seventh pulse width.

[0257] As shown in Figure 9B, at the second refresh rate, the pulse width of the second reset control signal provided by RST2 is the thirteenth pulse width, and the pulse width of the light emission control signal provided by EM is the ninth pulse width.

[0258] As shown in Figure 9C, at the third refresh rate, the pulse width of the second reset control signal provided by RST1 is the fourteenth pulse width, and the frequency of the light emission control signal provided by EM is the eleventh pulse width.

[0259] For example, the first refresh rate can be 120Hz, and the second and third refresh rates can be 180Hz.

[0260] In at least one embodiment shown in Figures 9A-9C, the second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate;

[0261] The twelfth pulse width is greater than the thirteenth pulse width, the seventh pulse width is greater than the ninth pulse width, and the thirteenth pulse width is greater than the fourteenth pulse width;

[0262] At the second refresh rate, the frequency of the second reset control signal is less than the frequency of the second reset control signal at the third refresh rate.

[0263] In at least one embodiment of this disclosure, the second driving module and the third driving module can be the same driving module. That is, the first reset control signal and the second reset control signal can be provided by the same driving module, and the first reset control signal and the second reset control signal can be the same control signal, but this is not a limitation. In actual operation, when the requirements for the frame are not high, the second driving module and the third driving module can be set to provide the first reset control signal and the second reset control signal respectively, which can enhance the stability and driving capability of the circuit and improve the flexibility of the circuit driving.

[0264] The display device according to at least one embodiment of this disclosure includes a fourth driving module and a fifth driving module; the fourth driving module is used to provide a scanning signal for the pixel circuit, and the fifth driving module is used to provide a compensation control signal for the pixel circuit;

[0265] The fourth driving module is electrically connected to the fourth frame start terminal. The fourth driving module includes a multi-stage fourth driving circuit, and the fourth driving circuit is electrically connected to the fourth clock signal terminal.

[0266] The fifth driving module is electrically connected to the fifth frame start terminal. The fifth driving module includes a multi-stage fifth driving circuit, and the fifth driving circuit is electrically connected to the fifth clock signal terminal.

[0267] The adjustment module in the adjustment module is used to adjust the fourth frame start signal provided by the fourth frame start terminal and / or the fourth clock signal provided by the fourth clock signal terminal, and adjust the fifth frame start signal provided by the fifth frame start terminal and / or the fifth clock signal provided by the fifth clock signal terminal, so as to control the frequency of the scanning signal to be greater than or equal to the frequency of the compensation control signal.

[0268] As shown in Figure 10, the display device according to at least one embodiment of the present disclosure includes a fourth driving module 64 and a fifth driving module 65; the pixel circuit 60 is electrically connected to the scanning end GL and the compensation control end S1 respectively;

[0269] The fourth drive module 64 is electrically connected to the scanning end GL and is used to provide scanning signals to the scanning end GL.

[0270] The fifth drive module 65 is electrically connected to the compensation control terminal S1 and is used to provide compensation control signals to the compensation control terminal S1.

[0271] The fourth driving module 64 is electrically connected to the fourth frame start terminal STV4. The fourth driving module 64 includes a multi-stage fourth driving circuit, and the fourth driving circuit is electrically connected to the fourth clock signal terminal CLK4.

[0272] The fifth driving module 65 is electrically connected to the fifth frame start terminal STV5. The fifth driving module 65 includes a multi-stage fifth driving circuit, and the fifth driving circuit is electrically connected to the fifth clock signal terminal CLK5.

[0273] The adjustment module 11 in the adjustment module 51 is electrically connected to the fourth frame start terminal STV4, the fourth clock signal terminal CLK4, the fifth frame start terminal STV5, and the fifth clock signal terminal CLK5, respectively. It is used to adjust the fourth frame start signal provided by the fourth frame start terminal STV4 and / or the fourth clock signal provided by the fourth clock signal terminal CLK4, and adjust the fifth frame start signal provided by the fifth frame start terminal STV5 and / or the fifth clock signal provided by the fifth clock signal terminal CLK5, so as to control the frequency of the scanning signal to be greater than or equal to the frequency of the compensation control signal.

[0274] In at least one embodiment of this disclosure, in the pixel circuit, the data voltage is written to the second pole of the driving transistor by the scanning signal provided by the scanning terminal GL, and the gate of the driving transistor is connected to the first pole of the driving transistor by the compensation control signal provided by the compensation control terminal S1.

[0275] In at least one embodiment of this disclosure, the adjustment module is used to control the frequency of the scanning signal to the fifteenth frequency and the frequency of the compensation control signal to the sixteenth frequency at a first refresh rate, and to control the frequency of the scanning signal to the seventeenth frequency and the frequency of the compensation control signal to the eighteenth frequency at a second refresh rate.

[0276] The second refresh rate is greater than the first refresh rate;

[0277] The eighteenth frequency is greater than the sixteenth frequency, the fifteenth frequency is greater than or equal to the sixteenth frequency, and the seventeenth frequency is greater than or equal to the eighteenth frequency.

[0278] As shown in Figure 11A, at the first refresh rate, the frequency of the scanning signal provided by GL is the fifteenth frequency, and the frequency of the compensation control signal provided by S1 is the sixteenth frequency.

[0279] As shown in Figure 11B, at the second refresh rate, the frequency of the scanning signal provided by GL is the seventeenth frequency, and the frequency of the compensation control signal provided by S1 is the eighteenth frequency.

[0280] As shown in Figure 11C, at the fourth refresh rate, the frequency of the scanning signal provided by GL is the nineteenth frequency, and the frequency of the compensation control signal provided by S1 is the twentieth frequency.

[0281] For example, the first refresh rate can be 60Hz, the second refresh rate can be 120Hz, and the fourth refresh rate can be 240Hz.

[0282] In at least one embodiment shown in Figures 11A-11C, the second refresh rate is greater than the first refresh rate, and the fourth refresh rate is greater than the second refresh rate;

[0283] The eighteenth frequency is greater than the sixteenth frequency, and the twentieth frequency is greater than the eighteenth frequency.

[0284] The fifteenth frequency is equal to the sixteenth frequency, the seventeenth frequency is equal to the eighteenth frequency, and the nineteenth frequency is equal to the twentieth frequency.

[0285] In Figure 11A, the time of the first frame is labeled F1; in Figure 11B, the time of the first frame is labeled F1 and the time of the second frame is labeled F2; in Figure 11C, the time of the first frame is labeled F1, the time of the second frame is labeled F2, the time of the third frame is labeled F3 and the time of the fourth frame is labeled F4.

[0286] As shown in Figures 11A-11C, the effective data writing voltage is applied once within one frame. When operating at high frequency, the frequency of the scanning signal is synchronously increased, and when operating at low frequency, the frequency of the scanning signal is synchronously decreased, which can achieve more delicate control of the image. Correspondingly, the conduction frequency of the compensation transistor can change synchronously with the data writing frequency.

[0287] In practical implementation, when displaying at low frequencies, such as when the refresh rate is 60Hz, the conduction frequency of S1 can be the same as when the refresh rate is 120Hz.

[0288] As shown in Figure 12A, at the first refresh rate, the frequency of the scanning signal provided by GL is the fifteenth frequency, and the frequency of the compensation control signal provided by S1 is the sixteenth frequency.

[0289] As shown in Figure 12B, at the second refresh rate, the frequency of the scanning signal provided by GL is the seventeenth frequency, and the frequency of the compensation control signal provided by S1 is the eighteenth frequency.

[0290] As shown in Figure 12C, at the fourth refresh rate, the frequency of the scanning signal provided by GL is the nineteenth frequency, and the frequency of the compensation control signal provided by S1 is the twentieth frequency.

[0291] For example, the first refresh rate can be 60Hz, the second refresh rate can be 120Hz, and the fourth refresh rate can be 240Hz.

[0292] In at least one embodiment shown in Figures 12A-12C, the second refresh rate is greater than the first refresh rate, and the fourth refresh rate is greater than the second refresh rate;

[0293] The eighteenth frequency is greater than the sixteenth frequency, and the twentieth frequency is greater than the eighteenth frequency.

[0294] The fifteenth frequency is greater than the sixteenth frequency, the seventeenth frequency is greater than the eighteenth frequency, and the nineteenth frequency is greater than the twentieth frequency.

[0295] In Figure 12A, the time marked F1 is the first frame time; in Figure 12B, the time marked F1 is the first frame time, and the time marked F2 is the second frame time; in Figure 12C, the time marked F1 is the first frame time, the time marked F2 is the second frame time, the time marked F3 is the third frame time, and the time marked F4 is the fourth frame time.

[0296] As shown in Figures 12A-12C, the effective data writing voltage is written twice within one frame, and the frequency of the scan signal can be greater than the frequency of the compensation control signal.

[0297] In at least one embodiment of this disclosure, the pixel circuit includes a light-emitting element, a driving transistor, a first light-emitting control circuit, and a first reset circuit; the first light-emitting control circuit is electrically connected to a light-emitting control terminal, the first electrode of the driving transistor, and the first electrode of the light-emitting element; the first reset circuit is electrically connected to a first reset control terminal, a first initial voltage terminal, and the first electrode of the light-emitting element; the second electrode of the light-emitting element is electrically connected to the first voltage terminal; the display cycle of the pixel circuit includes a stop-light-emitting phase; the stop-light-emitting phase includes at least one first reset phase;

[0298] The first driving module is used to provide the first reset control signal to the first reset control terminal, and the second driving module is used to provide the light emission control signal to the light emission control terminal, so that in the stop light emission phase, the first light emission control circuit, under the control of the light emission control signal, controls the first electrode of the driving transistor to disconnect from the first electrode of the light emission element. In the first reset phase, under the control of the first reset control signal, the first reset circuit writes the first initial voltage provided by the first initial voltage terminal into the first electrode of the light emission element to clear the residual charge on the first electrode of the light emission element.

[0299] Optionally, the first electrode of the light-emitting element can be an anode, and the second electrode of the light-emitting element can be a cathode.

[0300] As shown in Figure 13, at least one embodiment of the pixel circuit includes a light-emitting element E1, a driving transistor M0, a first light-emitting control circuit 131, and a first reset circuit 132.

[0301] The first light-emitting control circuit 131 is electrically connected to the light-emitting control terminal EM, the first electrode of the driving transistor M0 and the first electrode of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the first electrode of the driving transistor M0 and the first electrode of the light-emitting element E1 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0302] The first reset circuit 132 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first pole of the light-emitting element E1, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal I1 into the first pole of the light-emitting element E1 under the control of the first reset control signal provided by the first reset control terminal RST1.

[0303] The second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0304] In Figure 13, the gate of M0 is electrically connected to the first display node P1, the second terminal of M0 is electrically connected to the second display node P2, and the first terminal of M0 is electrically connected to the third display node P3.

[0305] Optionally, the first voltage terminal can be a low voltage terminal, and the light-emitting element E1 can be an organic light-emitting diode.

[0306] In at least one embodiment of this disclosure, the pixel circuit further includes a second reset circuit; the second reset circuit is electrically connected to a second reset control terminal, a second initial voltage terminal, and the second electrode of the driving transistor; the display device includes a third driving module; the display cycle of the pixel circuit includes a stop-light-emitting phase; the stop-light-emitting phase includes at least one second reset phase;

[0307] The third driving module is used to provide the second reset control signal to the second reset control terminal, so that during the second reset phase, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the second pole of the driving transistor, thereby improving the hysteresis phenomenon of the driving transistor.

[0308] As shown in FIG14, based on at least one embodiment of the pixel circuit shown in FIG13, the pixel circuit further includes a second reset circuit 133;

[0309] The second reset circuit 133 is electrically connected to the second reset control terminal RST2, the second initial voltage terminal I2, and the second pole of the driving transistor M0, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal I2 into the second pole of the driving transistor M0 under the control of the second reset control signal provided by the second reset control terminal RST2.

[0310] In at least one embodiment of this disclosure, the pixel circuit further includes a data writing circuit; the data writing circuit is electrically connected to the scanning terminal, the data line, and the second electrode of the driving transistor; the display cycle of the pixel circuit includes a stop-light-emitting phase; the first stop-light-emitting phase in the display cycle includes at least one writing phase;

[0311] The fourth driving module is used to provide a first scanning signal to the scanning end, so that during the writing stage, the data writing circuit, under the control of the first scanning signal, writes the data voltage provided by the data line to the second terminal of the driving transistor to perform data voltage writing.

[0312] The pixel circuit further includes a compensation control circuit; the compensation control circuit is electrically connected to the compensation control terminal, the gate of the driving transistor, and the first electrode of the driving transistor; the first stop-light-emitting stage in the display cycle includes a compensation stage;

[0313] The fifth driving module is used to provide a second scanning signal to the compensation control terminal, so that during the compensation stage, the compensation control circuit controls the gate of the driving transistor to connect with the first terminal of the driving transistor under the control of the second scanning signal, so as to perform threshold voltage compensation.

[0314] In at least one embodiment of this disclosure, at least one light-stopping phase in the display cycle, in addition to the first light-stopping phase, also includes a conduction phase;

[0315] The fifth driving module is used to provide a second scanning signal to the compensation control terminal, so that during the conduction phase, the compensation control circuit controls the gate of the driving transistor to be connected to the first pole of the driving transistor under the control of the second scanning signal. That is, during low-frequency display, the conduction frequency of S1 can be the same as that of S1 during high-frequency display.

[0316] As shown in Figure 15, at the first refresh frequency, the first frame time F1 may include a first stop-light-emitting stage ST1, a second stop-light-emitting stage ST2, a third stop-light-emitting stage ST3, and a fourth stop-light-emitting stage ST4; ST1 includes a compensation stage SC, and ST3 includes a conduction stage SD;

[0317] During the compensation phase SC and the conduction phase SD, S1 provides a high voltage signal to connect the gate of the driving transistor with the first pole of the driving transistor.

[0318] As shown in Figure 16, based on at least one embodiment of the pixel circuit shown in Figure 14, the pixel circuit further includes a data writing circuit 134 and a compensation control circuit 135.

[0319] The data writing circuit 134 is electrically connected to the scanning end GL, the data line DL and the second pole of the driving transistor M0, respectively, and is used to write the data voltage provided by the data line DL into the second pole of the driving transistor M0 under the control of the scanning signal provided by the scanning end;

[0320] The compensation control circuit 135 is electrically connected to the compensation control terminal S1, the gate of the driving transistor M0, and the first electrode of the driving transistor M0, respectively, and is used to control the connection or disconnection between the gate of the driving transistor M0 and the first electrode of the driving transistor M0 under the control of the compensation control signal provided by the compensation control terminal S1.

[0321] As shown in Figure 17, based on at least one embodiment of the pixel circuit shown in Figure 16, the pixel circuit may further include a second light-emitting control circuit 136, a third reset circuit 137, and an energy storage circuit 138.

[0322] The second light-emitting control circuit 136 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD, and the second electrode of the driving transistor M0, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second electrode of the driving transistor M0 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0323] The third reset circuit 137 is electrically connected to the third reset control terminal RST3, the third initial voltage terminal I3 and the gate of the driving transistor M0, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal I3 into the gate of the driving transistor M0 under the control of the third reset control signal provided by the third reset control terminal RST3.

[0324] The energy storage circuit 138 is electrically connected to the gate of the driving transistor M0 to maintain the potential of the gate of M0.

[0325] As shown in Figure 18, based on at least one embodiment of the pixel circuit shown in Figure 17, the light-emitting element is an organic light-emitting diode O1; the first reset circuit includes a first transistor M1, the first light-emitting control circuit includes a second transistor M2, the second reset circuit includes a third transistor M3, the data writing circuit includes a fourth transistor M4, the compensation control circuit includes a fifth transistor M5, the first light-emitting control circuit includes a sixth transistor M6, the third reset circuit includes a seventh transistor M7, and the energy storage circuit includes a storage capacitor Cst.

[0326] The gate of M0 is electrically connected to the first display node P1, the source of M0 is electrically connected to the second display node P2, the drain of M0 is electrically connected to the third display node P3, the first electrode of M0 is the drain of M0, and the second electrode of M0 is the source of M0.

[0327] The gate of M1 is electrically connected to the first reset control terminal RST1, the source of M1 is electrically connected to the first initial voltage terminal I1, the drain of M1 is electrically connected to the anode of O1; the anode of O1 is electrically connected to the fourth display node P4; and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0328] The gate of M2 is electrically connected to the light-emitting control terminal EM, the source of M2 is electrically connected to P3, and the drain of M2 is electrically connected to the anode of O1.

[0329] The gate of M3 is electrically connected to the second reset control terminal RST2, the source of M3 is electrically connected to the second initial voltage terminal I2, and the drain of M3 is electrically connected to P2.

[0330] The gate of M4 is electrically connected to the scan terminal GL, the source of M4 is electrically connected to the data line DL, and the drain of M4 is electrically connected to P2.

[0331] The gate of M5 is electrically connected to the compensation control terminal S1, the source of M5 is electrically connected to P1, and the drain of M5 is electrically connected to P3.

[0332] The gate of M6 is electrically connected to the light-emitting control terminal EM, the source of M6 is electrically connected to the power supply voltage terminal VDD, and the drain of M6 is electrically connected to P2.

[0333] The gate of M7 is electrically connected to the third reset control terminal RST3, the source of M7 is electrically connected to the third initial voltage terminal I3, and the drain of M7 is electrically connected to P1.

[0334] The first terminal of Cst is electrically connected to P1, and the second terminal of Cst is electrically connected to VDD.

[0335] In at least one embodiment shown in Figure 18, M5 and M7 are n-type transistors, and M0, M1, M2, M3, M4 and M6 are p-type transistors;

[0336] The effective pulses of the compensation control signal provided by S1 and the third reset control signal provided by RST3 are high-voltage pulses. The effective pulses of the first reset control signal provided by RST1, the second reset control signal provided by RST2, the scan signal provided by GL, and the light emission control signal provided by the light emission control terminal EM are low-voltage pulses.

[0337] In at least one embodiment of this disclosure, as shown in FIG19, the driving circuit includes a first node control circuit 191, a second node control circuit 192, a third node control circuit 193, a first energy storage circuit 194, and an output circuit 195.

[0338] The first node control circuit 191 is electrically connected to the first node N1, the cascade input terminal J1, the second node N2, the second voltage terminal V2, the first control clock signal terminal CKC1, and the second control clock signal terminal CKC2, respectively. It is used to write the cascade input signal provided by the cascade input terminal J1 into the first node under the control of the first control clock signal provided by the first control clock signal terminal CKC1, and to write the second voltage signal provided by the second voltage terminal V2 into the first node N1 under the control of the potential of the second node N2 and the second control clock signal provided by the second control clock signal terminal CKC2.

[0339] The second node control circuit 192 is electrically connected to the third control clock signal terminal CKC3, the third voltage terminal V3, the first node N1 and the second node N2 respectively. Under the control of the third control clock signal provided by the third control clock signal terminal CKC3, the third voltage signal provided by the third voltage terminal V3 is written into the second node N2. Under the control of the potential of the first node N1, the third control clock signal is written into the second node N2.

[0340] The third node control circuit 193 is electrically connected to the third voltage terminal V3, the first node N1 and the third node N3 respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the third voltage signal provided by the third voltage terminal V3.

[0341] The first energy storage circuit 194 is electrically connected to the second node N2, the third node N3 and the drive signal output terminal OT, respectively, to maintain the potential of the second node N2 and control the potential of the third node N3 according to the drive signal provided by the drive signal output terminal OT.

[0342] The output circuit 195 is electrically connected to the second node N2, the third node N3, the second voltage terminal V2, the output clock signal terminal CKO, and the drive signal output terminal OT, respectively. It is used to control the connection or disconnection between the drive signal output terminal OT and the second voltage terminal V2 under the control of the potential of the second node N2, and to control the connection or disconnection between the drive signal output terminal OT and the output clock signal terminal CKO under the control of the potential of the third node N3.

[0343] The clock signal terminal may include at least one of the first control clock signal terminal CKC1, the second control clock signal terminal CKC2, the third control clock signal terminal CKC3, and the output clock signal terminal CKO.

[0344] Optionally, the second voltage terminal can be a high voltage terminal, and the third voltage terminal can be a low voltage terminal.

[0345] In at least one embodiment of the driving circuit shown in Figure 19, the first control clock signal terminal CKC1 can be the first clock signal terminal CK1, the second control clock signal terminal CKC2 can be the third clock signal terminal CK3, the third control clock signal terminal CKC3 can be the second clock signal terminal CK2, and the output clock signal terminal CKO can be the third clock signal terminal CK3.

[0346] As shown in Figure 20, based on at least one embodiment of the driving circuit shown in Figure 19, the first node control circuit 191 includes a first generating transistor T1, a second generating transistor T2 and a third generating transistor T3, the second node control circuit includes a fourth generating transistor T4 and a fifth generating transistor T5, the third node control circuit includes a sixth generating transistor T6, the first energy storage circuit includes a first capacitor C1 and a second capacitor C2, and the output circuit includes a seventh generating transistor T7 and an eighth generating transistor T8.

[0347] The gate of T1 is electrically connected to CK1, the source of T1 is electrically connected to the cascade input terminal J1, and the drain of T1 is electrically connected to the first node N1.

[0348] The gate of T2 is electrically connected to the second node N2, the source of T2 is electrically connected to the high voltage terminal VGH, and the drain of T2 is electrically connected to the source of T3.

[0349] The gate of T3 is electrically connected to CK3, and the drain of T3 is electrically connected to N1;

[0350] The gate of T4 is electrically connected to CK2, the source of T4 is electrically connected to the low-level terminal VGL, and the drain of T4 is electrically connected to N2.

[0351] The gate of T5 is electrically connected to N1, the source of T5 is electrically connected to CK2, and the drain of T5 is electrically connected to N2.

[0352] The gate of T6 is electrically connected to VGL, the source of T6 is electrically connected to N1, and the drain of T6 is electrically connected to the third node N3.

[0353] The first terminal of C1 is electrically connected to N2, and the second terminal of C1 is electrically connected to VGH; the first terminal of C2 is electrically connected to N3, and the second terminal of C2 is electrically connected to CK3.

[0354] The gate of T7 is electrically connected to N2, the source of T7 is electrically connected to VGH, and the drain of T7 is electrically connected to the drive signal output terminal OT.

[0355] The gate of T8 is electrically connected to N3, the source of T8 is electrically connected to CK3, and the drain of T8 is electrically connected to the drive signal output terminal OT.

[0356] In at least one embodiment shown in FIG20, all transistors may be p-type transistors.

[0357] In at least one embodiment of this disclosure, the source of T8 can be electrically connected to the low-level terminal, that is, the driving circuit is not electrically connected to the output clock signal terminal. In this case, the frequency of the driving signal can be adjusted by adjusting the frequency and pulse width of the control clock signal provided by the control clock signal terminal.

[0358] When the driving module includes a multi-stage driving circuit as shown in at least one embodiment of FIG20, the cascaded input terminal J1 of the first-stage driving circuit included in the driving module can be electrically connected to the frame start terminal to receive the frame start signal from the frame start terminal; the clock signal terminal electrically connected to the adjustment module can include a third clock signal terminal CK3; further, the clock signal terminal electrically connected to the adjustment module can also include at least one of the first clock signal terminal CK1 and the second clock signal terminal CK2.

[0359] In at least one embodiment of this disclosure, as shown in FIG21, the driving circuit includes a first node control circuit 191, a second node control circuit 192, a third node control circuit 183, a first energy storage circuit 194, and an output circuit 195.

[0360] The first node control circuit 191 is electrically connected to the first node N1, the cascade input terminal J1, the second node N2, the second voltage terminal V2, the first control clock signal terminal CKC1, and the second control clock signal terminal CKC2, respectively. It is used to write the cascade input signal provided by the cascade input terminal J1 into the first node N1 under the control of the first control clock signal provided by the first control clock signal terminal CKC1, and to write the second voltage signal provided by the second voltage terminal V2 into the first node N1 under the control of the potential of the second node N2 and the second control clock signal provided by the second control clock signal terminal CKC2.

[0361] The second node control circuit 192 is electrically connected to the first control clock signal terminal CKC1, the third voltage terminal V3, the first node N1 and the second node N2 respectively. Under the control of the first control clock signal provided by the first control clock signal terminal CKC1, the third voltage signal provided by the third voltage terminal V3 is written into the second node N2. Under the control of the potential of the first node N1, the first control clock signal is written into the second node N2.

[0362] The third node control circuit 193 is electrically connected to the third voltage terminal V3, the first node N1 and the third node N3 respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the third voltage signal provided by the third voltage terminal V3.

[0363] The first energy storage circuit 194 is electrically connected to the second node N2, the third node N3 and the drive signal output terminal OT, respectively, to maintain the potential of the second node N2 and control the potential of the third node N3 according to the drive signal provided by the drive signal output terminal OT.

[0364] The output circuit 195 is electrically connected to the second node N2, the third node N3, the second voltage terminal V2, the output clock signal terminal CKO, and the drive signal output terminal OT, respectively. It is used to control the connection or disconnection between the drive signal output terminal OT and the second voltage terminal V2 under the control of the potential of the second node N2, and to control the connection or disconnection between the drive signal output terminal OT and the output clock signal terminal CKO under the control of the potential of the third node N3.

[0365] The clock signal terminal includes at least one of the first control clock signal terminal CKC1, the second control clock signal terminal CKC2, and the output clock signal terminal CKO.

[0366] In at least one embodiment shown in Figure 21, CKC1 can be the first clock signal terminal CK1, CKC2 can be the second clock signal terminal CK2, and CKO can be the second clock signal terminal.

[0367] As shown in Figure 22, based on at least one embodiment of the driving circuit shown in Figure 21, the first node control circuit 191 includes a first generating transistor T1, a second generating transistor T2 and a third generating transistor T3, the second node control circuit includes a fourth generating transistor T4 and a fifth generating transistor T5, the third node control circuit includes a sixth generating transistor T6, the first energy storage circuit includes a first capacitor C1 and a second capacitor C2, and the output circuit includes a seventh generating transistor T7 and an eighth generating transistor T8.

[0368] The gate of T1 is electrically connected to CK1, the source of T1 is electrically connected to the cascade input terminal J1, and the drain of T1 is electrically connected to N1.

[0369] The gate of T2 is electrically connected to N2, the source of T2 is electrically connected to the high voltage terminal VGH, and the drain of T2 is electrically connected to the source of T3.

[0370] The gate of T3 is electrically connected to CK2, and the drain of T3 is electrically connected to N1;

[0371] The gate of T4 is electrically connected to CK1, the source of T4 is electrically connected to the low-level terminal VGL, and the drain of T4 is electrically connected to N2.

[0372] The gate of T5 is electrically connected to N1, the source of T5 is electrically connected to CK1, and the drain of T5 is electrically connected to N2.

[0373] The gate of T6 is electrically connected to VGL, the source of T6 is electrically connected to N1, and the drain of T6 is electrically connected to N3.

[0374] The gate of T7 is electrically connected to N2, the source of T7 is electrically connected to VGH, and the drain of T7 is electrically connected to the drive signal output terminal OT.

[0375] The gate of T8 is electrically connected to N3, the source of T8 is electrically connected to CK2, and the drain of T8 is electrically connected to the drive signal output terminal OT.

[0376] The first terminal of C1 is electrically connected to N2, and the second terminal of C1 is electrically connected to VGH.

[0377] The first terminal of C2 is electrically connected to N3, and the second terminal of C2 is electrically connected to OT.

[0378] In at least one embodiment shown in Figure 22, all transistors are p-type transistors.

[0379] When the driving module includes a multi-stage driving circuit as shown in at least one embodiment of FIG22, the cascaded input terminal J1 of the first-stage driving circuit included in the driving module can be electrically connected to the frame start terminal to receive the frame start signal from the frame start terminal; the clock signal terminal electrically connected to the adjustment module can include a second clock signal terminal CK2; further, the clock signal terminal electrically connected to the adjustment module can also include a first clock signal terminal CK1.

[0380] In at least one embodiment of this disclosure, as shown in FIG23, the driving circuit includes a carry signal output circuit 230, a selection control circuit 231, a first on / off control circuit 232, a second on / off control circuit 233, a first energy storage circuit 194, a second energy storage circuit 196, and an output circuit 195.

[0381] The carry signal output circuit 230 is electrically connected to the cascade input terminal JI, the control clock signal terminal CKC, the second node N2, the third node N3, the output clock signal terminal CKO, and the carry signal output terminal CR, respectively. It is used to control the potential of the second node N2 and the potential of the third node N3 under the control of the cascade input signal provided by the cascade input terminal JI and the control clock signal provided by the control clock signal terminal CKC. Under the control of the potential of the second node N2 and the potential of the third node N3, the carry signal is provided through the carry signal output terminal CR according to the output clock signal provided by the output clock signal terminal CKO.

[0382] The selection control circuit 231 is electrically connected to the first control terminal SCA, the second control terminal SCB, the selection control terminal MS and the fourth node N4 respectively, and is used to write the selection control signal provided by the selection control terminal MS into the fourth node N4 under the control of the first control signal provided by the first control terminal SCA and the second control signal provided by the second control terminal SCB.

[0383] The first on / off control circuit 232 is electrically connected to the fourth node N4, the second node N2 and the first output control node NS1 respectively, and is used to control the connection or disconnection between the second node N2 and the first output control node NS1 under the control of the potential of the fourth node N4.

[0384] The second on / off control circuit 233 is electrically connected to the fourth node N4, the third node N3 and the second output control node NS2 respectively, and is used to control the connection or disconnection between the third node N3 and the second output control node NS2 under the control of the potential of the fourth node N4;

[0385] The first energy storage circuit 194 is electrically connected to the first output control node NS1, the second output control node NS2 and the drive signal output terminal OT, respectively, to maintain the potential of the first output control node NS1 and control the potential of the second output control node NS2 according to the drive signal provided by the drive signal output terminal OT.

[0386] The second energy storage circuit 196 is electrically connected to the fourth node N4 and the second output control node NS2 respectively, and is used to control the potential of the second output control node NS2 according to the potential of the fourth node N4;

[0387] The output circuit 195 is electrically connected to the first output control node NS1, the second output control node NS2, the second voltage terminal V2, the drive signal output terminal OT, and the output clock signal terminal CKO, respectively. It is used to control the connection or disconnection between the drive signal output terminal OT and the second voltage terminal V2 under the control of the potential of the first output control node NS1, and to control the connection or disconnection between the drive signal output terminal OT and the output clock signal terminal CKO under the control of the potential of the second output control node NS2.

[0388] The clock signal terminal includes at least one of the control clock signal terminal CKC and the output clock signal terminal CKO.

[0389] In at least one embodiment shown in Figure 23, the control clock signal terminal may include a fourth clock signal terminal CK4, a fifth clock signal terminal CK5, and a sixth clock signal terminal CK6; the output clock signal terminal may be the sixth clock signal terminal CK6.

[0390] The clock signal terminal may include at least one of CK4, CK5, and CK6.

[0391] In at least one embodiment shown in Figure 23, CR can be the nth level carry signal output terminal, JI can be electrically connected to the (n-2)th level carry signal output terminal, SCA can be the nth level first scan terminal, SCB can be the (n-2)th level carry signal output terminal, and the third control terminal ET is the nth level light emission control terminal; n is a positive integer.

[0392] When at least one embodiment of the drive circuit shown in Figure 23 is in operation, the selection control circuit 231 writes the selection control signal into the fourth node N4 under the control of the first control signal and the second control signal. At this time, when the selection control signal is a low voltage signal, it is in a refresh state, and when the selection control signal is a high voltage signal, it is in a hold state. By controlling the voltage value of the selection control signal, partitioned frequency conversion can be realized.

[0393] As shown in Figure 24, based on at least one embodiment of the driving circuit shown in Figure 23,

[0394] The carry signal output circuit may include a first generating transistor T1, a second generating transistor T2, a third generating transistor T3, a fourth generating transistor T4, a fifth generating transistor T5, a sixth generating transistor T6, a first capacitor C1, a second capacitor C2, a seventh generating transistor T7, and an eighth generating transistor T8.

[0395] The gate of T1 is electrically connected to CK4, the source of T1 is electrically connected to the cascade input terminal J1, and the drain of T1 is electrically connected to the first node N1.

[0396] The gate of T2 is electrically connected to the second node N2, the source of T2 is electrically connected to the high voltage terminal VGH, and the drain of T2 is electrically connected to the source of T3.

[0397] The gate of T3 is electrically connected to CK6, and the drain of T3 is electrically connected to N1;

[0398] The gate of T4 is electrically connected to CK5, the source of T4 is electrically connected to the low-level terminal VGL, and the drain of T4 is electrically connected to N2.

[0399] The gate of T5 is electrically connected to N1, the source of T5 is electrically connected to CK5, and the drain of T5 is electrically connected to N2.

[0400] The gate of T6 is electrically connected to VGL, the source of T6 is electrically connected to N1, and the drain of T6 is electrically connected to the third node N3.

[0401] The first terminal of C1 is electrically connected to N2, and the second terminal of C1 is electrically connected to VGH; the first terminal of C2 is electrically connected to N3, and the second terminal of C2 is electrically connected to CK6.

[0402] The gate of T7 is electrically connected to N2, the source of T7 is electrically connected to VGH, and the drain of T7 is electrically connected to the carry signal output terminal CR.

[0403] The gate of T8 is electrically connected to N3, the source of T8 is electrically connected to CK6, and the drain of T8 is electrically connected to the carry signal output terminal CR.

[0404] The selection control circuit includes a ninth generating transistor T9, a tenth generating transistor T10, and an eleventh generating transistor T11; the first on / off control circuit includes a twelfth generating transistor T12; the second on / off control circuit includes a thirteenth transistor T13; the first energy storage circuit includes a third capacitor C3 and a fourth capacitor C4; the second energy storage circuit includes a fifth capacitor C5; and the output circuit includes a fourteenth transistor T14 and a fifteenth transistor T15.

[0405] The gate of T9 is electrically connected to SCA, the source of T9 is electrically connected to the drain of T10, and the drain of T9 is electrically connected to N4.

[0406] The gate of T10 is electrically connected to SCB, and the source of T10 is electrically connected to MS.

[0407] The gate of T11 is electrically connected to the third control terminal ET, the source of T11 is electrically connected to the low voltage terminal VGL, and the drain of T11 is electrically connected to N4.

[0408] The gate of T12 is electrically connected to N4, the source of T12 is electrically connected to N2, and the drain of T12 is electrically connected to NS1.

[0409] The gate of T13 is electrically connected to N4, the source of T13 is electrically connected to N3, and the drain of T13 is electrically connected to NS2.

[0410] The first terminal of C3 is electrically connected to NS1, and the second terminal of C3 is electrically connected to VGH.

[0411] The first terminal of C4 is electrically connected to NS2, and the second terminal of C3 is electrically connected to OT.

[0412] The first terminal of C5 is electrically connected to N4, and the second terminal of C5 is electrically connected to NS2.

[0413] The gate of T14 is electrically connected to NS1, the source of T14 is electrically connected to VGH, and the drain of T14 is electrically connected to the drive signal output terminal OT.

[0414] The gate of T15 is electrically connected to NS2, the source of T15 is electrically connected to CK6, and the drain of T15 is electrically connected to OT.

[0415] In at least one embodiment shown in Figure 24, all transistors are p-type transistors.

[0416] In at least one embodiment shown in Figure 24, CR can be the nth level carry signal output terminal, JI can be electrically connected to the (n-2)th level carry signal output terminal, SCA can be the nth level first scan terminal, SCB can be the (n-2)th level carry signal output terminal, and ET can be the nth level light emission control terminal.

[0417] In at least one embodiment of the driving circuit shown in Figure 24, OT can be used to provide a low-level active nth-stage second scan signal to the pixel circuit, the nth-stage first scan terminal can be used to provide a high-level active nth-stage first scan signal to the pixel circuit, and the nth-stage light emission control terminal can be used to provide an nth-stage light emission control signal to the pixel circuit.

[0418] In at least one embodiment of the drive circuit shown in Figure 24, when both the potentials of SCA and SCB are low, T9 and T10 are turned on. At this time, when MS provides a low voltage signal, the potential of N4 is low, N2 is connected to NS1, and N3 is connected to NS2, and the circuit is in a refresh state. When MS provides a high voltage signal, the potential of N4 is high, N2 is disconnected from NS1, and N3 is disconnected from NS2, and the circuit is in a hold state.

[0419] As shown in Figure 25, in at least one embodiment shown in Figure 24, the driving circuit can be the nth stage driving circuit, the cascaded input terminal is electrically connected to the (n-2)th carry signal output terminal CR(n-2), the carry signal output terminal is the nth stage carry signal output terminal CR(n), the first control terminal can be the nth stage first scan terminal NG(n), the second control terminal can be the (n-2)th stage carry signal output terminal CR(n-2), the third control terminal can be the nth stage light emission control terminal EM(n), and the driving signal output terminal is the nth stage driving signal output terminal OT(n), where n is a positive integer.

[0420] As shown in Figure 26, when at least one embodiment of the driving circuit shown in Figure 25 is in operation, the display cycle may include a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, and a sixth stage t6 set sequentially.

[0421] In the first stage t1, CK4 provides a low voltage signal, T1 is turned on, CR(n-2) provides a low voltage signal, and N1 is at a low voltage. When T6 is turned on, N3 is at a low voltage. When T8 is turned on, CK6 provides a high voltage signal, and CR(n) provides a high voltage signal. When T5 is turned on, CK2 provides a high voltage signal, and N2 is at a high voltage.

[0422] In the first stage t1, CR(n-2) provides a low voltage signal, NG(n) provides a low voltage signal, T9 and T10 are turned on, and MS and N4 are connected; MS provides a low voltage signal, N4 has a low voltage potential, T12 and T13 are turned on to enable display refresh; NS2 has a low voltage signal, and OT(n) provides a high voltage signal.

[0423] In the second stage t2, CK4 provides a high voltage signal, T1 is closed, CK5 provides a low voltage signal, T4 is open, N2 is connected to VGL, the potential of N2 is low voltage, T7 is open, CR(n) provides a high voltage signal; T12 is open, the potential of NS1 is low voltage, T14 is open, OT(n) provides a high voltage signal;

[0424] In the third stage t3, CK5 provides a high voltage signal, T4 is off, N1 has a low voltage potential, T5 is on, and the potential of N2 is pulled high; CK6 provides a low voltage signal, the potentials of N1 and N3 are low, T8 is on, CK6 provides a low voltage signal, CR(n) provides a low voltage signal, T13 is on, the potential of NS2 is low, T12 is on, the potential of NS1 is high, T14 is off, T15 is on, and OT(n) outputs a low voltage signal;

[0425] In the fourth stage t4, CK6 provides a high voltage signal, NS2 is at a low voltage, T15 is turned on, and OT(n) outputs a high voltage signal.

[0426] In the fifth stage t5, CK4 provides a low voltage signal, T1 is turned on, CR(n-2) provides a high voltage signal, N1 is at a high voltage, T6 is turned on, N3 is at a high voltage, and T8 is turned off; CK5 provides a high voltage signal, T4 is turned off, N2 is maintained at a high voltage, T12 is turned on, NS1 is at a high voltage, and T14 is turned off; T13 is turned on, NS2 is at a high voltage, T15 is turned off, and OT(n) maintains a high voltage output signal.

[0427] In the sixth stage t6, CK4 provides a high voltage signal, T1 is closed, CK5 provides a low voltage signal, T4 is open, N2 is connected to VGL, the potential of N2 is low voltage, T7 is open, CR(n) outputs a high voltage signal; T12 is open, the potential of NS1 is low voltage, T14 is open, OT(n) outputs a high voltage signal.

[0428] In Figure 26, CR(1) is the first-stage carry signal output terminal, and CR(2) is the second-stage carry signal output terminal.

[0429] In at least one embodiment of the drive circuit shown in Figure 25, during operation, in the first stage t1, when the MS provides a high voltage signal, the potential of N4 is high, and T12 and T13 are turned off, so that the drive circuit is in the display hold state.

[0430] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. An adjustment module applied to a display device, the display device comprising at least one driving module and a plurality of pixel circuits, the driving module being configured to provide corresponding driving signals to the pixel circuits; the driving module being electrically connected to a frame start end and configured to receive a frame start signal from the frame start end; the adjustment module comprising an adjustment module; The adjustment module is electrically connected to the frame start terminal and is used to provide the frame start signal. By adjusting the frequency of the frame start signal, the frequency of the drive signal is adjusted.

2. The adjustment module as described in claim 1, wherein, The drive module includes a multi-stage drive circuit; the drive circuit is electrically connected to the clock signal terminal, and is used to receive the clock signal provided by the clock signal terminal, and provide the drive signal according to the clock signal; The adjustment module is also electrically connected to the clock signal terminal to provide the clock signal and adjust the frequency of the drive signal by adjusting the frequency of the clock signal.

3. The adjustment module as described in claim 2, wherein, The frequency of the clock signal is greater than or equal to the frequency of the frame start signal.

4. The adjustment module as described in claim 2, wherein, The adjustment module is further configured to adjust the pulse width of the drive signal by adjusting at least one of the pulse width of the frame start signal and the pulse width of the clock signal; The pulse width of the frame start signal is the width of the effective pulse of the frame start signal, the pulse width of the output clock signal is the width of the effective pulse of the output clock signal, and the pulse width of the drive signal is the width of the effective pulse of the drive signal.

5. The adjustment module as described in claim 4, wherein, The pulse width of the frame start signal is greater than or equal to the pulse width of the clock signal.

6. The adjustment module as described in claim 2, wherein, At the first refresh rate, the frequency of the frame start signal is a first frequency, and the frequency of the clock signal is a second frequency; at the second refresh rate, the frequency of the frame start signal is a third frequency, and the frequency of the clock signal is a fourth frequency; the second refresh rate is greater than the first refresh rate. The third frequency is greater than or equal to the first frequency, and the fourth frequency is greater than or equal to the second frequency.

7. The adjustment module as described in claim 6, wherein, The second frequency is greater than or equal to the first frequency, and the fourth frequency is greater than or equal to the third frequency.

8. The adjustment module as described in claim 6, wherein, At the third refresh rate, the frequency of the frame start signal is the fifth frequency; The second refresh rate is equal to the third refresh rate, and the fifth frequency is greater than or equal to the third frequency.

9. The adjustment module as described in claim 4, wherein, At the first refresh rate, the pulse width of the frame start signal is the first pulse width, and the pulse width of the clock signal is the second pulse width; at the second refresh rate, the pulse width of the frame start signal is the third pulse width, and the pulse width of the clock signal is the fourth pulse width; the second refresh rate is greater than the first refresh rate. The first pulse width is greater than the third pulse width, and the second pulse width is greater than the fourth pulse width.

10. The adjustment module as described in claim 4, wherein, At the second refresh rate, the pulse width of the frame start signal is the third pulse width; at the third refresh rate, the pulse width of the frame start signal is the fifth pulse width; the second refresh rate is equal to the third refresh rate. The third pulse width is greater than the fifth pulse width; At the second refresh rate, the frequency of the frame start signal is less than the frequency of the frame start signal at the third refresh rate.

11. An adjustment method applied to a display device, the display device comprising at least one driving module and a plurality of pixel circuits, the driving module being configured to provide corresponding driving signals to the pixel circuits; the driving module being electrically connected to a frame start end; the adjustment method comprising: The adjustment module adjusts the frequency of the drive signal by adjusting the frequency of the frame start signal provided by the frame start terminal.

12. A display device comprising at least one driving module and a plurality of pixel circuits, the display device further comprising an adjustment module as described in any one of claims 1 to 10; The driving module is used to provide corresponding driving signals to the pixel circuit; The driving module is electrically connected to the frame start terminal and is used to receive the frame start signal from the frame start terminal.

13. The display device as claimed in claim 12, wherein, It includes a first driving module and a second driving module; the first driving module is used to provide a first reset control signal to the pixel circuit, and the second driving module is used to provide a light emission control signal to the pixel circuit; The first driving module is electrically connected to the first frame start terminal, and the first driving module includes a multi-stage first driving circuit, which is electrically connected to the first clock signal terminal. The second driving module is electrically connected to the start end of the second frame. The second driving module includes a multi-stage second driving circuit, and the second driving circuit is electrically connected to the second clock signal terminal. The adjustment module includes an adjustment module for adjusting the first frame start signal provided by the first frame start terminal and / or the first clock signal provided by the first clock signal terminal, adjusting the second frame start signal provided by the second frame start terminal and / or the second clock signal provided by the second clock signal terminal, and controlling the frequency of the first reset control signal to be greater than or equal to the frequency of the light emission control signal.

14. The display device as claimed in claim 13, wherein, The adjustment module is used to control the frequency of the first reset control signal to be the sixth frequency and the frequency of the light emission control signal to be the seventh frequency at the first refresh rate; to control the frequency of the first reset control signal to be the eighth frequency and the frequency of the light emission control signal to be the ninth frequency at the second refresh rate; and to control the frequency of the first reset control signal to be the tenth frequency and the frequency of the light emission control signal to be the eleventh frequency at the third refresh rate. The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate; The eighth frequency is greater than the sixth frequency, the ninth frequency is greater than the seventh frequency, the tenth frequency is greater than the eleventh frequency; the tenth frequency is greater than the eighth frequency.

15. The display device as claimed in claim 13, wherein, The adjustment module is further configured to control the pulse width of the first reset control signal and the pulse width of the light emission control signal by adjusting the first frame start signal and / or the first clock signal, and adjusting the second frame start signal and / or the second clock signal; The adjustment module is used to control the pulse width of the first reset control signal to be the sixth pulse width and the pulse width of the light emission control signal to be the seventh pulse width at the first refresh rate; to control the pulse width of the first reset control signal to be the eighth pulse width and the pulse width of the light emission control signal to be the ninth pulse width at the second refresh rate; and to control the pulse width of the first reset control signal to be the tenth pulse width and the pulse width of the light emission control signal to be the eleventh pulse width at the third refresh rate. The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate; The sixth pulse width is greater than the eighth pulse width, the seventh pulse width is greater than the ninth pulse width, and the eighth pulse width is greater than the tenth pulse width; The adjustment module is used to control the frequency of the first reset control signal at the second refresh rate to be less than the frequency of the first reset control signal at the third refresh rate.

16. The display device as claimed in claim 12, wherein, It includes a second driving module and a third driving module; the second driving module is used to provide a light emission control signal to the pixel circuit; the third driving module is used to provide a second reset control signal to the pixel circuit; The adjustment module includes an adjustment module for adjusting the second frame start signal provided by the second frame start terminal and / or the second clock signal provided by the second clock signal terminal, and adjusting the third frame start signal provided by the third frame start terminal and / or the third clock signal provided by the third clock signal terminal, thereby controlling the frequency of the second reset control signal to be greater than or equal to the frequency of the light emission control signal.

17. The display device as claimed in claim 16, wherein, The adjustment module is used to control the frequency of the second reset control signal to be the twelfth frequency and the frequency of the light emission control signal to be the seventh frequency at the first refresh rate; to control the frequency of the second reset control signal to be the thirteenth frequency and the frequency of the light emission control signal to be the ninth frequency at the second refresh rate; and to control the frequency of the second reset control signal to be the fourteenth frequency and the frequency of the light emission control signal to be the eleventh frequency at the third refresh rate. The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate; The thirteenth frequency is greater than the twelfth frequency, the ninth frequency is greater than the seventh frequency, the fourteenth frequency is greater than the thirteenth frequency, and the fourteenth frequency is greater than the eleventh frequency.

18. The display device as claimed in claim 16, wherein, The adjustment module is also used to control the pulse width of the second reset control signal and the pulse width of the light emission control signal by adjusting the second frame start signal and / or the second clock signal, and adjusting the third frame start signal and / or the third clock signal; The adjustment module is used to control the pulse width of the second reset control signal to be the twelfth pulse width and the pulse width of the light emission control signal to be the seventh pulse width at the first refresh rate; to control the pulse width of the second reset control signal to be the thirteenth pulse width and the pulse width of the light emission control signal to be the ninth pulse width at the second refresh rate; and to control the pulse width of the second reset control signal to be the fourteenth pulse width and the pulse width of the light emission control signal to be the eleventh pulse width at the third refresh rate. The second refresh rate is greater than the first refresh rate, and the second refresh rate is equal to the third refresh rate; The twelfth pulse width is greater than the thirteenth pulse width, the seventh pulse width is greater than the ninth pulse width, and the thirteenth pulse width is greater than the fourteenth pulse width; The adjustment module is used to control the frequency of the second reset control signal at the second refresh rate to be less than the frequency of the second reset control signal at the third refresh rate.

19. The display device as claimed in claim 12, wherein, It includes a fourth driving module and a fifth driving module; the fourth driving module is used to provide scanning signals to the pixel circuit, and the fifth driving module is used to provide compensation control signals to the pixel circuit; The fourth driving module is electrically connected to the fourth frame start terminal. The fourth driving module includes a multi-stage fourth driving circuit, and the fourth driving circuit is electrically connected to the fourth clock signal terminal. The fifth driving module is electrically connected to the fifth frame start terminal. The fifth driving module includes a multi-stage fifth driving circuit, and the fifth driving circuit is electrically connected to the fifth clock signal terminal. The adjustment module in the adjustment module is used to adjust the fourth frame start signal provided by the fourth frame start terminal and / or the fourth clock signal provided by the fourth clock signal terminal, and adjust the fifth frame start signal provided by the fifth frame start terminal and / or the fifth clock signal provided by the fifth clock signal terminal, so as to control the frequency of the scanning signal to be greater than or equal to the frequency of the compensation control signal.

20. The display device as claimed in claim 19, wherein, The adjustment module is used to control the frequency of the scanning signal to the fifteenth frequency and the frequency of the compensation control signal to the sixteenth frequency at the first refresh rate, and to control the frequency of the scanning signal to the seventeenth frequency and the frequency of the compensation control signal to the eighteenth frequency at the second refresh rate. The second refresh rate is greater than the first refresh rate; The eighteenth frequency is greater than the sixteenth frequency, the fifteenth frequency is greater than or equal to the sixteenth frequency, and the seventeenth frequency is greater than or equal to the eighteenth frequency.

21. The display device as claimed in claim 13, wherein, The pixel circuit includes a light-emitting element, a driving transistor, a first light-emitting control circuit, and a first reset circuit; the first light-emitting control circuit is electrically connected to a light-emitting control terminal, the first electrode of the driving transistor is electrically connected to the first electrode of the light-emitting element, and the first reset circuit is electrically connected to a first reset control terminal, a first initial voltage terminal, and the first electrode of the light-emitting element; the second electrode of the light-emitting element is electrically connected to the first voltage terminal; the display cycle of the pixel circuit includes a stop-light-emitting phase; the stop-light-emitting phase includes at least one first reset phase; The first driving module is used to provide the first reset control signal to the first reset control terminal, and the second driving module is used to provide the light emission control signal to the light emission control terminal, so that in the stop light emission phase, the first light emission control circuit controls the first electrode of the driving transistor to disconnect from the first electrode of the light emission element under the control of the light emission control signal. In the first reset phase, the first reset circuit writes the first initial voltage provided by the first initial voltage terminal to the first electrode of the light emission element under the control of the first reset control signal.

22. The display device as claimed in claim 16, wherein, The pixel circuit further includes a second reset circuit; the second reset circuit is electrically connected to a second reset control terminal, a second initial voltage terminal, and the second electrode of the driving transistor; the display device includes a third driving module; the display cycle of the pixel circuit includes a stop-light-emitting phase; the stop-light-emitting phase includes at least one second reset phase; The third driving module is used to provide the second reset control signal to the second reset control terminal, so that during the second reset phase, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage provided by the second initial voltage terminal into the second terminal of the driving transistor.

23. The display device as claimed in claim 19, wherein, The pixel circuit further includes a data writing circuit; the data writing circuit is electrically connected to the scanning end, the data line and the second electrode of the driving transistor respectively; the display cycle of the pixel circuit includes a stop-light-emitting phase; the first stop-light-emitting phase in the display cycle includes at least one writing phase; The fourth driving module is used to provide a first scanning signal to the scanning end, so that during the writing stage, the data writing circuit, under the control of the first scanning signal, writes the data voltage provided by the data line into the second terminal of the driving transistor. The pixel circuit further includes a compensation control circuit; the compensation control circuit is electrically connected to the compensation control terminal, the gate of the driving transistor, and the first electrode of the driving transistor; the first stop-light-emitting stage in the display cycle includes a compensation stage; The fifth driving module is used to provide a second scanning signal to the compensation control terminal, so that during the compensation stage, the compensation control circuit controls the gate of the driving transistor to be connected to the first terminal of the driving transistor under the control of the second scanning signal.

24. The display device as claimed in claim 23, wherein, In addition to the first light-stopping phase, at least one of the light-stopping phases in the display cycle also includes a conduction phase; The fifth driving module is used to provide a second scanning signal to the compensation control terminal, so that during the conduction phase, the compensation control circuit controls the gate of the driving transistor to connect with the first electrode of the driving transistor under the control of the second scanning signal.

25. The display device according to at least one of claims 12 to 24, wherein, The driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a first energy storage circuit, and an output circuit. The first node control circuit is electrically connected to the first node, the cascade input terminal, the second node, the second voltage terminal, the first control clock signal terminal, and the second control clock signal terminal, respectively. It is used to write the cascade input signal provided by the cascade input terminal into the first node under the control of the first control clock signal provided by the first control clock signal terminal, and to write the second voltage signal provided by the second voltage terminal into the first node under the control of the potential of the second node and the second control clock signal provided by the second control clock signal terminal. The second node control circuit is electrically connected to the third control clock signal terminal, the third voltage terminal, the first node, and the second node, respectively. Under the control of the third control clock signal provided by the third control clock signal terminal, the third voltage signal provided by the third voltage terminal is written into the second node. Under the control of the potential of the first node, the third control clock signal is written into the second node. The third node control circuit is electrically connected to the third voltage terminal, the first node, and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the third voltage signal provided by the third voltage terminal; The first energy storage circuit is electrically connected to the second node, the third node and the drive signal output terminal respectively, and is used to maintain the potential of the second node and control the potential of the third node according to the drive signal provided by the drive signal output terminal. The output circuit is electrically connected to the second node, the third node, the second voltage terminal, the output clock signal terminal, and the drive signal output terminal, respectively. It is used to control the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node, and to control the connection or disconnection between the drive signal output terminal and the output clock signal terminal under the control of the potential of the third node. The clock signal terminal includes at least one of the first control clock signal terminal, the second control clock signal terminal, the third control clock signal terminal, and the output clock signal terminal.

26. The display device according to at least one of claims 12 to 24, wherein, The driving circuit includes a first node control circuit, a second node control circuit, a third node control circuit, a first energy storage circuit, and an output circuit. The first node control circuit is electrically connected to the first node, the cascade input terminal, the second node, the second voltage terminal, the first control clock signal terminal, and the second control clock signal terminal, respectively. It is used to write the cascade input signal provided by the cascade input terminal into the first node under the control of the first control clock signal provided by the first control clock signal terminal, and to write the second voltage signal provided by the second voltage terminal into the first node under the control of the potential of the second node and the second control clock signal provided by the second control clock signal terminal. The second node control circuit is electrically connected to the first control clock signal terminal, the third voltage terminal, the first node, and the second node, respectively. Under the control of the first control clock signal provided by the first control clock signal terminal, the third voltage signal provided by the third voltage terminal is written into the second node. Under the control of the potential of the first node, the first control clock signal is written into the second node. The third node control circuit is electrically connected to the third voltage terminal, the first node, and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the third voltage signal provided by the third voltage terminal; The first energy storage circuit is electrically connected to the second node, the third node and the drive signal output terminal respectively, and is used to maintain the potential of the second node and control the potential of the third node according to the drive signal provided by the drive signal output terminal. The output circuit is electrically connected to the second node, the third node, the second voltage terminal, the output clock signal terminal, and the drive signal output terminal, respectively. It is used to control the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node, and to control the connection or disconnection between the drive signal output terminal and the output clock signal terminal under the control of the potential of the third node. The clock signal terminal includes at least one of the first control clock signal terminal, the second control clock signal terminal, and the output clock signal terminal.

27. The display device according to at least one of claims 12 to 24, wherein, The driving circuit includes a carry signal output circuit, a selection control circuit, a first on / off control circuit, a second on / off control circuit, a first energy storage circuit, a second energy storage circuit, and an output circuit. The carry signal output circuit is electrically connected to the cascade input terminal, the control clock signal terminal, the second node, the third node, the output clock signal terminal, and the carry signal output terminal, respectively. It is used to control the potential of the second node and the potential of the third node under the control of the cascade input signal provided by the cascade input terminal and the control clock signal provided by the control clock signal terminal. Under the control of the potential of the second node and the potential of the third node, the carry signal is provided through the carry signal output terminal according to the output clock signal provided by the output clock signal terminal. The selection control circuit is electrically connected to the first control terminal, the second control terminal, the selection control terminal and the fourth node respectively, and is used to write the selection control signal provided by the selection control terminal into the fourth node under the control of the first control signal provided by the first control terminal and the second control signal provided by the second control terminal; The first on / off control circuit is electrically connected to the fourth node, the second node and the first output control node respectively, and is used to control the connection or disconnection between the second node and the first output control node under the control of the potential of the fourth node; The second on / off control circuit is electrically connected to the fourth node, the third node and the second output control node respectively, and is used to control the connection or disconnection between the third node and the second output control node under the control of the potential of the fourth node; The first energy storage circuit is electrically connected to the first output control node, the second output control node and the drive signal output terminal respectively, and is used to maintain the potential of the first output control node and control the potential of the second output control node according to the drive signal provided by the drive signal output terminal. The second energy storage circuit is electrically connected to the fourth node and the second output control node respectively, and is used to control the potential of the second output control node according to the potential of the fourth node; The output circuit is electrically connected to the first output control node, the second output control node, the second voltage terminal, the drive signal output terminal, and the output clock signal terminal, respectively. It is used to control the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the first output control node, and to control the connection or disconnection between the drive signal output terminal and the output clock signal terminal under the control of the potential of the second output control node. The clock signal terminal includes at least one of the control clock signal terminal and the output clock signal terminal.

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