Display apparatus and driving method

Abstract

A display apparatus (300, 600, 700, 1100, 1200) and a driving method. The display apparatus (300, 600, 700, 1100, 1200) comprises a display panel (310, 610, 710, 1110, 1210); and a first driving circuit (320, 620, 720, 1120, 1220), which is electrically connected to the display panel (310, 610, 710, 1110, 1210), first power supply wiring, and second power supply wiring. The first driving circuit (320, 620, 720, 1120, 1220) comprises a plurality of cascaded first shift registers. The first power supply wiring is electrically connected to odd-numbered first shift registers among the plurality of first shift registers. The second power supply wiring is electrically connected to even-numbered first shift registers among the plurality of first shift registers. The plurality of first shift registers are configured to output a plurality of first scanning signals to the display panel (310, 610, 710, 1110, 1210) on the basis of a first power supply voltage provided by the first power supply wiring and a second power supply voltage provided by the second power supply wiring.

Description

Display device and driving method Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display device and driving method. Background Technology

[0002] Some display products typically use partial refresh technology to reduce data cable loss caused by screen refresh. However, uneven brightness can occur at the junction of two areas refreshed at different refresh rates, thus affecting the display effect.

[0003] Summary of the Invention

[0004] This disclosure provides a display device and a driving method.

[0005] According to a first aspect, this disclosure provides a display device, including: a display panel; and a first driving circuit electrically connected to the display panel, a first power supply line, and a second power supply line; wherein the first driving circuit includes a plurality of cascaded first shift registers, the first power supply line is electrically connected to the odd-numbered first shift registers among the plurality of first shift registers, and the second power supply line is electrically connected to the even-numbered first shift registers among the plurality of first shift registers; the plurality of first shift registers are configured to output a plurality of first scan signals to the display panel based on a first power supply voltage provided by the first power supply line and a second power supply voltage provided by the second power supply line.

[0006] According to a second aspect, this disclosure provides a driving method applied to a display device provided in the embodiments of this disclosure, comprising: providing a first power supply voltage to an odd-level first shift register among a plurality of first shift registers via a first power supply line; providing a second power supply voltage to an even-level first shift register among a plurality of first shift registers via a second power supply line; and outputting a plurality of first scan signals to a display panel based on the first power supply voltage and the second power supply voltage. Attached Figure Description

[0007] Figure 1 shows a schematic diagram illustrating the principle of a partial refresh;

[0008] Figure 2 shows a schematic diagram of an example of a partially refreshed display screen;

[0009] Figure 3 shows a schematic diagram of the structure of a display device according to an embodiment of the present disclosure;

[0010] Figure 4A shows a schematic diagram of an example pixel circuit;

[0011] Figure 4B shows a schematic diagram of the structure of the output unit of the first driving circuit according to an embodiment of the present disclosure;

[0012] Figure 4C shows a timing diagram of the first scan signal in an example;

[0013] Figure 4D shows a schematic diagram of the principle of an example pull-down noise;

[0014] Figure 5 shows a timing diagram of the first scan signal according to an embodiment of the present disclosure;

[0015] Figure 6 shows a timing diagram of an example drive signal;

[0016] Figure 7 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure;

[0017] Figure 8 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure;

[0018] Figure 9A shows a timing diagram of the drive signals according to an embodiment of the present disclosure;

[0019] Figure 9B shows a timing diagram of the drive signals according to an embodiment of the present disclosure;

[0020] Figure 10 shows a timing diagram of a first scan signal according to another embodiment of the present disclosure;

[0021] Figure 11 shows a schematic diagram of a display device according to another embodiment of the present disclosure;

[0022] Figure 12 shows a schematic diagram of a display device according to another embodiment of the present disclosure; and

[0023] Figure 13 shows a schematic flowchart of a driving method according to an embodiment of the present disclosure. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the contents of the embodiments of this disclosure.

[0025] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0026] Furthermore, in the description of the embodiments disclosed herein, the terms "connected to" or "linked" can refer to a direct connection between two components, or to a connection between two components via one or more other components, wherein the connection method is electrical connection or electrical coupling. Additionally, the two components can also be connected or coupled via wired or wireless means.

[0027] It should be noted that in the description of the embodiments of this disclosure, a node is not an actual component existing in the circuit, but rather represents a point on a circuit in the circuit diagram. The symbol Ngate can represent either the first scan signal or the level of the first scan signal. The following embodiments are the same and will not be described again.

[0028] Figure 1 shows a schematic diagram illustrating the principle of a partial refresh as an example.

[0029] As shown in Figure 1, the display screen 100 can be the display screen of any display device. In the display screen 100, area 101 displays weather information, and area 102 displays time information. The display screens in areas 101 and 102 need to be refreshed in real time. Areas other than areas 101 and 102 in the display screen 100 can remain static and their display screens are not refreshed.

[0030] For example, the horizontal signal pulse HCT pulse can be a scan signal pulse, and the vertical signal pulse VCT pulse can be a data signal pulse.

[0031] In the row direction of the display screen 100, the horizontal signal pulse HCT pulse can control the transistors in the pixel circuits of regions 101 and 102 to conduct, so that in the column direction of the display screen 100, the vertical signal pulse VCT pulse is written into the pixel circuits of regions 101 and 102. This enables regions 101 and 102 to refresh in the row direction.

[0032] For areas other than regions 101 and 102 in the display screen 100, the horizontal signal pulse HCT pulse can control the transistors in the pixel circuits of that area to turn off, while the vertical signal pulse VCT pulse cannot be written, so that area will not be refreshed.

[0033] Figure 2 shows a schematic diagram of an example of a partially refreshed display.

[0034] As shown in Figure 2, the display screen 200 includes area 201 and area 202. Area 201 is a high refresh rate area, and area 202 is a low refresh rate area. For example, the refresh rate of area 201 can be 120Hz, and the refresh rate of area 202 can be 30Hz.

[0035] A bright line L exists in the part of region 201 near region 202, which causes uneven brightness in the display screen 200, thus limiting the application of partial refresh display devices.

[0036] This disclosure provides a display device that, by providing power supply voltages to the odd-numbered and even-numbered shift registers in a cascaded shift register system of a first driving circuit, reduces the coupling effect between adjacent shift register stages, thereby improving the voltage stability of the first scan signal output by each shift register. In this case, the voltage-stabilized first scan signal can control the conduction capability of transistors in the pixel circuit of the display panel and the writing capability of data signals, thereby improving the brightness unevenness in the displayed image.

[0037] Figure 3 shows a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

[0038] As shown in Figure 3, the display device 300 includes a display panel 310 and a first driving circuit 320.

[0039] In this embodiment of the disclosure, the display panel 310 may include multiple pixel circuits, which may be arranged in an array. For example, the display panel 310 may be an organic light-emitting diode (OLED) display panel, where each pixel unit includes a light-emitting element. When the light-emitting elements in the display panel 310 are lit, the display panel 310 displays an image.

[0040] In this embodiment, the first driving circuit 320 is electrically connected to the display panel 310, the first power supply line VGH1, and the second power supply line VGH2. The first power supply line VGH1 and the second power supply line VGH2 provide the first driving circuit 320 with a first power supply voltage VGH1 and a second power supply voltage VGH2, respectively. Based on the first power supply voltage VGH1 and the second power supply voltage VGH2, the first driving circuit 320 outputs a first scanning signal to the display panel 310 to drive the display panel 310 to emit light.

[0041] In this embodiment of the disclosure, the first driving circuit 320 includes a plurality of cascaded first shift registers, a first power supply line vgh1 is electrically connected to the odd-numbered first shift registers among the plurality of first shift registers, and a second power supply line vgh2 is electrically connected to the even-numbered first shift registers among the plurality of first shift registers.

[0042] For example, the odd-level first shift register can be electrically connected to the odd-numbered row pixel circuit in the display panel 310, and the odd-level first shift register outputs a first scan signal to the odd-numbered row pixel circuit in the display panel 310 based on the first power supply voltage VGH1.

[0043] For example, the even-numbered first shift register can be electrically connected to the even-numbered row pixel circuit in the display panel 310, and the even-numbered first shift register outputs a first scan signal to the even-numbered row pixel circuit in the display panel 310 based on the second power supply voltage VGH2.

[0044] For example, the first drive circuit 320 may include multiple cascaded first shift registers GOA1, GOA2, GOA3, GOA4, ... . The first power supply line vgh1 is electrically connected to the first shift registers GOA1, GOA3, ... , and the second power supply line vgh2 is electrically connected to the first shift registers GOA2, GOA4, ... .

[0045] In this embodiment, the first power supply voltage VGH1 and the second power supply voltage VGH2 can be the same. The effective level of the first scan signal is determined based on the first power supply voltage VGH1 and the second power supply voltage VGH2. For example, the effective voltage of the first scan signal can be the same as the first power supply voltage VGH1 and the second power supply voltage VGH2.

[0046] In this embodiment of the present disclosure, a plurality of cascaded first shift registers sequentially shift and output a plurality of first scan signals with valid voltage levels to the display panel 310. There are periods when the first scan signals output by the preceding and following first shift registers are simultaneously valid. The first scan signals output by adjacent shift registers are coupled, thereby affecting the voltage of the valid voltage level of the first scan signal.

[0047] For example, the first shift register of the preceding stage and the first shift register of the following stage sequentially shift and output a first scan signal with an effective level. Before the effective level of the first scan signal output by the first shift register of the preceding stage ends, the first shift register of the following stage also outputs a first scan signal with an effective level. At this time, if the effective levels of the first scan signals output by the first shift registers of the preceding and following stages are provided by the same power supply trace, the voltage of the effective level of the first scan signal output by the first shift register of the preceding stage will be affected by coupling, resulting in voltage instability of the effective level.

[0048] In this embodiment, the first power supply line Vgh1 and the second power supply line Vgh2 provide power supply voltages to the odd-even shift registers respectively, so that the effective levels of the first scan signals output by adjacent first shift registers are provided by different power supply lines. In this case, the coupling effect between the effective levels of the first scan signals output by adjacent first shift registers is small, thereby improving the voltage stability of the first scan signals. Multiple first scan signals with stable effective voltage levels can control the transistors in each row of pixel circuits in the display panel to have the same conduction capability and data signal writing capability, thereby improving the uneven brightness phenomenon in the displayed image.

[0049] The process of the first driving circuit driving the pixel circuit is illustrated in conjunction with Figures 4A, 4B, 4C, and 4D.

[0050] Figure 4A shows a schematic diagram of an example pixel circuit.

[0051] As shown in Figure 4A, the pixel circuit is an 8T1C circuit, which includes transistors T1 to T8, capacitor Cst, and the light-emitting element OLED. Transistors T1, T3 to T8 are PMOS transistors, transistor T2 is an NMOS transistor, and transistor T3 is a driving transistor.

[0052] In one example, the effective level of the first scan signal Ngate output by the first driving circuit controls the turn-on and turn-off of transistor T2, and the effective level of the first scan signal Ngate is high. The effective level of the second scan signal Pgate controls the turn-on and turn-off of transistor T4, and the effective level of the second scan signal Pgate is low. The effective level of the reset signal ResetP controls the turn-on and turn-off of transistor T1, and the effective level of the reset signal ResetP is low. The effective level of the reset signal ResetH controls the turn-on and turn-off of transistors T7 and T8, and the effective level of the reset signal ResetH is low.

[0053] When transistors T1 and T2 are turned on, the initialization signal Vinit1 is provided to the gate of transistor T3 through transistors T1 and T2 to initialize transistor T3. The low level of the initialization signal Vinit1 is used to charge capacitor Cst, so that transistor T3 remains in the on state.

[0054] When transistors T2, T3, and T4 are turned on, the data signal Data is provided to the gate of transistor T3 through transistors T2, T3, and T4, writing data to transistor T3, and using the low level of the data signal Data to charge capacitor Cst, so that transistor T3 remains in the on state.

[0055] With the reset signal ResetH controlling the conduction of transistors T7 and T8, the initialization signal Vinit2 initializes the light-emitting element OLED, and the initialization signal Vint3 initializes the source and drain of transistor T3.

[0056] When the light-emitting control signal EM controls transistors T5 and T6 to be turned on, the driving voltage VDD forms a driving current through transistors T5, T3 and T6. The driving current is provided to the light-emitting element OLED, and the light-emitting element OLED emits light.

[0057] Figure 4B shows a schematic diagram of the output unit of a first driving circuit according to an embodiment of the present disclosure. Figure 4B schematically illustrates the circuit structure of the output terminal of a shift register in the driving circuit.

[0058] As shown in Figure 4B, the output unit of the first shift register of the first driving circuit includes transistor M1 and transistor M2, both of which are Nmos transistors.

[0059] When node N1 is high, transistor M1 is turned on, and the operating power supply voltage VGHN is supplied to the output terminal OUT through transistor M1. When node N2 is high, transistor M2 is turned on, and the operating power supply voltage VGLN is supplied to the output terminal OUT through transistor M2. The signal output from the output terminal OUT is the first scan signal Ngate.

[0060] For example, the operating power supply voltages VGHN and VGLN are used only to distinguish between two power supply voltages with different amplitudes. For example, the operating power supply voltage VGHN is a relatively high voltage, and the operating power supply voltage VGLN is a relatively low voltage.

[0061] When the operating power supply voltage VGHN is provided to the output terminal OUT, the first scan signal Ngate output by the output terminal OUT is at a high level. When the operating power supply voltage VGLN is provided to the output terminal OUT, the first scan signal Ngate output by the output terminal OUT is at a low level.

[0062] Referring to the previous description, at least two first scan signals output by the first driving circuit may be high at the same time. At this time, the transistors M1 of at least two first shift registers in the first driving circuit are turned on, and at least two first shift registers sequentially output first scan signals Ngate with high levels.

[0063] The shift register's output terminal OUT is electrically connected to the gate of transistor T2 in the pixel circuit via a gate trace. Transistor M1 receives the operating power supply voltage VGHN via a power supply trace. The operating power supply voltage VGHN charges the gate trace through transistor M1, resulting in a large instantaneous current. Due to the resistive load in the power supply trace, the voltage value of the operating power supply voltage VGHN is momentarily pulled down. After the output terminal OUT stabilizes, the voltage value of the operating power supply voltage VGHN returns to the set voltage value. This process of decreasing and recovering the operating power supply voltage VGHN causes pull-down noise on the power line.

[0064] If the high voltages of multiple first scan signals are all provided by the same power supply line, when the operating power supply voltage VGHN is momentarily pulled low by any of the first shift registers, the voltages of the first scan signals in the charging gate lines are all momentarily pulled down, thus creating pull-down noise. Multiple first shift registers sequentially output the first scan signals, and the charging process of their respective connected gate lines will sequentially cause pull-down noise on the power supply lines, resulting in pull-down noise also appearing in the first scan signals received by the display panel.

[0065] Furthermore, under the continuous pull-down effect, there is a delay in the process of the drive circuit outputting the first scan signal. This causes the high-level voltage value of the first scan signal NGate output by the drive circuit to be lower than the set voltage value of the operating power supply voltage VGHN. At this time, the voltage value of the first scan signal received by the display panel decreases and pull-down noise is present.

[0066] In one example, the first scan signal Ngate output from each first shift register can be provided to two rows of pixel circuits in the display panel. Therefore, the noise period of the first scan signal Ngate is one cycle for every two rows. In this case, the odd and even row pixel circuits in the display panel are sequentially turned on by the second scan signal PGate, and the noise state of the odd and even row pixel circuits receiving the first scan signal NGate is also different. This leads to differences in the writing state of the data signals in the odd and even row pixel circuits, ultimately forming a horizontal stripe defect with uneven brightness in the odd and even rows on the display screen.

[0067] In one example, in a partial refresh scenario, the pixel circuits in the low refresh region do not need to write data signals. Therefore, the first scan signal Ngate output by the first shift register corresponding to the low refresh region is at a low level, and the operating power supply voltage VGHN does not need to charge the gate trace connected to the first shift register.

[0068] As the scanned pixel rows gradually switch from the high refresh rate region to the low refresh rate region, the number of first scan signals Ngate that need to be output with a high level gradually decreases. Since the first scan signal output by the shift register corresponding to the first row of pixel circuits in the low refresh rate region is low, the next-level shift register of the shift register corresponding to the last row of pixel circuits in the high refresh rate region will not pull down the operating power supply voltage VGHN.

[0069] Figure 4C shows a timing diagram of an example first scan signal, and Figure 4D shows a schematic diagram of an example pull-down noise. Figure 4C shows the timing of the first scan signal output by multiple first shift registers electrically connected to the same power supply trace vghN.

[0070] As shown in Figure 4C, the first scan signals Ngate m to Ngate m+6 are received by the high refresh rate area of ​​the display panel. The first scan signal Ngate m+7 is received by the low refresh rate area of ​​the display panel. For example, the first scan signal Ngate m+6 is used to scan the last row of pixel circuits in the high refresh rate area 201 shown in Figure 2, and the first scan signal Ngate m+7 is used to scan the first row of pixel circuits in the low refresh rate area 202 shown in Figure 2. The first scan signals Ngate m to Ngate m+6 are used to scan the last 7 rows of pixel circuits in the high refresh rate area 201 shown in Figure 2.

[0071] During the high-level output period of the first scan signal Ngate m, the first scan signal Ngate m+1 transitions from low to high. At this time, the high level of the first scan signal Ngate m+1 causes the operating power supply voltage VGHN of the power supply trace VghN to be momentarily pulled down, thereby draining the gate trace that outputs the first scan signal Ngate m. This results in pull-down noise 1 in the first scan signal Ngate m. Correspondingly, during the high-level output period of the first scan signal Ngate m, the sequential transitions from low to high of the first scan signals Ngate m+2 to Ngate m+6 cause pull-down noise 2 to pull-down noise 6 to appear in the first scan signal Ngate m.

[0072] As shown in Figure 4D, the power supply terminal provides the operating power supply voltage VGHN via the power supply trace vghN. During the high-level output period of the first scan signal Ngate m, the charge in the power supply trace vghN moves towards the gate trace of the first scan signal Ngate m. When the first scan signal Ngate m+1 is output high, since the power supply trace vghN and the gate trace of the first scan signal Ngate m are connected, the gate trace of the first scan signal Ngate m+1 will couple and pump the power supply voltage of the first scan signal Ngate m. This causes the charge in the gate trace of the first scan signal Ngate m to move towards the power supply trace vghN, pulling down the voltage of the first scan signal Ngate m, and then gradually restoring the operating power supply voltage VGHN, thus creating pull-down noise in the first scan signal Ngate m.

[0073] Referring to the preceding description, during the high-level output period of the first scan signal Ngate m+1, the sequential transitions from low to high levels of the first scan signals Ngate m+2 to Ngate m+6 will cause pull-down noise 1 to pull-down noise 5 to appear sequentially in the first scan signal Ngate m+1. During the high-level output period of the first scan signal Ngate m+2, the sequential transitions from low to high levels of the first scan signals Ngate m+3 to Ngate m+6 will cause pull-down noise 1 to pull-down noise 4 to appear sequentially in the first scan signal Ngate m+2. During the high-level output period of the first scan signal Ngate m+3, the sequential transitions from low to high levels of the first scan signals Ngate m+4 to Ngate m+6 will cause pull-down noise 1 to pull-down noise 3 to appear sequentially in the first scan signal Ngate m+3. During the high-level output period of the first scan signal Ngate m+4, the sequential transitions from low to high levels of the first scan signals Ngate m+5 to Ngate m+6 will cause pull-down noise 1 to pull-down noise 2 to appear sequentially in the first scan signal Ngate m+1. During the high-level output period of the first scan signal Ngate m+5, the sequential transition from low to high levels of the first scan signal Ngate m+6 will cause pull-down noise 1 to appear in the first scan signal Ngate m+5.

[0074] Since the level of the first scan signal Ngate m+7 remains low, it will not cause pull-down noise to the first scan signals Ngate m+1 to Ngate m+6. The pull-down noise in the first scan signals Ngate m+1 to Ngate m+5 will gradually disappear, and there is no pull-down noise in the first scan signal Ngate m+6.

[0075] The pull-down noise in the power trace VGHN will suddenly disappear, and the operating power supply voltage VGHN of the power trace VGHN will gradually rise to the set voltage value. This causes different voltage changes in the last few rows of pixel circuits in the high refresh rate region when receiving the first scan signal. Furthermore, as the number of pull-downs to the operating power supply voltage VGHN of the power trace VGHN gradually decreases, the voltage value of the last few rows of pixel circuits in the high refresh rate region when receiving the first scan signal is slightly higher than the voltage value of the first scan signal Ngate received by the pixel circuits in other rows of the high refresh rate region. The difference in the data signal writing capability between the last few rows of pixel circuits in the high refresh rate region and the other rows results in a higher brightness in the last few rows of pixel circuits in the high refresh rate region, leading to uneven brightness in the displayed image. For the high refresh rate region, the last row of pixel circuits in the high refresh rate region receives the highest voltage value of the first scan signal Ngate+7, therefore the last row of pixel circuits in the high refresh rate region has the highest brightness. The display effect can be seen in Figure 2.

[0076] Figure 5 shows a timing diagram of the first scan signal according to an embodiment of the present disclosure. Figure 5 illustrates the timing of the first scan signal Ngate m to the first scan signal Ngate m+7 based on the output of the first driving circuit shown in Figure 1.

[0077] In this embodiment of the disclosure, the first scan signal Ngate m to the first scan signal Ngate m+7 can be output by the first shift register of the m-th stage to the first shift register of the (m+7)-th stage in the first driving circuit, and the first scan signal Ngate m to the first scan signal Ngate m+7 are provided to the pixel circuit of the m-th row to the pixel circuit of the (m+7)-th row in the display panel.

[0078] In this embodiment, the m-th, m+2-th, m+4-th, and m+6-th level first shift registers can be odd-numbered first shift registers, and the m+1-th, m+3-th, m+5-th, and m+7-th level first shift registers can be even-numbered first shift registers. The high voltage levels of the first scan signals Ngate m, Ngate m+2, Ngate m+4, and Ngate m+6 are all provided by the first power supply line vgh1, and the high voltage levels of the first scan signals Ngate m+1, Ngate m+3, and Ngate m+5 are all provided by the second power supply line vgh2.

[0079] For example, the high level of the first scan signal Ngate m is less affected by the pumping coupling of the first scan signal Ngate m+1, the first scan signal Ngate m+3, and the first scan signal Ngate m+5, thus improving the pull-down noise 1, pull-down noise 3, and pull-down noise 5 of the first scan signal Ngate m.

[0080] Correspondingly, the high level of the first scan signal Ngate m+1 is less affected by the pumping coupling of the first scan signals Ngate m+2, Ngate m+4, and Ngate m+6, thus improving the pull-down noise 1, pull-down noise 3, and pull-down noise 5 of the first scan signal Ngate m+1.

[0081] The improvement effect of pull-down noise in the first scan signals Ngate m+2 to Ngate m+6 is referenced to the first scan signals Ngate m and Ngate m+1. For simplicity, similar parts will not be repeated.

[0082] In this embodiment of the disclosure, a separate power supply voltage VGH is provided for the odd and even stages of the multiple first shift registers in the first driving circuit. This reduces the influence of the even-stage first shift registers on the odd-stage first shift registers, and vice versa. In this case, the pull-down noise between the first scan signals output by adjacent first shift register stages is reduced, thereby reducing the voltage difference between the first scan signals used to scan the high-brush region and the high-brush transition region (the region in the high-brush region that is close to the low-brush region), and thus improving the brightness of the bright band in the high-frequency transition region.

[0083] Figure 6 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure.

[0084] As shown in Figure 6, the display device 600 includes a display panel 610, a first driving circuit 620, and a second driving circuit 630.

[0085] In this embodiment, the display panel 610 and the first driving circuit 620 can be referred to as the display panel 310 and the first driving circuit 320 described above. For the sake of brevity, similar parts will not be repeated.

[0086] In this embodiment, the second driving circuit 630 is electrically connected to the display panel 610. The second driving circuit 630 outputs a second scan signal, which is used to control the writing of data signals into the pixel circuit. For example, the second scan signal output by the second driving circuit 630 can be referred to as the second scan signal Pgate in FIG4A described above.

[0087] In this embodiment, the effective level of the second scan signal controls the writing of data signals into the pixel circuit. After the data signal is completely written into the pixel circuit, the duration of the effective level of the second scan signal ends to prevent data signals belonging to other pixel circuits from being unwritten. After the duration of the effective level of the second scan signal ends, the effective level of the first scan signal controls the writing of data signals into the driving transistor. Therefore, the duration of the effective level of the first scan signal is related to the duration of the effective level of the second scan signal.

[0088] In this embodiment of the disclosure, while ensuring that the second scan signal can control the writing of data signals into the pixel circuit, the driving circuit 320 can shorten the duration of the effective level of the second scan signal as much as possible. For example, a single second scan signal is provided to one row of pixel circuits of the display panel 610 to control the duration of the effective level of the second scan signal for writing data signals belonging to that row of pixel circuits into that row of pixel circuits to 1H, so as to avoid data signals belonging to other pixel circuits being not written, where H is the ratio of the display frame rate to the total number of rows of pixel circuits in the display panel 610.

[0089] In this embodiment, a single first scan signal can be provided to K rows of pixel circuits in the display panel 610, where K is a positive integer, and the duration of the first scan signal scanning one row of pixel circuits is approximately 1H. Since the first scan signal is provided to K rows of pixel circuits in the display panel 610, K second scan signals and 1 first scan signal are needed to scan the K rows of pixel circuits, so that data signals can be sequentially written into the K rows of pixel circuits.

[0090] In this embodiment, the first driving circuit 620 is electrically connected to a first clock terminal, and the second driving circuit 630 is electrically connected to a second clock terminal. The first driving circuit 620 outputs a first scan signal under the control of a first clock signal from the first clock terminal. The second driving circuit 630 outputs a second scan signal under the control of a second clock signal from the second clock terminal. Since K second scan signals and 1 first scan signal are used to scan K rows of pixel circuits, the duration of the effective level of the first clock signal within one clock cycle is K times the duration of the effective level of the second clock signal.

[0091] For example, the first clock input may include clock input NCK and clock input NCB. The second clock input may include clock input GCK and clock input GCB.

[0092] For example, the clock signals NCK and NCB are inverted, and they are not simultaneously active. For example, clock signal NCK is provided to the first-stage first shift register in the first driving circuit 620, and clock signal NCB is provided to the second-stage first shift register. When the first scan signals output from the first-stage and second-stage first shift registers are provided to the two rows of pixel circuits, the clock periods of clock signals NCK and NCB are 2*2 = 4H. For example, if the high level of clock signal NCK is maintained for 2H, the low level of clock signal NCB is maintained for 2H. If the low level of clock signal NCK is maintained for 2H, the high level of clock signal NCB is maintained for 2H. In this case, the high level of the first scan signal can be maintained for at least 2H, thereby achieving scanning of the two rows of pixel circuits.

[0093] For example, the clock signals GCK and GCB are inverted, and they are not simultaneously active. For example, clock signal GCK is provided to the first-stage second shift register in the second driver circuit 630, and clock signal GCB is provided to the second-stage second shift register. When the second scan signal output from the first-stage and second-stage second shift registers is provided to a row of pixel circuits, the clock period of clock signals GCK and GCB is 1*2 = 2H. For example, if the high level of clock signal GCK is maintained for 1H, the low level of clock signal GCB is maintained for 1H. If the low level of clock signal GCK is maintained for 1H, the high level of clock signal GCB is maintained for 1H. In this case, the high level of the second scan signal can be maintained for at least 1H, thereby achieving scanning of a row of pixel circuits.

[0094] Figure 7 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure.

[0095] As shown in Figure 7, the display device 700 includes a display panel 710, a first driving circuit 720, a second driving circuit 730, and a third driving circuit 740.

[0096] In this embodiment, the display panel 710, the first driving circuit 720, and the second driving circuit 730 can be referred to as the display panel 610, the first driving circuit 620, and the second driving circuit 630 described above. For the sake of brevity, similar parts will not be repeated.

[0097] In this embodiment, the third driving circuit 740 is electrically connected to the display panel 710. The third driving circuit 740 outputs a reset signal, which is used to control the driving transistors that write initialization signals into the pixel circuit. For example, the reset signal output by the third driving circuit 740 can be referred to as the reset signal ResetP in FIG4A described above.

[0098] In this embodiment of the present disclosure, a single reset signal can be provided to the K rows of pixel circuits in the display panel 710, and the duration of the reset signal scanning one row of pixel circuits is approximately 1 hour. Since the reset signal is provided to the K rows of pixel circuits in the display panel 710, K second scan signals, 1 reset signal, and 1 first scan signal are required to scan the K rows of pixel circuits, so that data signals can be sequentially written into the K rows of pixel circuits.

[0099] In this embodiment, the third driving circuit 740 can be electrically connected to the third clock terminal. Under the control of the third clock signal from the third clock terminal, the third driving circuit 740 outputs a reset signal. Since K second scan signals and 1 reset signal are used to scan the K rows of pixel circuits, the duration of the effective level of the third clock signal is K times the duration of the effective level of the second clock signal.

[0100] For example, the third clock input may include clock input RCK and clock input RCB. For instance, the clock signal RCK output by clock input RCK and the clock signal RCB output by clock input RCB can be referenced to clock signals NCK and NCB. For simplicity, similar details will not be repeated.

[0101] Referring to Figure 4C described above, during the refresh process of a single frame of the display, the levels of multiple first scan signals output by multiple shift registers will all be valid levels within the same time period. The simultaneous output of the operating power supply voltage VGHN by at least two shift registers providing valid first scan signals causes instability in the operating power supply voltage VGHN that provides the valid level for the first scan signals. This instability in the valid levels of the multiple first scan signals affects the writing of data signals to the pixel circuit, resulting in uneven brightness on the display panel.

[0102] In this embodiment of the disclosure, the duration of the effective level of the first scan signal output by the first driving circuit 720 can be shortened. Since the duration of the effective levels of multiple first scan signals is shortened, the number of first scan signals with an effective level at a certain moment is also reduced accordingly. Therefore, the impact on the operating power supply voltage is reduced, thereby improving the stability of the operating power supply voltage and the stability of the effective level of the first scan signal.

[0103] In this embodiment, before the first scan signal controls the data signal to be written to the driving transistor, the effective level of the first scan signal and the effective level of the reset signal jointly control the initialization signal to be written to the driving transistor. After the initialization signal is written, the duration of the effective level of the reset signal ends. After the duration of the effective level of the reset signal ends, the effective level of the first scan signal controls the data signal to be written to the driving transistor. Therefore, the duration of the effective level of the first scan signal is determined based on the duration of the effective level of the reset signal. For example, the effective level of the reset signal is low, and the level of the first scan signal is high.

[0104] During the initialization phase, the reset signal remains low. During the data writing phase, the reset signal remains low. During both the initialization and data writing phases, the first scan signal remains high. The duration of the active level of the first scan signal is longer than the duration of the active level of the reset signal.

[0105] While ensuring that the reset signal can control the initialization signal to fully initialize the driving transistor, the third driving circuit 740 can shorten the duration of the effective level of the reset signal as much as possible. Based on the duration of the effective level of the reset signal, the minimum duration of the effective level of the first scan signal can be determined. For example, the minimum duration of the effective level of the first scan signal can be determined based on the minimum duration of the effective level of the reset signal. The minimum duration indicates whether the duration of the effective level of the first scan signal is greater than or equal to the minimum duration.

[0106] In this embodiment, the duration of the effective level of the first scan signal can be the sum of the duration of the effective level of the reset signal, the duration of the effective level of the second scan signal, and the time required for the data signal to be completely written to the driving transistor. Ideally, the effective level of the first scan signal can achieve both the initialization of the driving transistor and the writing of data to the driving transistor.

[0107] In actual driving process, there will be a certain delay in the rise and fall of the level. Therefore, the minimum duration of the effective level of the first scan signal can be slightly greater than the sum of the effective level of the reset signal, the effective level of the second scan signal, and the time required for the data signal to be completely written to the driving transistor.

[0108] In this embodiment, the maximum duration of the effective level of the first scan signal is related to the rise and fall delays of each signal, and is also related to the turn-on and turn-off times of the transistors in the pixel circuit. After fully considering the rise and fall delays of each signal during actual driving, as well as the turn-on and turn-off delays that may occur due to transistor aging, the maximum duration of the effective level of the first scan signal can be determined.

[0109] In this embodiment, the end time of the effective level of the first scan signal is related to the initialization time of the light-emitting element. The light-emitting element needs to be initialized before the driving current is supplied to it, which avoids the influence of the data signal from the previous frame.

[0110] For example, the anode of the light-emitting element is initialized after the data signal is written to the driving transistor. The duration of the effective level of the first scan signal ends before the anode of the light-emitting element is initialized. Alternatively, the anode of the light-emitting element can also be initialized before the reset signal initializes the driving transistor. The duration of the effective level of the first scan signal ends after the data signal is completely written to the driving transistor.

[0111] In some embodiments, for scanning a row of pixel circuits in the display panel 710, the effective level of the second scan signal is low, and the effective level of the first scan signal is high. The time by which the second scan signal switches from low to high is greater than or equal to (K-1)*H before the time by which the first scan signal switches from high to low, and the duration of the effective level of the second scan signal is 1H.

[0112] In this embodiment, a single first scan signal drives K rows of pixel circuits, and a single second scan signal drives 1 row of pixel circuits. When both the second scan signal and the first scan signal are at active levels, the second scan signal controls transistor T4 to turn on, and the first scan signal also controls transistor T2 to turn on. Since the second scan signal controls the duration of writing the data signal into the 1 row of pixel circuits to be 1H, the time when the second scan signal switches from low to high level is at least (K-1)*H earlier than the time when the first scan signal switches from high to low level.

[0113] In this scenario, for a K-row pixel circuit, after the first and second scan signals have completed scanning the first row of pixel circuits, the first scan signal still needs to complete scanning the remaining K-1 rows of pixel circuits. With the second scan signal controlling the duration of writing the data signal to the first row of pixel circuits to be 1H, the timing of the second scan signal switching from low to high level is (K-1)*H earlier than the timing of the first scan signal switching from high to low level, allowing the first scan signal to complete scanning the remaining K-1 rows of pixel circuits.

[0114] In some embodiments, for scanning a row of pixel circuits in the display panel 710, the effective level of the reset signal is low, and the time by which the first scan signal switches from low to high is greater than or equal to K*H before the time by which the reset signal switches from low to high.

[0115] For example, if the number of pixel circuit rows driven by a single first scan signal is K rows, and the reset signal initializes the driving transistors at least K*H in advance, then transistor T1 shown in Figure 4A is turned on K*H before transistor T2. In this case, the initialization signal Vinit1 can be written first through transistor T1, and then through K*H via transistor T2.

[0116] When the first scan signal is high, transistor T2 is turned on. When the reset signal is low, transistor T1 is turned on. The initialization signal Vinit1 is written to the gate of the driving transistor T3 through transistors T1 and T2, thereby initializing the driving transistor T3. Since both a single first scan signal and a single first scan signal scan K rows of pixel circuits, the low level of the reset signal and the high level of the first scan signal need to be maintained simultaneously for at least K*H. The moment when the first scan signal switches from low to high is at least K*H earlier than the moment when the reset signal switches from low to high.

[0117] The reset signal can turn on transistor T1 in advance and write the initialization signal Vinit1 between transistor T2 and transistor T1. This ensures that when transistor T2 turns on after a time interval of K*H, the initialization signal Vinit1 can be directly provided to the driving transistor via transistor T2. Therefore, the reset signal switches from high to low level K*H earlier than the first scan signal switches from low to high level.

[0118] In this embodiment, the duration of the low level of the reset signal is also related to the clock period of the third clock signal. The duration of the low level of the reset signal needs to be greater than or equal to the clock period of the third clock signal. In practical applications, due to rise and fall delays during signal level switching, to ensure that the reset signal can complete the full initialization of the driving transistor, the duration of the effective level of the reset signal can be increased by one clock cycle, thereby utilizing the initialization signal to fully initialize the driving transistor.

[0119] In some embodiments, for scanning a row of pixel circuits in the display panel 710, the moment when the first scan signal switches from low level to high level is not earlier than the start moment of the low level of the reset signal.

[0120] In this embodiment of the disclosure, the reset signal requires a certain amount of time to transition from a high level to a low level, and the falling edge of the reset signal has a falling step.

[0121] Transistors T1 and T2 can be turned on simultaneously when the first scan signal switches from low to high and the reset signal starts its low state. The initialization signal Vinit1 is written to the gate of the driving transistor T3 through transistors T1 and T2. The duration of the high level of the first scan signal and the duration of the low level of the reset signal are at least K*H, thus enabling the initialization of the driving transistor T3 in the K-row pixel circuit.

[0122] If the first scan signal switches from low to high later than the start of the low level of the reset signal, transistor T1 can turn on earlier than transistor T2. The initialization signal Vinit1 first passes through transistor T1 and is written between transistors T1 and T2. After transistor T2 turns on, the initialization signal Vinit1 then passes through transistor T2 and is written to the gate of the driving transistor T3.

[0123] In this embodiment, when the first scan signal switches from low to high earlier than the start of the low level of the reset signal, transistor T2 can turn on earlier than transistor T1. At this time, the initialization signal Vinit1 cannot be written through transistor T1, and the conducting transistor T2 also cannot write the initialization signal Vinit1. Therefore, the moment when the first scan signal switches from low to high can be delayed. After the low level of the reset signal begins, the first scan signal switches from low to high.

[0124] In some embodiments, for scanning a row of pixel circuits in the display panel 710, the time by which the reset signal switches from low to high is greater than or equal to K*H before the time by which the second scan signal switches from high to low.

[0125] In this embodiment, after the reset signal switches from low to high, transistor T1 is turned off. At this time, the first scan signal can still control transistor T2 to be in the conducting state, thereby writing the initialization signal Vinitl between transistor T2 and transistor T1 into the gate of driving transistor T3, thus initializing driving transistor T3. Since a single first scan signal needs to scan K rows of pixel circuits, after the reset signal switches from low to high, the first scan signal can initialize driving transistor T3 using a high level for a duration of K*H.

[0126] After initializing the driving transistor T3, the second scan signal can transition from high to low, thereby controlling transistor T4 to turn on and write the data signal. Therefore, the interval between the moment the second scan signal transitions from high to low and the moment the reset signal transitions from low to high can be at least K*H.

[0127] In this embodiment of the disclosure, the duration of the high level of the first scan signal can be at least (K+K+K-1+1)*H=3K*H, thereby ensuring the complete initialization of the driving transistor T3 and the writing of all data signals to the driving transistor T3.

[0128] In this embodiment, the minimum duration of the effective level of the reset signal can be determined through pre-testing. Based on the minimum duration of the effective level of the reset signal, the duration of the effective level of the first scan signal can also be determined in advance. With the minimum duration of the effective level of the reset signal and the duration of the effective level of the first scan signal determined, the first driving circuit 720, the second driving circuit 730, and the third driving circuit 740 can directly output the first scan signal, the second scan signal, and the reset signal with corresponding effective levels of duration during the driving process, without needing to adjust the duration of the effective levels of each signal during the driving process.

[0129] In this embodiment, the end time of the effective level of the first scan signal is related to the initialization time of the light-emitting element. The light-emitting element needs to be initialized before the driving current is supplied to it, which avoids the influence of the data signal from the previous frame.

[0130] For example, after the data signal is written to the driving transistor, the anode of the OLED is initialized using the initialization signal Vinit2. The duration of the effective level of the first scan signal ends before the anode of the OLED is initialized. Alternatively, the anode of the OLED can also be initialized before the reset signal initializes the driving transistor. The duration of the effective level of the first scan signal ends after the data signal is completely written to the driving transistor.

[0131] In this embodiment of the present disclosure, the first driving circuit 720, the second driving circuit 730 and the third driving circuit 740 can also adjust the duration of the effective level of each signal according to the actual driving state.

[0132] In this embodiment of the disclosure, by shortening the duration of the effective level of the first scan signal as much as possible, the number of first scan signals with high level output at the same time can be effectively reduced, and the number of shift registers that charge the gate traces using the operating power supply voltage VGHN at the same time can be reduced, thereby stabilizing the voltage value of the operating power supply voltage VGHN and stabilizing the voltage value of the high level of the first scan signal.

[0133] In this embodiment of the disclosure, by controlling the duration of the effective level of the first scan signal provided to the display panel through the first driving circuit 720, the stability of the operating power supply voltage can be improved, thereby improving the stability of the pixel circuit driving and improving the uneven brightness phenomenon in the display screen.

[0134] Figure 8 shows a timing diagram of an example driving signal. Figure 8 illustrates the duration of the high level of the light emission control signal EM, the duration of the high level of the first scan signal Ngate, the duration of the low level of the second scan signal Pgate, the duration of the low level of the reset signal ResetP, and the duration of the low level of the reset signal ResetH. The effective level of the light emission control signal EM is low, the effective level of the first scan signal Ngate is high, the effective level of the second scan signal Pgate is low, and the effective levels of the reset signals ResetP and ResetH are low. The first scan signal Ngate, the reset signal ResetP, and the reset signal ResetH are used to scan two rows of pixel circuits, and the second scan signal Pgate is used to scan one row of pixel circuits.

[0135] As shown in Figure 8, the duration of the high level of the light emission control signal EM is 26H, the duration of the high level of the first scan signal Ngate is 14H, the duration of the low level of the second scan signal Pgate is 1H, the duration of the low level of the reset signal ResetP is 6H, and the duration of the low level of the reset signal ResetH is 6H.

[0136] The light emission control signal EM switches from low to high 4 hours earlier than the first scan signal Ngate switches from low to high. The first scan signal Ngate switches from low to high 2 hours earlier than the reset signal ResetP switches from high to low.

[0137] The reset signal ResetP switches from low to high 3 hours earlier than the second scan signal Pgate switches from high to low. The second scan signal Pgate switches from low to high 2 hours earlier than the first scan signal Ngate switches from high to low.

[0138] The first scan signal Ngate switches from high to low 3 hours earlier than the reset signal ResetH switches from high to low. The reset signal ResetH switches from low to high 1 hour earlier than the light emission control signal EM switches from high to low.

[0139] The duration of the effective level of the first scan signal Ngate shown in Figure 7A can be the maximum value. Under the driving of the low level duration of the light emission control signal EM, the first scan signal Ngate, the second scan signal Pgate, the reset signal ResetP shown in Figure 7A, and the reset signal ResetH, the pixel circuit can complete the driving of the light emission element. However, in the actual driving process, the first scan signal Ngate has pull-down noise as shown in Figure 4C, and the high level voltage value is less than the operating power supply voltage VGHN.

[0140] Figure 9A shows a timing diagram of the driving signals according to an embodiment of the present disclosure. Figure 9A shows the duration of the high level of the light emission control signal EM, the duration of the high level of the first scan signal Ngate, the duration of the low level of the second scan signal Pgate, the duration of the low level of the reset signal ResetP, and the duration of the low level of the reset signal ResetH when K=2.

[0141] As shown in Figure 9A, the duration of the high level of the light emission control signal EM is 26H, the duration of the high level of the first scan signal Ngate is 10H, the duration of the low level of the second scan signal Pgate is 1H, the duration of the low level of the reset signal ResetP is 6H, and the duration of the low level of the reset signal ResetH is 6H.

[0142] The light emission control signal EM switches from low to high 4 hours earlier than the reset signal ResetP switches from high to low. The reset signal ResetP switches from high to low 2 hours earlier than the first scan signal Ngate switches from high to low.

[0143] The first scan signal Ngate switches from high to low 4 hours earlier than the reset signal ResetP switches from low to high. The reset signal ResetP switches from low to high 3 hours earlier than the second scan signal Pgate switches from high to low.

[0144] The second scan signal Pgate switches from low to high level 2 hours earlier than the first scan signal Ngate switches from high to low level.

[0145] The first scan signal Ngate switches from high to low 3 hours earlier than the reset signal ResetH switches from high to low. The reset signal ResetH switches from low to high 1 hour earlier than the light emission control signal EM switches from high to low.

[0146] In this embodiment of the disclosure, the timing duration of the high level of the light emission control signal EM can be set according to actual driving requirements. For example, the duration of the high level of the light emission control signal can be increased or decreased by setting the time difference between the pull-down time of the first scan signal Ngate shown in FIG9A and the pull-down time of the reset signal ResetH, and the time difference between the pull-up time of the reset signal ResetH and the pull-down time of the light emission control signal EM.

[0147] Compared to the first scan signal shown in Figure 8, the duration of the high level of the first scan signal shown in Figure 9A is shortened. Consequently, the number of first scan signals with a high level output at the same time is also correspondingly smaller, thus stabilizing the voltage value of the high level of the first scan signal.

[0148] Figure 9B shows a timing diagram of the drive signals according to another embodiment of the present disclosure. Figure 9B shows the duration of the high level of the light emission control signal EM, the duration of the high level of the first scan signal Ngate, the duration of the low level of the second scan signal Pgate, the duration of the low level of the reset signal ResetP, and the duration of the low level of the reset signal ResetH when K=2.

[0149] As shown in Figure 9B, the duration of the high level of the light emission control signal EM is 22H, the duration of the high level of the first scan signal Ngate is 6H, the duration of the low level of the second scan signal Pgate is 1H, the duration of the low level of the reset signal ResetP is 4H, and the duration of the low level of the reset signal ResetH is 4H.

[0150] The light emission control signal EM switches from low to high 6 hours earlier than the reset signal ResetP switches from high to low. The reset signal ResetP switches from high to low 2 hours earlier than the first scan signal Ngate switches from high to low.

[0151] The first scan signal Ngate switches from high to low 2 hours earlier than the reset signal ResetP switches from low to high. Similarly, the reset signal ResetP switches from low to high 2 hours earlier than the second scan signal Pgate switches from high to low.

[0152] The second scan signal Pgate switches from low to high level 1 hour earlier than the first scan signal Ngate switches from high to low level.

[0153] The first scan signal Ngate switches from high to low 3 hours earlier than the reset signal ResetH switches from high to low. The reset signal ResetH switches from low to high 1 hour earlier than the light emission control signal EM switches from high to low.

[0154] Compared to the first scan signal shown in Figure 9A, the duration of the high level of the first scan signal shown in Figure 9B is shortened. Consequently, the number of first scan signals with a high level output at the same time is also correspondingly smaller, thus stabilizing the voltage value of the high level of the first scan signal.

[0155] In this embodiment of the disclosure, it should be noted that the signals shown in Figures 9A and 9B can be provided to the pixel circuit shown in Figure 4A. The signal levels shown in Figures 9A and 9B are merely illustrative; the signal levels can be changed accordingly after the structure of the pixel circuit and the type of transistors in the pixel circuit are changed.

[0156] In some embodiments, the first driving circuit may include M cascaded first shift registers, and the second driving circuit may include N cascaded second shift registers, where M and N are positive integers.

[0157] The first scan signal output from the m-th stage first shift register and the second scan signal output from the n-th stage second shift register are used to drive the same row of pixel circuits. When a single first scan signal is used to scan two rows of pixel circuits and a single second scan signal is used to scan one row of pixel circuits, the first scan signal output from the m-th stage first shift register and the second scan signal output from the (n+1)-th stage second shift register are used to drive the same row of pixel circuits, and n = 2m.

[0158] In this embodiment, during the duration of the high level of the first scan signal output by the m-th stage first shift register, the first scan signal output by the (m+2a)-th stage first shift register changes from low to high, and the first scan signal output by the (m+2a+2)-th stage first shift register also changes from low to high. 1 ≤ m ≤ M-2a-2, 1 ≤ n ≤ N, and a is a positive integer. Therefore, during the duration of the high level of the first scan signal output by the m-th stage first shift register, the phenomenon of the first scan signals output by the (m+2a)-th stage and the (m+2a+2)-th stage first shift register changing from low to high will pull down the high-level noise of the first scan signal output by the m-th stage first shift register, resulting in pull-down noise in the first scan signal output by the m-th stage first shift register.

[0159] For example, the first shift register of the m-th stage, the first shift register of the (m+2a)-th stage, and the first shift register of the (m+2a+2)-th stage are connected to the same power supply trace. The first shift register of the m-th stage, the first shift register of the (m+2a)-th stage, and the first shift register of the (m+2a+2)-th stage can all be odd-numbered first shift registers or all be even-numbered shift registers.

[0160] For example, the first shift register of the m-th stage, the first shift register of the (m+2a)-th stage, and the first shift register of the (m+2a+2)-th stage can be the first shift registers that output the first scan signals Ngate m, Ngate m+4, and Ngate m+6 in Figure 5, respectively. The first shift register of the m-th stage, the first shift register of the (m+2a)-th stage, and the first shift register of the (m+2a+2)-th stage can also be the first shift registers that output the first scan signals Ngate m+1, Ngate m+3, and Ngate m+5 in Figure 5, respectively.

[0161] In this embodiment of the present disclosure, the moment when the first scan signal output by the (m+2a)th stage first shift register switches from the first level to the second level is earlier than the moment when the second scan signal output by the nth stage second shift register switches from the second level to the first level. Similarly, the moment when the second scan signal output by the nth stage second shift register switches from the first level to the second level is earlier than the moment when the first scan signal output by the (m+2a+2)th stage first shift register switches from the first level to the second level.

[0162] The first scan signal output from the (m+2a)th stage first shift register and the first scan signal output from the (m+2a+2)th stage first shift register will cause two adjacent pull-down noises in the first scan signal output from the m-th stage first shift register. Between these two adjacent pull-down noises, the voltage of the first scan signal output from the m-th stage first shift register is relatively stable. Therefore, the duration of the low level of the second scan signal output from the n-th stage second shift register, which falls between the two adjacent pull-down noises, ensures that the second scan signal output from the n-th stage second shift register and the first scan signal output from the m-th stage first shift register can effectively complete the data writing to the pixel circuit rows.

[0163] In this embodiment, the moment when the first scan signal output by the (m+2a)th stage first shift register switches from the first level to the second level is earlier than the moment when the second scan signal output by the (n+1)th stage second shift register switches from the second level to the first level. Similarly, the moment when the second scan signal output by the (n+1)th stage second shift register switches from the first level to the second level is earlier than the moment when the first scan signal output by the (m+2a+2)th stage first shift register switches from the first level to the second level. Therefore, the duration of the low level of the second scan signal output by the (n+1)th stage second shift register is also located between two adjacent pull-down noises, ensuring that the second scan signal output by the nth stage second shift register and the first scan signal output by the mth stage first shift register can effectively complete the data writing to the pixel circuit row.

[0164] In this case, at the two moments when the two second scan signals are at a low level, the voltage state difference of the first scan signal is small, which can improve the display brightness difference of the odd and even row pixel circuits.

[0165] Referring to Figure 10, the timing of the first scan signal output by the (m+2a)th stage first shift register, the first scan signal output by the (m+2a+2)th stage first shift register, the second scan signal output by the nth stage second shift register, and the second scan signal output by the (n+1)th stage second shift register are illustrated schematically. Figure 10 shows a timing diagram of the first scan signal according to another embodiment of the present disclosure.

[0166] As shown in Figure 10, the first scanning signal Ngate m and the second scanning signal Pgate n can scan the nth row of pixel circuits, and the first scanning signal Ngate m and the second scanning signal Pgate n+1 can scan the (n+1)th row of pixel circuits.

[0167] Under the influence of the pumping coupling when the first scan signals Ngate m+2, Ngate m+4, and Ngate m+6 transition from low to high levels, the first scan signal Ngate m exhibits pull-down noise 2, pull-down noise 4, and pull-down noise 6. It should be noted that the first scan signal Ngate m also exhibits pull-down noise 1, pull-down noise 3, and pull-down noise 5. Since the pull-down amplitudes of pull-down noise 1, pull-down noise 3, and pull-down noise 5 are relatively small, the pull-down effect of the high-level voltage of the first scan signal Ngate m is minimal. Therefore, pull-down noise 1, pull-down noise 3, and pull-down noise 5 can be ignored, and the high-level voltages of pull-down noise 1, pull-down noise 3, and pull-down noise 5 can be considered as stable voltages.

[0168] In this embodiment, the voltage of the first scan signal Ngate m is relatively stable between pull-down noise 2 and pull-down noise 4. The voltage of the first scan signal Ngate m is also relatively stable between pull-down noise 4 and pull-down noise 6.

[0169] While meeting the driving requirements of the pixel circuit, the low-level duration of the second scan signal Pgate n can be located between the pull-down noise 2 and pull-down noise 4 of the first scan signal Ngate m, or between the pull-down noise 4 and pull-down noise 6 of the first scan signal Ngate m.

[0170] During the time interval between pull-down noise 2 and pull-down noise 4 of the first scan signal Ngate m, the high-level voltage of the first scan signal Ngate m and the low-level voltage of the second scan signal Pgate n can both be relatively stable. Therefore, scanning the nth row pixel circuit based on the first scan signal Ngate m and the second scan signal Pgate can improve the data writing capability of the nth row pixel circuit.

[0171] The duration of the low level of the second scan signal Pgate n+1 can be located within the same two adjacent pull-down noises as the duration of the low level of the second scan signal Pgate n. For example, when the duration of the low level of the second scan signal Pgate n is located between pull-down noise 2 and pull-down noise 4 of the first scan signal Ngate m, the duration of the low level of the second scan signal Pgate n+1 is also located between pull-down noise 2 and pull-down noise 4 of the first scan signal Ngate m. Similarly, when the duration of the low level of the second scan signal Pgate n is located between pull-down noise 4 and pull-down noise 6 of the first scan signal Ngate m, the duration of the low level of the second scan signal Pgate n+1 is also located between pull-down noise 4 and pull-down noise 6 of the first scan signal Ngate m.

[0172] In this case, the difference between the high-level voltage of the first scan signal Ngate m during the scanning period of the nth row pixel circuit and the high-level voltage of the first scan signal Ngate m during the scanning period of the (n+1)th row pixel circuit is small, which can reduce the brightness difference between odd and even row pixel circuits.

[0173] In some embodiments, the moment when the first scan signal output by the (m+2a)th stage first shift register switches from the first level to the second level is at least 1 hour earlier than the moment when the second scan signal output by the nth stage second shift register switches from the second level to the first level.

[0174] Before the second scan signal output from the nth-stage second shift register switches from the second level to the first level, the first scan signal output from the (m+2a)th-stage first shift register causes pull-down noise in the first scan signal output from the m-th-stage first shift register. The time when the first scan signal output from the (m+2a)th-stage first shift register switches from the first level to the second level is at least 1 hour earlier than the time when the second scan signal output from the nth-stage second shift register switches from the second level to the first level. This ensures that after the pull-down noise caused by the first scan signal output from the (m+2a)th-stage first shift register stabilizes, the second scan signal output from the nth-stage second shift register jumps to a low level. This makes the voltages of both the first and second scan signals of the scanning pixel circuit row relatively stable.

[0175] Referring to Figure 10, when the second scan signal Pgate n is located between the pull-down noise 2 and pull-down noise 4 of the first scan signal Ngate m, the moment when the first scan signal Ngate m+2 switches from low to high level is at least 1 hour earlier than the moment when the second scan signal Pgate n switches from high to low level. After 1 hour, the high-level voltage of the first scan signal Ngate m is in a stable state, and at this time, the output of the second scan signal Pgate n with a low level can ensure the driving effect of the nth row pixel circuit.

[0176] In this embodiment, the first scan signal Ngate m can be output based on the clock signal NCK, and the second scan signal Pgate n can be output based on the clock signal GCK. By adjusting the phase of the clock signal NCK and the phase of the clock signal GCK, the phase difference between the first scan signal Ngate m and the second scan signal Pgate n can be controlled, thereby ensuring that the low-level duration of the second scan signal Pgate n is also within the period between two adjacent pull-down noises of the first scan signal Ngate m.

[0177] For example, by increasing the phase difference between clock signal NCK and clock signal GCK, the phase difference between the first scan signal Ngate m and the second scan signal Pgate n can be increased, thereby increasing the time interval between pull-down noise and the second scan signal Pgate n, thus improving the problem of uneven display brightness in the display panel.

[0178] Figure 11 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure.

[0179] As shown in Figure 11, the display device 1100 includes a display panel 1110, a first driving circuit 1120, a flexible printed circuit (FPC) 1150, and a driving chip 1160.

[0180] In this embodiment, the display panel 1110 and the first driving circuit 1120 can be referred to the display panel 310 and the first driving circuit 320 described above, and will not be repeated for the sake of brevity.

[0181] In this embodiment, the flexible printed circuit board 1150 is connected to the display panel 1110. For example, the flexible printed circuit board 1150 can be bonded to the display panel 1110 using fan-out packaging (FOP) technology. The driver chip 1160 can be bonded to a non-display area of ​​the display panel 1110 using Chip On Pi (COP) technology. For example, the driver chip 1160 can be a display driver integrated circuit (DDIC) or a touch and display driver integration circuit (TDDIC).

[0182] The pixel circuit is located in the display area 1111 of the display panel 1110, and the first driving circuit 1120 is located in the non-display area of ​​the display panel 1110. For example, the first driving circuit 1120 can be located on one side of the display area 1111.

[0183] In this embodiment, the first power trace vgh1 and the second power trace vgh2 are shorted to the same pin on the flexible printed circuit board 1150, and the pin is electrically connected to the driver chip 1160. For example, a transmission line is led out from the pin of the driver chip 1160 and connected to the pin of the flexible printed circuit board 1150. The driver chip 1160 provides a first power supply voltage via the first power trace vgh1 and a second power supply voltage via the second power trace vgh2.

[0184] For example, the first power trace vgh1 and the second power trace vgh2 are connected to the pins of the flexible printed circuit board 1150, and the first power trace vgh1 and the second power trace vgh2 are arranged on the flexible printed circuit board 1150.

[0185] In this embodiment, a first power supply line vgh1 and a second power supply line vgh2 are used to provide power supply voltages to the parity and even stages of the first shift register in the first driving circuit 1120. In the non-display area of ​​the display panel 1110, the first power supply line vgh1 and the second power supply line vgh2 are two independent lines and are merged on the driver chip 1160. This can minimize the influence between the power supply voltages in the first power supply line vgh1 and the second power supply line vgh2, thereby reducing the noise influence between the first scan signals output between adjacent first shift register stages, thus reducing the brightness difference between the high refresh rate area and the high refresh rate transition area in the display panel, and improving the problem of uneven display brightness in the display panel 1110.

[0186] Figure 12 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure.

[0187] As shown in Figure 12, the display device 1200 includes a display panel 1210, a first driving circuit 1220, a flexible printed circuit board 1250, a driving chip 1260, a first capacitor C1, and a second capacitor C2.

[0188] In this embodiment, the display panel 1210, the first driving circuit 1220, the flexible printed circuit board 1250, and the driving chip 1260 can refer to the display panel 1110, the first driving circuit 1120, the flexible printed circuit board 1150, and the driving chip 1160 described above, and will not be repeated for the sake of brevity.

[0189] In this embodiment, a first capacitor C1 and a second capacitor C2 are disposed on a flexible printed circuit board 1250. The first terminal of the first capacitor C1 is electrically connected to a first power supply trace vgh1, and the second terminal of the first capacitor C1 is grounded to GND. The first terminal of the second capacitor C2 is electrically connected to a second power supply trace vgh2, and the second terminal of the second capacitor C2 is grounded to GND.

[0190] In this embodiment of the present disclosure, when the driver chip 1260 charges the first power supply line vgh1 using the first power supply voltage, the first power supply voltage also charges the first capacitor C1, causing the first capacitor C1 to store the first power supply voltage. When the driver chip 1260 charges the second power supply line vgh2 using the second power supply voltage, the second power supply voltage also charges the second capacitor C2, causing the second capacitor C2 to store the second power supply voltage.

[0191] When the odd-numbered stage first shift register drains power from the first power supply trace vgh1, causing instability in the first power supply voltage on vgh1, the first capacitor C1 can discharge to stabilize the first power supply voltage on vgh1. Similarly, when the even-numbered stage first shift register drains power from the second power supply trace vgh2, causing instability in the second power supply voltage on vgh2, the second capacitor C2 can discharge to stabilize the second power supply voltage on vgh2.

[0192] For example, the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 can be the same, and both the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 can be 4.7uF. Based on the display light-emitting area (display area 1211) of the display panel 1210, the load of the first power line vgh1, and the load of the second power line vgh2, capacitors with corresponding capacitances are set. The capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 can also be determined through electrical simulation, thereby achieving voltage regulation on the first power line vgh1 and the second power line vgh2.

[0193] Figure 13 shows a schematic flowchart of a driving method according to an embodiment of the present disclosure.

[0194] As shown in Figure 13, the driving method includes steps S1310 to S1330.

[0195] In the embodiments of this disclosure, the driving method can be applied to the display devices 300, 600, 700, 1100 and 1200 described above.

[0196] In operation S1310, a first power supply voltage is provided to the odd-numbered first shift registers among the plurality of first shift registers via a first power supply trace.

[0197] In operation S1320, a second power supply voltage is provided to the even-numbered first shift registers in a plurality of first shift registers via a second power supply trace.

[0198] During operation S1330, based on the first power supply voltage and the second power supply voltage, multiple first shift registers output multiple first scan signals to the display panel.

[0199] In the embodiments of this disclosure, steps S1310 to S1330 are similar to the operations performed by the display devices 300, 600, 700, 1100 and 1200 described above, and will not be repeated here.

[0200] The block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and combinations of blocks in the block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0201] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0202] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A display device, comprising: Display panel; as well as The first driving circuit is electrically connected to the display panel, the first power supply line, and the second power supply line. The first driving circuit includes a plurality of cascaded first shift registers, the first power supply line is electrically connected to the odd-numbered first shift registers among the plurality of first shift registers, and the second power supply line is electrically connected to the even-numbered first shift registers among the plurality of first shift registers. The plurality of first shift registers are configured to output a plurality of first scan signals to the display panel based on a first power supply voltage provided by the first power supply line and a second power supply voltage provided by the second power supply line.

2. The display device according to claim 1, wherein, It also includes a second driving circuit, which is electrically connected to the display panel. The second driving circuit is configured to output a second scanning signal. The display panel includes pixel circuits. The second scanning signal is used to control data signals to be written to the pixel circuits. Specifically, for scanning a row of pixel circuits in the display panel, the effective level of the second scanning signal is the first level, the effective level of the first scanning signal is the second level, and the time by which the second scanning signal switches from the first level to the second level precedes the time by which the first scanning signal switches from the second level to the first level is greater than or equal to (K-1)*H, where K is the number of pixel circuit rows driven by the first scanning signal, H is the ratio of the display frame rate to the total number of pixel circuit rows in the display panel, and the duration of the effective level of the second scanning signal is 1H.

3. The display device according to claim 1 further includes a third driving circuit, the third driving circuit being electrically connected to the display panel, the third driving circuit being configured to output a reset signal, the reset signal being used to control the driving transistor of the pixel circuit to write an initialization signal; in, The effective level of the reset signal is the first level. For scanning a row of pixel circuits in the display panel, the time by which the first scan signal switches from the first level to the second level is greater than or equal to K*H compared to the time by which the reset signal switches from the first level to the second level. The number of pixel circuit rows driven by the reset signal is K.

4. The display device according to claim 3, wherein, It also includes a second driving circuit, which is electrically connected to the display panel and is configured to output a second scan signal; Specifically, for scanning a row of pixel circuits in the display panel, the time by which the reset signal switches from the first level to the second level is greater than or equal to K*H before the time by which the second scan signal switches from the second level to the first level.

5. The display device according to claim 1 further includes a third driving circuit, the third driving circuit being electrically connected to the display panel, the third driving circuit being configured to output a reset signal, the reset signal being used to control the writing of an initialization signal into the driving transistor of the pixel circuit; in, The effective level of the reset signal is the first level. For scanning a row of pixel circuits in the display panel, the moment when the first scan signal switches from the first level to the second level is not earlier than the start time of the first level of the reset signal.

6. The display device according to claim 2, wherein, The first driving circuit includes M cascaded first shift registers, and the second driving circuit includes N cascaded second shift registers, where M and N are positive integers; The moment when the first scan signal output from the first shift register of the (m+2a)th stage switches from the first level to the second level is earlier than the moment when the second scan signal output from the second shift register of the nth stage switches from the second level to the first level; The moment when the second scan signal output by the nth stage second shift register switches from the first level to the second level is earlier than the moment when the first scan signal output by the m+2a+2th stage first shift register switches from the first level to the second level; Wherein, 1≤m≤M-2a-2, 1≤n≤N, and a is a positive integer; the first scan signal output by the m-th level first shift register and the second scan signal output by the n-th level second shift register are used to drive the same pixel circuit row; during the duration of the second level of the first scan signal output by the m-th level first shift register, the first scan signal output by the (m+2a)-th level first shift register jumps from the first level to the second level, and the first scan signal output by the (m+2a+2)-th level first shift register jumps from the first level to the second level.

7. The display device according to claim 6, wherein, The moment when the first scan signal output by the (m+2a)th stage first shift register switches from the first level to the second level is at least 1 hour earlier than the moment when the second scan signal output by the nth stage second shift register switches from the second level to the first level.

8. The display device according to claim 1 further includes a flexible printed circuit board, the flexible printed circuit board being connected to the display panel; The first power trace and the second power trace are shorted to the same pin on the flexible printed circuit board. The pin is electrically connected to the driver chip. The driver chip provides a first power supply voltage via the first power trace and a second power supply voltage via the second power trace.

9. The display device according to claim 8 further includes a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor are disposed on the flexible printed circuit board; The first terminal of the first capacitor is electrically connected to the first power supply line, and the second terminal of the first capacitor is grounded. The first terminal of the second capacitor is electrically connected to the second power supply line, and the second terminal of the second capacitor is grounded.

10. The display device according to claim 2, wherein, The first driving circuit is electrically connected to the first clock terminal, and the second driving circuit is electrically connected to the second clock terminal; The first driving circuit is configured to output the first scan signal under the control of a first clock signal from the first clock terminal; The second driving circuit is configured to output the second scan signal under the control of a second clock signal from the second clock terminal; Within one clock cycle, the duration of the effective level of the first clock signal is K times the duration of the effective level of the second clock signal.

11. The display device according to any one of claims 1-10, wherein, Among the plurality of first shift registers, there exists a period during which the first scan signal output by the previous first shift register and the first scan signal output by the next first shift register are simultaneously at an effective level.

12. A driving method applied to the display device according to any one of claims 1-11, comprising: The first power supply voltage is provided to the odd-numbered first shift registers among the plurality of first shift registers via the first power supply trace; The second power supply voltage is provided to the even-numbered first shift registers among the plurality of first shift registers via the second power supply trace; Based on the first power supply voltage and the second power supply voltage, the plurality of first shift registers output a plurality of first scan signals to the display panel.

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