Pixel circuit, pixel driving method and display apparatus

Abstract

A pixel circuit, a pixel driving method and a display apparatus. The pixel circuit comprises a light-emitting element (E1), a driving circuit (10), a first light emission control circuit (11), a first reset circuit (12), a data writing circuit (13) and a first energy storage circuit (14), wherein a driving transistor comprised in the driving circuit (10) is an n-type transistor, and at least one of a transistor comprised in the first light emission control circuit (11), a transistor comprised in the first reset circuit (12) and a transistor comprised in the data writing circuit (13) is a p-type transistor.

Description

Pixel circuits, pixel driving methods, and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method, and a display device. Background Technology

[0002] In related technologies, each transistor in the pixel circuit can be an NMOS (N-type metal-oxide-semiconductor) transistor, or an oxide transistor. Because oxide transistors have poor stability and low mobility, each transistor can be configured as a dual-gate transistor. The first gate of the transistor can be formed on a second gate metal layer, and the second gate can be formed on a third gate metal layer. The signal line electrically connected to the first and second gates of the transistor can be formed on the source-drain metal layer. This signal line is electrically connected to the first and second gates of the transistor through vias, resulting in a large capacitance on the signal line. The related display devices have complex layouts and poor brightness uniformity.

[0003] Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a pixel circuit, including a light-emitting element, a driving circuit, a first light-emitting control circuit, a first reset circuit, a data writing circuit, and a first energy storage circuit;

[0005] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node.

[0006] The first light-emitting control circuit is electrically connected to the first light-emitting control line, the first voltage terminal, and the second node, respectively, and is used to control the connection or disconnection between the first voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control line.

[0007] The first reset circuit is electrically connected to the first reset control line, the first initial voltage line and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage line into the first node under the control of the first reset control signal provided by the first reset control line.

[0008] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the fourth node.

[0009] The data writing circuit is electrically connected to the first scan line, the data line and the fourth node respectively, and is used to write the data voltage provided by the data line into the fourth node under the control of the first scan signal provided by the first scan line.

[0010] The driving circuit includes an n-type driving transistor, and at least one of the transistors in the first light-emitting control circuit, the first reset circuit, and the data writing circuit is a p-type transistor.

[0011] Optionally, the driving transistor is a dual-gate transistor, and at least one of the transistors included in the first light-emitting control circuit, the first reset circuit, and the data writing circuit is a single-gate transistor.

[0012] The pixel circuit described in at least one embodiment of this disclosure further includes a second reset circuit;

[0013] The second reset circuit is electrically connected to the second reset control line, the first node, and the second node, respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the second reset control signal provided by the second reset control line.

[0014] Optionally, the transistor included in the second reset circuit is a p-type transistor, or the transistor included in the second reset circuit is a single-gate transistor.

[0015] Optionally, the transistors included in the first reset circuit and the second reset circuit are both n-type transistors; or, the transistors included in the first reset circuit and the second reset circuit are both p-type transistors.

[0016] The first reset control signal and the second reset control signal are provided by the same GOA module.

[0017] The pixel circuit described in at least one embodiment of this disclosure further includes a second light-emitting control circuit and an on / off control circuit;

[0018] The second light-emitting control circuit is electrically connected to the second light-emitting control line, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control line; the second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0019] The on / off control circuit is electrically connected to the second scan line, the fourth node, and the third node, respectively, and is used to control the connection or disconnection between the fourth node and the third node under the control of the second scan signal provided by the second scan line.

[0020] Optionally, at least one of the transistors included in the second light-emitting control circuit and the transistors included in the on / off control circuit is a p-type transistor, and at least one of the transistors included in the second light-emitting control circuit and the transistors included in the on / off control circuit is a single-gate transistor.

[0021] The pixel circuit described in at least one embodiment of this disclosure further includes a third reset circuit;

[0022] The third reset circuit is electrically connected to the third reset control line and the second initial voltage line respectively. The third reset circuit is also electrically connected to the third node or the first electrode of the light-emitting element. The third reset circuit is used to write the second initial voltage provided by the second initial voltage line into the third node or the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control line.

[0023] Optionally, the transistor included in the third reset circuit is a p-type transistor, and the transistor included in the third reset circuit is a single-gate transistor.

[0024] The pixel circuit described in at least one embodiment of this disclosure further includes a second energy storage circuit;

[0025] The first end of the second energy storage circuit is electrically connected to the fourth node, and the second end of the second energy storage circuit is electrically connected to the third node.

[0026] Optionally, the transistors included in the on / off control circuit and the transistors included in the third reset circuit are both n-type transistors, or the transistors included in the on / off control circuit and the transistors included in the third reset circuit are both p-type transistors.

[0027] The second scan signal provided by the second scan line and the third reset control signal provided by the third reset control line are provided by the same GOA module.

[0028] Optionally, the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both n-type transistors; or, the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both p-type transistors.

[0029] The first light emission control signal and the second light emission control signal are provided by the same GOA module.

[0030] Optionally, the transistors included in the on / off control circuit are p-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both n-type transistors; or, the transistors included in the on / off control circuit are n-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both p-type transistors.

[0031] The on / off control signal, the first light emission control signal, and the second light emission control signal are provided by the same GOA module.

[0032] Optionally, the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both p-type transistors, and the transistors included in the third reset circuit are n-type transistors; or, the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both n-type transistors, and the transistors included in the third reset circuit are p-type transistors.

[0033] The first light emission control signal, the second light emission control signal, and the third reset control signal are provided by the same GOA module.

[0034] Optionally, the transistors included in the on / off control circuit and the third reset circuit are p-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are n-type transistors; or, the transistors included in the on / off control circuit and the third reset circuit are n-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are p-type transistors.

[0035] The on / off control signal, the third reset control signal, the first light emission control signal, and the second light emission control signal are provided by the same GOA module.

[0036] Optionally, the transistors included in the first reset circuit and the second reset transistor are both n-type transistors; or, the transistors included in the first reset circuit and the second reset transistor are both p-type transistors.

[0037] The first reset control signal and the second reset control signal are provided by the same GOA module.

[0038] Optionally, the transistors included in the first reset circuit, the second reset transistor, and the on / off control circuit are all n-type transistors; or, the transistors included in the first reset circuit, the second reset transistor, and the on / off control circuit are all p-type transistors.

[0039] The first reset control signal, the second reset control signal, and the on / off control signal are provided by the same GOA module.

[0040] Optionally, the second light-emitting control circuit includes a p-type transistor, and the third reset circuit includes an n-type transistor; or, the second light-emitting control circuit includes an n-type transistor, and the third reset circuit includes a p-type transistor.

[0041] The second light emission control signal and the third reset control signal are provided by the same GOA module.

[0042] Optionally, the third reset circuit is electrically connected to the first electrode of the light-emitting element; the pixel circuit further includes a fourth reset circuit;

[0043] The fourth reset circuit is electrically connected to the fourth reset control line, the third initial voltage line, and the reset node, respectively, and is used to write the third initial voltage provided by the third initial voltage line into the reset node under the control of the fourth reset control signal provided by the fourth reset control line.

[0044] The reset node includes a second node and / or a third node.

[0045] In a second aspect, embodiments of this disclosure provide a pixel driving method applied to the aforementioned pixel circuit, the pixel driving method comprising:

[0046] The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node;

[0047] The first light-emitting control circuit, under the control of the first light-emitting control signal, controls the connection or disconnection between the first voltage terminal and the second node;

[0048] The first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first node;

[0049] Under the control of the first scan signal, the data writing circuit writes the data voltage provided by the data line to the fourth node.

[0050] Optionally, the pixel circuit further includes a second reset circuit; the display cycle of the pixel circuit includes a reset phase and a compensation phase; there is an overlapping time period between the reset phase and the compensation phase; the pixel driving method includes:

[0051] During the reset phase, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first node;

[0052] During the compensation phase, the second reset circuit, under the control of the second reset control signal, controls the connection between the first node and the second node;

[0053] During the overlapping time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first node; the second reset circuit, under the control of the second reset control signal, controls the connection between the first node and the second node to write the first initial voltage into the second node.

[0054] Optionally, the pixel circuit further includes an on / off control circuit and a third reset circuit; the pixel driving method includes:

[0055] During the reset phase and the compensation phase, the on / off control circuit, under the control of the second scan signal, controls the connection between the fourth node and the third node; the third reset circuit, under the control of the third reset control signal, writes the second initial voltage into the third node or the first electrode of the light-emitting element.

[0056] Optionally, the display cycle further includes a write phase set after the compensation phase; the pixel driving method includes:

[0057] During the writing phase, the data writing circuit, under the control of the first scan signal, writes the data voltage to the fourth node.

[0058] Optionally, in low-frequency display, the display period is a refresh frame, the pixel circuit includes a fourth reset circuit; the holding frame includes a holding reset phase; the pixel driving method further includes:

[0059] During the hold reset phase, the fourth reset circuit, under the control of the fourth reset control signal, writes the third initial voltage into the second node and / or the third node.

[0060] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above. Attached Figure Description

[0061] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0062] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0063] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0064] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0065] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0066] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0067] Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0068] Figure 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0069] Figure 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0070] Figure 10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0071] Figure 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0072] Figure 12 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0073] Figure 13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0074] Figure 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0075] Figure 15 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 14;

[0076] Figure 16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0077] Figure 17 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 16;

[0078] Figure 18 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] Figure 19 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 18;

[0080] Figure 20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0081] Figure 21 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 20;

[0082] Figure 22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0083] Figure 23 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 22;

[0084] Figure 24 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0085] Figure 25 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 24;

[0086] Figure 26 is a layout diagram of at least one embodiment of the pixel circuit shown in Figure 9;

[0087] Figure 27 is a layout diagram of the first semiconductor layer in Figure 26;

[0088] Figure 28 is a layout diagram of the first gate metal layer in Figure 26;

[0089] Figure 29 is a layout diagram of the second gate metal layer in Figure 26;

[0090] Figure 30 is a layout diagram of the second semiconductor layer in Figure 26;

[0091] Figure 31 is a layout diagram of the third gate metal layer in Figure 26;

[0092] Figure 32 is a layout diagram of the first source / drain metal layer in Figure 26;

[0093] Figure 33 is a stack-up diagram of the first semiconductor layer and the first gate metal layer in Figure 26;

[0094] Figure 34 is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 26;

[0095] Figure 35 is a stack-up diagram of the second gate metal layer and the second semiconductor layer in Figure 26;

[0096] Figure 36 is a stack-up diagram of the second gate metal layer and the third gate metal layer in Figure 26;

[0097] Figure 37 is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 26;

[0098] Figure 38 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0099] Figure 39 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 38;

[0100] Figure 40 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0101] Figure 41 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0102] Figure 42 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0103] Figure 43 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Detailed Implementation

[0104] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0105] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0106] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0107] As shown in Figure 1, the pixel circuit described in this embodiment includes a light-emitting element E1, a driving circuit 10, a first light-emitting control circuit 11, a first reset circuit 12, a data writing circuit 13, and a first energy storage circuit 14.

[0108] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0109] The first light-emitting control circuit 11 is electrically connected to the first light-emitting control line EM1, the first voltage terminal V1 and the second node N2 respectively, and is used to control the connection or disconnection between the first voltage terminal V1 and the second node N2 under the control of the first light-emitting control signal provided by the first light-emitting control line EM1.

[0110] The first reset circuit 12 is electrically connected to the first reset control line R1, the first initial voltage line I1 and the first node N1 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage line I1 into the first node N1 under the control of the first reset control signal provided by the first reset control line R1.

[0111] The first terminal of the first energy storage circuit 14 is electrically connected to the first node N1, and the second terminal of the first energy storage circuit 14 is electrically connected to the fourth node N4.

[0112] The data writing circuit 13 is electrically connected to the first scan line GT, the data line DL and the fourth node N4 respectively, and is used to write the data voltage provided by the data line DL into the fourth node N4 under the control of the first scan signal provided by the first scan line GT.

[0113] The driving circuit 10 includes an n-type driving transistor, and at least one of the transistors in the first light-emitting control circuit 11, the first reset circuit 12, and the data writing circuit 13 is a p-type transistor.

[0114] Optionally, the first voltage terminal can be a power supply voltage line.

[0115] In at least one embodiment of this disclosure, at least one of the transistors included in the first light-emitting control circuit 11, the first reset circuit 12, and the data writing circuit 13 can be configured as p-type transistors to optimize layout space and reduce signal line capacitance.

[0116] In at least one embodiment of this disclosure, the driving transistor is a dual-gate transistor, and at least one of the transistors included in the first light-emitting control circuit, the first reset circuit, and the data writing circuit is a single-gate transistor.

[0117] In related technologies, each transistor in a pixel circuit can be an NMOS (N-type metal-oxide-semiconductor) transistor, and each transistor can be an oxide transistor. Since oxide transistors have poor characteristic stability and low mobility, each transistor can be configured as a dual-gate transistor. The first gate of the transistor can be formed on a second gate metal layer, and the second gate of the transistor can be formed on a third gate metal layer. A signal line electrically connected to the first and second gates of the transistor can be formed on a source-drain metal layer. This signal line is electrically connected to the first and second gates of the transistor through a via, therefore the capacitance on this signal line is large. In at least one embodiment of this disclosure, the first light-emitting control circuit includes a crystal... At least one of the transistors in the body tube, the first reset circuit, and the data writing circuit is configured as a p-type transistor. At least one of the transistors in the first light-emitting control circuit, the first reset circuit, and the data writing circuit is configured as a single-gate transistor. The gates of the transistors in the first light-emitting control circuit, the first reset circuit, and the data writing circuit can be formed on the first gate metal layer. The signal line electrically connected to the gate of the p-type transistor can also be formed on the first gate metal layer. The signal line can include the gate of the p-type transistor to optimize the layout space, reduce the capacitance of the signal line, and improve the uniformity of display brightness.

[0118] The pixel circuit described in at least one embodiment of this disclosure further includes a second reset circuit;

[0119] The second reset circuit is electrically connected to the second reset control line, the first node, and the second node, respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the second reset control signal provided by the second reset control line.

[0120] Optionally, the transistor included in the second reset circuit is a p-type transistor, or the transistor included in the second reset circuit is a single-gate transistor.

[0121] As shown in Figure 2, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a second reset circuit 21;

[0122] The second reset circuit 21 is electrically connected to the second reset control line R2, the first node N1 and the second node N2 respectively, and is used to control the connection or disconnection between the first node N1 and the second node N2 under the control of the second reset control signal provided by the second reset control line R2.

[0123] In specific implementation, the transistors included in the second reset circuit 21 can be set as p-type transistors or as single-gate transistors, so as to optimize the layout space and reduce the signal line capacitance.

[0124] In at least one embodiment of this disclosure, the transistors included in the first reset circuit and the second reset circuit are both n-type transistors; or, the transistors included in the first reset circuit and the second reset circuit are both p-type transistors.

[0125] The first reset control signal and the second reset control signal are provided by the same GOA module.

[0126] In specific implementation, the transistors included in the first reset circuit and the transistors included in the second reset circuit can be set to the same type of transistors. The first reset control signal and the second reset control signal can be provided by the same GOA (Gate Driver On Array) module to reduce the number of GOA modules used in the display device and facilitate the realization of narrow bezels.

[0127] The pixel circuit described in at least one embodiment of this disclosure further includes a second light-emitting control circuit and an on / off control circuit;

[0128] The second light-emitting control circuit is electrically connected to the second light-emitting control line, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control line; the second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0129] The on / off control circuit is electrically connected to the second scan line, the fourth node, and the third node, respectively, and is used to control the connection or disconnection between the fourth node and the third node under the control of the second scan signal provided by the second scan line.

[0130] In at least one embodiment of this disclosure, at least one of the transistors included in the second light-emitting control circuit and the transistors included in the on / off control circuit is a p-type transistor, and at least one of the transistors included in the second light-emitting control circuit and the transistors included in the on / off control circuit is a single-gate transistor.

[0131] Optionally, the second voltage terminal can be a low voltage terminal.

[0132] As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit of at least one embodiment of this disclosure further includes a second light-emitting control circuit 31 and an on / off control circuit 32.

[0133] The second light-emitting control circuit 31 is electrically connected to the second light-emitting control line EM2, the third node N3, and the first pole of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the third node N3 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control line EM2; the second pole of the light-emitting element E1 is electrically connected to the second voltage terminal V2.

[0134] The on / off control circuit 32 is electrically connected to the second scan line GT2, the fourth node N4 and the third node N3 respectively, and is used to control the connection or disconnection between the fourth node N4 and the third node N3 under the control of the second scan signal provided by the second scan line GT2.

[0135] In at least one embodiment of the pixel circuit shown in Figure 3, at least one of the transistors included in the second light emission control circuit and the transistors included in the on / off control circuit can be configured as p-type transistors, and at least one of the transistors included in the second light emission control circuit and the transistors included in the on / off control circuit can be configured as single-gate transistors, so as to optimize the layout space and reduce the signal line capacitance.

[0136] The pixel circuit described in at least one embodiment of this disclosure further includes a third reset circuit;

[0137] The third reset circuit is electrically connected to the third reset control line and the second initial voltage line respectively. The third reset circuit is also electrically connected to the third node or the first electrode of the light-emitting element. The third reset circuit is used to write the second initial voltage provided by the second initial voltage line into the third node or the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control line.

[0138] Optionally, the transistor included in the third reset circuit is a p-type transistor, and the transistor included in the third reset circuit is a single-gate transistor.

[0139] As shown in FIG4, in at least one embodiment of the pixel circuit shown in FIG3, the pixel circuit of at least one embodiment of the present disclosure further includes a third reset circuit 33;

[0140] The third reset circuit 33 is electrically connected to the third reset control line R3 and the second initial voltage line I2, respectively. The third reset circuit 33 is also electrically connected to the third node N3. The third reset circuit 33 is used to write the second initial voltage Vinit2 provided by the second initial voltage line I2 into the third node N3 under the control of the third reset control signal provided by the third reset control line R3.

[0141] In at least one embodiment of the pixel circuit shown in Figure 4, the transistors included in the third reset circuit 33 can be configured as p-type transistors or as single-gate transistors to optimize layout space and reduce signal line capacitance.

[0142] As shown in FIG5, in at least one embodiment of the pixel circuit shown in FIG3, the pixel circuit of at least one embodiment of the present disclosure further includes a third reset circuit 33;

[0143] The third reset circuit 33 is electrically connected to the third reset control line R3 and the second initial voltage line I2, respectively. The third reset circuit 33 is also electrically connected to the first pole of the light-emitting element E1. The third reset circuit 33 is used to write the second initial voltage Vinit2 provided by the second initial voltage line I2 into the first pole of the light-emitting element E1 under the control of the third reset control signal provided by the third reset control line R3.

[0144] In at least one embodiment of the pixel circuit shown in FIG5, the transistors included in the third reset circuit 33 can be configured as p-type transistors or as single-gate transistors, so as to optimize the layout space and reduce the signal line capacitance.

[0145] The pixel circuit described in at least one embodiment of this disclosure further includes a second energy storage circuit;

[0146] The first end of the second energy storage circuit is electrically connected to the fourth node, and the second end of the second energy storage circuit is electrically connected to the third node.

[0147] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 4, the pixel circuit of at least one embodiment of this disclosure further includes a second energy storage circuit 30;

[0148] The first end of the second energy storage circuit 30 is electrically connected to the fourth node N4, and the second end of the second energy storage circuit 30 is electrically connected to the third node N3.

[0149] As shown in Figure 7, based on at least one embodiment of the pixel circuit shown in Figure 5, the pixel circuit of at least one embodiment of this disclosure further includes a second energy storage circuit 30;

[0150] The first end of the second energy storage circuit 30 is electrically connected to the fourth node N4, and the second end of the second energy storage circuit 30 is electrically connected to the third node N3.

[0151] In at least one embodiment of this disclosure, the transistors included in the on / off control circuit and the transistors included in the third reset circuit are both n-type transistors, or the transistors included in the on / off control circuit and the transistors included in the third reset circuit are both p-type transistors.

[0152] The second scan signal provided by the second scan line and the third reset control signal provided by the third reset control line are provided by the same GOA module.

[0153] In practical implementation, the transistors included in the on / off control circuit and the transistors included in the third reset circuit can be set to the same type of transistors. The second scan signal and the third reset control signal can be provided by the same GOA module to reduce the number of GOA modules used in the display device and facilitate the realization of a narrow bezel.

[0154] In at least one embodiment of this disclosure, the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both n-type transistors; or, the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both p-type transistors.

[0155] The first light emission control signal and the second light emission control signal are provided by the same GOA module.

[0156] In specific implementation, the transistors included in the first light-emitting control circuit and the transistors included in the second light-emitting control circuit can be set to the same type of transistors. The first light-emitting control signal and the second light-emitting control signal can be provided by the same GOA module to reduce the number of GOA modules used in the display device and facilitate the realization of a narrow bezel.

[0157] In at least one embodiment of this disclosure, the transistor included in the on / off control circuit is a p-type transistor, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both n-type transistors; or, the transistor included in the on / off control circuit is an n-type transistor, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both p-type transistors.

[0158] The on / off control signal, the first light emission control signal, and the second light emission control signal are provided by the same GOA module.

[0159] In specific implementation, the transistors included in the on / off control circuit can be configured as p-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit can be configured as n-type transistors; or, the transistors included in the on / off control circuit can be configured as n-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit can be configured as p-type transistors. In this case, the on / off control signal, the first light-emitting control signal, and the second light-emitting control signal can be provided by the same GOA module to reduce the number of GOA modules used in the display device and facilitate the realization of a narrow bezel.

[0160] In at least one embodiment of this disclosure, the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both p-type transistors, and the transistors included in the third reset circuit are n-type transistors; or, the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both n-type transistors, and the transistors included in the third reset circuit are p-type transistors.

[0161] The first light emission control signal, the second light emission control signal, and the third reset control signal are provided by the same GOA module.

[0162] In specific implementation, the transistors included in the first light-emitting control circuit and the second light-emitting control circuit can be configured as p-type transistors, and the transistors included in the third reset circuit can be configured as n-type transistors; or, the transistors included in the first light-emitting control circuit and the second light-emitting control circuit can be configured as n-type transistors, and the transistors included in the third reset circuit can be configured as p-type transistors. In this case, the first light-emitting control signal, the second light-emitting control signal, and the third reset control signal can be provided by the same GOA module to reduce the number of GOA modules used in the display device and facilitate the realization of a narrow bezel.

[0163] In at least one embodiment of this disclosure, the transistors included in the on / off control circuit and the third reset circuit are p-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are n-type transistors; or, the transistors included in the on / off control circuit and the third reset circuit are n-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are p-type transistors.

[0164] The on / off control signal, the third reset control signal, the first light emission control signal, and the second light emission control signal are provided by the same GOA module.

[0165] In specific implementation, the transistors included in the on / off control circuit and the third reset circuit can be configured as p-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit can be configured as n-type transistors; or, the transistors included in the on / off control circuit and the third reset circuit can be configured as n-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit can be configured as p-type transistors. In this case, the on / off control signal, the third reset control signal, the first light-emitting control signal, and the second light-emitting control signal can be provided by the same GOA module to reduce the number of GOA modules used in the display device and facilitate the realization of a narrow bezel.

[0166] In at least one embodiment of this disclosure, the transistors included in the first reset circuit and the second reset transistor are both n-type transistors; or, the transistors included in the first reset circuit and the second reset transistor are both p-type transistors.

[0167] The first reset control signal and the second reset control signal are provided by the same GOA module.

[0168] In specific implementation, the transistors included in the first reset circuit and the transistors included in the second reset transistor can be set to the same type of transistors. The first reset control signal and the second reset control signal are provided by the same GOA module to reduce the number of GOA modules used in the display device, which is beneficial to achieving a narrow bezel.

[0169] In at least one embodiment of this disclosure, the transistor included in the first reset circuit, the transistor included in the second reset transistor, and the transistor included in the on / off control circuit are all n-type transistors; or, the transistor included in the first reset circuit, the transistor included in the second reset transistor, and the transistor included in the on / off control circuit are all p-type transistors.

[0170] The first reset control signal, the second reset control signal, and the on / off control signal are provided by the same GOA module.

[0171] In specific implementation, the transistors included in the first reset circuit, the second reset transistor, and the on / off control circuit can be set to the same type of transistor. The first reset control signal, the second reset control signal, and the on / off control signal can be provided by the same GOA module to reduce the number of GOA modules used in the display device and facilitate the realization of a narrow bezel.

[0172] In at least one embodiment of this disclosure, the second light-emitting control circuit includes a p-type transistor, and the third reset circuit includes an n-type transistor; or, the second light-emitting control circuit includes an n-type transistor, and the third reset circuit includes a p-type transistor.

[0173] The second light emission control signal and the third reset control signal are provided by the same GOA module.

[0174] In practical implementation, the transistors included in the second light-emitting control circuit and the transistors included in the third reset circuit can be set to different types of transistors. The second light-emitting control signal and the third reset control signal can be provided by the same GOA module to reduce the number of GOA modules used in the display device and facilitate the realization of a narrow bezel.

[0175] In at least one embodiment of this disclosure, the third reset circuit is electrically connected to the first electrode of the light-emitting element; the pixel circuit further includes a fourth reset circuit;

[0176] The fourth reset circuit is electrically connected to the fourth reset control line, the third initial voltage line, and the reset node, respectively, and is used to write the third initial voltage provided by the third initial voltage line into the reset node under the control of the fourth reset control signal provided by the fourth reset control line.

[0177] The reset node includes a second node and / or a third node.

[0178] In a specific implementation, the pixel circuit may further include a fourth reset circuit. During low-frequency display, in the hold reset phase of the hold frame, the fourth reset circuit may, under the control of the fourth reset control signal, write a third initial voltage into the second node and / or the third node to improve the hysteresis phenomenon of the drive transistor included in the drive circuit.

[0179] As shown in Figure 8, based on at least one embodiment of the pixel circuit shown in Figure 7, the pixel circuit further includes a fourth reset circuit 34;

[0180] The fourth reset circuit 34 is electrically connected to the fourth reset control line R4, the third initial voltage line I3 and the third node N3 respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage line I3 into the third node N3 under the control of the fourth reset control signal provided by the fourth reset control line R4.

[0181] When the pixel circuit does not include the fourth reset circuit 34, during the hold reset phase of the hold frame, the second initial voltage provided by the second initial voltage line is written to the third node through the third reset circuit and the second light emission control circuit to improve the hysteresis phenomenon of the driving transistor. However, when the display refresh frequency changes, the voltage value of the second initial voltage may be adjusted accordingly. Thus, during the hold reset phase of the hold frame, when the third node is reset by the second initial voltage, the potential of the first node will be changed through the coupling of the first energy storage circuit and the second energy storage circuit, resulting in a change in brightness. Therefore, at least one embodiment of this disclosure can employ the fourth reset circuit 34 to write the second initial voltage to the third node or the second node during the hold reset phase of the hold frame to improve the hysteresis phenomenon of the driving transistor.

[0182] As shown in Figure 9, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0; the first light-emitting control circuit includes a first transistor T1; the first reset circuit includes a second transistor T2; the data writing circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1; the second reset circuit includes a fourth transistor T4; the second energy storage circuit includes a second capacitor C2; the second light-emitting control circuit includes a fifth transistor T5; the on / off control circuit includes a sixth transistor T6; and the third reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0183] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0184] The gate of T1 is electrically connected to the first light-emitting control line EM1, the source of T1 is electrically connected to the power supply voltage line VDD, and the drain of T1 is electrically connected to the second node N2.

[0185] The gate of T2 is electrically connected to the first reset control line R1, the source of T2 is electrically connected to the first initial voltage line I1, and the drain of T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide the first initial voltage Vinit1.

[0186] The gate of T3 is electrically connected to the first scan line GT, the source of T3 is electrically connected to the data line DL, and the drain of T3 is electrically connected to the fourth node N4.

[0187] The first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the fourth node N4;

[0188] The gate of T4 is electrically connected to the second reset control line R2, the source of T4 is electrically connected to the first node N1, and the drain of T4 is electrically connected to the second node N2.

[0189] The gate of T5 is electrically connected to the second light-emitting control line EM2, the drain of T5 is electrically connected to the third node N3, the source of T5 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0190] The gate of T6 is electrically connected to the second scan line GT2, the source of T6 is electrically connected to the fourth node N4, and the drain of T6 is electrically connected to the third node N3.

[0191] The gate of T7 is electrically connected to the third reset control line R3, the source of T7 is electrically connected to the second initial voltage line I2, and the drain of T7 is electrically connected to the third node N3.

[0192] In at least one embodiment shown in Figure 9, the first voltage terminal is the power supply voltage line VDD, and the second voltage terminal is the low voltage terminal;

[0193] T5 is a PMOS (P-type metal-oxide-semiconductor) transistor, and T5 is a single-gate transistor;

[0194] T0, T1, T2, T3, T4, T6, and T7 are NMOS transistors, while T0, T1, T2, T3, T4, T6, and T7 are dual-gate transistors.

[0195] In at least one embodiment shown in Figure 9, setting T5 as a PMOS transistor or a single-gate transistor can optimize the layout space, reduce the capacitance on the second light-emitting control line EM2, and improve brightness uniformity.

[0196] In at least one embodiment shown in Figure 9, the voltage value of the first initial voltage Vinit1 provided by I1 can be greater than or equal to 2V and less than or equal to 3.5V, and the voltage value of the second initial voltage Vinit2 provided by I2 can be less than 0.5V, but is not limited thereto.

[0197] As shown in Figure 10, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0; the first light-emitting control circuit includes a first transistor T1; the first reset circuit includes a second transistor T2; the data writing circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1; the second reset circuit includes a fourth transistor T4; the second energy storage circuit includes a second capacitor C2; the second light-emitting control circuit includes a fifth transistor T5; the on / off control circuit includes a sixth transistor T6; and the third reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0198] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0199] The gate of T1 is electrically connected to the first light-emitting control line EM1, the drain of T1 is electrically connected to the power supply voltage line VDD, and the source of T1 is electrically connected to the second node N2.

[0200] The gate of T2 is electrically connected to the first reset control line R1, the source of T2 is electrically connected to the first initial voltage line I1, and the drain of T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide the first initial voltage Vinit1.

[0201] The gate of T3 is electrically connected to the first scan line GT, the source of T3 is electrically connected to the data line DL, and the drain of T3 is electrically connected to the fourth node N4.

[0202] The first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the fourth node N4;

[0203] The gate of T4 is electrically connected to the second reset control line R2, the source of T4 is electrically connected to the first node N1, and the drain of T4 is electrically connected to the second node N2.

[0204] The gate of T5 is electrically connected to the second light-emitting control line EM2, the source of T5 is electrically connected to the third node N3, the drain of T5 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0205] The gate of T6 is electrically connected to the second scan line GT2, the source of T6 is electrically connected to the fourth node N4, and the drain of T6 is electrically connected to the third node N3.

[0206] The gate of T7 is electrically connected to the third reset control line R3, the source of T7 is electrically connected to the second initial voltage line I2, and the drain of T7 is electrically connected to the third node N3.

[0207] In at least one embodiment shown in Figure 10, the first voltage terminal is the power supply voltage line VDD, and the second voltage terminal is the low voltage terminal;

[0208] T1 is a PMOS (P-type metal-oxide-semiconductor) transistor, and T1 is a single-gate transistor;

[0209] T0, T2, T3, T4, T5, T6, and T7 are NMOS transistors, while T0, T2, T3, T4, T5, T6, and T7 are dual-gate transistors.

[0210] In at least one embodiment shown in Figure 10, setting T1 as a PMOS transistor or a single-gate transistor can optimize the layout space, reduce the capacitance on the first light-emitting control line EM1, and improve brightness uniformity.

[0211] As shown in Figure 11, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0; the first light-emitting control circuit includes a first transistor T1; the first reset circuit includes a second transistor T2; the data writing circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1; the second reset circuit includes a fourth transistor T4; the second energy storage circuit includes a second capacitor C2; the second light-emitting control circuit includes a fifth transistor T5; the on / off control circuit includes a sixth transistor T6; and the third reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0212] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0213] The gate of T1 is electrically connected to the first light-emitting control line EM1, the source of T1 is electrically connected to the power supply voltage line VDD, and the drain of T1 is electrically connected to the second node N2.

[0214] The gate of T2 is electrically connected to the first reset control line R1, the source of T2 is electrically connected to the first initial voltage line I1, and the drain of T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide the first initial voltage Vinit1.

[0215] The gate of T3 is electrically connected to the first scan line GT, the drain of T3 is electrically connected to the data line DL, and the source of T3 is electrically connected to the fourth node N4.

[0216] The first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the fourth node N4;

[0217] The gate of T4 is electrically connected to the second reset control line R2, the source of T4 is electrically connected to the first node N1, and the drain of T4 is electrically connected to the second node N2.

[0218] The gate of T5 is electrically connected to the second light-emitting control line EM2, the source of T5 is electrically connected to the third node N3, the drain of T5 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0219] The gate of T6 is electrically connected to the second scan line GT2, the source of T6 is electrically connected to the fourth node N4, and the drain of T6 is electrically connected to the third node N3.

[0220] The gate of T7 is electrically connected to the third reset control line R3, the source of T7 is electrically connected to the second initial voltage line I2, and the drain of T7 is electrically connected to the third node N3.

[0221] In at least one embodiment shown in Figure 11, the first voltage terminal is the power supply voltage line VDD, and the second voltage terminal is the low voltage terminal;

[0222] T3 is a PMOS (P-type metal-oxide-semiconductor) transistor, and T3 is a single-gate transistor;

[0223] T0, T1, T2, T4, T5, T6, and T7 are NMOS transistors, while T0, T1, T2, T4, T5, T6, and T7 are dual-gate transistors.

[0224] In at least one embodiment shown in Figure 11, setting T3 as a PMOS transistor or a single-gate transistor can optimize the layout space, reduce the capacitance on the first scan line GT, improve the data voltage write current, and improve the data voltage write efficiency.

[0225] As shown in Figure 12, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0; the first light-emitting control circuit includes a first transistor T1; the first reset circuit includes a second transistor T2; the data writing circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1; the second reset circuit includes a fourth transistor T4; the second energy storage circuit includes a second capacitor C2; the second light-emitting control circuit includes a fifth transistor T5; the on / off control circuit includes a sixth transistor T6; and the third reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0226] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0227] The gate of T1 is electrically connected to the first light-emitting control line EM1, the source of T1 is electrically connected to the power supply voltage line VDD, and the drain of T1 is electrically connected to the second node N2.

[0228] The gate of T2 is electrically connected to the first reset control line R1, the source of T2 is electrically connected to the first initial voltage line I1, and the drain of T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide the first initial voltage Vinit1.

[0229] The gate of T3 is electrically connected to the first scan line GT, the source of T3 is electrically connected to the data line DL, and the drain of T3 is electrically connected to the fourth node N4.

[0230] The first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the fourth node N4;

[0231] The gate of T4 is electrically connected to the second reset control line R2, the drain of T4 is electrically connected to the first node N1, and the source of T4 is electrically connected to the second node N2.

[0232] The gate of T5 is electrically connected to the second light-emitting control line EM2, the source of T5 is electrically connected to the third node N3, the drain of T5 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0233] The gate of T6 is electrically connected to the second scan line GT2, the source of T6 is electrically connected to the fourth node N4, and the drain of T6 is electrically connected to the third node N3.

[0234] The gate of T7 is electrically connected to the third reset control line R3, the source of T7 is electrically connected to the second initial voltage line I2, and the drain of T7 is electrically connected to the third node N3.

[0235] In at least one embodiment shown in Figure 12, the first voltage terminal is the power supply voltage line VDD, and the second voltage terminal is the low voltage terminal.

[0236] T4 is a PMOS (P-type metal-oxide-semiconductor) transistor, and T4 is a single-gate transistor;

[0237] T0, T1, T2, T3, T5, T6, and T7 are NMOS transistors, while T0, T1, T2, T3, T5, T6, and T7 are dual-gate transistors.

[0238] In at least one embodiment shown in Figure 12, setting T4 as a PMOS transistor or a single-gate transistor can optimize the layout space, reduce the capacitance on the second reset control line R2, and improve the charging rate of N1.

[0239] As shown in Figure 13, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0; the first light-emitting control circuit includes a first transistor T1; the first reset circuit includes a second transistor T2; the data writing circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1; the second reset circuit includes a fourth transistor T4; the second energy storage circuit includes a second capacitor C2; the second light-emitting control circuit includes a fifth transistor T5; the on / off control circuit includes a sixth transistor T6; and the third reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0240] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0241] The gate of T1 is electrically connected to the first light-emitting control line EM1, the source of T1 is electrically connected to the power supply voltage line VDD, and the drain of T1 is electrically connected to the second node N2.

[0242] The gate of T2 is electrically connected to the first reset control line R1, the drain of T2 is electrically connected to the first initial voltage line I1, and the source of T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide the first initial voltage Vinit1.

[0243] The gate of T3 is electrically connected to the first scan line GT, the source of T3 is electrically connected to the data line DL, and the drain of T3 is electrically connected to the fourth node N4.

[0244] The first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the fourth node N4;

[0245] The gate of T4 is electrically connected to the second reset control line R2, the source of T4 is electrically connected to the first node N1, and the drain of T4 is electrically connected to the second node N2.

[0246] The gate of T5 is electrically connected to the second light-emitting control line EM2, the source of T5 is electrically connected to the third node N3, the drain of T5 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0247] The gate of T6 is electrically connected to the second scan line GT2, the source of T6 is electrically connected to the fourth node N4, and the drain of T6 is electrically connected to the third node N3.

[0248] The gate of T7 is electrically connected to the third reset control line R3, the source of T7 is electrically connected to the second initial voltage line I2, and the drain of T7 is electrically connected to the third node N3.

[0249] In at least one embodiment shown in Figure 13, the first voltage terminal is the power supply voltage line VDD, and the second voltage terminal is the low voltage terminal.

[0250] T2 is a PMOS (P-type metal-oxide-semiconductor) transistor, and T2 is a single-gate transistor;

[0251] T0, T1, T3, T4, T5, T6, and T7 are NMOS transistors, while T0, T1, T3, T4, T5, T6, and T7 are dual-gate transistors.

[0252] In at least one embodiment shown in Figure 13, setting T2 as a PMOS transistor or a single-gate transistor can optimize the layout space, reduce the capacitance on the first reset control line R1, and improve the charging rate of N1.

[0253] As shown in Figure 14, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0; the first light-emitting control circuit includes a first transistor T1; the first reset circuit includes a second transistor T2; the data writing circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1; the second reset circuit includes a fourth transistor T4; the second energy storage circuit includes a second capacitor C2; the second light-emitting control circuit includes a fifth transistor T5; the on / off control circuit includes a sixth transistor T6; and the third reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0254] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0255] The gate of T1 is electrically connected to the first light-emitting control line EM1, the source of T1 is electrically connected to the power supply voltage line VDD, and the drain of T1 is electrically connected to the second node N2.

[0256] The gate of T2 is electrically connected to the first reset control line R1, the drain of T2 is electrically connected to the first initial voltage line I1, and the source of T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide the first initial voltage Vinit1.

[0257] The gate of T3 is electrically connected to the first scan line GT, the source of T3 is electrically connected to the data line DL, and the drain of T3 is electrically connected to the fourth node N4.

[0258] The first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the fourth node N4;

[0259] The gate of T4 is electrically connected to the second reset control line R2, the source of T4 is electrically connected to the first node N1, and the drain of T4 is electrically connected to the second node N2.

[0260] The gate of T5 is electrically connected to the second light-emitting control line EM2, the source of T5 is electrically connected to the third node N3, the drain of T5 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0261] The gate of T6 is electrically connected to the second scan line GT2, the drain of T6 is electrically connected to the fourth node N4, and the source of T6 is electrically connected to the third node N3.

[0262] The gate of T7 is electrically connected to the third reset control line R3, the source of T7 is electrically connected to the second initial voltage line I2, and the drain of T7 is electrically connected to the third node N3.

[0263] In at least one embodiment shown in Figure 14, T6 is a PMOS transistor and T6 is a single-gate transistor;

[0264] T0, T1, T2, T3, T4, T5, and T7 are NMOS transistors, and T0, T1, T2, T3, T4, T5, and T7 are dual-gate transistors.

[0265] The first light emission control signal provided by EM1 can be the nth level first light emission control signal, and the second light emission control signal provided by EM2 can be the (n+2)th level first light emission control signal; the first reset control signal provided by R1 can be the nth level first reset control signal, and the second reset control signal provided by R2 can be the (n+2)th level first reset control signal; n is a positive integer;

[0266] The first light emission control signal, the second light emission control signal, and the second scan signal provided by the second scan line GT2 can be provided by different levels of GOA circuits included in the same GOA module, which helps to reduce the number of GOA modules used and helps to achieve a narrow bezel.

[0267] When the display device employs at least one embodiment of the pixel circuit shown in FIG14, the display device can use only four GOA modules, which is beneficial to achieving a narrow bezel.

[0268] In at least one embodiment shown in Figure 14, setting T6 as a PMOS transistor or a single-gate transistor can optimize the layout space, reduce the capacitance on the second scan line GT2, and improve brightness uniformity.

[0269] Figure 15 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 14.

[0270] In Figures 15, 17, 19, 21 and 23, the current labeled Id represents the luminous current of O1.

[0271] In at least one embodiment of the pixel circuit shown in Figure 14, when T6 is replaced with an NMOS transistor and T6 is replaced with a dual-gate transistor, the second scan signal provided by the second scan line and the third reset control signal provided by the third reset control line can be provided by the same GOA module, so as to reduce the number of GOA modules used and facilitate the realization of a narrow bezel.

[0272] In at least one embodiment of this disclosure, N5 is the fifth node, and N5 is electrically connected to the anode of O1.

[0273] As shown in Figure 16, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0; the first light-emitting control circuit includes a first transistor T1; the first reset circuit includes a second transistor T2; the data writing circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1; the second reset circuit includes a fourth transistor T4; the second energy storage circuit includes a second capacitor C2; the second light-emitting control circuit includes a fifth transistor T5; the on / off control circuit includes a sixth transistor T6; and the third reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0274] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0275] The gate of T1 is electrically connected to the first light-emitting control line EM1, the drain of T1 is electrically connected to the power supply voltage line VDD, and the source of T1 is electrically connected to the second node N2.

[0276] The gate of T2 is electrically connected to the first reset control line R1, the source of T2 is electrically connected to the first initial voltage line I1, and the drain of T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide the first initial voltage Vinit1.

[0277] The gate of T3 is electrically connected to the first scan line GT, the source of T3 is electrically connected to the data line DL, and the drain of T3 is electrically connected to the fourth node N4.

[0278] The first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the fourth node N4;

[0279] The gate of T4 is electrically connected to the second reset control line R2, the source of T4 is electrically connected to the first node N1, and the drain of T4 is electrically connected to the second node N2.

[0280] The gate of T5 is electrically connected to the second light-emitting control line EM2, the drain of T5 is electrically connected to the third node N3, the source of T5 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0281] The gate of T6 is electrically connected to the second scan line GT2, the source of T6 is electrically connected to the fourth node N4, and the drain of T6 is electrically connected to the third node N3.

[0282] The gate of T7 is electrically connected to the third reset control line R3, the source of T7 is electrically connected to the second initial voltage line I2, and the drain of T7 is electrically connected to the third node N3.

[0283] In at least one embodiment shown in FIG17, T1 and T5 are PMOS transistors and T1 and T5 are single-gate transistors.

[0284] T0, T2, T3, T4, T6, and T7 are NMOS transistors, and T0, T2, T3, T4, T6, and T7 are dual-gate transistors.

[0285] In at least one embodiment of the present invention, the light-emitting current denoted by Id is O1.

[0286] In at least one embodiment shown in Figure 16, the first light emission control signal provided by EM1 can be the nth level first light emission control signal, and the second light emission control signal provided by EM2 can be the (n+2)th level first light emission control signal; the first reset control signal provided by R1 can be the nth level first reset control signal, and the second reset control signal provided by R2 can be the (n+2)th level first reset control signal; n is a positive integer;

[0287] The first light emission control signal, the second light emission control signal, and the third reset control signal provided by the third reset control line R3 can be provided by different levels of GOA circuits included in the same GOA module, which helps to reduce the number of GOA modules used and facilitates the realization of a narrow bezel.

[0288] When the display device employs at least one embodiment of the pixel circuit shown in FIG16, the display device can use only four GOA modules, which is beneficial to achieving a narrow bezel.

[0289] Figure 17 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 16.

[0290] As shown in Figure 18, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0; the first light-emitting control circuit includes a first transistor T1; the first reset circuit includes a second transistor T2; the data writing circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1; the second reset circuit includes a fourth transistor T4; the second energy storage circuit includes a second capacitor C2; the second light-emitting control circuit includes a fifth transistor T5; the on / off control circuit includes a sixth transistor T6; and the third reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0291] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0292] The gate of T1 is electrically connected to the first light-emitting control line EM1, the source of T1 is electrically connected to the power supply voltage line VDD, and the drain of T1 is electrically connected to the second node N2.

[0293] The gate of T2 is electrically connected to the first reset control line R1, the source of T2 is electrically connected to the first initial voltage line I1, and the drain of T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide the first initial voltage Vinit1.

[0294] The gate of T3 is electrically connected to the first scan line GT, the source of T3 is electrically connected to the data line DL, and the drain of T3 is electrically connected to the fourth node N4.

[0295] The first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the fourth node N4;

[0296] The gate of T4 is electrically connected to the second reset control line R2, the source of T4 is electrically connected to the first node N1, and the drain of T4 is electrically connected to the second node N2.

[0297] The gate of T5 is electrically connected to the second light-emitting control line EM2, the source of T5 is electrically connected to the third node N3, the drain of T5 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0298] The gate of T6 is electrically connected to the second scan line GT2, the source of T6 is electrically connected to the fourth node N4, and the drain of T6 is electrically connected to the third node N3.

[0299] The gate of T7 is electrically connected to the third reset control line R3, the drain of T7 is electrically connected to the second initial voltage line I2, and the source of T7 is electrically connected to the third node N3.

[0300] In at least one embodiment shown in FIG18, T7 is a PMOS transistor and T7 is a single-gate transistor;

[0301] T0, T1, T2, T3, T4, T5, and T6 are NMOS transistors, while T0, T1, T2, T3, T4, T5, and T6 are dual-gate transistors.

[0302] In at least one embodiment shown in Figure 19, setting T7 as a PMOS transistor or a single-gate transistor can optimize the layout space, reduce the capacitance on the third reset control line R3, and improve the charging rate of N3.

[0303] In at least one embodiment shown in Figure 18, the first light emission control signal provided by EM1 can be the nth level first light emission control signal, and the second light emission control signal provided by EM2 can be the (n+2)th level first light emission control signal; the first reset control signal provided by R1 can be the nth level first reset control signal, and the second reset control signal provided by R2 can be the (n+2)th level first reset control signal; n is a positive integer;

[0304] The first light emission control signal, the second light emission control signal, and the third reset control signal provided by the third reset control line R3 can be provided by different levels of GOA circuits included in the same GOA module, which helps to reduce the number of GOA modules used and facilitates the realization of a narrow bezel.

[0305] When the display device employs at least one embodiment of the pixel circuit shown in FIG18, the display device can use only four GOA modules, which is beneficial to achieving a narrow bezel.

[0306] Figure 19 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 18.

[0307] As shown in Figure 20, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0; the first light-emitting control circuit includes a first transistor T1; the first reset circuit includes a second transistor T2; the data writing circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1; the second reset circuit includes a fourth transistor T4; the second energy storage circuit includes a second capacitor C2; the second light-emitting control circuit includes a fifth transistor T5; the on / off control circuit includes a sixth transistor T6; and the third reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0308] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0309] The gate of T1 is electrically connected to the first light-emitting control line EM1, the source of T1 is electrically connected to the power supply voltage line VDD, and the drain of T1 is electrically connected to the second node N2.

[0310] The gate of T2 is electrically connected to the first reset control line R1, the source of T2 is electrically connected to the first initial voltage line I1, and the drain of T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide the first initial voltage Vinit1.

[0311] The gate of T3 is electrically connected to the first scan line GT, the source of T3 is electrically connected to the data line DL, and the drain of T3 is electrically connected to the fourth node N4.

[0312] The first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the fourth node N4;

[0313] The gate of T4 is electrically connected to the second reset control line R2, the source of T4 is electrically connected to the first node N1, and the drain of T4 is electrically connected to the second node N2.

[0314] The gate of T5 is electrically connected to the second light-emitting control line EM2, the source of T5 is electrically connected to the third node N3, the drain of T5 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0315] The gate of T6 is electrically connected to the second scan line GT2, the drain of T6 is electrically connected to the fourth node N4, and the source of T6 is electrically connected to the third node N3.

[0316] The gate of T7 is electrically connected to the third reset control line R3, the drain of T7 is electrically connected to the second initial voltage line I2, and the source of T7 is electrically connected to the third node N3.

[0317] In at least one embodiment shown in FIG21, T6 and T7 are PMOS transistors and T6 and T7 are single-gate transistors;

[0318] T0, T1, T2, T3, T4, and T5 are NMOS transistors, and T0, T1, T2, T3, T4, and T5 are dual-gate transistors.

[0319] In at least one embodiment shown in Figure 20, the first light emission control signal provided by EM1 can be the nth level first light emission control signal, and the second light emission control signal provided by EM2 can be the (n+2)th level first light emission control signal; the first reset control signal provided by R1 can be the nth level first reset control signal, and the second reset control signal provided by R2 can be the (n+2)th level first reset control signal; n is a positive integer;

[0320] The first light emission control signal, the second light emission control signal, the third reset control signal provided by the third reset control line R3, and the second scan signal provided by the second scan line GT2 can be provided by different levels of GOA circuits included in the same GOA module, which helps to reduce the number of GOA modules used and helps to achieve a narrow bezel.

[0321] When the display device employs at least one embodiment of the pixel circuit shown in FIG20, the display device can use only three GOA modules, which is beneficial to achieving a narrow bezel.

[0322] Figure 21 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 20.

[0323] As shown in Figure 22, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0; the first light-emitting control circuit includes a first transistor T1; the first reset circuit includes a second transistor T2; the data writing circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1; the second reset circuit includes a fourth transistor T4; the second energy storage circuit includes a second capacitor C2; the second light-emitting control circuit includes a fifth transistor T5; the on / off control circuit includes a sixth transistor T6; and the third reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0324] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0325] The gate of T1 is electrically connected to the first light-emitting control line EM1, the drain of T1 is electrically connected to the power supply voltage line VDD, and the source of T1 is electrically connected to the second node N2.

[0326] The gate of T2 is electrically connected to the first reset control line R1, the source of T2 is electrically connected to the first initial voltage line I1, and the drain of T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide the first initial voltage Vinit1.

[0327] The gate of T3 is electrically connected to the first scan line GT, the source of T3 is electrically connected to the data line DL, and the drain of T3 is electrically connected to the fourth node N4.

[0328] The first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the fourth node N4;

[0329] The gate of T4 is electrically connected to the second reset control line R2, the source of T4 is electrically connected to the first node N1, and the drain of T4 is electrically connected to the second node N2.

[0330] The gate of T5 is electrically connected to the second light-emitting control line EM2, the drain of T5 is electrically connected to the third node N3, the source of T5 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0331] The gate of T6 is electrically connected to the second scan line GT2, the source of T6 is electrically connected to the fourth node N4, and the drain of T6 is electrically connected to the third node N3.

[0332] The gate of T7 is electrically connected to the third reset control line R3, the source of T7 is electrically connected to the second initial voltage line I2, and the drain of T7 is electrically connected to the third node N3.

[0333] In at least one embodiment shown in FIG22, T1 and T5 are PMOS transistors and T1 and T5 are single-gate transistors;

[0334] T0, T2, T3, T4, T6, and T7 are NMOS transistors, and T0, T2, T3, T4, T6, and T7 are dual-gate transistors.

[0335] In at least one embodiment shown in Figure 22, the first light emission control signal provided by EM1 can be the nth level first light emission control signal, and the second light emission control signal provided by EM2 can be the (n+2)th level first light emission control signal; the first reset control signal provided by R1 can be the nth level first reset control signal, and the second reset control signal provided by R2 can be the (n+2)th level first reset control signal; n is a positive integer;

[0336] The first light emission control signal, the second light emission control signal, the third reset control signal provided by the third reset control line R3, and the second scan signal provided by the second scan line GT2 can be provided by different levels of GOA circuits included in the same GOA module, which helps to reduce the number of GOA modules used and helps to achieve a narrow bezel.

[0337] When the display device employs at least one embodiment of the pixel circuit shown in FIG22, the display device can use only three GOA modules, which is beneficial to achieving a narrow bezel.

[0338] Figure 23 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 22.

[0339] As shown in Figure 24, based on at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor T0; the first light-emitting control circuit includes a first transistor T1; the first reset circuit includes a second transistor T2; the data writing circuit includes a third transistor T3; the first energy storage circuit includes a first capacitor C1; the second reset circuit includes a fourth transistor T4; the second energy storage circuit includes a second capacitor C2; the second light-emitting control circuit includes a fifth transistor T5; the on / off control circuit includes a sixth transistor T6; and the third reset circuit includes a seventh transistor T7; the light-emitting element is an organic light-emitting diode O1.

[0340] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0341] The gate of T1 is electrically connected to the first light-emitting control line EM1, the source of T1 is electrically connected to the power supply voltage line VDD, and the drain of T1 is electrically connected to the second node N2.

[0342] The gate of T2 is electrically connected to the first reset control line R1, the source of T2 is electrically connected to the first initial voltage line I1, and the drain of T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide the first initial voltage Vinit1.

[0343] The gate of T3 is electrically connected to the first scan line GT, the source of T3 is electrically connected to the data line DL, and the drain of T3 is electrically connected to the fourth node N4.

[0344] The first end of C1 is electrically connected to the first node N1, and the second end of C1 is electrically connected to the fourth node N4;

[0345] The gate of T4 is electrically connected to the second reset control line R2, the source of T4 is electrically connected to the first node N1, and the drain of T4 is electrically connected to the second node N2.

[0346] The gate of T5 is electrically connected to the second light-emitting control line EM2, the source of T5 is electrically connected to the third node N3, the drain of T5 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0347] The gate of T6 is electrically connected to the second scan line GT2, the source of T6 is electrically connected to the fourth node N4, and the drain of T6 is electrically connected to the third node N3.

[0348] The gate of T7 is electrically connected to the third reset control line R3, the source of T7 is electrically connected to the second initial voltage line I2, and the drain of T7 is electrically connected to the third node N3.

[0349] In at least one embodiment shown in Figure 24, T0, T1, T2, T3, T4, T5, T6 and T7 are NMOS transistors, and T0, T1, T2, T3, T4, T5, T6 and T7 are dual-gate transistors.

[0350] In at least one embodiment shown in Figure 24, the first light emission control signal provided by EM1 can be the nth level first light emission control signal, and the second light emission control signal provided by EM2 can be the (n+2)th level first light emission control signal; n is a positive integer; the first reset control signal provided by R1 can be the nth level first reset control signal, and the second reset control signal provided by R2 can be the (n+2)th level first reset control signal.

[0351] The second reset control signal provided by the second reset control line R2, the first reset control signal provided by the first reset control line R1, and the second scan signal provided by the second scan line GT2 can be provided by different levels of GOA circuits included in the same GOA module, which helps to reduce the number of GOA modules used and facilitates the achievement of a narrow bezel.

[0352] When the display device employs at least one embodiment of the pixel circuit shown in FIG24, the display device can use only three GOA modules, which is beneficial to achieving a narrow bezel.

[0353] Figure 25 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 24.

[0354] Figure 26 is a layout diagram of at least one embodiment of the pixel circuit shown in Figure 9.

[0355] Figure 27 is a layout diagram of the first semiconductor layer in Figure 26, Figure 28 is a layout diagram of the first gate metal layer in Figure 26, Figure 29 is a layout diagram of the second gate metal layer in Figure 26, Figure 30 is a layout diagram of the second semiconductor layer in Figure 26, Figure 31 is a layout diagram of the third gate metal layer in Figure 26, and Figure 32 is a layout diagram of the first source / drain metal layer in Figure 26.

[0356] Figure 33 is a stack-up diagram of the first semiconductor layer and the first gate metal layer in Figure 26. Figure 34 is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 26. Figure 35 is a stack-up diagram of the second gate metal layer and the second semiconductor layer in Figure 26. Figure 36 is a stack-up diagram of the second gate metal layer and the third gate metal layer in Figure 26. Figure 37 is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 26.

[0357] In Figure 26, the line labeled VDD is the power supply voltage line, the line labeled EM1 is the first light-emitting control line, the line labeled EM2 is the second light-emitting control line, the line labeled R3 is the third reset control line, and the line labeled I2 is the second initial voltage line.

[0358] The transistor labeled T1 is the first transistor, the transistor labeled T2 is the second transistor, the transistor labeled T3 is the third transistor, the transistor labeled T4 is the fourth transistor, the transistor labeled T5 is the fifth transistor, the transistor labeled T6 is the sixth transistor, and the transistor labeled T7 is the seventh transistor.

[0359] In Figure 27, the active pattern of the fifth transistor is labeled A5.

[0360] In Figure 28, the line labeled EM2 is the second light-emitting control line, the line labeled C1a is the first electrode of C1, and the line labeled C2a is the second electrode of C2.

[0361] In Figure 29, the gate labeled G11 is the first gate of T1, the gate labeled G41 is the first gate of T4, the gate labeled G21 is the first gate of T2, the gate labeled G31 is the first gate of T3, the gate labeled G61 is the first gate of T6, and the gate labeled G71 is the first gate of T7.

[0362] The plate labeled C1b is the second plate of C1, and the plate labeled C2b is the second plate of C2.

[0363] In Figure 30, the part labeled A0 is the active graphics unit;

[0364] The active graphics unit A0 includes active graphics of T1, active graphics of T2, active graphics of T3, active graphics of T4, active graphics of T6 and active graphics of T7.

[0365] In Figure 31, the gate labeled G12 is the second gate of T1, the gate labeled G42 is the second gate of T4, the gate labeled G22 is the first gate of T2, the gate labeled G32 is the second gate of T3, the gate labeled G62 is the second gate of T6, and the gate labeled G72 is the second gate of T7.

[0366] In Figure 32, the line labeled EM1 is the first light emission control line, the line labeled R2 is the second reset control line, the line labeled R1 is the first reset control line, the line labeled GT is the first scan line, and the line labeled GT2 is the second scan line.

[0367] In at least one embodiment shown in FIG26, C1a is multiplexed as the first gate of T0, and C1b is multiplexed as the second gate of T0;

[0368] In at least one embodiment shown in Figures 26-37, T1, T2, T3, T4, T6, T7 and T0 are all NMOS transistors, and T5 is a PMOS transistor;

[0369] T1, T2, T3, T4, T6, T7, and T0 are all dual-gate transistors, while T5 is a single-gate transistor.

[0370] In at least one embodiment shown in Figures 26-37, the first gate of the NMOS transistor is formed on the second gate metal layer, the second gate of the NMOS transistor is formed on the third gate metal layer, and the control signal line electrically connected to the gate of the NMOS transistor is formed on the first source-drain metal layer; the control signal line formed on the first source-drain metal layer is electrically connected to the first gate and the second gate of the corresponding NMOS transistor through vias, so the capacitance of the control signal line is large;

[0371] The gate of the PMOS transistor is formed on the first gate metal layer, and the control signal line electrically connected to the PMOS transistor is also formed on the first gate metal layer. The control signal line electrically connected to the gate of the PMOS transistor includes the gate of the PMOS transistor. Therefore, the capacitance on the control signal line electrically connected to the gate of the PMOS transistor is small, which can provide brightness uniformity.

[0372] The differences between at least one embodiment of the pixel circuit shown in Figure 38 and at least one embodiment of the pixel circuit shown in Figure 24 are as follows:

[0373] The drain of T7 is electrically connected to the anode of O1.

[0374] In at least one embodiment of the pixel circuit shown in Figure 38, when in operation, the threshold voltage of the driving transistor T0 is written to the gate of T0 by means of diode compensation, which can reduce compensation loss while increasing the compensation time.

[0375] In at least one embodiment shown in Figure 38, the first reset control signal provided by R1 can be the nth level first reset control signal, and the second reset control signal provided by R2 can be the n+4th level first reset control signal. The first reset control signal and the second reset control signal can be provided by different levels of GOA circuits included in the same GOA module, which helps to reduce the number of GOA modules used in the display device and helps to achieve a narrow bezel.

[0376] As shown in Figure 39, when at least one embodiment of the pixel circuit shown in Figure 38 is in operation, the display cycle may include a reset phase S1, a compensation phase S2, a writing phase S3, and a light emission phase S4.

[0377] During the reset phase S1, R1 provides a high voltage signal, EM2 provides a high voltage signal, R3 provides a high voltage signal, GT2 provides a high voltage signal, T2, T5, T7 and T6 are turned on, I1 provides a first initial voltage Vinit1 to write to N1, and I2 provides a second initial voltage Vinit2 to N5, N3 and N4.

[0378] During the compensation phase S2, R3 provides a high voltage signal, EM2 provides a high voltage signal, R2 provides a high voltage signal, T7 and T5 are turned on, and T4 is turned on.

[0379] At the start of the compensation phase S2, T0 is turned on, charging C1 and C2 through Vinit2, changing the potential of N1 until the potential of N1 becomes Vinit2 + Vth, at which point T0 is turned off; Vth is the threshold voltage of T0.

[0380] During the write phase S3, GT provides a high voltage signal, R3 provides a high voltage signal, EM2 provides a low voltage signal, T7 is turned on, I2 provides Vinit2 to the anode of O1, T3 is turned on, DL provides the data voltage Vdata to N4, and the potential of N1 is changed accordingly.

[0381] During the light-emitting stage S4, EM1 and EM2 provide high voltage signals, while R1, R2, R3, GT, and GT2 all provide low voltage signals. T1 and T5 are turned on, and T0 drives O1 to emit light.

[0382] There is an overlapping time period SJ between the reset phase S1 and the compensation phase S2;

[0383] During the overlapping time period SJ, R1 and R2 both provide high voltage signals, and T2 and T4 are turned on, resulting in a momentary large current in T0, which improves the hysteresis phenomenon.

[0384] During the overlapping time period SJ, R3 provides a high voltage signal and EM2 provides a high voltage signal to maintain the potential of N3 and the potential of N5 stable.

[0385] The differences between at least one embodiment of the pixel circuit shown in Figure 40 and at least one embodiment of the pixel circuit shown in Figure 38 are as follows:

[0386] T3 is a PMOS transistor, T3 is an LTPS (Low Temperature Polycrystalline Silicon) transistor, and T3 is a single-gate transistor, which can improve the data voltage write current and improve the data voltage write efficiency at high frequencies.

[0387] The differences between at least one embodiment of the pixel circuit shown in Figure 41 and at least one embodiment of the pixel circuit shown in Figure 38 are as follows:

[0388] T5 is a PMOS transistor, T5 is an LTPS (Low Temperature Polycrystalline Silicon) transistor, and T5 is a single-gate transistor;

[0389] EM2 and R3 can be the same control terminal. The second light emission control signal provided by EM2 and the third reset control signal provided by R3 can be the same control signal, so as to save the number of GOA modules used in the display device, which is beneficial to optimize the layout space and achieve a narrow bezel.

[0390] The differences between at least one embodiment of the pixel circuit shown in Figure 42 and at least one embodiment of the pixel circuit shown in Figure 38 are as follows:

[0391] T6 is a PMOS transistor, T6 is an LTPS (Low Temperature Polysilicon) transistor, T6 is a single-gate transistor, which increases the signal reset capability of N4.

[0392] The difference between at least one embodiment of the pixel circuit shown in Figure 43 and at least one embodiment of the pixel circuit shown in Figure 42 is as follows: it further includes a fourth reset circuit;

[0393] The fourth circuit includes an eighth transistor T8;

[0394] The gate of T8 is electrically connected to the fourth reset control terminal R4, the source of T8 is electrically connected to the third initial voltage line I3, and the drain of T8 is electrically connected to the third node N3; I3 is used to provide the third initial voltage Vinit3.

[0395] T8 is an NMOS transistor.

[0396] In at least one embodiment of the pixel circuit shown in Figure 43, during low-frequency display, in the hold-reset phase of the hold frame, R4 provides a high voltage signal, T8 is turned on, and I3 provides a third initial voltage Vinit3 to N3 to improve the hysteresis phenomenon of T0.

[0397] When at least one embodiment of the pixel circuit shown in Figure 43 does not include T8, during the hold reset phase, N3 is reset using the second initial voltage Vinit2 provided by I2 through the conducting T7 and T5. However, when the display refresh frequency changes, the voltage value of the second initial voltage may be adjusted accordingly. Thus, during the hold reset phase included in the hold frame, when the third node is reset by the second initial voltage, the potential of the first node will be changed through the coupling of the first energy storage circuit and the second energy storage circuit, resulting in a change in brightness. Therefore, at least one embodiment of this disclosure can use an eighth transistor T8 to write the second initial voltage into the third node or the second node during the hold reset phase included in the hold frame, thereby improving the hysteresis phenomenon of the driving transistor.

[0398] In at least one embodiment of the pixel circuit shown in Figure 43, the voltage value of the third initial voltage Vinit3 provided by I3 can be greater than -8V and less than 0V, but is not limited thereto.

[0399] The pixel driving method described in this disclosure is applied to the pixel circuit described above, and the pixel driving method includes:

[0400] The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node;

[0401] The first light-emitting control circuit, under the control of the first light-emitting control signal, controls the connection or disconnection between the first voltage terminal and the second node;

[0402] The first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first node;

[0403] Under the control of the first scan signal, the data writing circuit writes the data voltage provided by the data line to the fourth node.

[0404] In at least one embodiment of this disclosure, the pixel circuit further includes a second reset circuit; the display cycle of the pixel circuit includes a reset phase and a compensation phase; there is an overlapping time period between the reset phase and the compensation phase; the pixel driving method includes:

[0405] During the reset phase, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first node;

[0406] During the compensation phase, the second reset circuit, under the control of the second reset control signal, controls the connection between the first node and the second node;

[0407] During the overlapping time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first node; the second reset circuit, under the control of the second reset control signal, controls the connection between the first node and the second node to write the first initial voltage into the second node.

[0408] In at least one embodiment of this disclosure, the pixel circuit further includes an on / off control circuit and a third reset circuit; the pixel driving method includes:

[0409] During the reset phase and the compensation phase, the on / off control circuit, under the control of the second scan signal, controls the connection between the fourth node and the third node; the third reset circuit, under the control of the third reset control signal, writes the second initial voltage into the third node or the first electrode of the light-emitting element.

[0410] In at least one embodiment of this disclosure, the display cycle further includes a write phase disposed after the compensation phase; the pixel driving method includes:

[0411] During the writing phase, the data writing circuit, under the control of the first scan signal, writes the data voltage to the fourth node.

[0412] In at least one embodiment of this disclosure, during low-frequency display, the display period is a refresh frame, the pixel circuit includes a fourth reset circuit; the hold frame includes a hold-reset phase; the pixel driving method further includes:

[0413] During the hold reset phase, the fourth reset circuit, under the control of the fourth reset control signal, writes the third initial voltage into the second node and / or the third node.

[0414] The display device described in this disclosure includes the pixel circuit described above.

[0415] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a light-emitting element, a driving circuit, a first light-emitting control circuit, a first reset circuit, a data writing circuit, and a first energy storage circuit; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node. The first light-emitting control circuit is electrically connected to the first light-emitting control line, the first voltage terminal and the second node respectively, and is used to control the connection or disconnection between the first voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control line. The first reset circuit is electrically connected to the first reset control line, the first initial voltage line and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage line into the first node under the control of the first reset control signal provided by the first reset control line. The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the fourth node. The data writing circuit is electrically connected to the first scan line, the data line and the fourth node respectively, and is used to write the data voltage provided by the data line into the fourth node under the control of the first scan signal provided by the first scan line. The driving circuit includes an n-type driving transistor, and at least one of the transistors in the first light-emitting control circuit, the first reset circuit, and the data writing circuit is a p-type transistor.

2. The pixel circuit as described in claim 1, wherein, The driving transistor is a dual-gate transistor, and at least one of the transistors included in the first light-emitting control circuit, the first reset circuit, and the data writing circuit is a single-gate transistor.

3. The pixel circuit as described in claim 1, wherein, It also includes a second reset circuit; The second reset circuit is electrically connected to the second reset control line, the first node, and the second node, respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the second reset control signal provided by the second reset control line.

4. The pixel circuit as described in claim 3, wherein, The second reset circuit includes a p-type transistor and a single-gate transistor.

5. The pixel circuit as described in claim 3, wherein, The transistors included in the first reset circuit and the second reset circuit are both n-type transistors; or, the transistors included in the first reset circuit and the second reset circuit are both p-type transistors. The first reset control signal and the second reset control signal are provided by the same GOA module.

6. The pixel circuit as described in claim 3, wherein, It also includes a second light-emitting control circuit and an on / off control circuit; The second light-emitting control circuit is connected to the second light-emitting control line, the third node, and the first light-emitting element, respectively. The electrode is electrically connected to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control line; the second electrode of the light-emitting element is electrically connected to the second voltage terminal. The on / off control circuit is electrically connected to the second scan line, the fourth node, and the third node, respectively, and is used to control the connection or disconnection between the fourth node and the third node under the control of the second scan signal provided by the second scan line.

7. The pixel circuit as described in claim 6, wherein, At least one of the transistors included in the second light-emitting control circuit and the transistors included in the on / off control circuit is a p-type transistor, and at least one of the transistors included in the second light-emitting control circuit and the transistors included in the on / off control circuit is a single-gate transistor.

8. The pixel circuit as described in claim 6, wherein, It also includes a third reset circuit; The third reset circuit is electrically connected to the third reset control line and the second initial voltage line respectively. The third reset circuit is also electrically connected to the third node or the first electrode of the light-emitting element. The third reset circuit is used to write the second initial voltage provided by the second initial voltage line into the third node or the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control line.

9. The pixel circuit as described in claim 8, wherein, The third reset circuit includes a p-type transistor and a single-gate transistor.

10. The pixel circuit as claimed in claim 1, wherein, It also includes a second energy storage circuit; The first end of the second energy storage circuit is electrically connected to the fourth node, and the second end of the second energy storage circuit is electrically connected to the third node.

11. The pixel circuit as claimed in claim 8, wherein, The transistors included in the on / off control circuit and the transistors included in the third reset circuit are both n-type transistors, or the transistors included in the on / off control circuit and the transistors included in the third reset circuit are both p-type transistors. The second scan signal provided by the second scan line and the third reset control signal provided by the third reset control line are provided by the same GOA module.

12. The pixel circuit as claimed in claim 5, wherein, The transistors included in the first light-emitting control circuit and the transistors included in the second light-emitting control circuit are both n-type transistors; or, the transistors included in the first light-emitting control circuit and the transistors included in the second light-emitting control circuit are both p-type transistors. The first light emission control signal and the second light emission control signal are provided by the same GOA module.

13. The pixel circuit as claimed in claim 5, wherein, The on / off control circuit includes a p-type transistor, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both n-type transistors; or, the on / off control circuit includes an n-type transistor, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both p-type transistors. The on / off control signal, the first light emission control signal, and the second light emission control signal are provided by the same GOA module.

14. The pixel circuit as claimed in claim 8, wherein, The transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both p-type transistors, and the transistors included in the third reset circuit are n-type transistors; or, the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are both n-type transistors, and the transistors included in the third reset circuit are p-type transistors. The first light emission control signal, the second light emission control signal, and the third reset control signal are provided by the same GOA module.

15. The pixel circuit as claimed in claim 8, wherein, The transistors included in the on / off control circuit and the third reset circuit are p-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are n-type transistors; or, the transistors included in the on / off control circuit and the third reset circuit are n-type transistors, and the transistors included in the first light-emitting control circuit and the second light-emitting control circuit are p-type transistors. The on / off control signal, the third reset control signal, the first light emission control signal, and the second light emission control signal are provided by the same GOA module.

16. The pixel circuit as claimed in claim 3, wherein, The transistors included in the first reset circuit and the second reset transistor are both n-type transistors; or, the transistors included in the first reset circuit and the second reset transistor are both p-type transistors. The first reset control signal and the second reset control signal are provided by the same GOA module.

17. The pixel circuit as claimed in claim 5, wherein, The transistors included in the first reset circuit, the second reset transistor, and the on / off control circuit are all n-type transistors; or, the transistors included in the first reset circuit, the second reset transistor, and the on / off control circuit are all p-type transistors. The first reset control signal, the second reset control signal, and the on / off control signal are provided by the same GOA module.

18. The pixel circuit as claimed in claim 8, wherein, The second light-emitting control circuit includes a p-type transistor, and the third reset circuit includes an n-type transistor; or, the second light-emitting control circuit includes an n-type transistor, and the third reset circuit includes a p-type transistor. The second light emission control signal and the third reset control signal are provided by the same GOA module.

19. The pixel circuit as claimed in claim 8, wherein, The third reset circuit is electrically connected to the first electrode of the light-emitting element; the pixel circuit also includes a fourth reset circuit. The fourth reset circuit is electrically connected to the fourth reset control line, the third initial voltage line, and the reset node, respectively, and is used to write the third initial voltage provided by the third initial voltage line into the reset node under the control of the fourth reset control signal provided by the fourth reset control line. The reset node includes a second node and / or a third node.

20. A pixel driving method, applied to a pixel circuit as described in any one of claims 1 to 19, the pixel driving method comprising: The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node; The first light-emitting control circuit, under the control of the first light-emitting control signal, controls the connection or disconnection between the first voltage terminal and the second node; The first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first node; Under the control of the first scan signal, the data writing circuit writes the data voltage provided by the data line to the fourth node.

21. The pixel driving method as described in claim 20, wherein, The pixel circuit further includes a second reset circuit; the display cycle of the pixel circuit includes a reset phase and a compensation phase; there is an overlapping time period between the reset phase and the compensation phase; the pixel driving method includes: During the reset phase, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first node; During the compensation phase, the second reset circuit, under the control of the second reset control signal, controls the connection between the first node and the second node; During the overlapping time period, the first reset circuit, under the control of the first reset control signal, writes the first initial voltage into the first node; the second reset circuit, under the control of the second reset control signal, controls the connection between the first node and the second node to write the first initial voltage into the second node.

22. The pixel driving method as described in claim 21, wherein, The pixel circuit further includes an on / off control circuit and a third reset circuit; the pixel driving method includes: During the reset phase and the compensation phase, the on / off control circuit, under the control of the second scan signal, controls the connection between the fourth node and the third node; the third reset circuit, under the control of the third reset control signal, writes the second initial voltage into the third node or the first electrode of the light-emitting element.

23. The pixel driving method as described in claim 21, wherein, The display cycle also includes a write phase set after the compensation phase; The pixel driving method includes: During the writing phase, the data writing circuit, under the control of the first scan signal, writes the data voltage to the fourth node.

24. The pixel driving method according to any one of claims 21 to 23, wherein, In low-frequency display, the display cycle is a refresh frame, the pixel circuit includes a fourth reset circuit; the holding frame includes a holding reset phase; the pixel driving method further includes: During the hold reset phase, the fourth reset circuit, under the control of the fourth reset control signal, writes the third initial voltage into the second node and / or the third node.

25. A display device comprising a pixel circuit as described in any one of claims 1 to 19.

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