Method for preparing solar cell, and solar cell

Abstract

The present application relates to a method for preparing a solar cell, and a solar cell. The method for preparing a solar cell in the present application comprises the following steps: forming a groove on the back surface of a substrate; and preparing a tunnel oxide layer and an intrinsic silicon material layer, which are sequentially stacked, on the back surface of the substrate provided with the groove, wherein the intrinsic silicon material layer is provided with a first region and a second region that are respectively located on two opposite sides of the groove, the part of the intrinsic silicon material layer in the first region is doped to obtain a first doped silicon material layer, and the part of the intrinsic silicon material layer in the second region is doped to obtain a second doped silicon material layer.

Description

Methods for fabricating solar cells, solar cells

[0001] This application claims priority to Chinese Patent Application No. 202411524535.9, filed on October 29, 2024, entitled "Method for Preparing Solar Cells, Solar Cells", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and a solar cell. Background Technology

[0003] Back-contact solar cells are a type of solar cell structure used to improve cell efficiency. Their core design involves placing all the metal electrodes of the solar cell on the back of the cell, thereby ensuring that the front of the cell is not blocked by the metal grid lines. This increases the area of ​​the cell that absorbs sunlight, reduces optical losses, and improves photoelectric conversion efficiency.

[0004] In back-contact solar cells, the emitters are all located on the back of the cell and are composed of two different types of doped regions, which makes the fabrication process of back-contact solar cells more complex.

[0005] Summary of the Invention

[0006] Therefore, it is necessary to provide a method for fabricating a solar cell and a solar cell itself. The method for fabricating a solar cell in this application can achieve good fabrication results for back-contact solar cells with fewer process steps.

[0007] In a first aspect, this application provides a method for fabricating a solar cell, comprising the following steps:

[0008] A substrate is provided, the substrate having a front side and a back side disposed opposite to each other;

[0009] A groove is formed on the back side of the substrate;

[0010] A tunneling oxide layer and an intrinsic silicon material layer are sequentially stacked on the back side of the substrate;

[0011] The intrinsic silicon material layer has a first region and a second region located on opposite sides of the groove. The intrinsic silicon material layer in the first region is doped to obtain a first doped silicon material layer, and the intrinsic silicon material layer in the second region is doped to obtain a second doped silicon material layer. The doping types of the first doped silicon material layer and the second doped silicon material layer are opposite.

[0012] In some embodiments, doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer, and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer, includes the following steps:

[0013] A first paste is disposed on the surface of the intrinsic silicon material layer in the first region, the first paste comprising a first doping element;

[0014] A second paste is disposed on the surface of the intrinsic silicon material layer in the second region, the second paste comprising a second doping element, wherein the doping types of the first doping element and the second doping element are opposite;

[0015] The intrinsic silicon material layer is doped by laser processing using the first slurry and the second slurry.

[0016] In some embodiments, the laser power of the laser processing is 30W to 80W.

[0017] In some embodiments, the maximum width of the laser-processed spot is 100 μm to 300 μm.

[0018] In some embodiments, the laser processing spot overlap rate is less than 80%.

[0019] In some embodiments, after doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer, and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer, the following steps are further included:

[0020] The first doped silicon material layer and the second doped silicon material layer are subjected to hydrogen plasma treatment.

[0021] In some embodiments, the pressure of the hydrogen plasma treatment is 1 Torr to 2 Torr.

[0022] In some embodiments, the temperature of the hydrogen plasma treatment is 150°C to 250°C.

[0023] In some embodiments, the hydrogen plasma treatment time is 30s to 200s.

[0024] In some embodiments, forming a groove on the back side of the substrate includes the following steps:

[0025] A mask layer is prepared on the back side of the substrate;

[0026] An opening is formed on the mask layer by using a laser, and a groove is formed within the opening by using a laser.

[0027] In some embodiments, after forming the groove within the opening, the following steps are further included:

[0028] The sample after the groove is formed is texturized using an alkaline solution to form a texturized structure on the bottom of the groove and the front side of the substrate.

[0029] In some embodiments, after doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer, and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer, the following steps are further included:

[0030] A first passivation antireflection layer and a second passivation antireflection layer are respectively prepared on the front and back sides of the substrate.

[0031] Secondly, this application provides a solar cell prepared by any of the methods described above.

[0032] In some embodiments, the solar cell includes a substrate having a front side and a back side disposed opposite to each other, the front side of the substrate having a textured structure and having a first passivation antireflection layer disposed thereon;

[0033] A groove is formed on the back side of the substrate, and a tunneling oxide layer, an intrinsic silicon material layer and a second passivation antireflection layer are sequentially stacked in the groove.

[0034] The solar cell includes a first region and a second region located on opposite sides of the groove. The substrate in the first region has a tunneling oxide layer, a first doped silicon material layer and a second passivation antireflection layer stacked sequentially on its back side. The substrate in the second region has a tunneling oxide layer, a second doped silicon material layer and a second passivation antireflection layer stacked sequentially on its back side. The doping types of the first doped silicon material layer and the second doped silicon material layer are opposite.

[0035] The solar cell further includes a first electrode and a second electrode disposed on the second passivation antireflection layer, wherein the first electrode is electrically in contact with the first doped silicon material layer, and the second electrode is electrically in contact with the second doped silicon material layer.

[0036] In the aforementioned method for fabricating solar cells, a groove is first formed on the back side of the substrate, and then a first doped silicon material layer and a second doped silicon material layer with opposite doping types are fabricated in a first region and a second region located on opposite sides of the groove, respectively. This allows for the isolation of different types of emitters with fewer process steps. The solar cell fabrication method of this application can achieve better back-contact solar cell fabrication results with fewer process steps.

[0037] Furthermore, the above-mentioned method for preparing solar cells can produce solar cells with low leakage current and high fill factor, thereby achieving high photoelectric conversion efficiency. Attached Figure Description

[0038] Figure 1 is a schematic diagram of the structure of forming a mask layer on the back side of the substrate;

[0039] Figure 2 is a schematic diagram of a structure with an opening formed on the basis of the structure shown in Figure 1;

[0040] Figure 3 is a schematic diagram of the structure after forming grooves and fabricating the pile based on the structure shown in Figure 2;

[0041] Figure 4 is a schematic diagram of the structure for fabricating a tunneling oxide layer and an intrinsic silicon material layer based on the structure shown in Figure 3.

[0042] Figure 5 is a schematic diagram of the structure for forming the first slurry and the second slurry based on the structure shown in Figure 4;

[0043] Figure 6 is a schematic diagram of the structure of the first doped silicon material layer and the second doped silicon material layer prepared based on the structure shown in Figure 5;

[0044] Figure 7 is a schematic diagram of the structure in which the first passivation anti-reflection layer and the second passivation anti-reflection layer are formed based on the structure shown in Figure 6;

[0045] Figure 8 is a schematic diagram of the structure in which the first electrode and the second electrode are formed based on the structure shown in Figure 7.

[0046] Explanation of reference numerals in the attached figures: 10, substrate; 20, mask layer; 30, trench; 40, tunneling oxide layer; 50, intrinsic silicon material layer; 61, first paste; 62, second paste; 71, first doped silicon material layer; 72, second doped silicon material layer; 81, first passivation antireflection layer; 82, second passivation antireflection layer; 91, first electrode; 92, second electrode. Detailed Implementation

[0047] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, a detailed description of specific embodiments of this application is provided below. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0049] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0051] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0052] Referring to Figures 1 to 8, one embodiment of this application provides a method for fabricating a solar cell, comprising the following steps:

[0053] A substrate 10 is provided, the substrate 10 having a front side and a back side disposed opposite to each other;

[0054] A groove 30 is formed on the back side of the substrate 10;

[0055] A tunneling oxide layer 40 and an intrinsic silicon material layer 50 are sequentially stacked on the back side of the substrate 10.

[0056] The intrinsic silicon material layer 50 has a first region and a second region located on opposite sides of the groove 30. The intrinsic silicon material layer 50 in the first region is doped to obtain a first doped silicon material layer 71, and the intrinsic silicon material layer 50 in the second region is doped to obtain a second doped silicon material layer 72. The doping types of the first doped silicon material layer 71 and the second doped silicon material layer 72 are opposite.

[0057] In the above-described method for fabricating a solar cell, a groove 30 is first formed on the back side of the substrate 10. Then, a first doped silicon material layer 71 and a second doped silicon material layer 72 with opposite doping types are fabricated in a first region and a second region located on opposite sides of the groove 30, respectively. This allows for the isolation of different types of emitters with fewer process steps. The solar cell fabrication method of this application can achieve good back-contact solar cell fabrication results with fewer process steps. Furthermore, the above-described method for fabricating a solar cell can produce a solar cell with low leakage current and high fill factor, thereby achieving high photoelectric conversion efficiency.

[0058] In some embodiments, the method for fabricating a solar cell includes the following steps:

[0059] S10: Provide a substrate 10 having a front side and a back side disposed opposite to each other; form a groove 30 on the back side of the substrate 10.

[0060] In some embodiments, forming a groove 30 on the back side of the substrate 10 includes the following steps:

[0061] A mask layer 20 is prepared on the back side of the substrate 10;

[0062] An opening is formed on the mask layer 20 by laser, and a groove 30 is formed in the opening by laser.

[0063] Referring to Figures 1 and 2, Figure 1 is a schematic diagram of a structure in which a mask layer 20 is formed on the back side of a substrate 10. Figure 2 is a schematic diagram of a structure in which an opening is formed based on the structure shown in Figure 1.

[0064] In some embodiments, the mask preparation method includes at least one of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, catalytic chemical vapor deposition, and atomic layer deposition.

[0065] In some embodiments, the material of the mask layer 20 includes SiO2. x and Si x N y At least one of them.

[0066] In some embodiments, the groove 30 is prepared by laser grooving ablation.

[0067] In some embodiments, the groove 30 is prepared by laser grooving ablation, with a laser wavelength of 355nm, a laser power of 30W to 80W, and a square laser spot size of 100μm to 300μm, and the horizontal spot overlap rate is controlled to be below 80%.

[0068] In some embodiments, after forming the groove 30 in the opening, the following steps are further included:

[0069] The sample after the groove 30 is formed is texturized using an alkaline solution, forming a texturized structure on the bottom of the groove 30 and the front side of the substrate 10.

[0070] It is understandable that during the texturing process, the back of the substrate 10 on both sides of the groove 30 is protected by the mask layer 20, so the texturing structure is only formed on the bottom of the groove 30 and the front of the substrate 10. Referring to Figure 3, Figure 3 is a schematic diagram of the structure after the groove 30 is formed and texturing is performed based on the structure shown in Figure 2. In the solar cell fabrication method of this application, the process of first preparing the groove 30 and then performing texturing can reduce the number of process steps in the traditional back contact solar cell fabrication process.

[0071] In some embodiments, the texturing process takes 300s to 420s.

[0072] Optionally, the texturing process can be performed for 300s, 320s, 340s, 360s, 380s, 400s, or 420s, or the texturing process can be performed within any two of the above times.

[0073] In some embodiments, the temperature of the flocking process is 70°C to 85°C.

[0074] Optionally, the temperature for the flocking process is 70°C, 72°C, 74°C, 76°C, 78°C, 80°C, 82°C, or 85°C, or the temperature for the flocking process can be within any two of the above temperatures.

[0075] In some embodiments, the width of the groove 30 is 100 μm to 300 μm.

[0076] Optionally, the width of the groove 30 is 100μm, 120μm, 140μm, 160μm, 180μm, 200μm, 220μm, 240μm, 260μm, 280μm or 300μm, or the width of the groove 30 may be within any two of the above widths.

[0077] In some embodiments, after texturing the sample after forming the groove 30 with an alkaline solution, the following steps are also included:

[0078] Use acid to remove the remaining mask layer 20.

[0079] In some embodiments, the following steps are included before fabricating the mask layer 20 on the back side of the substrate 10:

[0080] The substrate 10 is polished using an alkaline solution.

[0081] In some embodiments, the alkaline solution comprises an alkaline solution and water in a volume ratio of 1:5.

[0082] In some embodiments, the alkaline solution includes at least one of NH4OH, KOH, and NaOH.

[0083] In some embodiments, the concentration of the alkaline solution is 40 wt% to 50 wt%.

[0084] Optionally, the concentration of the alkaline solution is 40 wt%, 42 wt%, 44 wt%, 46 wt%, 48 wt%, or 50 wt%, or the concentration of the alkaline solution may be within any two of the above concentrations.

[0085] In some of these embodiments, the polishing temperature is 60°C to 80°C.

[0086] Optionally, the polishing temperature is 60°C, 62°C, 64°C, 66°C, 68°C, 70°C, 72°C, 74°C, 76°C, 78°C, or 80°C, or the polishing temperature may be within any two of the above temperatures.

[0087] In some of these embodiments, the polishing time is 200s to 400s.

[0088] Optionally, the polishing time can be 200s, 220s, 240s, 260s, 280s, 300s, 320s, 340s, 360s, 380s, or 400s, or the polishing time can be within any two of the above times.

[0089] In some embodiments, after polishing the substrate 10 with an alkaline solution, the following steps are also included:

[0090] The polished substrate 10 was cleaned sequentially with acid and deionized water.

[0091] In some embodiments, the acid solution comprises a hydrofluoric acid solution and water in a volume ratio of 1:20.

[0092] In some embodiments, the concentration of the hydrofluoric acid solution is 45 wt% to 50 wt%.

[0093] Optionally, the concentration of the hydrofluoric acid solution is 45 wt%, 46 wt%, 47 wt%, 48 wt%, 49 wt%, or 50 wt%, or the concentration of the hydrofluoric acid solution may be within any two of the above concentrations.

[0094] In some embodiments, the acid cleaning time is 30s to 200s.

[0095] Optionally, the acid cleaning time can be 30s, 50s, 80s, 100s, 120s, 140s, 160s, 180s or 200s, or the acid cleaning time can be within any two of the above times.

[0096] In some embodiments, the base morphology of the cleaned substrate 10 surface has a size of 8 μm to 40 μm and a reflectivity of 40% to 50%.

[0097] S20: A tunneling oxide layer 40 and an intrinsic silicon material layer 50 are sequentially stacked on the back side of the substrate 10 where a groove 30 is formed.

[0098] Referring to Figure 4, which is a schematic diagram of the structure for fabricating a tunneling oxide layer 40 and an intrinsic silicon material layer 50 based on the structure shown in Figure 3, it can be understood that the tunneling oxide layer 40 covers both the bottom and walls of the groove 30 and the back side of the substrate 10.

[0099] In some embodiments, the material of the tunneling oxide layer 40 includes silicon oxide.

[0100] In some embodiments, the thickness of the tunneling oxide layer 40 is 1 nm to 3 nm.

[0101] Optionally, the thickness of the tunneling oxide layer 40 is 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm or 3 nm, or the thickness of the tunneling oxide layer 40 may be within any two of the above thicknesses.

[0102] In some embodiments, the tunneling oxide layer 40 is prepared by low-pressure chemical vapor deposition.

[0103] In some embodiments, the deposition temperature of the tunnel oxide layer 40 is 500°C to 800°C.

[0104] Optionally, the deposition temperature of the tunneling oxide layer 40 is 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, or 800°C, or the deposition temperature of the tunneling oxide layer 40 may be within the range of any two of the above deposition temperatures.

[0105] In some embodiments, the thickness of the intrinsic silicon material layer 50 is 80 nm to 300 nm.

[0106] Optionally, the thickness of the intrinsic silicon material layer 50 is 80nm, 100nm, 120nm, 150nm, 180nm, 200nm, 220nm, 250nm, 280nm or 300nm, or the thickness of the intrinsic silicon material layer 50 may be within any two of the above thicknesses.

[0107] In some embodiments, the intrinsic silicon material layer 50 is an intrinsic polycrystalline silicon layer.

[0108] In some embodiments, the intrinsic silicon material layer 50 is prepared by low-pressure chemical vapor deposition.

[0109] In some embodiments, the silane flow rate is 200 sccm to 1000 sccm during the preparation of the intrinsic silicon material layer 50.

[0110] Optionally, in the preparation of the intrinsic silicon material layer 50, the silane flow rate is 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm or 1000 sccm, or the silane flow rate can be within the range of any two of the above flow rates.

[0111] In some embodiments, the deposition temperature of the intrinsic silicon material layer 50 is 500°C to 900°C.

[0112] Optionally, the deposition temperature of the intrinsic silicon material layer 50 is 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, 800°C, 850°C, or 900°C, or the deposition temperature of the intrinsic silicon material layer 50 may be within the range of any two of the above temperatures.

[0113] S30: The intrinsic silicon material layer 50 has a first region and a second region located on opposite sides of the groove 30. The intrinsic silicon material layer 50 in the first region is doped to obtain a first doped silicon material layer 71, and the intrinsic silicon material layer 50 in the second region is doped to obtain a second doped silicon material layer 72. The doping types of the first doped silicon material layer 71 and the second doped silicon material layer 72 are opposite.

[0114] In some embodiments, doping the intrinsic silicon material layer 50 in the first region to obtain a first doped silicon material layer 71, and doping the intrinsic silicon material layer 50 in the second region to obtain a second doped silicon material layer 72, includes the following steps:

[0115] A first paste 61 is disposed on the surface of the intrinsic silicon material layer 50 in the first region, the first paste 61 comprising a first doping element;

[0116] A second paste 62 is disposed on the surface of the intrinsic silicon material layer 50 in the second region. The second paste 62 includes a second doping element, and the doping types of the first doping element and the second doping element are opposite.

[0117] The intrinsic silicon material layer 50 is doped by laser processing using the first slurry 61 and the second slurry 62.

[0118] Referring to Figures 5 and 6, Figure 5 is a schematic diagram of the structure in which the first slurry 61 and the second slurry 62 are formed based on the structure shown in Figure 4; Figure 6 is a schematic diagram of the structure in which the first doped silicon material layer 71 and the second doped silicon material layer 72 are prepared based on the structure shown in Figure 5. It can be understood that by setting the first slurry 61 and the second slurry 62 on the intrinsic silicon material in the first and second regions, and performing doping through laser processing, the film layer within the intermediate groove 30 can remain unchanged, allowing the groove 30 to separate the first doped silicon material layer 71 and the second doped silicon material layer 72. Furthermore, laser processing enables high-precision doping.

[0119] In some embodiments, the following steps are included before the intrinsic silicon material layer 50 is doped with the first slurry 61 and the second slurry 62 by laser processing:

[0120] The first slurry 61 and the second slurry 62 are dried and cured.

[0121] In some embodiments, the first slurry 61 and the second slurry 62 are boron slurry and phosphorus slurry, respectively.

[0122] In some embodiments, the printing width of the phosphate paste is 30 μm to 200 μm.

[0123] Optionally, the printing width of the phosphate paste is 30μm, 50μm, 80μm, 100μm, 120μm, 150μm, 180μm or 200μm, or the printing width of the phosphate paste may be within the range of any two of the above widths.

[0124] In some embodiments, the solid content of the phosphate paste is 15% to 35%.

[0125] Optionally, the solid content of the phosphate syrup is 15%, 20%, 25%, 30%, or 35%, or the solid content of the phosphate syrup may be within the range of any two of the above solid contents.

[0126] In some embodiments, the viscosity of the phosphate paste is 20 Pa·s to 50 Pa·s.

[0127] Optionally, the viscosity of the phosphate paste is 20 Pa·s, 25 Pa·s, 30 Pa·s, 35 Pa·s, 40 Pa·s, 45 Pa·s or 50 Pa·s, or the viscosity of the phosphate paste may be within the range of any two of the above viscosity values.

[0128] In some embodiments, the printing width of the boron paste is 50 μm to 200 μm.

[0129] Optionally, the printing width of the boron paste is 50μm, 80μm, 100μm, 120μm, 140μm, 160μm, 180μm or 200μm, or the printing width of the boron paste may be within any two of the above widths.

[0130] In some embodiments, the solid content of the boron paste is 20% to 55%.

[0131] Optionally, the solid content of the boron paste is 20%, 25%, 30%, 35%, 40%, 45%, 50%, or 55%, or the solid content of the boron paste may be within the range of any two of the above solid contents.

[0132] In some embodiments, the viscosity of the boron paste is 20 Pa·s to 50 Pa·s.

[0133] Optionally, the viscosity of the boron paste is 20 Pa·s, 25 Pa·s, 30 Pa·s, 35 Pa·s, 40 Pa·s, 45 Pa·s or 50 Pa·s, or the viscosity of the boron paste may be within any two of the above viscosity ranges.

[0134] Within the parameter ranges of the aforementioned phosphate paste and boron paste, a good printing effect of the paste on the intrinsic silicon material layer 50 can be achieved, thereby achieving a more uniform doping effect through laser processing.

[0135] In some embodiments, the laser power for laser processing is 30W to 80W.

[0136] Optionally, the laser power for laser processing is 30W, 40W, 50W, 60W, 70W or 80W, or the laser power for laser processing can be within the range of any two of the above powers.

[0137] In some embodiments, the maximum width of the laser-processed spot is 100 μm to 300 μm.

[0138] Optionally, the maximum width of the laser-processed spot is 100μm, 150μm, 200μm, 250μm or 300μm, or the maximum width of the laser-processed spot can be within any two of the above widths.

[0139] In some embodiments, the laser-processed spot is a square spot.

[0140] In some of these embodiments, the overlap rate of the laser-processed spot is less than 80%.

[0141] In some embodiments, the laser processing scans the area of ​​the printed boron paste with a width of 500 μm to 700 μm.

[0142] Optionally, the scanning width of the area of ​​the printed boron paste by laser processing is 500μm, 550μm, 600μm, 650μm or 700μm, or the scanning width of the area of ​​the printed boron paste by laser processing can also be within the range of any two of the above widths.

[0143] In some embodiments, the laser processing scans the area of ​​the printed phosphate paste with a width of 300 μm to 500 μm.

[0144] Optionally, the scanning width of the area of ​​the printed phosphate paste by laser processing is 300μm, 350μm, 400μm, 450μm or 500μm, or the scanning width of the area of ​​the printed phosphate paste by laser processing can also be within the range of any two of the above widths.

[0145] Understandably, the width of the groove 30 remains unchanged after laser treatment.

[0146] Within the range of parameters for the aforementioned laser processing, a good doping effect can be achieved on the intrinsic silicon material layer 50 through the slurry.

[0147] In some embodiments, after doping the intrinsic silicon material layer 50 in the first region to obtain a first doped silicon material layer 71, and doping the intrinsic silicon material layer 50 in the second region to obtain a second doped silicon material layer 72, the following steps are further included:

[0148] The first doped silicon material layer 71 and the second doped silicon material layer 72 are subjected to hydrogen plasma treatment.

[0149] After preparing the first doped silicon material layer 71 and the second doped silicon material layer 72 by doping the intrinsic silicon material layer 50 with the first slurry 61 and the second slurry 62, the first doped silicon material layer 71 and the second doped silicon material layer 72 are subjected to hydrogen plasma treatment, which can effectively improve the quality of interface passivation.

[0150] In some embodiments, the hydrogen plasma treatment pressure is 1 Torr to 2 Torr.

[0151] Optionally, the pressure of the hydrogen plasma treatment is 1 Torr, 1.2 Torr, 1.4 Torr, 1.6 Torr, 1.8 Torr, or 2 Torr, or the pressure of the hydrogen plasma treatment can be within any two of the above pressures.

[0152] In some embodiments, the temperature of the hydrogen plasma treatment is 150°C to 250°C.

[0153] Optionally, the temperature of the hydrogen plasma treatment is 150°C, 160°C, 170°C, 180°C, 190°C, 200°C, 210°C, 220°C, 230°C, 240°C, or 250°C, or the temperature of the hydrogen plasma treatment may be within any two of the above temperatures.

[0154] In some embodiments, the hydrogen plasma treatment time is 30s to 200s.

[0155] Optionally, the hydrogen plasma treatment time is 30s, 50s, 80s, 100s, 120s, 150s, 180s, or 200s, or the hydrogen plasma treatment time can be within any two of the above times.

[0156] Within the parameter range of the above-mentioned hydrogen plasma treatments, a good treatment effect can be achieved on the first doped silicon material layer 71 and the second doped silicon material layer 72, and the effect of improving the interface passivation quality is good.

[0157] S40: A first passivation antireflection layer 81 and a second passivation antireflection layer 82 are respectively prepared on the front and back sides of the substrate 10.

[0158] Referring to Figure 7, which is a schematic diagram of the structure in which a first passivation antireflection layer 81 and a second passivation antireflection layer 82 are formed based on the structure shown in Figure 6. It can be understood that the first passivation antireflection layer 81 covers the front side of the substrate 10, and the second passivation antireflection layer 82 covers the back side of the substrate 10, as well as the bottom and walls of the groove 30.

[0159] In some embodiments, the first passivation antireflection layer 81 includes a first passivation film and a first antireflection film stacked together, with the first antireflection film disposed on the surface of the first passivation film away from the substrate 10.

[0160] In some embodiments, the material of the first passivation film includes aluminum oxide.

[0161] In some embodiments, the thickness of the first passivation film is 3 nm to 10 nm.

[0162] Optionally, the thickness of the first passivation film is 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, or the thickness of the first passivation film may be within any two of the above thicknesses.

[0163] In some of these embodiments, the first passivation film is prepared by atomic layer deposition.

[0164] In some embodiments, the material of the first antireflective film includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0165] In some embodiments, the thickness of the first antireflective film is 70 nm to 110 nm.

[0166] Optionally, the thickness of the first antireflective film is 70nm, 80nm, 90nm, 100nm or 110nm, or the thickness of the first antireflective film may be within any two of the above thicknesses.

[0167] In some embodiments, the refractive index of the first antireflective coating is 2 to 2.4.

[0168] Optionally, the refractive index of the first antireflective coating is 2, 2.1, 2.2, 2.3 or 2.4, or the refractive index of the first antireflective coating may be within the range of any two of the above reflectivities.

[0169] In some embodiments, the first antireflective film is prepared by plasma-enhanced chemical vapor deposition.

[0170] In some embodiments, the second passivation antireflection layer 82 includes a second passivation film and a second antireflection film stacked together, with the second antireflection film disposed on the surface of the second passivation film away from the substrate 10.

[0171] In some of these embodiments, the material of the second passivation film includes aluminum oxide.

[0172] In some embodiments, the thickness of the second passivation film is 3 nm to 10 nm.

[0173] Optionally, the thickness of the second passivation film is 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, or the thickness of the second passivation film can be within any two of the above thicknesses.

[0174] In some embodiments, the second passivation film is prepared by atomic layer deposition.

[0175] In some embodiments, the material of the second antireflective film includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0176] In some embodiments, the thickness of the second antireflective film is 70 nm to 110 nm.

[0177] Optionally, the thickness of the second antireflective film is 70nm, 80nm, 90nm, 100nm or 110nm, or the thickness of the second antireflective film may be within any two of the above thicknesses.

[0178] In some embodiments, the refractive index of the second antireflective coating is 2 to 2.4.

[0179] Optionally, the refractive index of the second antireflective coating is 2, 2.1, 2.2, 2.3 or 2.4, or the refractive index of the second antireflective coating may be within the range of any two of the above reflectivities.

[0180] In some embodiments, the first antireflective film is prepared by plasma-enhanced chemical vapor deposition.

[0181] S50: A first electrode 91 and a second electrode 92 are prepared on the surface of the second passivation antireflection layer 82. The first electrode 91 is in electrical contact with the first doped silicon material layer 71, and the second electrode 92 is in electrical contact with the second doped silicon material layer 72.

[0182] Referring to Figure 8, Figure 8 is a schematic diagram of a structure in which a first electrode 91 and a second electrode 92 are formed based on the structure shown in Figure 7.

[0183] In some embodiments, the first electrode 91 and the second electrode 92 are prepared by sintering silver paste.

[0184] In some of these embodiments, the sintering temperature is 700°C to 900°C.

[0185] Optionally, the sintering temperature is 700°C, 750°C, 800°C, 850°C or 900°C, or the sintering temperature may be within the range of any two of the above temperatures.

[0186] Another embodiment of this application provides a solar cell prepared by any of the above-described methods.

[0187] Referring again to FIG8, in some embodiments, the solar cell includes a substrate 10 having a front side and a back side disposed opposite to each other, the front side of the substrate 10 having a textured structure and having a first passivation antireflection layer 81 disposed thereon.

[0188] A groove 30 is formed on the back side of the substrate 10, and a tunneling oxide layer 40, an intrinsic silicon material layer 50 and a second passivation antireflection layer 82 are sequentially stacked in the groove 30.

[0189] The solar cell includes a first region and a second region located on opposite sides of the groove 30. A tunneling oxide layer 40, a first doped silicon material layer 71 and a second passivation antireflection layer 82 are sequentially stacked on the back side of the substrate 10 located in the first region. A tunneling oxide layer 40, a second doped silicon material layer 72 and a second passivation antireflection layer 82 are sequentially stacked on the back side of the substrate 10 located in the second region. The doping types of the first doped silicon material layer 71 and the second doped silicon material layer 72 are opposite.

[0190] The solar cell also includes a first electrode 91 and a second electrode 92 disposed on the second passivation antireflection layer 82. The first electrode 91 is in electrical contact with the first doped silicon material layer 71, and the second electrode 92 is in electrical contact with the second doped silicon material layer 72.

[0191] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0192] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims, and the specification and drawings can be used to interpret the content of the claims.

Claims

1. A method for fabricating a solar cell, comprising the following steps: A substrate is provided, the substrate having a front side and a back side disposed opposite to each other; A groove is formed on the back side of the substrate; A tunneling oxide layer and an intrinsic silicon material layer are sequentially stacked on the back side of the substrate; The intrinsic silicon material layer has a first region and a second region located on opposite sides of the groove. The intrinsic silicon material layer in the first region is doped to obtain a first doped silicon material layer, and the intrinsic silicon material layer in the second region is doped to obtain a second doped silicon material layer. The doping types of the first doped silicon material layer and the second doped silicon material layer are opposite.

2. The method for preparing a solar cell according to claim 1, wherein, The process of doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer, and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer, includes the following steps: A first paste is disposed on the surface of the intrinsic silicon material layer in the first region, the first paste comprising a first doping element; A second paste is disposed on the surface of the intrinsic silicon material layer in the second region. The second paste includes a second doping element, and the doping types of the first doping element and the second doping element are opposite. The intrinsic silicon material layer is doped by laser processing using the first slurry and the second slurry.

3. The method for preparing a solar cell according to claim 2, wherein, The laser power of the laser processing is 30W to 80W.

4. The method for preparing a solar cell according to any one of claims 2 to 3, wherein, The maximum width of the laser-processed spot is 100μm to 300μm.

5. The method for preparing a solar cell according to any one of claims 2 to 4, wherein, The overlap rate of the laser-processed spot is below 80%.

6. The method for preparing a solar cell according to any one of claims 1 to 5, wherein, After doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer, and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer, the following steps are further included: The first doped silicon material layer and the second doped silicon material layer are subjected to hydrogen plasma treatment.

7. The method for preparing a solar cell according to claim 6, wherein, The pressure of the hydrogen plasma treatment is 1 Torr to 2 Torr.

8. The method for preparing a solar cell according to any one of claims 6 to 7, wherein, The temperature of the hydrogen plasma treatment is 150℃~250℃.

9. The method for preparing a solar cell according to any one of claims 6 to 8, wherein, The hydrogen plasma treatment time is 30s to 200s.

10. The method for preparing a solar cell according to any one of claims 1 to 9, wherein, Forming a groove on the back side of the substrate includes the following steps: A mask layer is prepared on the back side of the substrate; An opening is formed on the mask layer by using a laser, and a groove is formed within the opening by using a laser.

11. The method for preparing a solar cell according to claim 10, wherein, After forming the groove within the opening, the process further includes the following steps: The sample after the groove is formed is texturized using an alkaline solution to form a texturized structure on the front side of the substrate at the bottom of the groove.

12. The method for preparing a solar cell according to any one of claims 1 to 11, wherein, After doping the intrinsic silicon material layer in the first region to obtain a first doped silicon material layer, and doping the intrinsic silicon material layer in the second region to obtain a second doped silicon material layer, the following steps are further included: A first passivation antireflection layer and a second passivation antireflection layer are respectively prepared on the front and back sides of the substrate.

13. A solar cell, prepared by the method of any one of claims 1 to 12.

14. The solar cell according to claim 13, wherein, It includes a substrate having a front side and a back side arranged opposite to each other, wherein the front side of the substrate has a textured structure and is provided with a first passivation antireflection layer; A groove is formed on the back side of the substrate, and a tunneling oxide layer, an intrinsic silicon material layer and a second passivation antireflection layer are sequentially stacked in the groove. The solar cell includes a first region and a second region located on opposite sides of the groove. The substrate in the first region has a tunneling oxide layer, a first doped silicon material layer and a second passivation antireflection layer stacked sequentially on its back side. The substrate in the second region has a tunneling oxide layer, a second doped silicon material layer and a second passivation antireflection layer stacked sequentially on its back side. The doping types of the first doped silicon material layer and the second doped silicon material layer are opposite. The solar cell further includes a first electrode and a second electrode disposed on the second passivation antireflection layer, wherein the first electrode is electrically in contact with the first doped silicon material layer, and the second electrode is electrically in contact with the second doped silicon material layer.

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