Solar cell

Abstract

Disclosed is a solar cell including: a semiconductor substrate; a first tunneling layer entirely formed on a surface of the semiconductor substrate; a first conductivity type region provided on the surface of the semiconductor substrate; and an electrode including a first electrode connected to the first conductivity type region.

Description

[0001] This application is a divisional application of the original invention patent application with application number 201410130976.0 (application date: April 2, 2014, invention title: solar cell). Technical Field

[0002] Embodiments of the present invention relate to solar cells, and more specifically, to a solar cell comprising a semiconductor substrate. Background Technology

[0003] In recent years, with the anticipated depletion of traditional energy sources such as oil and coal, attention has been growing on alternative energy sources to replace them. Among these, solar cells, as the next generation of batteries that convert solar energy into electricity, have attracted considerable attention.

[0004] This type of solar cell can be manufactured by forming conductive regions on a semiconductor substrate and electrodes electrically connected to those conductive regions to induce photoelectric conversion. Additionally, the solar cell may include a passivation film that passivates the conductive regions, an anti-reflection film to prevent reflection, etc., to improve the performance of the solar cell.

[0005] In this regard, the efficiency of traditional solar cells may be degraded due to factors such as carrier recombination on the semiconductor substrate and the long migration distance of carriers. Therefore, solar cells should be designed to maximize their efficiency. Summary of the Invention

[0006] The purpose of this invention is to provide a solar cell that can maximize efficiency.

[0007] According to one aspect of the present invention, the above and other aspects can be achieved by providing a solar cell comprising: a semiconductor substrate; a first tunneling layer formed entirely on the surface of the semiconductor substrate; a first conductivity type region disposed on the surface of the semiconductor substrate; and an electrode comprising a first electrode connected to the first conductivity type region, wherein the first conductivity type region comprises a first portion disposed on the first tunneling layer and comprises a polycrystalline semiconductor, an amorphous semiconductor, or a microcrystalline semiconductor doped with a dopant of the first conductivity type.

[0008] According to an embodiment of the present invention, after forming the tunneling layer on the semiconductor substrate, a conductive type region (emitter region, back surface field region, etc.) is formed on the tunneling layer. As a result, defects on the back surface of the semiconductor substrate are effectively removed, and photoelectric conversion carriers are effectively migrated. Therefore, damage to the semiconductor substrate is prevented, and recombination sites on the back surface of the semiconductor substrate are effectively removed. Therefore, the efficiency of the solar cell can be further improved.

[0009] In a solar cell according to another embodiment of the invention, the conductive type region comprises a plurality of portions, said portions being configured such that a tunneling layer is interposed between said portions, thereby minimizing recombination on the semiconductor substrate and improving electrical connection with the electrodes. As a result, the efficiency of the solar cell can be improved. Attached Figure Description

[0010] The above and other objects, features, and advantages of embodiments of the present invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a cross-sectional view showing a solar cell according to an embodiment of the present invention;

[0012] Figure 2 This is a plan view showing a solar cell according to this embodiment;

[0013] Figure 3 It shows the basis Figure 1 A cross-sectional view of the solar cell in the modified embodiment shown;

[0014] Figure 4 This is a cross-sectional view showing a solar cell according to another embodiment of the present invention;

[0015] Figure 5 It shows the basis Figure 4 A cross-sectional view of the solar cell in the modified embodiment shown;

[0016] Figure 6 It is shown Figure 4 A cross-sectional view of another modified embodiment of the illustrated implementation;

[0017] Figure 7 It shows the basis Figure 4 A cross-sectional view of a solar cell according to another modified embodiment of the illustrated embodiment;

[0018] Figure 8 This is a cross-sectional view showing a solar cell according to another embodiment of the present invention;

[0019] Figure 9 It shows the basis Figure 8 A cross-sectional view of the solar cell in the modified embodiment shown;

[0020] Figure 10 It shows the basis Figure 8 A cross-sectional view of a solar cell according to another modified embodiment of the illustrated embodiment;

[0021] Figure 11 This is a cross-sectional view showing a solar cell according to another embodiment of the present invention;

[0022] Figure 12 It shows the basis Figure 11 A cross-sectional view of a solar cell according to another modified embodiment of the illustrated embodiment;

[0023] Figure 13 It shows the basis Figure 11 A cross-sectional view of a solar cell according to another modified embodiment of the illustrated embodiment;

[0024] Figure 14 It shows the basis Figure 11 A cross-sectional view of a solar cell according to another modified embodiment of the illustrated embodiment;

[0025] Figure 15 It shows the basis Figure 11 A cross-sectional view of a solar cell according to another modified embodiment of the illustrated embodiment;

[0026] Figures 16A to 16E It is shown Figure 11 A cross-sectional view of the method for manufacturing a solar cell is shown; and

[0027] Figure 17 This is a cross-sectional view showing a solar cell according to another embodiment of the present invention. Detailed Implementation

[0028] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. The embodiments of the invention are not limited to those described, and may be modified in various ways.

[0029] In the accompanying drawings, for the sake of clarity and brevity in describing the embodiments of the present invention, parts unrelated to the description are not shown, and throughout the specification, the same reference numerals will be used to refer to the same or similar parts.

[0030] In the accompanying drawings, thicknesses or dimensions have been exaggerated or reduced for clarity. Furthermore, the dimensions or areas of the individual components are not limited to those shown in the figures.

[0031] It will also be understood that throughout this specification, when an element is referred to as "comprising" another element, the term "comprising" indicates the presence of the other element but does not exclude the presence of other additional elements unless the context clearly indicates otherwise. Furthermore, it will be understood that when an element such as a layer, film, region, or plate is referred to as "on" another element, this element may be directly on said other element, and one or more intermediate elements may also be present. Conversely, when an element such as a layer, film, region, or plate is referred to as "directly on" another element, one or more intermediate elements are not present.

[0032] The solar cell according to an embodiment of the present invention will now be described in more detail with reference to the accompanying drawings.

[0033] Figure 1 This is a cross-sectional view showing a solar cell according to an embodiment of the present invention. Figure 2 This is a plan view showing a solar cell according to this embodiment.

[0034] Reference Figure 1 and Figure 2 A solar cell 100 according to an embodiment of the present invention includes a substrate (e.g., a semiconductor substrate, hereinafter referred to as "semiconductor substrate") 10, conductive type regions 20 and 30, electrodes 24 and 34 connected to the conductive type regions 20 and 30, and at least one tunneling layer 40. The conductive type regions 20 and 30 may include an emitter region 20 and a back surface field region 30, and the electrodes 24 and 34 may include a first electrode 24 and a second electrode 34 connected to the emitter region 20 and the back surface field region 30, respectively. The tunneling layer 40 may be located between the semiconductor substrate 10 and at least one of the conductive type regions 20 and 30. The tunneling layer 40 may be included together with a first passivation film 21, a first antireflection film 22, a second passivation film 31, a second antireflection film 32, etc. This configuration will be described in more detail.

[0035] One of the emitter region 20 and the back surface field region 30 is referred to as a "first conductivity type region" and the other as a "second conductivity type region". In embodiments of the present invention, terms such as first or second are used only to distinguish elements, and embodiments of the present invention are not limited thereto.

[0036] The semiconductor substrate 10 may include a base region 110 containing dopants of a first conductivity type with a relatively low doping concentration. The base region 110 may be constructed of a crystalline semiconductor containing dopants of the first conductivity type. For example, the base region 110 may include a single-crystal or polycrystalline semiconductor (e.g., single-crystal silicon or polycrystalline silicon) containing dopants of the first conductivity type. Specifically, the base region 110 may be constructed of a single-crystal semiconductor (e.g., a single-crystal semiconductor wafer, more specifically, a semiconductor silicon wafer) containing dopants of the first conductivity type. Therefore, when the base region 110 is constructed of single-crystal silicon, the solar cell 100 constitutes a single-crystal silicon solar cell. Thus, the solar cell 100, which includes a single-crystal semiconductor, is based on the base region 110 or the semiconductor substrate 10, which exhibits excellent electrical performance due to its excellent crystallinity and low defect content.

[0037] For example, the dopant of the first conductivity type is an n-type or p-type dopant. That is, the dopant of the first conductivity type can be an n-type impurity such as a group V element (including phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb), etc.). Alternatively, the dopant of the first conductivity type can be a p-type impurity such as a group III element (including boron (B), aluminum (Al), gallium (Ga), indium (In), etc.).

[0038] In this configuration, the base region 110 may include n-type impurities as dopants of the first conductivity type. Consequently, the emitter region 20, which forms a pn junction with the base region 110, is p-type. When light is emitted to the pn junction, electrons generated by the photoelectric effect move toward the second surface (hereinafter referred to as the "back side") of the semiconductor substrate 10 and are collected by the second electrode 34, while holes move toward the front side of the semiconductor substrate 10 and are collected by the first electrode 24. As a result, electrical energy is generated. Holes with low migration speed move toward the front side (rather than the back side) of the semiconductor substrate 10, thereby improving photoelectric conversion efficiency. However, embodiments of the present invention are not limited to this; in other embodiments, the base region 110 and the back side field region 30 may be p-type, and the emitter region 20 may be n-type.

[0039] In embodiments of the present invention, the semiconductor substrate 10 may include only the base region 110. That is, in conventional solar cells, doped regions having a different conductivity type than the semiconductor substrate 10, or doped regions having the same conductivity type as the semiconductor substrate 10 but with a relatively high doping concentration, are formed on the semiconductor substrate 10. On the other hand, in embodiments of the present invention, the semiconductor substrate 10 includes only the base region 110 and does not include additional doped regions.

[0040] As described above, the semiconductor substrate 10 consists only of the base region and does not include any additional doped regions. For example, the difference between the lowest and highest doping concentrations in the semiconductor substrate 10 may be 10% or lower. A difference of 10% or lower is given as an example to determine the level at which doping for forming additional doped regions is not performed, but embodiments of the invention are not limited thereto. That is, a difference of 10% or lower represents the range of possible doping variations within the substrate, similar to an error tolerance. Therefore, embodiments of the invention include all cases where the semiconductor substrate 10 generally does not have any additional doped regions.

[0041] In an embodiment of the present invention, the semiconductor substrate 10 is not provided with additional doped regions, thus improving the open-circuit voltage. This is because surface recombination of charge carriers that may be generated or occur due to the formation of doped regions on the semiconductor substrate 10 can be prevented.

[0042] In embodiments of the present invention, the front and back surfaces of the semiconductor substrate 10 are textured, resulting in an unevenness such as a pyramid shape. When the surface roughness increases due to the unevenness formed on the front surface of the semiconductor substrate 10 through texturing, the reflection of light incident on the front surface of the semiconductor substrate 10 can be reduced. Therefore, the amount of light reaching the tunnel junction formed by the semiconductor substrate 10 and the emitter region 20 increases, thus minimizing light loss. However, embodiments of the present invention are not limited to this; only one of the front and back surfaces of the semiconductor substrate 10 may be textured, or neither surface may be textured.

[0043] The first tunneling layer 42 is formed entirely on one surface (e.g., the front side, hereinafter referred to as "front side") of the semiconductor substrate 10. As used herein, the expression "entirely formed on" means that elements such as layers are formed on the entire surface without any blank or uncovered areas, or are formed on the entire area except for areas that are pre-designed or unavoidably formed (e.g., peripheral areas, isolation areas, etc.).

[0044] The first tunneling layer 42 passivates the surface of the semiconductor substrate 10, which has many recombination sites, and facilitates the migration of charge carriers through the tunneling effect.

[0045] The first tunneling layer 42 may include a material that provides passivation and tunneling effects, such as oxides, nitrides, semiconductors, conductive polymers, etc. For example, the first tunneling layer 42 may include silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, etc. In this case, the first tunneling layer 42 can be easily and stably formed.

[0046] To provide sufficient passivation and tunneling effects, the first tunneling layer 42 may have a thickness of 5 nm or less, or 0.5 nm to 5 nm (e.g., 0.5 nm to 4 nm, e.g., 0.5 nm to 2 nm). When the thickness of the first tunneling layer 42 exceeds 5 nm, tunneling cannot be effectively performed, and the solar cell 100 may not function. When the thickness of the first tunneling layer 42 is less than 0.5 nm, the passivation performance may deteriorate. To further improve the tunneling effect, the thickness of the first tunneling layer 42 may be 0.5 nm to 4 nm, more specifically, 0.5 nm to 2 nm, but embodiments of the present invention are not limited thereto, and the thickness of the first tunneling layer 42 may be varied.

[0047] In an embodiment of the present invention, a first tunneling layer 42 is formed on the front side of the semiconductor substrate 10, thereby completely eliminating defects on the front side of the semiconductor substrate 10. As a result, the open-circuit voltage of the solar cell 100 is improved, thus enhancing the efficiency of the solar cell 100.

[0048] In embodiments of the present invention, the emitter region 20 includes a first portion 20a formed on the first tunneling layer 42. The first portion 20a may include a polycrystalline semiconductor, amorphous semiconductor, or microcrystalline semiconductor having a different conductivity type (e.g., p-type or n-type) than the semiconductor substrate 10. For example, the emitter region may include polycrystalline silicon, amorphous silicon, or microcrystalline silicon doped with a dopant of a second conductivity type. In this case, the emitter region 20 including the first portion 20a can be readily manufactured according to various methods by forming the first portion 20a using a polycrystalline semiconductor, amorphous semiconductor, or microcrystalline semiconductor.

[0049] In embodiments of the invention, a first portion 20a of the emitter region 20 may be entirely formed on the first tunneling layer 42. As used herein, the expression "entirely formed on" means that an element such as a layer is formed over the entire surface without any blank or uncovered areas, or over the entire area except for areas pre-designed or unavoidably formed (e.g., peripheral areas, isolation areas, etc.). A first passivation film 21 and / or a first antireflection film 22 may be formed on the emitter region 20 (more specifically, the first portion 20a). In embodiments of the invention, an example is a configuration in which the first passivation film 21 is formed on the emitter region 20 and the first antireflection film 22 is formed on the first passivation film 21. In this embodiment, the first passivation film 21 may be formed over substantially the entire area of ​​the front side of the back surface field region 30, except for the area corresponding to the first electrode 24. Additionally, the first antireflection film 22 may be formed over substantially the entire area of ​​the front side of the first passivation film 21, except for the area corresponding to the first electrode 24.

[0050] The first passivation film 21 passivates defects present in the emitter region 20, removing recombination sites for minority carriers and thereby increasing the open-circuit voltage of the solar cell 100. Additionally, the first antireflection film 22 reduces the reflectivity of light incident on the front surface of the semiconductor substrate 10, thereby increasing the amount of light reaching the tunnel junction formed between the semiconductor substrate 10 and the emitter region 20. Therefore, the short-circuit current (Isc) of the solar cell 100 can be increased. Thus, the first passivation film 21 and the first antireflection film 22 increase the open-circuit voltage and short-circuit current of the solar cell 100, thereby improving the efficiency of the solar cell 100.

[0051] The first passivation film 21 may be formed of a material capable of effectively passivating the emitter region 20. For example, the first passivation film 21 may be a single film comprising one selected from the group consisting of silicon nitride, hydrogen-containing silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, zinc oxide, hafnium dioxide, MgF2, ZnS, TiO2, and CeO2, or a multilayer film comprising a combination of two or more films. When the emitter region 20 is n-type, the first passivation film 21 may comprise positively charged silicon oxide or silicon nitride, etc., and when the emitter region 20 is p-type, the first passivation film 21 may comprise negatively charged aluminum oxide, zinc oxide, hafnium dioxide, etc.

[0052] Furthermore, the first antireflective film 22 can be formed of various materials capable of preventing surface reflection. For example, the first antireflective film 22 can be a single film comprising one selected from the group consisting of silicon nitride, hydrogen-containing silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, MgF2, ZnS, TiO2, and CeO2, or a multilayer film comprising a combination of two or more films. However, embodiments of the present invention are not limited thereto, and the first antireflective film 22 may comprise various materials.

[0053] The first electrode 24 is electrically connected to the emitter region 20 via openings formed in the first passivation film 21 and the first antireflection film 22 (i.e., passing through the first passivation film 21 and the first antireflection film 22). The first electrode 24 can be formed in various shapes using various materials. The planar shape of the first electrode 24, etc., will be described in more detail later.

[0054] Furthermore, the second tunneling layer 44 is formed entirely on another surface (e.g., the back side, hereinafter referred to as the "back side") of the semiconductor substrate 10. As used herein, the expression "entirely formed on" means that elements such as the layer are formed on the entire surface without any blank or uncovered areas, or are formed on the entire area except for areas that are pre-designed or unavoidably formed (e.g., peripheral areas, isolation areas, etc.).

[0055] The second tunneling layer 44 passivates the surface of the semiconductor substrate 10, which has many recombination sites, and facilitates carrier migration through the tunneling effect.

[0056] The second tunneling layer 44 may include materials that provide passivation and tunneling effects, such as oxides, nitrides, semiconductors, conductive polymers, etc. For example, the second tunneling layer 44 may include silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, etc. In this case, the second tunneling layer 44 can be easily and stably formed.

[0057] To provide sufficient passivation and tunneling effects, the second tunneling layer 44 may have a thickness of 5 nm or less, or 0.5 nm to 5 nm (e.g., 0.5 nm to 4 nm, e.g., 0.5 nm to 2 nm). When the thickness of the second tunneling layer 44 exceeds 5 nm, tunneling cannot be effectively performed, and the solar cell 100 may not function. When the thickness of the second tunneling layer 44 is less than 0.5 nm, the passivation performance may deteriorate. To further improve the tunneling effect, the thickness of the second tunneling layer 44 may be 0.5 nm to 4 nm, more specifically, 0.5 nm to 2 nm, but embodiments of the present invention are not limited thereto, and the thickness of the second tunneling layer 44 may be varied.

[0058] A second tunneling layer 44 is formed on the back side of the semiconductor substrate 10, thereby completely eliminating defects on the back side of the semiconductor substrate 10. As a result, the open-circuit voltage of the solar cell 100 is improved, thus enhancing the efficiency of the solar cell 100.

[0059] In an embodiment of the present invention, the back surface field region 30 includes a first portion 30a formed on the second tunneling layer 44. The first portion 30a of the back surface field region 30 formed on the second tunneling layer 44 may include a polycrystalline semiconductor, amorphous semiconductor, or microcrystalline semiconductor having the same conductivity type (e.g., p-type or n-type) as the semiconductor substrate 10. For example, the first portion 30a of the back surface field region 30 may include polycrystalline silicon, amorphous silicon, or microcrystalline silicon doped with a dopant of a first conductivity type. In this case, the back surface field region 30 can be readily manufactured according to various methods by forming the first portion 30a of the back surface field region 30 using a polycrystalline semiconductor, amorphous semiconductor, or microcrystalline semiconductor.

[0060] In embodiments of the invention, the back surface field region 30 may be entirely formed on the second tunneling layer 44. As used herein, the expression "entirely formed on" means that elements such as layers are formed over the entire surface without any blank or uncovered areas, or over the entire area except for areas that are pre-designed or unavoidably formed (e.g., peripheral areas, isolation areas, etc.).

[0061] The second passivation film 31 and / or the second antireflection film 32 may be formed on the back surface field region 30. In an embodiment of the present invention, an example is taken where the second passivation film 31 is formed on the back surface field region 30, and the second antireflection film 32 is formed on the second passivation film 31. In an embodiment of the present invention, the second passivation film 31 may be formed on the front surface of the back surface field region 30, covering substantially the entire region except for the region corresponding to the second electrode 34. Furthermore, the second antireflection film 32 may be formed on the front surface of the second passivation film 31, covering substantially the entire region except for the region corresponding to the second electrode 34.

[0062] The second passivation film 31 passivates defects present in the back surface field region 30, removing recombination sites for minority carriers and thereby increasing the open-circuit voltage of the solar cell 100. Furthermore, the second antireflection film 32 reduces the reflectivity of light incident on the back surface of the semiconductor substrate 10, thereby increasing the amount of light reaching the tunnel junction formed between the semiconductor substrate 10 and the emitter region 20. Therefore, the short-circuit current (Isc) of the solar cell 100 can be increased. Thus, the second passivation film 31 and the second antireflection film 32 increase the open-circuit voltage and short-circuit current of the solar cell 100, thereby improving the efficiency of the solar cell 100.

[0063] The second passivation film 31 may be formed of a material capable of effectively passivating the back surface field region 30. For example, the second passivation film 31 may be a single film comprising one selected from the group consisting of silicon nitride, hydrogen-containing silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, zinc oxide, hafnium dioxide, MgF2, ZnS, TiO2, and CeO2, or a multilayer film comprising a combination of two or more films. When the back surface field region 30 is p-type, the second passivation film 31 may comprise negatively charged materials such as aluminum oxide, zinc oxide, and hafnium dioxide; when the back surface field region 30 is n-type, the second passivation film 31 may comprise positively charged materials such as silicon oxide and silicon nitride.

[0064] Furthermore, the second antireflective film 32 can be formed of various materials capable of preventing surface reflection. For example, the second antireflective film 32 can be a single film comprising one selected from the group consisting of silicon nitride, hydrogen-containing silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, MgF2, ZnS, TiO2, and CeO2, or a multilayer film comprising a combination of two or more films. However, embodiments of the present invention are not limited thereto, and the second antireflective film 32 may comprise various materials.

[0065] The second electrode 34 is electrically connected to the back surface field region 30 via an opening formed in the second passivation film 31 and the second antireflection film 32 (i.e., passing through both the second passivation film 31 and the second antireflection film 32). The second electrode 34 can be formed in various shapes using various materials. The planar shape of the second electrode 34, etc., will be described in more detail later.

[0066] The following will refer to Figure 2 The planar shapes of the first electrode 24 and the second electrode 34 are described in more detail.

[0067] Reference Figure 2 For example, the first electrode 24 and the second electrode 34 may include a plurality of finger electrodes 24a and 34a having a first spacing P1 and arranged parallel to each other. The first electrode 24 and the second electrode 34 may include bus bar electrodes 24b and 34b, which are formed in a direction intersecting the direction in which the finger electrodes 24a and 34a are arranged and connect the finger electrodes 24a and 34a. There may be only one such bus bar electrode 24b or 34b, and a total line electrode with a second spacing P2 larger than the first spacing P1 may be provided. In this case, the width W2 of the bus bar electrode 24b may be greater than the width W1 of the finger electrode 24a, but the embodiments of the present invention are not limited thereto, and the width W2 of the bus bar electrode 24b may be equal to or less than the width W1 of the finger electrode 24a. In addition, various configurations, such as those in which the bus bar electrode 24b is not formed, are also possible. The shape of the first electrode 24 is provided only as an example, but the embodiments of the present invention are not limited thereto. In the accompanying drawings, the first distance P1 between the first electrode 24 and the second electrode 34 is described without distinction, and the second distance P2 between the first electrode 24 and the second electrode 34 is described without distinction. The first distance P1 between the first electrode 24 may be the same as or different from the first distance P1 between the second electrode 34, and the second distance P2 between the first electrode 24 and the second distance P2 between the second electrode 34 may be the same as or different from the second distance P2 between the second electrode 34.

[0068] As can be seen from the cross-section, the finger electrode 24a and the bus strip electrode 24b of the first electrode 24 can pass through the first passivation film 21 and the first antireflection film 22. Similarly, the finger electrode 34a and the bus strip electrode 34b of the second electrode 34 can pass through the second passivation film 31 and the second antireflection film 32. Alternatively, the finger electrode 24a of the first electrode 24 can pass through the first passivation film 21 and the first antireflection film 22, and the bus strip electrode 24b can be formed on the first passivation film 21. Similarly, the finger electrode 34a of the second electrode 34 can pass through the second passivation film 31 and the second antireflection film 32, and the bus strip electrode 34b can be formed on the second passivation film 31 and the antireflection film 32.

[0069] The first electrode 24 and the second electrode 34 may be made of highly conductive metals or the like, and may be formed by various methods such as coating, deposition, and printing. Embodiments of the present invention are not limited to the materials and formation methods of the first electrode 24 and the second electrode 34.

[0070] In the solar cell 100 having the aforementioned structure, a first portion 20a of the emitter region 20, which is another type of conductivity region, is formed on the front side of the semiconductor substrate 10, such that a first tunneling layer 42 is located between the first portion 20a and the semiconductor substrate 10. The first tunneling layer 42 is formed entirely on the front side of the semiconductor substrate 10, thereby effectively removing defects on the front side of the semiconductor substrate 10. In this case, the first tunneling layer 42 effectively facilitates carrier migration, resulting in photoelectric conversion. That is, in conventional solar cells, a portion of the semiconductor substrate is doped with a high concentration of dopant, thereby forming a doped region in the semiconductor substrate that serves as the emitter region. In this case, doping with the dopant causes damage to the semiconductor substrate and leads to the formation of recombination sites on the surface of the semiconductor substrate. Although a passivation film is formed to prevent these problems, the passivation film is not provided in the portion of the semiconductor substrate adjacent to the electrode, making it difficult to effectively remove recombination sites. Therefore, due to recombination sites on the surface of the semiconductor substrate, the efficiency of the solar cell is low.

[0071] On the other hand, in an embodiment of the present invention, the entire front side of the semiconductor substrate 10, where many recombination sites may exist, is passivated using a first tunneling layer 42, and a first portion 20a of the emitter region 20 is formed on the first tunneling layer 42. As a result, damage to the semiconductor substrate 10 is prevented, and recombination sites on the front side of the semiconductor substrate 10 are effectively removed. Specifically, the emitter region 20 is composed only of the first portion 20a, thereby simplifying the structure of the emitter region 20 and minimizing damage to the semiconductor substrate 10. As a result, the efficiency of the solar cell 100 can be improved.

[0072] Furthermore, a back-side field region 30, which is another type of conductivity region, is formed on the back side of the semiconductor substrate 10, such that a second tunneling layer 44 is located between the back-side field region 30 and the semiconductor substrate 10. The second tunneling layer 44 is formed entirely on the back side of the semiconductor substrate 10, thereby effectively removing defects on the back side of the semiconductor substrate 10. In this case, the second tunneling layer 44 effectively facilitates carrier migration, resulting in photoelectric conversion. As a result, damage to the semiconductor substrate 10 is further prevented, and recombination sites on the back side of the semiconductor substrate 10 are effectively removed. Specifically, the back-side field region 30 is composed only of the first portion 30a, thereby simplifying the structure of the back-side field region 30 and minimizing damage to the semiconductor substrate 10. As a result, the efficiency of the solar cell 100 can be further improved.

[0073] Based on this structure, the semiconductor substrate 10 includes only the base region 110 without any additional doped regions, thus maintaining the excellent performance of the semiconductor substrate 10.

[0074] In this configuration, the emitter region 20 and the back surface field region 30 can be disposed on different sides of the semiconductor substrate 10 to form a double-sided light-receiving structure. As a result, light is incident on both the back and front surfaces of the semiconductor substrate 10, thereby increasing the amount of incident light and improving the efficiency of the solar cell 100. Since the emitter region 20 and the back surface field region 30 are not adjacent to each other, the isolation process required when the emitter region 20 and the back surface field region 30 are formed adjacent to each other is eliminated. Furthermore, since the emitter region 20 and the back surface field region 30 are formed integrally, additional patterning and alignment processes are not required. Consequently, the manufacturing process is simplified, and therefore the cost is reduced.

[0075] In addition, the first passivation film 21 and the first antireflection film 22 are formed on the front side of the semiconductor substrate 10, thereby further improving the efficiency of the solar cell 100.

[0076] Furthermore, the second electrode 34 is configured to include a finger electrode 34a and a bus bar electrode 34b, thereby allowing light to be incident on the back surface of the semiconductor substrate 10 and enhancing light utilization. In this case, a second passivation film 31 and a second antireflection film 32 are formed on the back surface of the semiconductor substrate 10, thereby further improving the efficiency of the solar cell 100.

[0077] The following will refer to Figures 3 to 10 A solar cell according to modified and other embodiments of the present invention will be described in more detail. Details of contents or elements that are the same as or similar to those described above will not be mentioned again; only descriptions that differ from the above descriptions will be described in detail.

[0078] Figure 3 It shows the basis Figure 1 A cross-sectional view of the solar cell in the modified embodiment shown.

[0079] Reference Figure 3 The solar cell according to the modified embodiment does not include the first passivation film 21 and the second passivation film 31, but includes a first antireflection film 22 formed on the emitter region 20 and a second antireflection film 32 formed on the back field region 30. Based on this structure, the overall process is simplified, thus reducing manufacturing costs. In addition, the first antireflection film 22 and the second antireflection film 32 also serve as passivation films. As a result, production efficiency is improved while maintaining the excellent performance of the solar cell.

[0080] Embodiments of the present invention allow for various other modifications. For example, all configurations that do not include at least one of the first passivation film 21 and the second passivation film 31, and the first antireflection film 22 and the second antireflection film 32, fall within the scope of embodiments of the present invention.

[0081] Figure 4This is a cross-sectional view showing a solar cell according to another embodiment of the present invention.

[0082] Reference Figure 4 According to an embodiment of the present invention, a solar cell has a structure in which the back surface field region 30 includes a second portion 30b, which includes a doped region formed in a semiconductor substrate 10. That is, the semiconductor substrate 10 may include a base region 110 as an undoped region and a second portion 30b of the back surface field region 30, which is formed by doping the semiconductor substrate 10 with a dopant of the same conductivity type as the semiconductor substrate 10. As a result, the second portion 30b may have the same crystal structure as the base region 110. The second portion 30b of the back surface field region 30 may be formed by various doping methods (e.g., thermal diffusion, ion implantation, etc.).

[0083] In the accompanying drawings, an example is taken where the second portion 30b of the back-side field region 30 has a homogeneous structure with uniform doping concentration. However, the embodiments of the present invention are not limited to this, and related modified embodiments will be referred to. Figure 5 and Figure 6 Let me describe it again.

[0084] The second passivation film 31 and / or the second antireflection film 32 may be formed on the back field region 30.

[0085] When forming a back surface field region 30 including a second portion 30b formed by doping the semiconductor substrate 10, previous processes can be used on the back surface during the formation of the back surface field region 30. That is, a first portion 20a of the emitter region 20 is formed on the first tunneling layer 42 on the front surface of the semiconductor substrate 10, thereby improving the efficiency of the solar cell, and previous equipment can be used in the second portion 30b of the back surface field region 30. In other words, performance can be improved by taking efficiency and manufacturing efficiency into account.

[0086] Figure 5 It shows the basis Figure 4 A cross-sectional view of the solar cell in the modified embodiment shown.

[0087] Reference Figure 5 In the modified embodiment, the back surface field region 30 may have a selective structure for the back surface field region 30. That is, the back surface field region 30 may include a first region 301 having a high doping concentration and therefore a relatively low resistance, and a second region 302 having a lower doping concentration than the first region 301 and therefore a relatively high resistance. The first region 301 is formed such that the first region 301 contacts a portion or all (i.e., at least a portion) of the second electrode 34.

[0088] Based on this configuration, a second region 302 with relatively high resistance is formed between the second electrodes 34, onto which light is incident, thereby improving the passivation effect. Simultaneously, a first region 301 with relatively low resistance is formed in the region adjacent to the first electrode 34, thereby reducing the contact resistance with the first electrode 34. In other words, the second portion 30b of the back surface field region 30 in this embodiment of the invention maximizes the efficiency of the solar cell through a selective structure.

[0089] Figure 6 It is shown Figure 4 A cross-sectional view of another modified embodiment of the illustrated implementation.

[0090] Reference Figure 6 In embodiments of the present invention, the second portion 30b of the back surface field region 30 may have a localized structure. That is, the second portion 30b of the back surface field region 30 may include a first region 301 formed locally only in a region corresponding to at least a portion of the second electrode 34. As a result, damage to the semiconductor substrate 10 is minimized, and thus surface recombination sites are minimized.

[0091] Figure 7 It shows the basis Figure 4 A cross-sectional view of a solar cell according to another modified embodiment of the illustrated embodiment.

[0092] Reference Figure 7 The solar cell according to the modified embodiment does not include the first passivation film 21 and the second passivation film 31, but includes a first antireflection film 22 formed on the emitter region 20 and a second antireflection film 32 formed on the back field region 30. As a result, the overall process is simplified and the cost is reduced. In addition, the first antireflection film 22 and the second antireflection film 32 also serve as passivation films. As a result, production efficiency is improved while maintaining the excellent performance of the solar cell.

[0093] Embodiments of the present invention allow for various other modifications. For example, all configurations that do not include at least one of the first passivation film 21 and the second passivation film 31, and the first antireflection film 22 and the second antireflection film 32, fall within the scope of embodiments of the present invention.

[0094] Figure 7 The second portion 30b of the back field region 30 is shown to have Figure 4 The example shown is a uniform structure, but the second portion 30b of the back field region 30 may have... Figure 5 or Figure 6 The selective or local structures shown.

[0095] Figure 8 This is a cross-sectional view showing a solar cell according to another embodiment of the present invention.

[0096] Reference Figure 8 In a solar cell according to an embodiment of the present invention, the emitter region 20 includes a second portion 20b, which includes a doped region formed in the semiconductor substrate 10. That is, the semiconductor substrate 10 may include a base region 110 as an undoped region and a second portion 20b of the emitter region 20, which is formed by doping the semiconductor substrate 10 with a dopant of a different conductivity type. As a result, the second portion 20b may have the same crystal structure as the base region 110. The emitter region 20 can be formed by various doping methods (e.g., thermal diffusion, ion implantation, etc.).

[0097] In the accompanying drawings, the second portion 20b of the emitter region 20 is shown as an example, possessing a homogeneous structure with uniform doping concentration. However, the embodiments of the present invention are not limited to this, and related modified embodiments will be referred to. Figure 9 Let me describe it again.

[0098] The first passivation film 21 and / or the first antireflection film 22 may be formed on the emitter region 20.

[0099] In the case of forming an emitter region 20 including a second portion 20b formed by doping the semiconductor substrate 10, a previous process can be used on the back side during the formation of the emitter region 20. Therefore, previous equipment can be used. That is, performance can be improved by taking efficiency and production efficiency into consideration.

[0100] Figure 9 It shows the basis Figure 8 A cross-sectional view of the solar cell in the modified embodiment shown.

[0101] Reference Figure 9 In an embodiment of the present invention, the second portion 20b of the emitter region 20 may have a selective structure.

[0102] That is, the emitter region 20 may include a first region 201 having a high doping concentration and thus a relatively low resistance, and a second region 202 having a lower doping concentration and thus a relatively high resistance. The first region 201 is formed such that the first region 201 contacts a portion or all (i.e., at least a portion) of the first electrode 24.

[0103] Therefore, in an embodiment of the invention, a second region 202 with relatively high resistance is formed in the region between the first electrodes 24, where light is incident, thereby achieving a shallow junction emitter. As a result, the current density of the solar cell is improved. Simultaneously, a first region 201 with relatively low resistance is formed in the region adjacent to the first electrodes 24, thereby reducing the contact resistance with the first electrodes 24. That is, the second portion 20b of the emitter region 20 according to an embodiment of the invention maximizes the efficiency of the solar cell through a selective emitter structure.

[0104] Figure 10 It shows the basis Figure 8 A cross-sectional view of a solar cell according to another modified embodiment of the illustrated embodiment.

[0105] Reference Figure 10 The solar cell according to the modified embodiment does not include the first passivation film 21 and the second passivation film 31, but includes a first antireflection film 22 formed on the emitter region 20 and a second antireflection film 32 formed on the back field region 30. As a result, the overall process is simplified and the cost is reduced. In addition, the first antireflection film 22 and the second antireflection film 32 also serve as passivation films. As a result, production efficiency is improved while maintaining the excellent performance of the solar cell.

[0106] Embodiments of the present invention allow for various other modifications. For example, all configurations that do not include at least one of the first passivation film 21 and the second passivation film 31, and the first antireflection film 22 and the second antireflection film 32, fall within the scope of embodiments of the present invention.

[0107] Figure 10 The second portion 20b of the emitter region 20 is shown to have Figure 8 The example shown is a uniform structure, but in other embodiments of the invention, the second portion 20b of the emitter region 20 may have Figure 9 The selective structure shown.

[0108] Figure 11 This is a cross-sectional view showing a solar cell according to another embodiment of the present invention. (Refer to...) Figure 11 In embodiments of the invention, at least one of the conductive type regions 20 and 30 may include a plurality of portions 20a, 20b, 30a and 30b, which are configured such that tunneling layers 42 and 44 are located between these portions.

[0109] In embodiments of the present invention, the emitter region 20 includes multiple portions configured such that a first tunneling layer 42 is interposed between these portions. Specifically, in embodiments of the present invention, the emitter region 20 includes a first portion 20a and a second portion 20b, which are configured such that the first tunneling layer 42 is interposed between the first portion 20a and the second portion 20b. In the drawings and description, the case in which the portions of the emitter region 20 comprise a total of two layers (i.e., the first portion 20a and the second portion 20b) is used as an example; however, embodiments of the present invention are not limited to this, and the portions of the emitter region 20 may include multiple portions, comprising three or more layers. The emitter region 20 will be described in more detail.

[0110] In this case, the first portion 20a of the emitter region 20 may be disposed between the first tunneling layer 42 and the first electrode 24 on the first tunneling layer 42. The first portion 20a has been referenced. Figure 1 The embodiments shown are described, but detailed descriptions of the same content are omitted.

[0111] The second portion 20b of the emitter region 20 is formed inside the semiconductor substrate 10 adjacent to the front side of the semiconductor substrate 10, or is formed on the front side of the semiconductor substrate 10 adjacent to the semiconductor substrate 10. That is, the emitter region 20 may be formed in a part of the semiconductor substrate 10 adjacent to the first tunneling layer 42, or may be disposed between the semiconductor substrate 10 and the first tunneling layer 42 or between the base region 110 and the first tunneling layer 42.

[0112] For example, in an embodiment of the present invention, the second portion 20b may be constituted by a doped region formed by doping the semiconductor substrate 10 with a dopant of a second conductivity type. Therefore, the second portion 20b may be constituted by a single-crystal semiconductor (e.g., single-crystal silicon) doped with a dopant of a second conductivity type. In this case, the dopant of the second conductivity type may be any impurity having a second conductivity type opposite to that of the base region 110. That is, when the dopant of the second conductivity type is p-type, group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. When the dopant of the second conductivity type is n-type, group V elements such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb) may be used.

[0113] The first portion 20a and the second portion 20b can be entirely formed on the front side of the semiconductor substrate 10. As used herein, the expression "entirely formed on" means that the first portion 20a or the second portion 20b is formed on 100% of the front side, or that the area where the first portion 20a or the second portion 20b is not formed is unavoidably present in part of the surface. By forming the first portion 20a and the second portion 20b entirely, the area of ​​the pn junction is maximized, and additional patterning processes are omitted.

[0114] The second portion 20b may include a doped region formed by diffusing a dopant of a second conductivity type from the first portion 20a into the semiconductor substrate 10. In this case, the dopant of the second conductivity type in the second portion 20b and the dopant of the second conductivity type in the first portion 20a may include the same material. For example, when the first portion 20a includes boron (B) as a dopant of the second conductivity type, the second portion 20b also includes boron as a dopant of the second conductivity type. This will be described in more detail later, but embodiments of the invention are not limited thereto, and various processes such as forming the first portion 20a and the second portion 20b respectively can be performed.

[0115] The second part 20b is the region that forms a pn junction with the base region 110 in the semiconductor substrate 10. The first part 20a is the region that is connected to the first electrode 24 on the first tunneling layer 42.

[0116] In this configuration, the second portion 20b and the first portion 20a of the emitter region 20 are doped with dopants of a second conductivity type at different doping concentrations. Specifically, since the doping concentration of the first portion 20a is higher than that of the second portion 20b, the second portion 20b forms a low-concentration doped portion, and the first portion 20a forms a high-concentration doped portion. In this configuration, the doping concentration in the first portion 20a can be uniform. Alternatively, the doping concentration in the region adjacent to the first electrode 24 can be higher than that in the region adjacent to the first tunneling layer 42. In this configuration, by controlling the process conditions for forming the first portion 20a, the doping concentration gradually or stepwise increases with increasing distance from the first tunneling layer 42. Therefore, when the doping concentration in the region adjacent to the first electrode 24 is relatively high, the contact resistance between the emitter region 20 and the first electrode 24 can be minimized.

[0117] The second portion 20b disposed in the semiconductor substrate 10 is formed at a low concentration, thereby minimizing carrier recombination (specifically, Auger recombination) that may occur or be generated in the second portion 20b. Conversely, the first portion 20a connected to the first electrode 24 while simultaneously contacting the first electrode 24 is formed at a high concentration, thereby minimizing the contact resistance with the first electrode 24.

[0118] For example, the ratio of the doping concentration of the first part 20a to the doping concentration of the second part 20b can be 5 to 10. When the concentration ratio is less than 5, the effect of reducing recombination may be insufficient due to the high doping concentration of the second part 20b. When the concentration ratio exceeds 10, the performance of the pn junction may be degraded due to insufficient formation of the second part 20b. In this case, the doping concentration of the second part 20b can be 5 × 10⁻⁶. 18 / cm 3 Up to 5×10 19 / cm 3 The doping concentration of the first part 20a can be 5 × 10⁻⁶. 19 / cm 3 Up to 5×10 20 / cm 3 The doping concentration of the first part 20a is higher than that of the second part 20b. Within this doping concentration range, the first part 20a forms a pn junction and minimizes recombination, while the second part 20b can have excellent electrical performance with the first electrode 24. However, the embodiments of the present invention are not limited thereto, and the doping concentrations of the first part 20a and the second part 20b can be changed.

[0119] Furthermore, the thicknesses of the second portion 20b and the first portion 20a of the emitter region 20 may differ from each other. More specifically, the first portion 20a is thicker than the second portion 20b, and both the first portion 20a and the second portion 20b may be thicker than the first tunneling layer 42. The thickness of the second portion 20b is controlled to a relatively small level, thereby minimizing the recombination of carriers that may be generated or occur in the semiconductor substrate 10. Additionally, the first portion 20a is formed with a relatively large thickness to maintain good contact with the first electrode 24. Furthermore, the thickness of the first tunneling layer 42 is controlled to a minimum to prevent obstruction of the flow of majority carriers between the second portion 20b and the first portion 20a; however, embodiments of the invention are not limited to this, and the second portion 20b may be thicker than the first portion 20a.

[0120] For example, the ratio of the thickness of the first portion 20a to the thickness of the second portion 20b can be from 0.5 to 100, more specifically, from 1 to 100. When considering the recombination of charge carriers that may be generated or occur through the second portion 20b, the minimization of damage to the semiconductor substrate 10, the electrical performance of the first portion 20a, etc., the thickness ratio can be from 10 to 50. In this case, the thickness of the second portion 20b can be from 5 nm to 100 nm, and the thickness of the first portion 20a can be from 50 nm to 500 nm, but the embodiments of the present invention are not limited to this, and the thicknesses of the first portion 20a and the second portion 20b, etc., can be changed.

[0121] As described above, the low-concentration doped portion (second portion 20b) forms a pn junction with the base region 110. Unlike the embodiment of the present invention, the emitter layer is formed only on the first tunneling layer 42, thereby preventing problems that arise when a pn junction is formed between the first tunneling layer 42 and the emitter layer. That is, when the emitter layer is formed only on the first tunneling layer 42, a physical interface constituting the pn junction is formed between the first tunneling layer 42 and the emitter layer, and the properties of the emitter layer are greatly affected by the properties of the interface. Therefore, it is difficult to ensure the stability of the emitter layer's quality. On the other hand, in the embodiment of the present invention, the second portion 20b of the emitter region 20 forms a pn junction, such that the second portion 20b is disposed in or in contact with the semiconductor substrate 10, thus ensuring the stability of the pn junction. As a result, the open-circuit voltage of the solar cell 100 is improved, and therefore the efficiency of the solar cell 100 is improved.

[0122] The first tunneling layer 42 disposed between the second portion 20b and the first portion 20a prevents minority carriers from being injected from the second portion 20b into the first portion 20a, thereby preventing recombination between carriers in the first portion 20a with a high concentration. Additionally, the first electrode 24 is connected to the highly doped portion (first portion 20a), thereby minimizing the contact resistance between the emitter region 20 and the first electrode 24. As a result, the fill factor of the solar cell 100 is improved, and therefore the efficiency of the solar cell 100 is improved.

[0123] In embodiments of the present invention, the backfield region 30 includes multiple portions configured such that a second tunneling layer 44 is interposed between these portions. Specifically, in embodiments of the present invention, the backfield region 30 includes a second portion 30b and a first portion 30a, configured such that the second tunneling layer 44 is interposed between portions 30b and 30a. In the drawings and description, the case where the portions of the backfield region 30 comprise a total of two layers (i.e., the first portion 30a and the second portion 30b) is used as an example; however, embodiments of the present invention are not limited thereto, and the portions of the backfield region 30 may include multiple portions, comprising three or more layers. The backfield region 30 will be described in more detail.

[0124] The second portion 30b of the back surface field region 30 may be formed inside the semiconductor substrate 10 adjacent to the back surface of the semiconductor substrate 10, or may be formed on the back surface of the semiconductor substrate 10 adjacent to the semiconductor substrate 10. That is, the back surface field region 30 may be formed in a portion of the semiconductor substrate 10 adjacent to the second tunneling layer 44, or may be formed between the semiconductor substrate 10 and the second tunneling layer 44, or between the base region 110 and the second tunneling layer 44.

[0125] In this case, the first portion 30a of the back surface field region 30 may be disposed between the second tunneling layer 44 and the second electrode 34 on the second tunneling layer 44. The first portion 30a has been referenced. Figure 1 The embodiments shown are described, but detailed descriptions of the same content are omitted.

[0126] For example, in an embodiment of the present invention, the second portion 30b may be constituted by a doped region formed by doping the semiconductor substrate 10 with a dopant of a first conductivity type at a concentration higher than that of the base region 100. Therefore, the second portion 30b may be constituted by a single-crystal semiconductor (e.g., single-crystal silicon) doped with a dopant of the first conductivity type. In this case, the dopant of the first conductivity type may be any impurity having the same first conductivity type as the base region 110. That is, when the dopant of the first conductivity type is n-type, group V elements such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb) may be used. When the dopant of the first conductivity type is p-type, group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used.

[0127] The first portion 30a and the second portion 30b can be entirely formed on the back side of the semiconductor substrate 10. As used herein, the expression "entirely formed on" means that the first portion 30a or the second portion 30b is formed on 100% of the front side, or that the area where the first portion 30a or the second portion 30b is not formed is unavoidably present in part of the surface. By forming the second portion 30b and the first portion 30a entirely, the area of ​​the back side field structure is maximized, and additional patterning processes are omitted.

[0128] The second portion 30b may include a doped region formed by diffusing a dopant of a first conductivity type from the first portion 30a into the semiconductor substrate 10. In this case, the dopant of the first conductivity type in the second portion 30b and the dopant of the first conductivity type in the first portion 30a may include the same material. For example, when the first portion 30a includes phosphorus (P) as a dopant of the first conductivity type, the second portion 30b may also include phosphorus (P) as a dopant of the first conductivity type. This will be described in more detail later, but embodiments of the invention are not limited thereto, and various processes such as forming the second portion 30b and the first portion 30a respectively may be performed.

[0129] The second part 30b is the region that forms a back surface field structure with the base region 110 in the semiconductor substrate 10. The first part 30a is the region that is connected to the second electrode 34 on the second tunneling layer 44.

[0130] In this configuration, the second portion 30b and the first portion 30a of the back surface field region 30 are doped with dopants of a first conductivity type at different doping concentrations. Specifically, since the doping concentration of the first portion 30a is higher than that of the second portion 30b, the second portion 30b forms a low-concentration doped portion, and the first portion 30a forms a high-concentration doped portion. In this configuration, the doping concentration in the first portion 30a can be uniform. Alternatively, the doping concentration in the region adjacent to the second electrode 34 can be higher than that in the region adjacent to the second tunneling layer 44. In this configuration, by controlling the process conditions for forming the first portion 30a, the doping concentration gradually or stepwise increases with increasing distance from the second tunneling layer 44. Therefore, when the doping concentration in the region adjacent to the second electrode 34 is relatively high, the contact resistance between the back surface field region 30 and the second electrode 34 can be minimized.

[0131] The second portion 30b disposed in the semiconductor substrate 10 is formed at a low concentration, thereby minimizing the recombination of carriers that may be generated or occur in the second portion 30b. In addition, the first portion 30a connected to the second electrode 34 at the same time as contacting the second electrode 34 is formed at a high concentration, thereby minimizing the contact resistance with the second electrode 34.

[0132] For example, the ratio of the doping concentration of the first portion 30a to the doping concentration of the second portion 30b can be 5 to 10. When the concentration ratio is less than 5, the effect of reducing recombination may be insufficient due to the high doping concentration of the second portion 30b. When the concentration ratio exceeds 10, the back-side field effect may be insufficient due to the inadequate formation of the second portion 30b. In this case, the doping concentration of the second portion 30b can be 5 × 10⁻⁶. 18 / cm 3 Up to 5×10 19 / cm 3 The doping concentration of the first part 30a can be 5 × 10⁻⁶. 19 / cm 3 Up to 5×10 20 / cm 3 The doping concentration of the first part 30a is higher than that of the second part 30b. Within this doping concentration range, the second part 30b forms a back surface field structure with excellent performance, and the second part 30a can have excellent electrical performance with the second electrode 34. However, the embodiments of the present invention are not limited thereto, and the doping concentrations of the first part 30a and the second part 30b can be changed.

[0133] Furthermore, the thicknesses of the second portion 30b and the first portion 30a of the back surface field region 30 may differ from each other. More specifically, the first portion 30a is thicker than the second portion 30b, and both the first portion 30a and the second portion 30b may be thicker than the second tunneling layer 44. The thickness of the second portion 30b is controlled to a relatively small level, thereby minimizing the recombination of carriers that may be generated or occur in the semiconductor substrate 10. Additionally, the first portion 30a is formed with a relatively large thickness to maintain good contact with the second electrode 44. Furthermore, the thickness of the second tunneling layer 44 is controlled to a minimum to prevent obstruction of the flow of majority carriers between the second portion 30b and the first portion 30a; however, embodiments of the invention are not limited to this, and the second portion 30b may be thicker than the first portion 30a.

[0134] For example, the ratio of the thickness of the first portion 30a to the thickness of the second portion 30b can be from 0.5 to 100, more specifically, from 1 to 100. When considering the recombination of charge carriers that may be generated or occur through the second portion 30b, the minimization of damage to the semiconductor substrate 10, the electrical performance of the first portion 30a, etc., the thickness ratio can be from 10 to 50. In this case, the thickness of the second portion 30b can be from 5 nm to 100 nm, and the thickness of the first portion 30a can be from 50 nm to 500 nm, but embodiments of the present invention are not limited thereto, and the thicknesses of the first portion 30a and the second portion 30b, etc., can be changed.

[0135] As described above, the low-concentration doped portion (second portion 30b) forms a back-side field structure with the base region 110. Therefore, the back-side field structure is formed either in the semiconductor substrate 10 or simultaneously with contact with the semiconductor substrate 10, thereby ensuring the stability of the back-side field structure. As a result, the open-circuit voltage of the solar cell 100 is improved, and thus the efficiency of the solar cell 100 is enhanced.

[0136] The second tunneling layer 44 disposed between the second portion 30b and the first portion 30a prevents minority carriers from being injected from the second portion 30b into the first portion 30a, thereby preventing recombination between carriers in the first portion 30a with a high concentration. Additionally, the second electrode 34 is connected to the highly doped portion (first portion 20a), thereby minimizing the contact resistance between the back surface field region 30 and the second electrode 34. As a result, the fill factor of the solar cell 100 is improved, and therefore the efficiency of the solar cell 100 is improved.

[0137] In an embodiment of the invention, the conductivity types 20 and 30 include first portions 20a and 30a and second portions 20b and 30b, which are configured such that tunneling layers 42 and 44 are interposed therebetween, thereby minimizing recombination in the semiconductor substrate 10 and improving electrical connections with the first electrode 24 and the second electrode 34. As a result, the efficiency of the solar cell 100 can be improved.

[0138] exist Figure 11 In the figure, the example shown is that the emitter region 20 includes a first portion 20a and a second portion 20b, while the back surface field region 30 includes a first portion 30a and a second portion 30b. However, the embodiments of the present invention are not limited to this. In modified embodiments, such as... Figure 12 and Figure 13 As shown, the emitter region 20 includes a first portion 20a and a second portion 20b, while the back surface field region 30 includes a single portion. In this case, as... Figure 12 As shown, the back surface field region 30 may include a second portion 30b, which includes a doped region disposed in the semiconductor substrate 10. Alternatively, as Figure 13 As shown, the back surface field region 30 may include an additional first portion 30a formed on the second tunneling layer 44 on the back surface of the semiconductor substrate 10. In another modified embodiment, as Figure 14 and Figure 15 As shown, the back surface field region 30 includes a first portion 30a and a second portion 30b, while the emitter region 20 includes a single portion. In this case, as... Figure 14 As shown, the emitter region 20 may include a second portion 20b, which includes a doped region disposed in the semiconductor substrate 10. Alternatively, as Figure 15 As shown, the emitter region 20 may include an additional first portion 20a formed on the second tunneling layer 44 on the back side of the semiconductor substrate 10. Additionally, the second portions 20b and 30b of the emitter region 20 or the back side field region 30 may have various structures, such as selective structures including portions with different doping concentrations or local structures formed in regions adjacent to electrodes 42 and 44. Selective structures or local structures, etc., have been referred to... Figure 5 , Figure 6 and Figure 9 A description has been provided, but its detailed explanation has been omitted.

[0139] The following will refer to Figures 16A to 16E Detailed description based on Figure 11 The manufacturing method of the solar cell 100 according to the illustrated embodiment. Hereinafter, the details of the above description will not be repeated, only the differences from the above description will be described in detail. Furthermore, the above manufacturing method can be applied to… Figure 1 The corresponding part of the embodiment shown.

[0140] Figures 16A to 16E This is a cross-sectional view showing a method for manufacturing a solar cell according to an embodiment of the present invention.

[0141] First, such as Figure 16A As shown, a semiconductor substrate 10 is fabricated including a base region 110 with dopants having a first conductivity type. In embodiments of the invention, the semiconductor substrate 10 may include silicon with n-type impurities. Examples of n-type impurities include (but are not limited to) group V elements, such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb).

[0142] At least one of the front and back surfaces of the semiconductor substrate 10 is textured to create an uneven surface. Wet or dry texturing methods can be used to texture the surface of the semiconductor substrate 10. Wet texturing is performed by immersing the semiconductor substrate 10 in a texturing solution and has the advantage of short processing time. Dry texturing is performed by cutting the surface of the semiconductor substrate 10 using a diamond drill bit, laser, etc., and can create a uniform uneven surface, but it has the disadvantage of long processing time and damage to the semiconductor substrate 10. Alternatively, the semiconductor substrate 10 can be textured by reactive ion etching (RIE), etc. Therefore, the semiconductor substrate 10 can be textured using various methods.

[0143] Then, as Figure 16B As shown, a first tunneling layer 42 and a first portion 20a of an emitter region 20 are formed on the front side of the semiconductor substrate 10, and a second tunneling layer 44 and a first portion 30a of a back field region 30 are formed on the back side of the semiconductor substrate 10.

[0144] In this case, the first tunneling layer 42 and the second tunneling layer 44 can be formed, for example, by methods such as thermal growth or deposition (e.g., plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD)). However, embodiments of the present invention are not limited to this, and the first tunneling layer 42 and the second tunneling layer 44 can be formed by various methods. Additionally, the first portions 20a and 30a of the conductivity type regions 20 and 30 can be formed of amorphous, microcrystalline, or polycrystalline semiconductors. In this case, the first portions 20a and 30a can be formed by methods such as thermal growth, deposition (e.g., plasma-enhanced chemical vapor deposition (PECVD)).

[0145] In addition, dopants of the first conductivity type or the second conductivity type may be incorporated when forming the semiconductor layer constituting the first portions 20a and 30a, and may be doped after forming the semiconductor layer constituting the first portions 20a and 30a. However, the embodiments of the present invention are not limited thereto, and the first portions 20a and 30a may be formed by various methods.

[0146] The formation order of the first tunneling layer 42, the second tunneling layer 44, and the first parts 20a and 30a can vary.

[0147] Then, as Figure 16C As shown, a dopant of a second conductivity type in the first portion 20a is diffused into the semiconductor substrate 10 by heat treatment to form the second portion 20b of the emitter region 20, and a dopant of a first conductivity type in the first portion 30a is diffused into the semiconductor substrate 10 to form the second portion 30b of the back surface field region 30. Therefore, in embodiments of the present invention, the first portions 20a and 30a serve as dopant sources, thereby forming the second portions 20b and 30b by diffusion using heat treatment, without using additional doping methods such as ion implantation. As a result, the manufacturing process is simplified.

[0148] Then, as Figure 16D As shown, a first passivation film 21 and a first antireflection film 22 are formed on the first portion 20a of the emitter region 20, and a second passivation film 31 and a second antireflection film 32 are formed on the first portion 30a of the back surface field region 30. The passivation films 21 and 31, and the antireflection films 22 and 32, can be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing, or spraying. The formation order of the passivation films 21 and 31, and the antireflection films 22 and 32, etc., can be varied.

[0149] Then, as Figure 16E As shown, a first electrode 24 and a second electrode 34 are formed, respectively connected to conductive type regions 20 and 30. In this case, for example, openings are formed in passivation films 21 and 31 and antireflection films 22 and 32, and the first electrode 24 and the second electrode 34 are formed in said openings by various methods such as coating or deposition.

[0150] In another embodiment, the first electrode 24 and the second electrode 34 can be formed by applying a paste for forming the first and second electrodes to the passivation films 21 and 31 and the antireflection films 22 and 32 by means of screen printing or the like, and then performing burn-through, laser burn-through contact, or the like thereon. In this case, since the opening is formed during the formation of the first electrode 24 and the second electrode 34, a separate process for forming the opening is not required.

[0151] According to embodiments of the present invention, the second portions 20b and 30b can be formed by diffusion of dopants of a first or second conductivity type in the first portions 20a and 30a without using additional doping methods such as ion implantation. As a result, a solar cell 100 with excellent efficiency can be manufactured using a simple manufacturing process.

[0152] In the above embodiment, the formation of a first tunneling layer 42 and a second tunneling layer 44, conductive regions 20 and 30, passivation films 21 and 31, and antireflection films 22 and 32 are taken as examples, followed by the formation of a first electrode 24 and a second electrode 34. However, the embodiments of the present invention are not limited to this. Therefore, the formation order of the first tunneling layer 42 and the second tunneling layer 44, conductive regions 20 and 30, passivation films 21 and 31, antireflection films 22 and 32, and the first electrode 24 and the second electrode 34 can vary.

[0153] Furthermore, in the above embodiments, the second portion 20b is formed by diffusing a dopant of the second conductivity type in the first portion 20a of the emitter region 20, and the second portion 30b is formed by diffusing a dopant of the second conductivity type in the first portion 30a of the back surface field region 30. However, the embodiments of the present invention are not limited to this. The second portions 20b and 30b can be formed by additional processes (ion implantation, thermal diffusion, laser doping, etc.).

[0154] Figure 17 This is a cross-sectional view showing a solar cell according to another embodiment of the present invention.

[0155] Reference Figure 17 In an embodiment of the present invention, the emitter region 20 includes a first portion 20a and a second portion 20b, which is configured such that a first tunneling layer 42 is located between portions 20a and 20b, and the back surface field region 30 includes a first portion 30a and a second portion 30b, which is configured such that a second tunneling layer 44 is located between portions 20a and 20b.

[0156] In embodiments of the present invention, the second portions 20b and 30b of the conductivity type regions 20 and 30 can be formed by doping an amorphous, microcrystalline, or polycrystalline semiconductor layer (e.g., a silicon layer) formed on the semiconductor substrate 10 with a conductivity type dopant. That is, the second portions 20b and 30b of the conductivity type regions 20 and 30 can be located between the semiconductor substrate 10 and the tunneling layers 42 and 44. In this case, the conductivity type dopant can be incorporated during the formation of the semiconductor layer constituting the second portions 20b and 30b, and can be doped after the formation of the semiconductor layer constituting the second portions 20b and 30b.

[0157] Therefore, when the first portion 20 and the second portion 30a are formed on the semiconductor substrate 10, the semiconductor substrate 10 may include only the base region 110. As a result, problems such as damage to the semiconductor substrate 10 or increased carrier recombination that may occur during the formation of the doped region on the semiconductor substrate 10 can be fundamentally prevented; however, embodiments of the invention are not limited thereto. Second portions 20b and 30b may be formed on the semiconductor substrate 10 only of one of the emitter region 20 and the back surface field region 30. Alternatively, either the emitter region 20 or the back surface field region 30 may include the first portions 20a and 30a and the second portions 20b and 30b.

[0158] Although exemplary embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions may be made without departing from the scope and spirit of the invention as disclosed in the appended claims.

[0159] Cross-reference to related applications

[0160] This application claims priority to Korean Patent Application No. 10-2013-0036455 filed on April 3, 2013 and Korean Patent Application No. 10-2013-0108046 filed on September 9, 2013, the disclosures of all of which are incorporated herein by reference.

Claims

1. A solar cell, comprising: A single-crystal silicon semiconductor substrate, doped with a first type of conductivity dopant; A first tunneling layer is formed entirely on a first surface of the semiconductor substrate, the first surface being the back side of the semiconductor substrate, the first tunneling layer being silicon oxide and having a thickness of 0.5 nm to 5 nm. A first conductivity type region is located on the first surface of the semiconductor substrate; The second conductivity type region is located on the second surface opposite to the first surface of the semiconductor substrate. middle; A first passivation film formed on a second conductivity type region, a second passivation film formed on a first conductivity type region, a first electrode connected to the second conductivity type region through an opening in the first passivation film, and a second electrode connected to the first conductivity type region through an opening in the second passivation film. The first conductivity type region includes a first portion and includes dopant of the first conductivity type. The object is a polycrystalline semiconductor; the first portion is entirely formed on the first tunneling layer, and the second electrode is connected to the first portion; The thickness of the first part is between 50 nm and 500 nm; The second conductivity type region has the same crystal structure as the semiconductor substrate. The first conductivity type is N-type, and the second conductivity type is P-type.

2. The solar cell according to claim 1, wherein the first electrode and the second electrode include a plurality of finger electrodes having a first spacing P1 and arranged parallel to each other, and the first electrode and the second electrode include a bus bar electrode formed in a direction intersecting the direction in which the finger electrodes are arranged and connecting the finger electrodes.

3. The solar cell of claim 1, wherein the first conductivity type region further comprises a second portion, the second portion being located within the first surface of the semiconductor substrate, such that the first tunneling layer is located between the first portion and the second portion.

4. The solar cell according to claim 3, wherein the doping concentration of the first portion of the first conductivity type region is higher than the doping concentration of the second portion.

5. The solar cell according to claim 1, wherein the doping concentration in the region adjacent to the second electrode in the first portion of the first conductivity type region is higher than the doping concentration in the region adjacent to the first tunneling layer.

6. The solar cell according to claim 1, wherein the first passivation film comprises negatively charged aluminum oxide, zinc oxide, hafnium dioxide and / or the second passivation film comprises positively charged silicon oxide, silicon nitride.

7. The solar cell according to claim 6 further includes a first antireflective film on the first passivation film.

8. The solar cell according to claim 3, wherein the first portion and the second portion of the first conductivity type region are thicker than the first tunneling layer, the ratio of the doping concentration of the first portion to the doping concentration of the second portion is 5 to 10 and / or the ratio of the thickness of the first portion to the thickness of the second portion is 0.5 to 100.

9. The solar cell according to claim 1, wherein a first region of a second conductivity type region has a high doping concentration and thus a relatively low resistance, and a second region has a lower doping concentration than the first region and thus a relatively high resistance, the first region being formed such that the first region contacts part or all of the first electrode, and the second region being formed in the region between the first electrodes.

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