On-chip power supply switching circuit of processor, and processor

Abstract

The present application relates to an on-chip power supply switching circuit of a processor, and a processor. In the present application, the on-chip power supply switching circuit can generate a determined higher voltage by performing higher-voltage determination on an LDO output voltage and a backup external voltage, wherein the determined higher voltage is equal to the higher one of the LDO output voltage and the backup external voltage. The LDO output voltage and the backup external voltage can be alternatively selected by a first PMOS transistor (10) to be used as an on-chip power supply voltage of the processor, the determined higher voltage can be used for driving the first PMOS transistor (10) to be in an off state in which the LDO output voltage is selected, and the determined higher voltage can also be used for maintaining a substrate voltage of the first PMOS transistor (10) at the highest voltage in the device, so that the first PMOS transistor (10) is in a fully off state.

Description

The processor's on-chip power supply switching circuit and the processor

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411562347.5, filed on November 4, 2024, entitled “On-chip power supply switching circuit for processor and processor”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to power supply technology, and more particularly to an on-chip power supply switching circuit for a processor, and a processor. Background Technology

[0004] The on-chip loads of a processor have diverse power supply requirements. For example, the on-chip loads may include I / O circuits and the core, and the I / O voltage required by the I / O circuits may be higher than the core voltage required by the core. Therefore, the external power supply voltage received by the processor is usually a high voltage that can meet all power supply requirements. To meet the low-voltage requirements of the processor, which are lower than the external power supply voltage, the processor typically uses an LDO (Low Dropout Regulator) to step down the external power supply voltage. The LDO can generate a stable output voltage by stepping down the external power supply voltage, and the output voltage generated by the LDO can be adapted and adjusted according to the requirements of the target on-chip load (e.g., core voltage), so that the target on-chip load can operate in an optimal state when the output voltage generated by the LDO is used as the on-chip power supply voltage.

[0005] If the processor's on-chip power supply relies solely on an LDO (Low-Density Variable Voltage) system, a failure of the LDO will cause the target on-chip load to malfunction. Therefore, relying solely on an LDO to provide on-chip power to the processor is unreliable. To improve the reliability of the processor's on-chip power supply, related technologies attempt to introduce an additional backup external voltage. This backup external voltage can be lower than the external power supply voltage. This backup external voltage is a setpoint used to maintain the target on-chip load in a basic operating state. Furthermore, this backup external voltage can replace the LDO's output voltage as the on-chip power supply voltage for the target on-chip load when the LDO fails.

[0006] However, if the LDO's output voltage during normal operation is adjusted to be greater than the backup external voltage when the processor is given an additional backup external voltage, leakage may occur from the LDO to the backup external voltage. This leakage will cause the LDO's output voltage to be unstable, resulting in low stability of the processor's on-chip power supply provided by the LDO.

[0007] As can be seen above, it is difficult for the on-chip power supply of a processor to simultaneously ensure both reliability and stability. Summary of the Invention

[0008] According to various embodiments disclosed in this application, an on-chip power supply switching circuit for a processor and a processor are provided.

[0009] An on-chip power supply switching circuit for a processor includes:

[0010] A high-voltage decision circuit has a first decision input terminal, a second decision input terminal, and a high-voltage decision output terminal. The first decision input terminal receives the LDO output voltage generated by the LDO in the processor. The second decision input terminal receives the backup external voltage of the processor. The high-voltage decision output terminal is used to generate a high-voltage decision voltage. The LDO output voltage is adjustable, and the high-voltage decision voltage is set to the higher of the LDO output voltage and the backup external voltage.

[0011] A first PMOS transistor has a gate, and first and second terminals located on opposite sides of a substrate channel. The first terminal of the first PMOS transistor is used to connect to a target on-chip load in the processor. The first terminal of the first PMOS transistor receives the LDO output voltage, and the second terminal of the first PMOS transistor receives the backup external voltage. Furthermore, the substrate voltage of the first PMOS transistor is normally set to the high-voltage decision voltage.

[0012] The switching execution circuit is used for:

[0013] When the LDO is enabled normally, the gate voltage of the first PMOS transistor is set to the high voltage decision voltage, so that the LDO output voltage is selected as the on-chip power supply voltage for the target on-chip load;

[0014] When the LDO malfunctions, the gate voltage of the first PMOS transistor is pulled low, causing the on-chip power supply voltage to switch from the LDO output voltage to the backup external voltage.

[0015] A processor includes an on-chip power supply switching circuit, the on-chip power supply switching circuit comprising:

[0016] A high-voltage decision circuit has a first decision input terminal, a second decision input terminal, and a high-voltage decision output terminal. The first decision input terminal receives the LDO output voltage generated by the LDO in the processor. The second decision input terminal receives the backup external voltage of the processor. The high-voltage decision output terminal is used to generate a high-voltage decision voltage. The LDO output voltage is adjustable, and the high-voltage decision voltage is set to the higher of the LDO output voltage and the backup external voltage.

[0017] A first PMOS transistor has a gate, and first and second terminals located on opposite sides of a substrate channel. The first terminal of the first PMOS transistor is used to connect to a target on-chip load in the processor. The first terminal of the first PMOS transistor receives the LDO output voltage, and the second terminal of the first PMOS transistor receives the backup external voltage. Furthermore, the substrate voltage of the first PMOS transistor is normally set to the high-voltage decision voltage.

[0018] The switching execution circuit is used for:

[0019] When the LDO is enabled normally, the gate voltage of the first PMOS transistor is set to the high voltage decision voltage, so that the LDO output voltage is selected as the on-chip power supply voltage for the target on-chip load;

[0020] When the LDO malfunctions, the gate voltage of the first PMOS transistor is pulled low, causing the on-chip power supply voltage to switch from the LDO output voltage to the backup external voltage.

[0021] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 is a schematic diagram of leakage current from the LDO to the backup external voltage.

[0024] Figure 2 is an exemplary structural diagram of an on-chip power supply switching circuit for a processor according to one or more embodiments.

[0025] Figure 3 is a schematic diagram of an example structure of a high-voltage decision circuit in an on-chip power supply switching circuit according to one or more embodiments.

[0026] Figure 4 is a schematic diagram of an example structure of the switching execution circuit in the on-chip power supply switching circuit according to one or more embodiments. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0028] Figure 1 is a schematic diagram of leakage current from the LDO to the backup external voltage. Referring to Figure 1, the processor may include an LDO, and to improve the reliability of the on-chip power supply provided by the LDO, the processor may also introduce a backup external voltage VDDC. In this case, the processor may also include a switching transistor 10, which is used to provide on-chip power to the target on-chip load (e.g., the core) of the processor by switching the LDO output voltage V_LDO generated by the LDO and the backup external voltage VDDC.

[0029] Specifically, the switching transistor 10 can be a PMOS (P-Metal Oxide Semiconductor) transistor. The backup external voltage VDDC can be connected to the source of the PMOS transistor 10. The LDO can have an input terminal for receiving the external power supply voltage VDDH and an output terminal for generating the LDO output voltage V_LDO. The output terminal of the LDO is connected to the drain of the PMOS transistor 10, and the drain of the PMOS transistor 10 is connected to the target on-chip load of the processor.

[0030] Based on the above structure, the gate of PMOS transistor 10 is controlled by the switching control signal Sig_sw0. For example, this switching control signal Sig_sw0 can be generated by the processor's power management module, wherein:

[0031] When the LDO can be powered normally, the switching control signal Sig_sw0 is set to high level, so that the gate-source voltage difference Vgs of PMOS transistor 10 is lower than the threshold voltage. At this time, PMOS transistor 10 is turned off, so that the LDO output voltage V_LDO is used as the on-chip power supply voltage and is transferred from the drain of PMOS transistor 10 to the target on-chip load of the processor.

[0032] When the LDO malfunctions, the switching control signal Sig_sw0 is set to low level, causing the gate-source voltage difference Vgs of PMOS transistor 10 to be greater than the threshold voltage. At this time, PMOS transistor 10 is turned on, and the backup external voltage VDDC connected to the source replaces the LDO output voltage V_LDO as the on-chip power supply voltage and is transmitted from the drain of PMOS transistor 10 to the target on-chip load of the processor.

[0033] If a high-voltage device is selected for PMOS transistor 10, meaning its threshold voltage matches or is close to the external supply voltage VDDH, then the gate-source voltage difference Vgs formed when the switching control signal Sig_sw0 is set to low is equal to and less than the backup external voltage VDDC. In this case, PMOS transistor 10 may not be fully turned on, and the incompletely turned-on PMOS transistor 10 cannot fully supply the backup external voltage VDDC to the target on-chip load of the processor. Therefore, to ensure the reliability of the on-chip power supply of the backup external voltage VDDC, PMOS transistor 10 is preferably a low-voltage device, meaning its threshold voltage matches or is close to the backup external voltage VDDC.

[0034] When a low-voltage device is selected for PMOS transistor 10, its leakage prevention capability is relatively weak. Furthermore, if the LDO output voltage V_LDO is adjusted to be greater than the backup external voltage VDDC, the drain voltage of PMOS transistor 10 will be higher than the source voltage. At this time, since the substrate and source of PMOS transistor 10 are at the same potential, both the source voltage and substrate potential of PMOS transistor 10 are lower than the drain voltage. As a result, forward bias conduction occurs from the drain through the substrate to the source, leading to leakage of the LDO output voltage V_LDO to the backup external voltage VDDC through the forward biased PMOS transistor 10.

[0035] Based on the above analysis, the embodiments of this application can improve the reliability of on-chip power supply by utilizing the backup external voltage VDDC, and prevent leakage of the LDO output voltage V_LDO to the backup external voltage VDDC by suppressing the forward bias conduction of PMOS transistor 10 when the LDO output voltage V_LDO is greater than the backup external voltage VDDC. Thus, the stability of LDO providing on-chip power supply to the processor can be taken into account.

[0036] Figure 2 is an exemplary structural diagram of the on-chip power supply switching circuit of the processor in an embodiment of this application. Referring to Figure 2, in an embodiment of this application, the on-chip power supply switching circuit of the processor may include a high-voltage decision circuit 30, a first PMOS transistor 50, and a switching execution circuit 70.

[0037] For example, in an embodiment of this application, the high-voltage decision circuit 30 may have a first decision input terminal, a second decision input terminal, and a high-voltage decision output terminal. The first decision input terminal of the high-voltage decision circuit 30 receives the LDO output voltage V_LDO generated by the LDO in the processor. The second decision input terminal of the high-voltage decision circuit 30 receives the backup external voltage VDDC of the processor. The high-voltage decision output terminal of the high-voltage decision circuit 30 is used to generate a high-voltage decision voltage.

[0038] For example, in an embodiment of this application, the LDO can generate an LDO output voltage V_LDO using the processor's external power supply voltage VDDH, and both the LDO output voltage V_LDO and the backup external voltage VDDC can be lower than the external power supply voltage VDDH.

[0039] For example, in the embodiments of this application, the external power supply voltage VDDH can be applied to the I / O circuit in the on-chip load of the processor, that is, the external power supply voltage VDDH can be used as the I / O voltage of the I / O circuit. For example, the external power supply voltage VDDH can be 1.8V.

[0040] For example, in the embodiments of this application, the LDO output voltage V_LDO and the backup external voltage can be applied to the core in the on-chip load of the processor. That is, the target on-chip load of the processor may include the core, and the LDO output voltage V_LDO and the backup external voltage can be used as the core voltage when used as the on-chip power supply voltage. For example, the LDO output voltage V_LDO can be adjusted in a range of less than 1.8V, and the backup external voltage VDDC can be 0.75V.

[0041] For example, in the embodiments of this application, the LDO output voltage V_LDO is adjustable, and the backup external voltage VDDC can be a fixed value. Therefore, there may be different situations where the LDO output voltage V_LDO is higher than, equal to, or lower than the backup external voltage VDDC. Thus, the high-voltage decision voltage V_high can be set by the high-voltage decision circuit 30 to the higher of the LDO output voltage V_LDO and the backup external voltage VDDC. Furthermore, when the LDO output voltage V_LDO is equal to the backup external voltage VDDC, any value of the LDO output voltage V_LDO to the backup external voltage VDDC can be considered as the higher of the two voltages. That is, the high-voltage decision circuit 30 can adaptively set the high-voltage decision voltage V_high to the higher of the two voltages.

[0042] For example, in an embodiment of this application, the first PMOS transistor 50 has a gate, and a first electrode and a second electrode located on opposite sides of the substrate channel, that is, one of the first electrode and the second electrode of the first PMOS transistor 50 can be the source electrode and the other electrode can be the drain electrode, and the first PMOS transistor 50 can preferably be a low-voltage device as described above.

[0043] For example, in an embodiment of this application, the first terminal of the first PMOS transistor 50 is used to connect to the target on-chip load in the processor, the first terminal of the first PMOS transistor 50 receives the LDO output voltage V_LDO, the second terminal of the first PMOS transistor 50 receives the backup external voltage VDDC, and the substrate voltage of the first PMOS transistor 50 is normally set to the high voltage decision voltage V_high.

[0044] Exemplary, in an embodiment of this application, the switching execution circuit 70 can be used to:

[0045] When the LDO is normally enabled, the gate voltage of the first PMOS transistor 50 is set to the high-voltage decision voltage V_high, so that the LDO output voltage V_LDO is selected as the on-chip supply voltage for the target on-chip load (e.g., the processor core). That is, setting the gate voltage of the first PMOS transistor 50 to the high-voltage decision voltage V_high allows the first PMOS transistor 50 to be turned off when its substrate voltage is at the highest voltage within the device. The highest voltage within the device refers to the highest voltage among all internal voltages of the first PMOS transistor 50, including the gate voltage, the first electrode voltage, the second electrode voltage, and the substrate voltage. Furthermore, turning off the first PMOS transistor 50 can be used to select the LDO output voltage V_LDO as the on-chip supply voltage for the target on-chip load (e.g., the processor core).

[0046] When the LDO malfunctions, the gate voltage of the first PMOS transistor 50 is pulled low (e.g., a low voltage at the same potential as ground), causing the on-chip supply voltage to switch from the LDO output voltage V_LDO to the backup external voltage VDDC. That is, setting the gate voltage of the first PMOS transistor 50 to pull low can turn on the first PMOS transistor 50, and the turning on of the first PMOS transistor 50 is used to switch the on-chip supply voltage from the LDO output voltage V_LDO to the backup external voltage VDDC.

[0047] For example, in an embodiment of this application, if the LDO output voltage V_LDO is higher than the backup external voltage VDDC, then the high-voltage decision voltage V_high is the LDO output voltage V_LDO, that is, the high-voltage decision voltage V_high is equal to the LDO output voltage V_LDO, and when the switching execution circuit 70 sets the gate voltage of the first PMOS transistor 50 to the high-voltage decision voltage V_high (i.e., when the LDO is normally enabled):

[0048] The first terminal voltage of the first PMOS transistor 50 is equal to the substrate voltage. That is, the first terminal voltage of the first PMOS transistor 50 and the substrate voltage are both high voltage decision voltage V_high, which is equal to the LDO output voltage V_LDO. At this time, the first terminal of the first PMOS transistor 50 that receives the LDO output voltage V_LDO can be regarded as the source of the first PMOS transistor 50, and the second terminal of the first PMOS transistor 50 that receives the backup external voltage VDDC can be regarded as the drain of the first PMOS transistor 50.

[0049] The first gate voltage (e.g., source voltage) and gate voltage of the first PMOS transistor 50 are equal, that is, the first gate voltage (e.g., source voltage) and gate voltage of the first PMOS transistor 50 are both high-voltage decision voltages V_high that are equal to the LDO output voltage V_LDO. At this time, the gate-source voltage difference Vgs of the first PMOS transistor 50 is less than the threshold voltage of the first PMOS transistor, causing the first PMOS transistor 50 to turn off.

[0050] The second terminal voltage (e.g., drain voltage) of the first PMOS transistor 50 is currently lower than the high voltage decision voltage V_high, which is a backup external voltage VDDC. Therefore, the substrate voltage of the first PMOS transistor 50 is also higher than the second terminal voltage (e.g., drain voltage) of the first PMOS transistor 50. Thus, the substrate voltage of the first PMOS transistor 50 is at the highest potential of the first PMOS transistor 50 when the first PMOS transistor 50 is turned off, so as to ensure that the turn-off of the first PMOS transistor 50 is a complete turn-off.

[0051] For example, in an embodiment of this application, if the LDO output voltage V_LDO is lower than the backup external voltage VDDC, then the high-voltage decision voltage V_high is the backup external voltage VDDC, that is, the high-voltage decision voltage V_high and the backup external voltage VDDC are equal. Furthermore, when the switching execution circuit 70 sets the gate voltage of the first PMOS transistor 50 to the high-voltage decision voltage V_high (i.e., when the LDO is normally enabled):

[0052] The first terminal voltage of the first PMOS transistor 50 is equal to the substrate voltage. That is, the first terminal voltage of the first PMOS transistor 50 and the substrate voltage are both high voltage decision voltage V_high, which is equal to the backup external voltage VDDC. At this time, the second terminal of the first PMOS transistor 50 receiving the backup external voltage VDDC can be regarded as the source of the first PMOS transistor 50, and the first terminal of the first PMOS transistor 50 receiving the LDO output voltage V_LDO can be regarded as the drain of the first PMOS transistor 50.

[0053] The second-terminal voltage (e.g., source voltage) and gate voltage of the first PMOS transistor 50 are equal, that is, the second-terminal voltage (e.g., source voltage) and gate voltage of the first PMOS transistor 50 are both high-voltage decision voltages V_high that are equal to the backup external voltage VDDC. At this time, the gate-source voltage difference Vgs of the first PMOS transistor 50 is less than the threshold voltage of the first PMOS transistor, causing the first PMOS transistor 50 to turn off.

[0054] The first terminal voltage (e.g., drain voltage) of the first PMOS transistor 50 is currently lower than the LDO output voltage V_LDO, which is lower than the high voltage decision voltage V_high. Therefore, the substrate voltage of the first PMOS transistor 50 is also higher than the first terminal voltage (e.g., drain voltage). Thus, the substrate voltage of the first PMOS transistor 50 is at the highest potential of the first PMOS transistor 50 when the first PMOS transistor 50 is turned off, ensuring that the turn-off of the first PMOS transistor 50 is a complete turn-off.

[0055] For example, in the embodiments of this application, if the LDO output voltage V_LDO is equal to the backup external voltage VDDC, then any one of the LDO output voltage V_LDO and the backup external voltage VDDC can be regarded as the higher of the LDO output voltage V_LDO and the backup external voltage VDDC. Furthermore, when the switching execution circuit 70 sets the gate voltage of the first PMOS transistor 50 to the high voltage decision voltage V_high (i.e., when the LDO is normally enabled), the first PMOS transistor 50 can still be completely turned off, just as it can be in the case where the LDO output voltage V_LDO is higher or lower than the backup external voltage VDDC.

[0056] Based on the above embodiments of this application, the on-chip power supply switching circuit can generate a high-voltage decision voltage V_high equal to the higher of the two high voltages by making a high-voltage decision on the LDO output voltage V_LDO and the backup external voltage VDDC. The LDO output voltage V_LDO and the backup external voltage VDDC can be selectively selected as the on-chip power supply voltage for the processor when the first PMOS transistor 50 is off and on, respectively. The high-voltage decision voltage V_high can be used to drive the first PMOS transistor 50 into a off state where the LDO output voltage V_LDO is selected as the on-chip power supply voltage. Furthermore, the high-voltage decision voltage V_high can also be applied to the substrate of the first PMOS transistor 50. Therefore, by maintaining the substrate voltage of the first PMOS transistor 50 at the highest voltage within the device when the first PMOS transistor 50 is off, forward bias conduction of the first PMOS transistor 50 when the LDO output voltage V_LDO is greater than the backup external voltage VDDC can be suppressed, ensuring that the off state of the first PMOS transistor 50 is completely off. Furthermore, leakage current from the LDO output voltage V_LDO to the backup external voltage VDDC can be suppressed, so as to improve the reliability of on-chip power supply by utilizing the backup external voltage VDDC while ensuring the stability of the LDO when providing on-chip power supply to the processor.

[0057] For example, in an embodiment of this application, the high-voltage decision circuit 30 may have a contention interlock loop, which is used for:

[0058] When the LDO output voltage V_LDO is higher than the backup external voltage VDDC, the first decision input terminal of the high voltage decision circuit 30 is connected to the high voltage decision output terminal of the high voltage decision circuit 30, and the second decision input terminal of the high voltage decision circuit 30 is disconnected from the high voltage decision output terminal of the high voltage decision circuit 30, so that the high voltage decision voltage V_high is set to the higher of the LDO output voltage V_LDO and the backup external voltage VDDC.

[0059] When the LDO output voltage V_LDO is lower than the backup external voltage VDDC, the second decision input terminal of the high voltage decision circuit 30 is connected to the high voltage decision output terminal of the high voltage decision circuit 30, and the first decision input terminal of the high voltage decision circuit 30 is disconnected from the high voltage decision output terminal of the high voltage decision circuit 30, so that the high voltage decision voltage V_high is set to the higher of the LDO output voltage V_LDO and the backup external voltage VDDC.

[0060] When the LDO output voltage V_LDO is equal to the standby external voltage VDDC, the current conduction state between the first decision input terminal or the second decision input terminal of the high voltage decision circuit 30 and the high voltage decision output terminal of the high voltage decision circuit 30 is maintained.

[0061] Figure 3 is a schematic diagram of an example structure of the high-voltage decision circuit in the on-chip power supply switching circuit of this application embodiment. Referring to Figure 3, in the embodiment of this application, the competition interlocking loop of the high-voltage decision circuit 30 may include a second PMOS transistor 32 and a third PMOS transistor 33. Preferably, the second PMOS transistor 32 and the third PMOS transistor 33 may be selected from the low-voltage devices described above.

[0062] For example, in an embodiment of this application, the second PMOS transistor 32 may be located between the first decision input terminal of the high-voltage decision circuit 30 that receives the LDO output voltage V_LDO and the high-voltage decision output terminal of the high-voltage decision circuit 30 that generates the high-voltage decision voltage V_high. The third PMOS transistor 33 may be located between the second decision input terminal of the high-voltage decision circuit 30 that receives the backup external voltage VDDC and the high-voltage decision output terminal of the high-voltage decision circuit 30 that generates the high-voltage decision voltage V_high. Furthermore, the second PMOS transistor 32 and the third PMOS transistor 33 may be selectively turned on, so that the high-voltage decision voltage V_high can adaptively maintain the higher of the LDO output voltage V_LDO and the backup external voltage VDDC according to the change in the relative relationship between the LDO output voltage V_LDO and the backup external voltage VDDC.

[0063] For example, in an embodiment of this application, the second PMOS transistor 32 can be turned on when the LDO output voltage V_LDO is higher than the backup external voltage VDDC, and the second PMOS transistor 32 can be turned off when the backup external voltage VDDC is lower than the LDO output voltage V_LDO, so that the first decision input terminal of the high voltage decision circuit 30 is connected to the high voltage decision output terminal of the high voltage decision circuit 30, and the second decision input terminal of the high voltage decision circuit 30 is disconnected from the high voltage decision output terminal of the high voltage decision circuit 30, thereby setting the high voltage decision voltage V_high to the higher of the LDO output voltage V_LDO and the backup external voltage VDDC.

[0064] For example, in an embodiment of this application, the third PMOS transistor 33 can be turned on when the backup external voltage VDDC is higher than the LDO output voltage V_LDO, and the second PMOS transistor 32 can be turned off when the LDO output voltage V_LDO is lower than the backup external voltage VDDC. This causes the second decision input terminal of the high voltage decision circuit 30 to be connected to the high voltage decision output terminal of the high voltage decision circuit 30, and the first decision input terminal of the high voltage decision circuit 30 to be disconnected from the high voltage decision output terminal of the high voltage decision circuit 30. Consequently, the high voltage decision voltage V_high is set to the higher of the LDO output voltage V_LDO and the backup external voltage VDDC, namely the backup external voltage VDDC.

[0065] For example, in the embodiments of this application, the second PMOS transistor 32 and the third PMOS transistor 33 can maintain their current on or off state when the LDO output voltage V_LDO is equal to the standby external voltage VDDC, so as to maintain the on state that has been formed at the first decision input terminal or the second decision input terminal of the high voltage decision circuit 30 and the high voltage decision output terminal of the high voltage decision circuit 30.

[0066] For example, in an embodiment of this application, the drain of the second PMOS transistor 32 can be connected to the first decision input terminal of the high-voltage decision circuit 30 to receive the LDO output voltage V_LDO, the source of the second PMOS transistor 32 can be connected to the high-voltage decision output terminal of the high-voltage decision circuit 30 to generate the high-voltage decision voltage V_high, and the gate of the second PMOS transistor 32 can be connected to the second decision input terminal of the high-voltage decision circuit 30 to receive the backup external voltage VDDC, so that: the second PMOS transistor 32 is turned on when the LDO output voltage V_LDO is higher than the backup external voltage VDDC, turned off when the LDO output voltage V_LDO is lower than the backup external voltage VDDC, and turned on or off when the LDO output voltage V_LDO is equal to the backup external voltage VDDC.

[0067] For example, in an embodiment of this application, the drain of the third PMOS transistor 33 can be connected to the second decision input terminal of the high-voltage decision circuit 30 to receive the backup external voltage VDDC. For example, a protection element such as an ESD (Electro-Static discharge) resistor can be connected in series between the drain of the third PMOS transistor 33 and the second decision input terminal. The source of the third PMOS transistor 33 can be connected to the high-voltage decision output terminal of the high-voltage decision circuit 30 to generate the high-voltage decision voltage V_high. Furthermore, the gate of the third PMOS transistor 33 can be connected to the first decision input terminal of the high-voltage decision circuit 30 to receive the LDO output voltage V_LDO, so that the third PMOS transistor 33 is turned on when the backup external voltage VDDC is higher than the LDO output voltage V_LDO, turned off when the backup external voltage VDDC is lower than the LDO output voltage V_LDO, and turned on or off when the backup external voltage VDDC is equal to the LDO output voltage V_LDO.

[0068] For example, in an embodiment of this application, the switching execution circuit 70 can use a control signal to switch the gate voltage of the first PMOS transistor 50. For example, the control signal received by the switching execution circuit 70 can be generated by the power management module in the processor, and the power management module in the processor can be independent of the target on-chip load.

[0069] For example, in an embodiment of this application, the signal level of the control signal used by the switching execution circuit 70 to control the gate voltage of the first PMOS transistor 50 can be configured as follows:

[0070] When the LDO is enabled normally, the gate of the first PMOS transistor 50 is turned on to the high voltage decision output terminal of the high voltage decision circuit 30, so that the gate voltage of the first PMOS transistor 50 is set to the high voltage decision voltage V_high. Then, the substrate voltage of the first PMOS transistor 50 is turned off (i.e., completely turned off) at the highest voltage state in the device, so as to select the LDO output voltage V_LDO as the on-chip power supply voltage for the target on-chip load (e.g., the processor core).

[0071] When the LDO malfunctions, the gate of the first PMOS transistor 50 is grounded, and the gate voltage of the first PMOS transistor 50 is set to a low voltage that is at the same potential as the ground level Vss. Then, the first PMOS transistor 50 is turned on to switch the on-chip power supply voltage from the LDO output voltage V_LDO to the backup external voltage VDDC.

[0072] Figure 4 is a schematic diagram of an example structure of the switching execution circuit in the on-chip power supply switching circuit of this application embodiment. Referring to Figure 4, in the embodiment of this application, the switching execution circuit 70 can use an NMOS (N-Metal Oxide Semiconductor) transistor or a PMOS transistor to perform the response operation to the control signal. Taking the switching execution circuit 70 as an example that can use an NMOS transistor to perform the response operation to the control signal, the switching execution circuit 70 may include a first NMOS transistor 71 and a second NMOS transistor 72.

[0073] For example, in an embodiment of this application, the first NMOS transistor 71 is connected between the gate of the first PMOS transistor 50 and the high-voltage decision output terminal of the high-voltage decision circuit 30, and the second NMOS transistor 72 is connected between the gate of the first PMOS transistor 50 and ground.

[0074] For example, in an embodiment of this application, the control signal used to switch the gate voltage of the first PMOS transistor 50 controlled by the execution circuit 70 may include a first control signal Sig_sw1 and a second control signal Sig_sw2 with opposite signal levels. The first control signal Sig_sw1 is used to control the first NMOS transistor 71, and the second control signal Sig_sw2 can be used to control the second NMOS transistor 72.

[0075] For example, in an embodiment of this application, the signal level of the first control signal Sig_sw1 can be configured as follows:

[0076] When the LDO is normally enabled, the first NMOS transistor 71 is turned on to connect the gate of the first PMOS transistor 50 to the high-voltage decision output terminal of the high-voltage decision circuit 30. This sets the gate voltage of the first PMOS transistor 50 to the high-voltage decision voltage V_high. Consequently, the substrate voltage of the first PMOS transistor 50 is turned off (i.e., completely turned off) at its highest internal voltage state, thus selecting the LDO output voltage V_LDO as the on-chip supply voltage for the target on-chip load (e.g., the processor core).

[0077] When an LDO malfunctions, the first NMOS transistor 71 is turned off to disconnect the gate of the first PMOS transistor 50 from the high-voltage decision output terminal of the high-voltage decision circuit 30.

[0078] For example, in an embodiment of this application, the signal level of the second control signal Sig_sw2 can be configured as follows:

[0079] When the LDO is normally enabled, the second NMOS transistor 72 is turned off to disconnect the ground connection of the gate of the first PMOS transistor 50; and,

[0080] When an LDO malfunctions, the second NMOS transistor 72 is turned on to ground the gate of the first PMOS transistor 50, thereby setting the gate voltage of the first PMOS transistor 50 to a pull-down voltage at the same potential as ground level Vss. Then, the first PMOS transistor 50 is turned on to switch the on-chip power supply voltage from the LDO output voltage V_LDO to the backup external voltage VDDC.

[0081] Exemplarily, in an embodiment of this application, the drain of the first NMOS transistor 71 can be connected to the high-voltage decision output terminal of the high-voltage decision circuit 30, the source of the first NMOS transistor 71 can be connected to the gate of the first PMOS transistor 50, the substrate voltage of the first NMOS transistor 71 can be set to ground level Vss, and the gate of the first NMOS transistor 71 receives the first control signal Sig_sw1. In this case:

[0082] The signal level of the first control signal Sig_sw1 can be set to ground level Vss when the LDO is normally enabled, so as to turn on the first NMOS transistor 71; and,

[0083] The signal level of the first control signal Sig_sw1 can be set to the reference level when the LDO malfunctions, so as to turn off the first NMOS transistor 71.

[0084] Exemplarily, in an embodiment of this application, the drain of the second NMOS transistor 72 can be connected to the gate of the first PMOS transistor 50, the source of the second NMOS transistor 72 can be grounded, the substrate voltage of the second NMOS transistor 72 can be set to ground level Vss, and the gate of the second NMOS transistor 72 receives the second control signal Sig_sw2. In this case:

[0085] The signal level of the second control signal Sig_sw2 can be set to the reference level when the LDO is normally enabled, so as to turn off the second NMOS transistor 72; and,

[0086] When the LDO malfunctions, the signal level of the second control signal Sig_sw2 can be set to ground level Vss to turn on the second NMOS transistor 72.

[0087] For example, in an embodiment of this application, the reference levels of the first control signal Sig_sw1 and the second control signal Sig_sw2 can be higher than or equal to the high-voltage decision voltage V_high, to ensure that the gate voltages of the first NMOS transistor 71 and the second NMOS transistor 72 can be greater than the high-voltage decision voltage V_high, thereby ensuring that the first NMOS transistor 71 and the second NMOS transistor 72 can reach a fully conducting state when turned on. In this case, the first NMOS transistor and the second NMOS transistor are preferably high-voltage devices as described above.

[0088] For example, in the embodiments of this application, the reference levels of the first control signal Sig_sw1 and the second control signal Sig_sw2 can be at the same potential as the processor's external power supply voltage VDDH (e.g., I / O voltage).

[0089] In another embodiment of this application, a processor is provided, including the on-chip power supply switching circuit as described in the foregoing embodiments.

[0090] Exemplary examples, in embodiments of this application, the processor can be any one of a CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit). The above description of processor types in the embodiments of this application is intended to illustrate that implementations of the embodiments of this application are not limited to specific processor types.

[0091] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An on-chip power supply switching circuit for a processor, comprising: A high-voltage decision circuit has a first decision input terminal, a second decision input terminal, and a high-voltage decision output terminal. The first decision input terminal receives the LDO output voltage generated by the LDO in the processor. The second decision input terminal receives the backup external voltage of the processor. The high-voltage decision output terminal is used to generate a high-voltage decision voltage. The LDO output voltage is adjustable, and the high-voltage decision voltage is set to the higher of the LDO output voltage and the backup external voltage. A first PMOS transistor has a gate, and a first terminal and a second terminal located on opposite sides of a substrate channel. The first terminal of the first PMOS transistor is used to connect to a target on-chip load in the processor. The first terminal of the first PMOS transistor receives the LDO output voltage. The second terminal of the first PMOS transistor receives the backup external voltage. Furthermore, the substrate voltage of the first PMOS transistor is normally set to the high-voltage decision voltage. and The switching execution circuit is used for: When the LDO is enabled normally, the gate voltage of the first PMOS transistor is set to the high voltage decision voltage, so that the LDO output voltage is selected as the on-chip power supply voltage of the target on-chip load; When the LDO malfunctions, the gate voltage of the first PMOS transistor is pulled low, causing the on-chip power supply voltage to switch from the LDO output voltage to the backup external voltage.

2. The on-chip power supply switching circuit according to claim 1, characterized in that, The high-voltage decision circuit has a contention interlocking loop, which is used for: When the LDO output voltage is higher than the backup external voltage, the first decision input terminal is connected to the high voltage decision output terminal, and the second decision input terminal is disconnected from the high voltage decision output terminal, so that the high voltage decision voltage is set to the higher of the LDO output voltage and the backup external voltage. When the LDO output voltage is lower than the backup external voltage, the second decision input terminal is connected to the high voltage decision output terminal, and the first decision input terminal is disconnected from the high voltage decision output terminal, so that the high voltage decision voltage is set to the backup external voltage, which is the higher of the LDO output voltage and the backup external voltage. and When the LDO output voltage is equal to the backup external voltage, the current conduction state between the first decision input terminal or the second decision input terminal and the high voltage decision output terminal is maintained.

3. The on-chip power supply switching circuit according to claim 2, characterized in that, The competition interlock circuit includes a second PMOS transistor and a third PMOS transistor, wherein: The second PMOS transistor is located between the first decision input terminal and the high-voltage decision output terminal; The third PMOS transistor is located between the second decision input terminal and the high voltage decision output terminal; The second PMOS transistor is turned on when the LDO output voltage is higher than the backup external voltage, and the second PMOS transistor is turned off when the backup external voltage is lower than the LDO output voltage; The third PMOS transistor is turned on when the backup external voltage is higher than the LDO output voltage, and the second PMOS transistor is turned off when the LDO output voltage is lower than the backup external voltage. The second PMOS transistor and the third PMOS transistor maintain their current on or off state when the LDO output voltage is equal to the backup external voltage.

4. The on-chip power supply switching circuit according to claim 3, characterized in that, The source of the second PMOS transistor is connected to the first decision input terminal, the drain of the second PMOS transistor is connected to the high voltage decision output terminal, and the gate of the second PMOS transistor is connected to the second decision input terminal. The source of the third PMOS transistor is connected to the second decision input terminal, the drain of the third PMOS transistor is connected to the high-voltage decision output terminal, and the gate of the third PMOS transistor is connected to the first decision input terminal.

5. The on-chip power supply switching circuit according to claim 1, characterized in that, The switching execution circuit uses a control signal to switch and control the gate voltage of the first PMOS transistor, wherein the signal level of the control signal is configured as follows: When the LDO is enabled normally, the gate of the first PMOS transistor is connected to the high voltage decision output terminal, so that the gate voltage of the first PMOS transistor is set to the high voltage decision voltage. When the LDO malfunctions, the gate of the first PMOS transistor is grounded, and the gate voltage of the first PMOS transistor is set to the pull-down voltage, which is at the same potential as the ground level.

6. The on-chip power supply switching circuit according to claim 5, characterized in that, The control signal is generated by the power management module in the processor, and the power management module is independent of the target on-chip load.

7. The on-chip power supply switching circuit according to claim 5, characterized in that, The switching execution circuit includes a first NMOS transistor and a second NMOS transistor. The first NMOS transistor is connected between the gate of the first PMOS transistor and the high voltage decision output terminal, and the second NMOS transistor is connected between the gate of the first PMOS transistor and ground. The control signals include a first control signal and a second control signal with opposite signal levels, wherein: The signal level of the first control signal is configured to: turn on the first NMOS transistor when the LDO is normally enabled, and turn off the first NMOS transistor when the LDO malfunctions; The signal level of the second control signal is configured to: turn off the second NMOS transistor when the LDO is normally enabled, and turn on the second NMOS transistor when the LDO malfunctions.

8. The on-chip power supply switching circuit according to claim 7, characterized in that, The drain of the first NMOS transistor is connected to the high-voltage decision output terminal, the source of the first NMOS transistor is connected to the gate of the first PMOS transistor, the substrate voltage of the first NMOS transistor is set to the ground level, and the gate of the first NMOS transistor receives the first control signal. When the LDO is normally enabled, the signal level of the first control signal is set to the ground level to turn on the first NMOS transistor; Furthermore, the signal level of the first control signal is set to a reference level when the LDO malfunctions, so as to turn off the first NMOS transistor; The drain of the second NMOS transistor is connected to the gate of the first PMOS transistor, the source of the second NMOS transistor is grounded, the substrate voltage of the second NMOS transistor is set to the ground level, and the gate of the second NMOS transistor receives the second control signal. The signal level of the second control signal is set to the reference level when the LDO is normally enabled, so as to turn off the second NMOS transistor; Furthermore, the signal level of the second control signal is set to the ground level when the LDO malfunctions, so as to turn on the second NMOS transistor; The reference level is higher than or equal to the high voltage decision voltage.

9. The on-chip power supply switching circuit according to claim 8, characterized in that, The LDO uses the external power supply voltage of the processor to generate the LDO output voltage; The LDO output voltage and the backup external voltage are both lower than the external power supply voltage; The reference level is at the same potential as the external power supply voltage.

10. A processor, comprising an on-chip power supply switching circuit, the on-chip power supply switching circuit comprising: A high-voltage decision circuit has a first decision input terminal, a second decision input terminal, and a high-voltage decision output terminal. The first decision input terminal receives the LDO output voltage generated by the LDO in the processor. The second decision input terminal receives the backup external voltage of the processor. The high-voltage decision output terminal is used to generate a high-voltage decision voltage. The LDO output voltage is adjustable, and the high-voltage decision voltage is set to the higher of the LDO output voltage and the backup external voltage. A first PMOS transistor has a gate, and a first terminal and a second terminal located on opposite sides of a substrate channel. The first terminal of the first PMOS transistor is used to connect to a target on-chip load in the processor. The first terminal of the first PMOS transistor receives the LDO output voltage. The second terminal of the first PMOS transistor receives the backup external voltage. Furthermore, the substrate voltage of the first PMOS transistor is normally set to the high-voltage decision voltage. and The switching execution circuit is used for: When the LDO is enabled normally, the gate voltage of the first PMOS transistor is set to the high voltage decision voltage, so that the LDO output voltage is selected as the on-chip power supply voltage of the target on-chip load; When the LDO malfunctions, the gate voltage of the first PMOS transistor is pulled low, causing the on-chip power supply voltage to switch from the LDO output voltage to the backup external voltage.

11. The processor according to claim 10, characterized in that, The high-voltage decision circuit has a contention interlocking loop, which is used for: When the LDO output voltage is higher than the backup external voltage, the first decision input terminal is connected to the high voltage decision output terminal, and the second decision input terminal is disconnected from the high voltage decision output terminal, so that the high voltage decision voltage is set to the higher of the LDO output voltage and the backup external voltage. When the LDO output voltage is lower than the backup external voltage, the second decision input terminal is connected to the high voltage decision output terminal, and the first decision input terminal is disconnected from the high voltage decision output terminal, so that the high voltage decision voltage is set to the backup external voltage, which is the higher of the LDO output voltage and the backup external voltage. and When the LDO output voltage is equal to the backup external voltage, the current conduction state between the first decision input terminal or the second decision input terminal and the high voltage decision output terminal is maintained.

12. The processor according to claim 11, characterized in that, The competition interlock circuit includes a second PMOS transistor and a third PMOS transistor, wherein: The second PMOS transistor is located between the first decision input terminal and the high-voltage decision output terminal; The third PMOS transistor is located between the second decision input terminal and the high voltage decision output terminal; The second PMOS transistor is turned on when the LDO output voltage is higher than the backup external voltage, and the second PMOS transistor is turned off when the backup external voltage is lower than the LDO output voltage; The third PMOS transistor is turned on when the backup external voltage is higher than the LDO output voltage, and the second PMOS transistor is turned off when the LDO output voltage is lower than the backup external voltage. The second PMOS transistor and the third PMOS transistor maintain their current on or off state when the LDO output voltage is equal to the backup external voltage.

13. The processor according to claim 12, characterized in that, The source of the second PMOS transistor is connected to the first decision input terminal, the drain of the second PMOS transistor is connected to the high voltage decision output terminal, and the gate of the second PMOS transistor is connected to the second decision input terminal. The source of the third PMOS transistor is connected to the second decision input terminal, the drain of the third PMOS transistor is connected to the high-voltage decision output terminal, and the gate of the third PMOS transistor is connected to the first decision input terminal.

14. The processor according to claim 10, characterized in that, The switching execution circuit uses a control signal to switch and control the gate voltage of the first PMOS transistor, wherein the signal level of the control signal is configured as follows: When the LDO is enabled normally, the gate of the first PMOS transistor is connected to the high voltage decision output terminal, so that the gate voltage of the first PMOS transistor is set to the high voltage decision voltage. When the LDO malfunctions, the gate of the first PMOS transistor is grounded, and the gate voltage of the first PMOS transistor is set to the pull-down voltage, which is at the same potential as the ground level.

15. The processor according to claim 14, characterized in that, The control signal is generated by the power management module in the processor, and the power management module is independent of the target on-chip load.

16. The processor according to claim 14, characterized in that, The switching execution circuit includes a first NMOS transistor and a second NMOS transistor. The first NMOS transistor is connected between the gate of the first PMOS transistor and the high voltage decision output terminal, and the second NMOS transistor is connected between the gate of the first PMOS transistor and ground. The control signals include a first control signal and a second control signal with opposite signal levels, wherein: The signal level of the first control signal is configured to: turn on the first NMOS transistor when the LDO is normally enabled, and turn off the first NMOS transistor when the LDO malfunctions; The signal level of the second control signal is configured to: turn off the second NMOS transistor when the LDO is normally enabled, and turn on the second NMOS transistor when the LDO malfunctions.

17. The processor according to claim 16, characterized in that, The drain of the first NMOS transistor is connected to the high-voltage decision output terminal, the source of the first NMOS transistor is connected to the gate of the first PMOS transistor, the substrate voltage of the first NMOS transistor is set to the ground level, and the gate of the first NMOS transistor receives the first control signal. When the LDO is normally enabled, the signal level of the first control signal is set to the ground level to turn on the first NMOS transistor; Furthermore, the signal level of the first control signal is set to a reference level when the LDO malfunctions, so as to turn off the first NMOS transistor; The drain of the second NMOS transistor is connected to the gate of the first PMOS transistor, the source of the second NMOS transistor is grounded, the substrate voltage of the second NMOS transistor is set to the ground level, and the gate of the second NMOS transistor receives the second control signal. The signal level of the second control signal is set to the reference level when the LDO is normally enabled, so as to turn off the second NMOS transistor; Furthermore, the signal level of the second control signal is set to the ground level when the LDO malfunctions, so as to turn on the second NMOS transistor; The reference level is higher than or equal to the high voltage decision voltage.

18. The processor according to claim 17, characterized in that, The LDO uses the external power supply voltage of the processor to generate the LDO output voltage; The LDO output voltage and the backup external voltage are both lower than the external power supply voltage; The reference level is at the same potential as the external power supply voltage.

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