Solar cell preparation method and solar cell

Abstract

The present disclosure provides a solar cell preparation method and a solar cell. The solar cell preparation method comprises the following steps: providing a semiconductor substrate; forming a first passivation structure on the back surface of the semiconductor substrate, the first passivation structure comprising a first tunneling layer and a first intrinsic silicon layer that are stacked in sequence; patterning the first passivation structure to form a groove exposing the semiconductor substrate; forming a second passivation structure on the semiconductor substrate exposed from the groove, the second passivation structure comprising a second tunneling layer and a second doped silicon layer that are stacked in sequence; and forming a dopant source paste on the first intrinsic silicon layer, and perform doping by irradiating the first intrinsic silicon layer with a laser.

Description

Methods for fabricating solar cells and solar cells

[0001] This application claims priority to Chinese Patent Application No. 202411526880.6, filed on October 29, 2024, entitled "Method for Preparing Solar Cells and Solar Cells", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and the solar cell itself. Background Technology

[0003] Back-contact solar cells refer to solar cells with both the positive and negative electrodes located on the back side. Since the concept of back-contact cells was proposed in 1975, continuous research and technological improvements have made them one of the most recognized high-efficiency technologies in the solar photovoltaic industry. Their front-side appearance not only maximizes the light-receiving area by eliminating grid lines but also boasts a more aesthetically pleasing design. Furthermore, this structure can serve as a platform technology, combining with various battery technologies to highlight the unique characteristics of back-contact solar cells.

[0004] Traditional back-contact solar cell fabrication typically requires patterning to form isolation trenches, which are located between two regions with different doping types to prevent excessive carrier recombination due to short circuits. This process still presents a high degree of fabrication complexity, and the presence of the isolation trenches also limits the area that the doped layer can occupy, leading to a decrease in the number of carriers extracted by the solar cell. Summary of the Invention

[0005] According to embodiments of this disclosure, a method for fabricating a solar cell is provided, comprising the following steps:

[0006] Provide semiconductor substrates;

[0007] A first passivation structure is formed on the back side of the semiconductor substrate, the first passivation structure comprising a first tunneling layer and a first intrinsic silicon layer stacked sequentially.

[0008] The first passivation structure is patterned to form a groove that exposes the semiconductor substrate;

[0009] A second passivation structure is formed on the semiconductor substrate exposed from the groove, the second passivation structure comprising a second tunneling layer and a second doped silicon layer sequentially stacked; and,

[0010] A doping source paste is formed on the first intrinsic silicon layer, and the first intrinsic silicon layer is doped by irradiating it with a laser to form a first doped silicon layer having doped and undoped regions. The undoped regions are disposed on both sides of the doped regions, and the doped regions and the second doped silicon layer are separated by the undoped regions.

[0011] In some embodiments of this disclosure, the step of patterning the first passivation structure includes:

[0012] A protective layer is formed on the surface of the first passivated structure;

[0013] The protective layer is patterned using laser etching; and,

[0014] The first passivation structure exposed from the protective layer is removed using a first etching solution containing alkali to form the groove.

[0015] In some embodiments of this disclosure, the step of forming the second passivation structure includes:

[0016] The semiconductor substrate is placed in the deposition chamber of a chemical vapor deposition apparatus, and a second tunneling layer and a second intrinsic silicon layer are sequentially deposited on the back side of the semiconductor substrate. The second tunneling layer extends and is deposited on the sidewall and top wall of the first intrinsic silicon layer.

[0017] The semiconductor substrate is placed in a diffusion chamber, a reactive gas containing a doped source is introduced into the diffusion chamber, and a doped precursor material is deposited on the surface of the second intrinsic silicon layer; and...

[0018] Annealing is performed to allow the doping element in the doped precursor material to diffuse into the second intrinsic silicon layer, forming the second doped silicon layer and a doped oxide layer located on the second doped silicon layer.

[0019] In some embodiments of this disclosure, the second passivation structure and the doped oxide layer further extend onto the protective layer; prior to forming the doped source paste on the first intrinsic silicon layer, the following steps are also included:

[0020] The doped oxide layer on the protective layer is selectively removed by laser etching.

[0021] The second passivation structure located on the protective layer is selectively removed using a second etching solution containing alkali; and,

[0022] The front side of the semiconductor substrate is texturized.

[0023] In some embodiments of this disclosure, the step of forming the first passivation structure includes:

[0024] The semiconductor substrate is placed in the deposition chamber of a chemical vapor deposition apparatus, and a first tunneling layer and a first intrinsic silicon layer are sequentially deposited on the back side of the semiconductor substrate.

[0025] In some embodiments of this disclosure, the doping type of the semiconductor substrate is the same as that of the second doped silicon layer, and the doping type of the semiconductor substrate is different from that of the first doped silicon layer.

[0026] In some embodiments of this disclosure, the doped source slurry comprises a boron-containing compound, and the solid content of the doped source slurry is 20% to 55%.

[0027] In some embodiments of this disclosure, the viscosity of the doped source slurry is 20 Pa·s to 50 Pa·s.

[0028] In some embodiments of this disclosure, during the step of forming the doped source paste, the region where the doped source paste is located is spaced apart from the edge of the first intrinsic silicon layer.

[0029] In some embodiments of this disclosure, the linewidth of the region where the doped source slurry is located is 400 μm to 500 μm.

[0030] In some embodiments of this disclosure, in the step of doping the first intrinsic silicon layer by irradiating it with a laser, the power of the laser used is 30W to 60W, and the scanning width of the laser used is 300μm to 600μm.

[0031] Furthermore, according to some embodiments of this disclosure, a solar cell is provided, the solar cell comprising a semiconductor substrate, a first tunneling layer, a second tunneling layer, a first doped silicon layer, and a second doped silicon layer;

[0032] The first tunneling layer and the first doped silicon layer are stacked sequentially on the back side of the semiconductor substrate, and the second tunneling layer and the second doped silicon layer are stacked sequentially on the back side of the semiconductor substrate; the first doped silicon layer includes a doped region and an undoped region, the undoped region is disposed on both sides of the doped region, and the doped region and the second doped silicon layer are separated by the undoped region.

[0033] In some embodiments of this disclosure, the doped regions of the first doped silicon layer contain dopant elements, and the undoped regions of the first doped silicon layer do not contain dopant elements or the doping concentration of the dopant elements is less than 1 × 10⁻⁶. 18 . Attached Figure Description

[0034] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in this application will be briefly described below. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without any creative effort.

[0035] Figure 1 is a schematic diagram of the steps in a method for fabricating a solar cell according to the present disclosure;

[0036] Figure 2 is a schematic cross-sectional view of the first passivation structure formed on the semiconductor substrate;

[0037] Figure 3 is a schematic diagram of a patterned protective layer formed on the basis of the structure shown in Figure 2;

[0038] Figure 4 is a schematic diagram of the first passivation structure after graphical processing based on the structure shown in Figure 3.

[0039] Figure 5 is a schematic diagram of the structure in which the second tunneling layer and the second intrinsic silicon layer are formed based on the structure shown in Figure 4.

[0040] Figure 6 is a schematic diagram of the structure in which a second doped silicon layer and a doped oxide layer are formed based on the structure shown in Figure 5.

[0041] Figure 7 is a schematic diagram of the structure shown in Figure 6, after removing the doped oxide layer and the second passivation structure located on the protective layer.

[0042] Figure 8 is a schematic diagram of the structure of the doped source paste formed on the basis of the structure shown in Figure 7;

[0043] Figure 9 is a schematic diagram of the structure in which the first doped silicon layer is formed based on the structure shown in Figure 8;

[0044] Figure 10 is a schematic diagram of the structure in which the first surface functional layer and the second surface functional layer are formed based on the structure shown in Figure 9.

[0045] The reference numerals and their meanings in the accompanying drawings are as follows: 100, semiconductor substrate; 110, first tunneling layer; 120, first doped silicon layer; 121, doped region; 122, undoped region; 130, second tunneling layer; 140, second doped silicon layer; 150, first surface functional layer; 160, second surface functional layer; 170, first electrode; 180, second electrode; 210, first intrinsic silicon layer; 220, second intrinsic silicon layer; 230, protective layer; 240, doped oxide layer; 250, doping source paste. Detailed Implementation

[0046] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0048] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0049] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0050] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0051] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0052] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0053] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0054] This disclosure provides a method for fabricating a solar cell, comprising the following steps: providing a semiconductor substrate; forming a first passivation structure on the back side of the semiconductor substrate, the first passivation structure comprising a first tunneling layer and a first intrinsic silicon layer stacked sequentially; patterning the first passivation structure to form a groove exposing the semiconductor substrate; forming a second passivation structure on the semiconductor substrate exposed from the groove, the second passivation structure comprising a second tunneling layer and a second doped silicon layer stacked sequentially; and forming a doping source paste on the first intrinsic silicon layer and doping the first intrinsic silicon layer by irradiating it with a laser to form a first doped silicon layer.

[0055] In the solar cell fabrication method disclosed herein, a patterned first passivation structure is first formed, followed by the formation of a second passivation structure on a semiconductor substrate exposed from a groove. A doping source paste is then formed on a first intrinsic silicon layer, and a first doped silicon layer is formed by laser irradiation. The second tunneling layer in the second passivation structure serves to separate the first intrinsic silicon layer and the second doped silicon layer. Furthermore, laser irradiation exhibits strong localization, making it difficult or impossible for dopant elements to diffuse laterally into the second doped silicon layer during doping of the first intrinsic silicon layer. Therefore, this fabrication method, which involves forming the second passivation structure followed by laser doping based on the doping source paste, ensures an insulating gap between the first and second doped silicon layers, preventing excessive recombination of charge carriers. This eliminates the need for additional isolation trenches, simplifying the solar cell fabrication process. Moreover, since this method eliminates the need for additional isolation trenches, the area on the back side of the semiconductor substrate available for the first and second doped silicon layers is increased, which is beneficial for increasing the number of charge carriers that the solar cell can extract.

[0056] Figure 1 is a schematic diagram of the steps in a method for fabricating a solar cell according to the present disclosure. Referring to Figure 1, the fabrication method includes steps S1 to S5, as detailed below.

[0057] Step S1, provide a semiconductor substrate 100.

[0058] As an example of this embodiment, the material of the semiconductor substrate 100 may be selected from one or more of silicon, germanium, gallium nitride, gallium arsenide, and silicon carbide. In this embodiment, the material of the semiconductor substrate 100 may be silicon, such as a silicon wafer, which may be a monocrystalline silicon wafer or a polycrystalline silicon wafer.

[0059] As an example of this embodiment, the semiconductor substrate 100 may contain doping elements, and the doping type of the semiconductor substrate 100 may be N-type or P-type. When the doping type of the semiconductor substrate 100 is N-type, the doping element in the semiconductor substrate 100 may be one or more of phosphorus and arsenic. When the doping type of the semiconductor substrate 100 is P-type, the doping element in the semiconductor substrate 100 may be one or more of aluminum, boron, gallium, and indium.

[0060] As an example of this embodiment, the step of providing the semiconductor substrate 100 includes performing an alkaline polishing treatment on the semiconductor substrate 100. Further, the semiconductor substrate 100 can be subjected to the alkaline polishing treatment using an alkaline polishing solution, wherein the alkaline in the alkaline polishing solution can be selected from sodium hydroxide.

[0061] As a further example of this embodiment, the temperature of the alkaline polishing treatment can be 60°C to 80°C, and the time of the alkaline polishing treatment can be 200s to 400s.

[0062] Step S2: A first passivation structure is formed on the back side of the semiconductor substrate 100. The first passivation structure includes a first tunneling layer 110 and a first intrinsic silicon layer 210 stacked sequentially.

[0063] Figure 2 is a cross-sectional schematic diagram of the first passivation structure formed on the semiconductor substrate 100. Referring to Figure 2, the first tunneling layer 110 and the first intrinsic silicon layer 210 are sequentially stacked on the back side of the semiconductor substrate 100.

[0064] As an example of this embodiment, the material of the first tunneling layer 110 includes silicon oxide or aluminum oxide. In this embodiment, the material of the first tunneling layer 110 includes silicon oxide.

[0065] As an example of this embodiment, the material of the first intrinsic silicon layer 210 is intrinsic amorphous silicon.

[0066] As an example of this embodiment, the step of forming the first passivation structure includes: placing a semiconductor substrate 100 in the deposition chamber of a chemical vapor deposition apparatus, and sequentially depositing a first tunneling layer 110 and a first intrinsic silicon layer 210 on the back side of the semiconductor substrate 100. In this embodiment, the deposition chamber may be the deposition chamber of a low-pressure chemical vapor deposition apparatus.

[0067] As an example of this embodiment, the thickness of the first tunneling layer 110 is 1 nm to 3 nm.

[0068] As an example of this embodiment, the thickness of the first intrinsic silicon layer 210 is 80nm to 150nm.

[0069] As an example of this embodiment, during the deposition of the first tunneling layer 110, a silicon source gas and an oxygen source gas can be introduced into the deposition chamber. The silicon source gas can be selected from hydrides, such as silane (SiH4), and the oxygen source gas can be selected from oxygen or an oxidizing gas.

[0070] As an example of this embodiment, during the deposition of the first intrinsic silicon layer 210, a silicon source gas, such as silane, can be introduced into the deposition chamber. The flow rate of the silane can be from 600 sccm to 2000 sccm.

[0071] As an example of this embodiment, during the deposition of the first tunneling layer 110 and / or the first intrinsic silicon layer 210, the temperature in the deposition chamber can be controlled to be 480°C to 680°C, and the pressure in the deposition chamber can be controlled to be 60 mTorr to 200 mTorr.

[0072] Step S3: The first passivation structure is patterned to form a groove that exposes the semiconductor substrate 100.

[0073] As an example of this embodiment, the step of patterning the first passivation structure includes: forming a protective layer 230 on the surface of the first passivation structure; patterning the protective layer 230 by laser etching; and using a first etching solution containing alkali to remove the first passivation structure exposed from the protective layer 230 to form a groove.

[0074] Figure 3 is a schematic diagram of a patterned protective layer 230 formed on the structure shown in Figure 2. Referring to Figure 3, the protective layer 230 is disposed on the first passivation structure and contacts the first intrinsic silicon layer 210. After patterning, the protective layer 230 has an opening exposing the first passivation structure.

[0075] The protective layer 230 serves as a mask during patterning of the first passivation structure, and the material of the protective layer 230 differs from the material of the first intrinsic silicon layer 210. As an example of this embodiment, the material of the protective layer 230 is selected from silicon oxide (SiO2). x ), silicon nitride (SiN) x ) and silicon oxynitride (SiON) x One or more of the following.

[0076] As an example of this embodiment, the method of forming the protective layer 230 on the surface of the first passivated structure can be selected from low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, catalytic chemical vapor deposition, or atomic layer deposition.

[0077] As an example of this embodiment, the thickness of the protective layer 230 is 2nm to 50nm.

[0078] As an example of this embodiment, during the patterning process of the protective layer 230 by laser etching, the power of the laser source is 20W to 100W, and the laser spot size is 100μm to 300μm.

[0079] Figure 4 is a schematic diagram of the first passivation structure patterned based on the structure shown in Figure 3. Referring to Figure 4, a groove is formed in the first passivation structure that exposes the semiconductor substrate 100.

[0080] As an example of this embodiment, the alkali in the first etching solution can be one or more of sodium hydroxide and potassium hydroxide.

[0081] As an example of this embodiment, the first etching solution includes sodium hydroxide and water. Further, a sodium hydroxide solution with a mass concentration of 45%–55% can be mixed with water at a volume ratio of 1:20 to form the first etching solution.

[0082] As an example of this embodiment, during the process of removing the first passivation structure exposed from the protective layer 230 using a first etching solution containing alkali, the etching time is 180s to 420s, and the temperature of the first etching solution is 65°C to 80°C.

[0083] As an example of this embodiment, the depth of the groove formed after etching is 1μm to 5μm.

[0084] In this embodiment, after etching and forming the groove, the protective layer 230 can be temporarily retained. The protective layer 230 can also protect the first intrinsic silicon layer 210 located below in subsequent fabrication processes.

[0085] Step S4: A second passivation structure is formed on the semiconductor substrate 100 exposed from the groove.

[0086] As an example of this embodiment, the steps of forming the second passivation structure include: placing a semiconductor substrate 100 in a deposition chamber of a chemical vapor deposition apparatus, sequentially depositing a second tunneling layer 130 and a second intrinsic silicon layer 220 on the back side of the semiconductor substrate 100, the second tunneling layer 130 further extending and deposited on the sidewalls and top wall of the first intrinsic silicon layer 210; placing the semiconductor substrate 100 in a diffusion chamber, introducing a reactive gas containing a dopant source into the diffusion chamber, depositing a doped precursor material on the surface of the second intrinsic silicon layer 220; and annealing the material to diffuse the dopant element in the doped precursor material into the second intrinsic silicon layer 220, forming a second doped silicon layer 140 and a doped oxide layer 240.

[0087] Figure 5 is a schematic diagram of the structure in which the second tunneling layer 130 and the second intrinsic silicon layer 220 are formed based on the structure shown in Figure 4. Referring to Figure 5, the second tunneling layer 130 and the second intrinsic silicon layer 220 are sequentially stacked on the semiconductor substrate 100.

[0088] As an example of this embodiment, the thickness of the second tunneling layer 130 is 1 nm to 3 nm.

[0089] As an example of this embodiment, the thickness of the second intrinsic silicon layer 220 is 80nm to 150nm.

[0090] As an example of this embodiment, during the deposition of the second tunneling layer 130, a silicon source gas and an oxygen source gas can be introduced into the deposition chamber. The silicon source gas can be selected from hydrides, such as silanes, and the oxygen source gas can be selected from oxygen or an oxidizing gas.

[0091] As an example of this embodiment, during the deposition of the second intrinsic silicon layer 220, a silicon source gas, such as silane, can be introduced into the deposition chamber. The flow rate of the silane can be from 600 sccm to 2000 sccm.

[0092] As an example of this embodiment, during the deposition of the second tunneling layer 130 and / or the second intrinsic silicon layer 220, the temperature in the deposition chamber can be controlled to be 480°C to 680°C, and the pressure in the deposition chamber can be controlled to be 60 mTorr to 200 mTorr.

[0093] Referring to FIG5, as an example of this embodiment, the second tunneling layer 130 is also deposited on the sidewalls and topwalls of the first intrinsic silicon layer 210 to separate the second intrinsic silicon layer 220 and the subsequently formed second doped silicon layer 140, and to prevent dopant elements from diffusing from the second doped silicon layer 140 into the first intrinsic silicon layer 210.

[0094] Figure 6 is a schematic diagram of the structure in which a second doped silicon layer 140 and a doped oxide layer 240 are formed based on the structure shown in Figure 5. Referring to Figure 6, the second intrinsic silicon layer 220 is transformed into a second doped silicon layer 140, and a doped oxide layer 240 is also formed on the surface of the second doped silicon layer 140. It can be understood that the second intrinsic silicon layer 220 can serve as a precursor material for the second doped silicon layer 140, and after doping treatment, it can form the second doped silicon layer 140.

[0095] As an example of this embodiment, during the process of introducing a reaction gas containing a doped source into the diffusion chamber, the doped source can be selected according to the doping element in the second doped silicon layer 140. For example, in this embodiment, the doping type of the second doped silicon layer 140 is the same as the doping type of the semiconductor substrate 100, so the doping element in the second doped silicon layer 140 can be selected from phosphorus, and correspondingly, the doping source can include phosphorus oxychloride (POCl3). When introducing the reaction gas, nitrogen can be used as the carrier gas for phosphorus oxychloride.

[0096] As an example of this embodiment, the temperature within the diffusion chamber can be controlled to be 800°C to 1000°C during the introduction of the reaction gas. At this temperature, the dopant source can be deposited on the surface of the second intrinsic silicon layer 220 to form a doped precursor material. The concentration of the dopant element in the doped precursor material can be 1 × 10⁻⁶. 21 cm - 3 ~5×10 21 cm -3 .

[0097] As an example of this embodiment, during the annealing process, the dopant element in the precursor material diffuses into the second intrinsic silicon layer 220, thereby transforming the second intrinsic silicon layer 220 into a second doped silicon layer 140. Simultaneously, a doped oxide layer 240 is formed on the surface of the second intrinsic silicon layer 220. In this embodiment, the doped oxide layer 240 is a phosphosilicate glass (PSG) layer. The doped oxide layer 240 can be temporarily retained and serves a protective function in subsequent fabrication processes.

[0098] Step S5: A doped source paste 250 is formed on the first intrinsic silicon layer 210, and the first intrinsic silicon layer 210 is doped by laser irradiation to form a first doped silicon layer 120.

[0099] Referring to FIG6, as an example of this embodiment, the second passivation structure and the doped oxide layer 240 are further extended onto the protective layer 230. Before forming the doped source paste 250 on the first intrinsic silicon layer 210, the following steps are included: selectively removing the doped oxide layer 240 located on the protective layer 230 by laser etching; selectively removing the second passivation structure located on the protective layer 230 by a second etchant containing an alkali; and texturing the front side of the semiconductor substrate 100.

[0100] Figure 7 is a schematic diagram of the structure shown in Figure 6, in which the doped oxide layer 240 and the second passivation structure located on the protective layer 230 are removed. As shown in Figure 7, the doped oxide layer 240 and the second passivation structure deposited on the protective layer 230 are removed, while the second passivation structure in the groove is retained.

[0101] As an example of this embodiment, during the selective removal of the doped oxide layer 240 located on the protective layer 230, the power of the laser source is 50W to 100W, and the laser spot size is 100μm to 300μm.

[0102] As an example of this embodiment, in the process of selectively removing the second passivation structure located on the protective layer 230, the second etching solution includes sodium hydroxide and water. Further, a sodium hydroxide solution with a mass concentration of 45% to 55% can be mixed with water at a volume ratio of 1:10 to form the second etching solution.

[0103] As an example of this embodiment, during the selective removal of the second passivation structure located on the protective layer 230, the temperature of the second etching solution can be controlled to be 60°C to 80°C. Since the doped oxide layer 240 on the protective layer 230 is removed, the second etching solution can directly remove the second doped silicon layer 140 and the second tunneling layer 130 located on the protective layer 230. The second passivation structure in the trench is retained.

[0104] As an example of this embodiment, during the texturing process of the front side of the semiconductor substrate 100, an alkaline texturing agent can be used for texturing.

[0105] As a further example of this embodiment, a sodium hydroxide solution with a mass concentration of 45% to 55%, a texturing additive, and water can be mixed in a volume ratio of 3:1:20 to form a texturing agent.

[0106] As a further example of this embodiment, during the texturing process on the front side of the semiconductor substrate 100, the temperature of the texturing agent is controlled to be 70°C to 85°C, and the texturing time is controlled to be 300s to 420s.

[0107] Referring to FIG7, in this embodiment, after texturing, the front side of the semiconductor substrate 100 opposite to the back side has a texturized structure.

[0108] As an example of this embodiment, after the texturing process, the step of removing the residual doped oxide layer 240 and protective layer 230 is also included.

[0109] As an example of this embodiment, a cleaning agent containing hydrofluoric acid can be used to clean and remove the doped oxide layer 240 and the protective layer 230.

[0110] As a further example of this embodiment, hydrofluoric acid and water can be mixed at a volume ratio of 1:15 to form a cleaning agent. During the cleaning process of removing the doped oxide layer 240 and the protective layer 230, the cleaning time can be 30s to 200s to ensure the thorough removal of the doped oxide layer 240 and the protective layer 230, and to reduce damage to the first intrinsic silicon layer 210 and the second doped silicon layer 140.

[0111] It is understood that after removing the protective layer 230, a doped source paste 250 can be formed on the first intrinsic silicon layer 210. Figure 8 is a schematic diagram of the structure of the doped source paste 250 formed based on the structure shown in Figure 7. The doped source paste 250 may include a compound containing a dopant element, which can be selected corresponding to the doping type of the first doped silicon layer 120. In this embodiment, the doping type of the first doped silicon layer 120 is P-type, so the compound containing the dopant element can be a boron compound, such as boric acid.

[0112] As an example of this embodiment, the solid content of the doped source paste 250 is 20% to 55%. In some examples, the solid content of the doped source paste 250 may be 20%, 25%, 30%, 35%, 40%, 45%, 50%, or 55%, or the solid content of the doped source paste 250 may be between any two of the above solid contents.

[0113] As an example of this embodiment, the viscosity of the doped source slurry 250 is 20 Pa·s to 50 Pa·s. In some examples, the viscosity of the doped source slurry 250 can be 20 Pa·s, 25 Pa·s, 30 Pa·s, 35 Pa·s, 40 Pa·s, 45 Pa·s, or 50 Pa·s, or the viscosity of the doped source slurry 250 can be between any two of the above viscosity values.

[0114] As an example of this embodiment, the doped source paste 250 can be formed on the first intrinsic silicon layer 210 by printing, such as screen printing or inkjet printing. After forming the doped source paste 250, it can be dried to remove the solvent and temporarily solidify the doped source paste 250.

[0115] Referring to FIG8, as an example of this embodiment, in the step of forming the doped source paste 250, the region where the doped source paste 250 is located is spaced apart from the edge of the first intrinsic silicon layer 210. This can minimize the doping concentration of the dopant element at the edge of the first doped silicon layer 120, thereby reducing carrier recombination.

[0116] As an example of this embodiment, in the step of forming the doped source paste 250, the linewidth of the region where the doped source paste 250 is located is 400 μm to 500 μm.

[0117] Figure 9 is a schematic diagram of the structure in which the first doped silicon layer 120 is formed based on the structure shown in Figure 8. Combining Figures 8 and 9, the first intrinsic silicon layer 210 is transformed into the first doped silicon layer 120.

[0118] It is understood that in this embodiment, laser irradiation is a process capable of instantly heating the surface of the first intrinsic silicon layer 210 to an extremely high temperature, which can promote the diffusion of dopant elements into the first intrinsic silicon layer 210 and form the first doped silicon layer 120 in a very short time. Furthermore, laser irradiation has strong localization; the dopant elements only dope within the irradiated area, with very little lateral diffusion. This, combined with the blocking effect of the second tunneling layer 130, effectively prevents contact between the first doped silicon layer 120 and the second doped silicon layer 140. Therefore, this embodiment can achieve the separation between the first doped silicon layer 120 and the second doped silicon layer 140 without the need for additional isolation trenches.

[0119] As an example of this embodiment, during the doping process by irradiating the first intrinsic silicon layer 210 with a laser, the laser power is 30W to 60W, and the laser scanning width is 300μm to 600μm. This is beneficial for making the dopant elements more uniformly distributed within the laser-irradiated area.

[0120] Referring to FIG9, in this embodiment, the first doped silicon layer 120 formed corresponding to the position of the doped source paste 250 includes a doped region 121 and an undoped region 122. The undoped region 122 is disposed on both sides of the doped region 121. The doped region 121 and the second doped silicon layer 140 are separated by the undoped region 122 to avoid short-circuiting between the doped region 121 and the second doped silicon layer 140. The doped region 121 of the first doped silicon layer 120 contains a dopant element, and the undoped region 122 of the first doped silicon layer 120 does not contain a dopant element or the doping concentration of the dopant element is less than 1×10⁻⁶. 18 .

[0121] As an example of this embodiment, after forming the first doped silicon layer 120, a thermal annealing step is also included, which is used to improve the crystallinity of the first doped silicon layer 120 and the second doped silicon layer 140, thereby improving their electrical contact performance.

[0122] As an example of this embodiment, after forming the first doped silicon layer 120, the method further includes forming a first surface functional layer 150 and a second surface functional layer 160. FIG10 shows a schematic diagram of the structure in which the first surface functional layer 150 and the second surface functional layer 160 are formed based on the structure shown in FIG9. Referring to FIG10, the first surface functional layer 150 is stacked on the front side of the semiconductor substrate 100, and the second surface functional layer 160 is stacked on the back side of the semiconductor substrate 100 and is located above the first doped silicon layer 120 and the second doped silicon layer 140.

[0123] As an example of this embodiment, the first surface functional layer 150 includes at least one of a first passivation film and a first antireflection film, and the second surface functional layer 160 includes at least one of a second passivation film and a second antireflection film.

[0124] As a further example of this embodiment, both the first passivation film and the second passivation film are made of aluminum oxide (Al). x O y The first and second passivation films can be formed using atomic layer deposition (ALD), such as plasma-enhanced ALD or plate ALD. When depositing the first and second passivation films, aluminum and oxygen sources can be used as reactant gases; the aluminum source is selected from trimethylaluminum, and the oxygen source is selected from water or oxygen.

[0125] As a further example of this embodiment, the thickness of the first passivation film and the second passivation film is 3nm to 10nm.

[0126] As a further example of this embodiment, the materials of both the first and second antireflective films include one or more of silicon nitride, silicon oxide, and silicon oxynitride. The first and second antireflective films can be formed using plasma-enhanced chemical vapor deposition.

[0127] As a further example of this embodiment, the thickness of the first antireflective film and the second antireflective film is 70nm to 110nm, and the refractive index is 2.0 to 2.4.

[0128] As an example of this embodiment, after forming the second surface functional layer 160, the step of forming a first electrode 170 and a second electrode 180 is further included. The first electrode 170 is electrically contacted with the first doped silicon layer 120, and the second electrode 180 is electrically contacted with the second doped silicon layer 140.

[0129] As a further example of this embodiment, the step of forming the first electrode 170 includes: printing aluminum paste on the first doped silicon layer 120 and sintering it to form the first electrode 170.

[0130] As a further example of this embodiment, the step of forming the second electrode 180 includes: printing silver paste on the second doped silicon layer 140 and sintering it to form the second electrode 180.

[0131] It is understood that, through the above steps S1 to S5, the method for preparing the solar cell disclosed herein can be completed, and a solar cell can be prepared.

[0132] Furthermore, this disclosure also provides a solar cell that can be fabricated by the above-described method, and the cross-sectional structure of the solar cell is shown in Figure 10. Referring to Figure 10, the solar cell includes a semiconductor substrate 100, a first tunneling layer 110, a second tunneling layer 130, a first doped silicon layer 120, and a second doped silicon layer 140. The first tunneling layer 110 and the first doped silicon layer 120 are sequentially stacked on the back side of the semiconductor substrate 100, and the second tunneling layer 130 and the second doped silicon layer 140 are also sequentially stacked on the back side of the semiconductor substrate 100. The first doped silicon layer 120 includes a doped region 121 and an undoped region 122. The undoped region 122 is disposed on both sides of the doped region 121, and the doped region 121 and the second doped silicon layer 140 are separated by the undoped region 122 to avoid short-circuiting between the doped region 121 and the second doped silicon layer 140. The doped region 121 of the first doped silicon layer 120 contains a doping element, and the undoped region 122 of the first doped silicon layer 120 does not contain a doping element or the doping concentration of the doping element is less than 1×10⁻⁶. 18 .

[0133] As an example of this embodiment, the second tunneling layer also extends between the first doped silicon layer and the second doped silicon layer, and spaced between the first doped silicon layer and the second doped silicon layer.

[0134] It should be noted that this application is not limited to the above-described embodiments. The above embodiments are merely examples, and any embodiments with the same structure and effect as the technical concept within the scope of this application are included in the technical scope of this application. Furthermore, various modifications that can be conceived by those skilled in the art to the embodiments, and other ways of constructing by combining some of the constituent elements of the embodiments, without departing from the spirit of this application, are also included in the scope of this application.

Claims

1. A method for fabricating a solar cell, characterized in that, Includes the following steps: Provide semiconductor substrates; A first passivation structure is formed on the back side of the semiconductor substrate, the first passivation structure comprising a first tunneling layer and a first intrinsic silicon layer stacked sequentially. The first passivation structure is patterned to form a groove that exposes the semiconductor substrate; A second passivation structure is formed on the semiconductor substrate exposed from the groove, the second passivation structure comprising a second tunneling layer and a second doped silicon layer sequentially stacked; and, A doping source paste is formed on the first intrinsic silicon layer, and the first intrinsic silicon layer is doped by irradiating it with a laser to form a first doped silicon layer having doped and undoped regions. The undoped regions are disposed on both sides of the doped regions, and the doped regions and the second doped silicon layer are separated by the undoped regions.

2. The method for preparing a solar cell according to claim 1, characterized in that, The steps for patterning the first passivation structure include: A protective layer is formed on the surface of the first passivated structure; The protective layer is patterned using laser etching; and, The first passivation structure exposed from the protective layer is removed using a first etching solution containing alkali to form the groove.

3. The method for preparing a solar cell according to claim 2, characterized in that, The steps to form the second passivation structure include: The semiconductor substrate is placed in the deposition chamber of a chemical vapor deposition apparatus, and a second tunneling layer and a second intrinsic silicon layer are sequentially deposited on the back side of the semiconductor substrate. The second tunneling layer extends and is deposited on the sidewall and top wall of the first intrinsic silicon layer. The semiconductor substrate is placed in a diffusion chamber, a reactive gas containing a doped source is introduced into the diffusion chamber, and a doped precursor material is deposited on the surface of the second intrinsic silicon layer; and... Annealing is performed to allow the doping element in the doped precursor material to diffuse into the second intrinsic silicon layer, forming the second doped silicon layer and a doped oxide layer located on the second doped silicon layer.

4. The method for preparing a solar cell according to claim 3, characterized in that, The second passivation structure and the doped oxide layer further extend onto the protective layer; before forming the doped source paste on the first intrinsic silicon layer, the following steps are also included: The doped oxide layer on the protective layer is selectively removed by laser etching. The second passivation structure located on the protective layer is selectively removed using a second etching solution containing alkali; and, The front side of the semiconductor substrate is texturized.

5. The method for preparing a solar cell according to any one of claims 1 to 4, characterized in that, The steps for forming the first passivation structure include: The semiconductor substrate is placed in the deposition chamber of a chemical vapor deposition apparatus, and a first tunneling layer and a first intrinsic silicon layer are sequentially deposited on the back side of the semiconductor substrate.

6. The method for preparing a solar cell according to any one of claims 1 to 5, characterized in that, The doping type of the semiconductor substrate is the same as that of the second doped silicon layer, and the doping type of the semiconductor substrate is different from that of the first doped silicon layer.

7. The method for preparing a solar cell according to any one of claims 1 to 6, characterized in that, The doped source slurry comprises a boron-containing compound, and the solid content of the doped source slurry is 20% to 55%.

8. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that, The viscosity of the doped source slurry is 20 Pa·s to 50 Pa·s.

9. The method for preparing a solar cell according to any one of claims 1 to 8, characterized in that, In the step of forming the doped source paste, the region where the doped source paste is located is spaced apart from the edge of the first intrinsic silicon layer.

10. The method for preparing a solar cell according to any one of claims 1 to 9, characterized in that, The linewidth of the region where the doped source slurry is located is 400 μm to 500 μm.

11. The method for preparing a solar cell according to any one of claims 1 to 10, characterized in that, In the step of doping the first intrinsic silicon layer by irradiating it with a laser, the power of the laser used is 30W to 60W, and the scanning width of the laser used is 300μm to 600μm.

12. A solar cell, characterized in that, The solar cell includes a semiconductor substrate, a first tunneling layer, a second tunneling layer, a first doped silicon layer, and a second doped silicon layer; The first tunneling layer and the first doped silicon layer are stacked sequentially on the back side of the semiconductor substrate, and the second tunneling layer and the second doped silicon layer are stacked sequentially on the back side of the semiconductor substrate; the first doped silicon layer includes a doped region and an undoped region, the undoped region is disposed on both sides of the doped region, and the doped region and the second doped silicon layer are separated by the undoped region.

13. The solar cell according to claim 12, characterized in that, The doped regions of the first doped silicon layer contain doping elements, while the undoped regions of the first doped silicon layer do not contain doping elements or the doping concentration of the doping elements is less than 1 × 10⁻⁶. 18 .

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