Gate driving circuit and display apparatus

Abstract

The present invention relates to the field of display apparatuses. Provided are a gate driving circuit and a display apparatus. The gate driving circuit is configured with cascaded shift register units, and each shift register unit comprises eight transistors, two capacitors, a signal input end, a signal output end and three timing control ends, wherein a first transistor is of a double-gate structure. In the present invention, a plurality of transistors are respectively controlled by using multiple timing control signals, thereby realizing precise control over a gate signal. A dual-gate transistor in a shift register unit can flexibly respond to changes in a timing control signal and an input signal, thereby precisely switching signal transmission paths at different moments to ensure the accurate timing of gate driving. The gate driving circuit can operate stably in a high-resolution display apparatus, thereby ensuring the normal turn-on and turn-off of transistors, effectively improving the transmission efficiency and timing stability of a gate signal, and finally achieving a higher image display quality.

Description

Gate driving circuit and display device

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 2024115348270, filed on October 30, 2024, entitled “Gate Driving Circuit and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of display devices, and more specifically, to a gate driving circuit and a display device. Background Technology

[0004] With advancements in display technology, various flat panel displays, such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs), have gradually replaced traditional cathode ray tube displays and become the mainstream display devices due to their smaller weight and size, faster response times, and lower power consumption. OLED displays, in particular, rely on organic light-emitting diodes to emit light through the recombination of electrons and holes, resulting in superior display performance. A typical OLED display uses transistors within pixels to supply current to the OLED light-emitting devices, thereby enabling image display.

[0005] In these displays, the gate drive circuit plays a crucial role in controlling the on and off states of thin-film transistors (TFTs), ensuring that pixels operate according to a predetermined timing sequence. Traditional gate drive circuits typically employ step-by-step control via shift registers. However, current technologies still have shortcomings in the transmission of timing control signals, the flexibility of timing control, and the stability of the circuit, easily leading to insufficient timing accuracy of the gate signal and consequently affecting display performance. Therefore, there is an urgent need for an improved gate drive circuit that can effectively solve problems such as inaccurate timing control and unstable switching of timing control signals to ensure efficient driving and stable operation of the display.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] In view of this, the present invention provides a gate driving circuit and a display device. By employing a cascaded shift register unit structure and combining it with multi-timing control signal driving, the present invention solves the problems of inaccurate timing control and unstable signal switching existing in the prior art gate driving circuit. By optimizing the transistor layout and signal path, the present invention aims to improve the timing control signal transmission efficiency and signal switching stability of the gate driving circuit, thereby improving the driving effect of the display device under high resolution conditions and increasing the response speed and reliability of the display.

[0008] One aspect of the present invention provides a gate driving circuit configured with cascaded shift register units, the shift register units comprising:

[0009] The first transistor has a dual-gate structure and is used to switch the current path between the input voltage signal and the first reference voltage terminal in response to the voltage signal of the third timing control signal.

[0010] The second transistor is used to switch the current path between the positive voltage signal and the third transistor in response to the voltage signal of the second timing control signal.

[0011] The third transistor is used to switch the current path between the second transistor and the first reference voltage terminal in response to the voltage signal of the first node.

[0012] The fourth transistor is used to switch the current path between the second reference voltage terminal and the first node in response to the voltage signal of the input voltage signal.

[0013] The fifth transistor is used to switch the current path between the negative voltage signal and the first node in response to the voltage signal of the first timing control signal;

[0014] The sixth transistor is used to switch the current path between the first reference voltage terminal and the second node in response to a negative voltage signal;

[0015] The seventh transistor is used to switch the current path between the positive voltage signal and the output voltage signal in response to the voltage signal of the first node;

[0016] The eighth transistor is used to switch the current path between the second timing control signal and the output voltage signal in response to the voltage signal of the second node;

[0017] The first capacitor is coupled between the positive voltage signal and the first node;

[0018] The second capacitor is coupled between the second node and the output voltage signal.

[0019] In some embodiments, the second reference voltage terminal is connected to a positive voltage signal.

[0020] In some embodiments, the second reference voltage terminal is connected to either the first timing control signal or the second timing control signal.

[0021] In some embodiments, the first transistor switches the current path between the input voltage signal and the sixth transistor;

[0022] The sixth transistor switches the current path between the first transistor and the second node;

[0023] The third transistor switches the current path between the second transistor and the second node.

[0024] In some embodiments, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all N-type thin-film transistors.

[0025] In some embodiments, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all P-type thin-film transistors.

[0026] In some embodiments, the input voltage signal of the first-stage shift register unit is a pulse signal, and the input voltage signals of the remaining shift register units are the output voltage signals of the previous-stage shift register unit.

[0027] In some embodiments, the duty cycle of the first timing control signal, the duty cycle of the second timing control signal, and the duty cycle of the third timing control signal are all no greater than 1 / 3.

[0028] In some embodiments, the first timing control signal, the second timing control signal, and the third timing control signal are all square wave signals with the same output frequency, and are arranged sequentially in time.

[0029] Another aspect of the present invention provides a display device including the gate driving circuit described above.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention.

[0031] This invention achieves precise control of the gate signal by employing multiple timing control signals, such as a first timing control signal, a second timing control signal, and a third timing control signal, to control multiple transistors respectively. The dual-gate transistor within the shift register unit can flexibly respond to changes in the third timing control signal and the input signal, thereby precisely switching the signal transmission path at different times and ensuring accurate gate driving timing. By combining the first and second capacitors to adjust the voltage of the first and second nodes, the circuit's voltage regulation capability is further enhanced, reducing the impact of voltage fluctuations on signal transmission. This gate driving circuit can operate stably in high-resolution display devices, ensuring the normal conduction and turn-off of the transistors, effectively improving the gate signal transmission efficiency and timing stability, and ultimately achieving higher image display quality. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0033] Figure 1 shows a cascaded schematic diagram of the gate drive circuit of the present invention;

[0034] Figure 2 shows a circuit diagram of the shift register unit according to the first embodiment of the present invention;

[0035] Figure 3 shows the waveform diagram of the shift register unit of the first embodiment of the present invention during operation;

[0036] Figure 4a is a schematic diagram of the conduction state of the shift register unit under the first timing of the first embodiment of the present invention.

[0037] Figure 4b is a timing diagram of the shift register unit of the first embodiment of the present invention under the first timing condition;

[0038] Figure 5a is a schematic diagram of the conduction state of the shift register unit under the second timing of the first embodiment of the present invention;

[0039] Figure 5b is a timing diagram of the shift register unit of the first embodiment of the present invention under the second timing;

[0040] Figure 6a is a schematic diagram of the conduction state of the shift register unit under the third timing according to the first embodiment of the present invention;

[0041] Figure 6b is a timing diagram of the shift register unit of the first embodiment of the present invention under the third timing.

[0042] Figure 7a is a schematic diagram of the conduction state of the shift register unit under the fourth timing according to the first embodiment of the present invention;

[0043] Figure 7b is a timing diagram of the shift register unit of the first embodiment of the present invention under the fourth timing.

[0044] Figure 8a is a schematic diagram of the conduction state of the shift register unit under the fifth timing according to the first embodiment of the present invention;

[0045] Figure 8b is a timing diagram of the shift register unit of the first embodiment of the present invention under the fifth timing.

[0046] Figure 9a is a schematic diagram of the conduction state of the shift register unit under the sixth timing of the first embodiment of the present invention;

[0047] Figure 9b is a timing diagram of the shift register unit of the first embodiment of the present invention under the sixth timing condition;

[0048] Figure 10 shows a circuit diagram of the shift register unit according to the second embodiment of the present invention;

[0049] Figure 11 shows a circuit diagram of the shift register unit according to the third embodiment of the present invention. Detailed Implementation

[0050] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand the other advantages and effects of this application from the content disclosed herein. This application can also be implemented or applied to systems through other different specific embodiments, and various details in this application can also be modified or changed according to different viewpoints and application systems without departing from the spirit of this application.

[0051] In the representation of this application, the reference to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., means that a specific feature, structure, material, or characteristic represented in connection with that embodiment or example is included in at least one embodiment or example of this application. The specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples, and, without conflict, the embodiments and features of this application may be combined and integrated with each other.

[0052] Furthermore, the terms "first" and "second" are used only to distinguish different components or features and should not be construed as indicating or implying their relative importance, or implicitly indicating the number of the technical features. A feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Although the terms "first," "second," etc., are used in some instances to refer to various components, these terms should not limit the components themselves, but are only used to distinguish one component from another. For example, "first interface" and "second interface" are only used to distinguish different interfaces.

[0053] In the representation of this application, "multiple" should be understood as two or more, unless otherwise expressly specified. Furthermore, the singular forms used herein, such as "a," "an," and "the," should also include the plural forms, unless the context indicates otherwise.

[0054] To clearly illustrate this application, devices unrelated to the description are omitted, and the same or similar constituent elements throughout the specification are given the same reference numerals.

[0055] Throughout this specification, when referring to a device being "connected" to another device, this includes both "direct connection" and "indirect connection" where other components are inserted in between. Furthermore, when a device is said to "comprise" a certain constituent element, unless specifically stated otherwise, the presence of other constituent elements is not excluded; rather, it means that other constituent elements may also be included. The terms "comprising" and "including" are used to indicate the presence of features, steps, operations, components, items, types, etc., and do not exclude the presence or addition of other features, steps, operations, components, items, types, etc. The use of "or" and "and / or" should be understood as inclusive, indicating any one or any combination, such as "A, B, or C" meaning "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions only apply when certain combinations are mutually exclusive under certain circumstances. Moreover, the technical terms used herein are only for describing specific embodiments and are not intended to limit this application; the singular form should include the plural form unless there is an explicit contrary meaning. The term "includes" indicates the specification of a particular feature, region, step, etc., but does not exclude the presence or addition of other features, regions, steps.

[0056] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the content of this present application, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0057] This invention provides a solution to the problems existing in the prior art. Figure 1 is a schematic diagram of the cascaded gate drive circuit according to an embodiment of the present invention. Figure 1 uses five cascaded shift register units as an example. The signal input terminal IN of the first-stage shift register unit G1 receives the start pulse signal STV as the input signal. The signal output terminal Gout of the first-stage shift register unit G1 outputs a light-emitting drive signal as the input signal of the second-stage shift register unit G2. The signal output terminal Gout of the first-stage shift register unit G1 is connected to the signal input terminal IN of the second-stage shift register unit G2. The signal output terminal Gout of the second-stage shift register unit G2 outputs a light-emitting drive signal as the input signal of the third-stage shift register unit G3. The signal output terminal Gout of the second-stage shift register unit G2 is connected to the signal input terminal IN of the third-stage shift register unit G3. The signal output terminal Gout of the third-stage shift register unit G3 outputs a light-emitting drive signal as the input signal of the fourth-stage shift register unit G4. The signal output terminal Gout of the third-stage shift register unit G3 is connected to the signal input terminal IN of the fourth-stage shift register unit G4. The signal output terminal Gout of the fourth-stage shift register unit G4 outputs a light-emitting drive signal as the input signal of the fifth-stage shift register unit G5. The signal output terminal Gout of the fourth-stage shift register unit G4 is connected to the signal input terminal IN of the fifth-stage shift register unit G5… This process is repeated for subsequent shift register units, forming a gate drive circuit. In the first-stage shift register unit, the first timing control terminal CKV1 is connected to the first timing control signal line CLK1 to receive the first timing control signal. The second timing control terminal CKV2 is connected to the second timing control signal line CLK2 to receive the second timing control signal. The third timing control terminal CKV3 is connected to the third timing control signal line CLK3 to receive the third timing control signal. In the second-stage shift register unit, the first timing control terminal CKV1 is connected to the third timing control signal line CLK3 to receive the third timing control signal. The second timing control terminal CKV2 is connected to the first timing control signal line CLK1 to receive the first timing control signal. The third timing control terminal CKV3 is connected to the second timing control signal line CLK2 to receive the second timing control signal. In the third-stage shift register unit, the first timing control terminal CKV1 is connected to the second timing control signal line CLK2 to receive the second timing control signal. The second timing control terminal CKV2 is connected to the third timing control signal line CLK3 to receive the third timing control signal. The third timing control terminal CKV3 is connected to the first timing control signal line CLK1 to receive the first timing control signal. In the fourth-stage shift register unit, the first timing control terminal CKV1 is connected to the first timing control signal line CLK1 to receive the first timing control signal.The second timing control terminal CKV2 is connected to the second timing control signal line CLK2 to receive the second timing control signal. The third timing control terminal CKV3 is connected to the third timing control signal line CLK3 to receive the third timing control signal. In the fifth-stage shift register unit, the first timing control terminal CKV1 is connected to the third timing control signal line CLK3 to receive the third timing control signal. The second timing control terminal CKV2 is connected to the first timing control signal line CLK1 to receive the first timing control signal. The third timing control terminal CKV3 is connected to the second timing control signal line CLK2 to receive the second timing control signal. ...and so on, resulting in a cyclical connection of the timing control terminals to the timing control signal lines for each of the three shift register units, used to receive timing control signals.

[0058] Figure 2 is a circuit diagram of the shift register unit of the first embodiment of the present invention. Figure 3 is a waveform diagram of the shift register unit of the first embodiment of the present invention during operation. As shown in Figures 2 and 3, the gate drive circuit of the first embodiment of the present invention is configured with cascaded shift register units, which include: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first transistor M1 has a dual-gate structure, including transistor unit M1_a and transistor unit M1_b, and is used to switch the current path between the input voltage signal IN and the first reference voltage terminal in response to the voltage signal of the third timing control signal received by the third timing control terminal CKV3. The second transistor M2 is used to switch the current path between the positive voltage signal VDD and the third transistor M3 in response to the voltage signal of the second timing control signal received by the second timing control terminal CKV2. The third transistor M3 is used to switch the current path between the second transistor M2 and the first reference voltage terminal in response to the voltage signal of the first node N1. The fourth transistor M4 is used to switch the current path between the second reference voltage terminal and the first node N1 in response to the voltage signal of the input voltage signal IN. The fifth transistor M5 is used to switch the current path between the negative voltage signal VEE and the first node N1 in response to the voltage signal of the first timing control signal received by the first timing control terminal CKV1. The sixth transistor M6 is used to switch the current path between the first reference voltage terminal and the second node N2 in response to the negative voltage signal VEE. The seventh transistor M7 is used to switch the current path between the positive voltage signal VDD and the output voltage signal Gout in response to the voltage signal of the first node N1. The eighth transistor M8 is used to switch the current path between the second timing control signal received by the second timing control terminal CKV2 and the output voltage signal Gout in response to the voltage signal of the second node N2. The first capacitor C1 is coupled between the positive voltage signal VDD and the first node N1. The second capacitor C2 is coupled between the second node N2 and the output voltage signal Gout.

[0059] In some alternative embodiments, as shown in FIG2, the first reference voltage terminal is the third node N3.

[0060] In some alternative embodiments, the second reference voltage terminal is connected to a positive voltage signal VDD, but this is not a limitation.

[0061] In some alternative embodiments, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all N-type thin-film transistors, but are not limited thereto.

[0062] In some optional embodiments, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all P-type thin-film transistors. The P-type thin-film transistor has a low on-state and a high off-state. The circuit diagram does not show the circuit connection scheme of the P-type thin-film transistors, but it is understood that by replacing the N-type thin-film transistors in the shift register unit shown in Figure 2 with P-type thin-film transistors, those skilled in the art can easily deduce the need for adaptive adjustments to the high and low voltage levels of other signals in the circuit, which will not be elaborated upon here.

[0063] In some optional embodiments, the input voltage signal IN of the first-stage shift register unit is the pulse signal STV, and the input voltage signal IN of the other shift register units is the output voltage signal Gout of the previous-stage shift register unit, but this is not a limitation.

[0064] In some optional embodiments, the duty cycle of the first timing control signal received by the first timing control terminal CKV1, the duty cycle of the second timing control signal received by the second timing control terminal CKV2, and the duty cycle of the third timing control signal received by the third timing control terminal CKV3 are all no greater than 1 / 3, but are not limited thereto. In this embodiment, the duty cycle is the ratio of the high-level time to the period time.

[0065] In some optional embodiments, the first timing control signal, the second timing control signal, and the third timing control signal are all square wave signals with the same output frequency and are arranged sequentially in time, but this is not a limitation.

[0066] The working principle of the shift register unit of the present invention under various timing conditions will be specifically described below with reference to Figures 4 to 9.

[0067] Figure 4a is a schematic diagram of the conduction state of the shift register unit under the first timing T1 of the first embodiment of the present invention. Figure 4b is a timing diagram of the shift register unit under the first timing of the first embodiment of the present invention. As shown in Figures 4a and 4b, when the shift register unit of the first embodiment of the present invention is in the first timing, the states of each transistor are as follows: the first transistors M1_a and M1_b of the dual-gate structure, the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 are all turned on, while the second transistor M2, the third transistor M3, the fifth transistor M5, and the seventh transistor M7 are all turned off. Among them, the input voltage signal IN pulse signal STV of the first-stage shift register unit outputs a low level, causing the fourth transistor M4 to turn on, and the positive voltage signal VDD is written into the first node N1, causing the seventh transistor M7 to turn off. The third timing control signal received by the third timing control terminal CKV3 outputs a low level, causing the input voltage signal IN pulse signal STV of the first-stage shift register unit to output a low level and write into the third node N3 and the second node N2, thereby turning on the eighth transistor M8. Finally, the output voltage signal Gout outputs a high potential.

[0068] Figure 5a is a schematic diagram of the conduction state of the shift register unit under the second timing T2 of the first embodiment of the present invention. Figure 5b is a timing diagram of the shift register unit under the second timing of the first embodiment of the present invention. As shown in Figures 5a and 5b, when the shift register unit of the first embodiment of the present invention is in the second timing, the states of each transistor are as follows: the first transistors M1_a and M1_b of the dual-gate structure, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the seventh transistor M7 are all off, while the second transistor M2, the sixth transistor M6, and the eighth transistor M8 are all on. The input voltage signal IN and the pulse signal STV output a high level, causing the fourth transistor M4 to be off, and the first node N1 maintains the high level of the previous moment. The third timing control signal received by the third timing control terminal CKV3 outputs a high level, causing the first transistor M1 to be dual-gate off. The second timing control signal received by the second timing control terminal CKV2 outputs a low level, the second node N2 is low, and finally, the output voltage signal Gout outputs a low potential.

[0069] Figure 6a is a schematic diagram of the conduction state of the shift register unit under the third timing T3 of the first embodiment of the present invention. Figure 6b is a timing diagram of the shift register unit under the third timing of the first embodiment of the present invention. As shown in Figures 6a and 6b, when the shift register unit of the first embodiment of the present invention is in the third timing, the states of each transistor are as follows: the first transistor M1_a and M1_b of the dual-gate structure, the second transistor M2, and the fourth transistor M4 are all off, while the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all on. The input voltage signal IN pulse signal STV outputs a high level, causing the fourth transistor M4 to be off. The second timing control signal received by the second timing control terminal CKV2 outputs a high level, causing the second transistor M2 to be off. The third timing control signal received by the third timing control terminal CKV3 outputs a high level, causing the first transistor M1 to be dual-gate off, and the second node N2 maintains the low level of the previous moment, causing the eighth transistor M8 to be on. The first timing control signal received at the first timing control terminal CKV1 outputs a low level, turning on the fifth transistor M5. The first node N1 is written with a low level, turning on the seventh transistor M7. Finally, the output voltage signal Gout outputs a high level.

[0070] Figure 7a is a schematic diagram of the conduction state of the shift register unit under the fourth timing T4 of the first embodiment of the present invention. Figure 7b is a timing diagram of the shift register unit under the fourth timing of the first embodiment of the present invention. As shown in Figures 7a and 7b, when the shift register unit of the first embodiment of the present invention is in the fourth timing, the states of each transistor are as follows: the first transistors M1_a and M1_b of the dual-gate structure, the third transistor M3, the sixth transistor M6, and the seventh transistor M7 are all turned on, while the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 are all turned off. Specifically, the input voltage signal IN pulse signal STV outputs a high level, causing the fourth transistor M4 to turn off. The second timing control signal received by the second timing control terminal CKV2 outputs a high level, causing the second transistor M2 to turn off. The third timing control signal received by the third timing control terminal CKV3 outputs a low level, causing the first transistors M1_a and M1_b of the dual-gate structure to turn on, and the second node N2 is written with a high level, causing the eighth transistor M8 to turn off. The first timing control signal received at the first timing control terminal CKV1 outputs a high level, causing the fifth transistor M5 to turn off. The first node N1 maintains the low level from the previous moment, causing the seventh transistor M7 to turn on. Finally, the output voltage signal Gout outputs a high potential.

[0071] Figure 8a is a schematic diagram of the conduction state of the shift register unit under the fifth timing T5 of the first embodiment of the present invention. Figure 8b is a timing diagram of the shift register unit under the fifth timing of the first embodiment of the present invention. As shown in Figures 8a and 8b, when the shift register unit of the first embodiment of the present invention is in the fifth timing, the states of each transistor are as follows: the first transistors M1_a and M1_b of the dual-gate structure, the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 are all off, while the second transistor M2, the third transistor M3, the sixth transistor M6, and the seventh transistor M7 are all on. The input voltage signal IN pulse signal STV outputs a high level, causing the fourth transistor M4 to be off. The first timing control signal received by the first timing control terminal CKV1 outputs a high level, causing the fifth transistor M5 to be off. The first node N1 maintains the low level of the previous moment, causing the seventh transistor M7 to be on, and causing the third transistor M3 to be on. The second timing control signal received by the second timing control terminal CKV2 outputs a low level, causing the second transistor M2 to be on. VDD is written to the first node N1, causing the eighth transistor M8 to be off. Finally, the output voltage signal Gout outputs a high potential.

[0072] Figure 9a is a schematic diagram of the conduction state of the shift register unit under the sixth timing T6 of the first embodiment of the present invention. Figure 9b is a timing diagram of the shift register unit under the sixth timing of the first embodiment of the present invention. As shown in Figures 9a and 9b, when the shift register unit of the first embodiment of the present invention is in the sixth timing, the states of each transistor are as follows: the first transistors M1_a and M1_b of the dual-gate structure, the second transistor M2, the fourth transistor M4, and the eighth transistor M8 are all off, while the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all on. Among them, the input voltage signal IN pulse signal STV outputs a high level, causing the fourth transistor M4 to be off. The first timing control signal received by the first timing control terminal CKV1 outputs a low level, causing the fifth transistor M5 to be on. The first node N1 is written with a low level, causing the seventh transistor M7 to be on, and causing the third transistor M3 to be on. The second timing control terminal CKV2 receives a high-level second timing control signal, causing the second transistor M2 to turn off. The third timing control terminal CKV3 receives a high-level third timing control signal, causing the first transistor M1 to turn off. The second node N2 maintains the high level from the previous moment, causing the eighth transistor M8 to turn off. Finally, the output voltage signal Gout outputs a high potential.

[0073] Figure 10 is a circuit diagram of the shift register unit of the second embodiment of the present invention. In the gate drive circuit of the above embodiment, the shift register unit realizes the timing control of line-by-line scanning through the control of multiple transistors. However, since the STV signal of the first embodiment is in a high-level state for a long time, the first node N1 is in a low-level state, which causes the S terminal of the fourth transistor M4 connected to the first node N1 to maintain a high level with the power supply voltage VDD for a long time. This will cause the fourth transistor M4 to bear a large positive voltage stress of Vds and Vgd for a long time, which will have a negative impact on the stability of the transistor and lead to a decrease in the long-term reliability of the device. In order to solve this problem, the present invention proposes an improvement scheme to alleviate the stress problem caused by the fourth transistor M4 bearing positive voltage for a long time, and improve the stability and service life of the circuit. As shown in Figure 10, the present invention also provides a gate drive circuit with cascaded shift register units, wherein the second reference voltage terminal is connected to the first timing control terminal CKV1 or the second timing control terminal CKV2, and the connection relationship of other devices is the same as that of the first embodiment, which will not be repeated here. With this design, the S terminal of the fourth transistor M4 can be connected to the first timing control terminal CKV1 or the second timing control terminal CKV2. The received timing control signals are pulse signals, which can prevent the fourth transistor M4 from being subjected to a large Vds positive voltage for a long time, thereby effectively alleviating the electrical stress problem, reducing the aging phenomenon of the transistor caused by long-term high voltage stress, and improving the device stability and durability of the gate drive circuit.

[0074] Figure 11 is a circuit diagram of the shift register unit according to the third embodiment of the present invention. In the gate drive circuit of the above embodiment, since the pulse signal STV is at a high level in the fourth timing T4, the eighth transistor M8 is in the off state after the signal is written to the second node N2. However, when the timing control signal received by the second timing control terminal CKV2 is pulled low in the fifth timing T5, the thin-film transistor TFT capacitor and parasitic capacitance of the eighth transistor M8 may produce capacitive coupling to the second node N2, causing the potential of the second node N2 to be pulled down. This situation may cause the eighth transistor M8 to conduct, causing the output terminal Gout to be unable to maintain a high level, especially after long-term use or reliability testing, when the characteristics of the TFT device have drifted to a certain extent. To improve this problem, it is necessary to improve the power supply capability to the second node N2, thereby improving the voltage regulation capability of the positive voltage of the second node N2. As shown in Figure 11, this invention also provides a gate driving circuit configured with cascaded shift register units. The first transistor M1 switches the current path between the input voltage signal IN and the sixth transistor M6; the sixth transistor M6 switches the current path between the first transistor M1 and the second node N2; and the third transistor M3 switches the current path between the second transistor M2 and the second node N2. The connection relationships of other devices are the same as in Embodiment 1 and will not be repeated here. With this design, in this embodiment, the drain of the third transistor M3 is connected to the second node N2. When the second transistor M2 is turned on at the fifth timing T5, the third transistor M3 is also turned on. The positive voltage VDD is written to the second node N2 through the second transistor M2 and the third transistor M3, instead of being transmitted through the sixth transistor M6. This improvement reduces the difficulty of writing voltage to the second node N2, effectively improves the voltage regulation capability of the positive voltage at the second node N2, and further enhances the stability and performance of the gate driving circuit.

[0075] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the gate driving circuit described above in the embodiments of the present invention. This display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Implementation of this display device can refer to the embodiments of the gate driving circuit described above; repeated technical solutions and effects will not be described again.

[0076] In summary, the gate driving circuit and display device of the present invention, by providing a new gate driving circuit, effectively solve the problem of transistor stability degradation caused by long-term high voltage stress in the prior art. Specifically, in the shift register unit, a first transistor M1 with a dual-gate structure and an improved capacitive coupling design are adopted, rationally configuring the current paths between each transistor and the node. By connecting the drain of specific transistors to the node and optimizing the coupling between the timing control signal and the reference voltage, the risk of node voltage drift is reduced, significantly improving the voltage regulation capability of the first node N1 and the second node N2. Furthermore, by connecting some transistors to the first timing control terminal CKV1 or the second timing control terminal CKV2 of the timing control signal, the voltage stress problem caused by long-term high-level operation is effectively alleviated, thereby improving the stability and lifespan of the device. Through the above improvements, the gate driving circuit of the present invention can ensure the reliability of the shift register unit during long-term operation and improve the stability of the output signal, especially when driving the display device, effectively avoiding abnormal fluctuations in the output voltage signal Gout. Therefore, this invention not only solves the voltage drift and transistor stress problems in the prior art, but also significantly improves the overall performance and stability of the gate drive circuit, making it suitable for various high-resolution, high-refresh-rate display devices.

[0077] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A gate driving circuit, characterized in that, The system is configured with cascaded shift register units, each shift register unit comprising: The first transistor has a dual-gate structure and is used to switch the current path between the input voltage signal and the first reference voltage terminal in response to the voltage signal of the third timing control signal. The second transistor is used to switch the current path between the positive voltage signal and the third transistor in response to the voltage signal of the second timing control signal. The third transistor is used to switch the current path between the second transistor and the first reference voltage terminal in response to the voltage signal of the first node. The fourth transistor is used to switch the current path between the second reference voltage terminal and the first node in response to the voltage signal of the input voltage signal. The fifth transistor is used to switch the current path between the negative voltage signal and the first node in response to the voltage signal of the first timing control signal; The sixth transistor is used to switch the current path between the first reference voltage terminal and the second node in response to a negative voltage signal; The seventh transistor is used to switch the current path between the positive voltage signal and the output voltage signal in response to the voltage signal of the first node; The eighth transistor is used to switch the current path between the second timing control signal and the output voltage signal in response to the voltage signal of the second node; A first capacitor is coupled between the positive voltage signal and the first node; The second capacitor is coupled between the second node and the output voltage signal.

2. The gate driving circuit according to claim 1, characterized in that, The second reference voltage terminal is connected to the positive voltage signal.

3. The gate driving circuit according to claim 1, characterized in that, The second reference voltage terminal is connected to either the first timing control signal or the second timing control signal.

4. The gate driving circuit according to claim 1, characterized in that, The first transistor is also used to switch the current path between the input voltage signal and the sixth transistor; The sixth transistor is also used to switch the current path between the first transistor and the second node; The third transistor is also used to switch the current path between the second transistor and the second node.

5. The gate driving circuit according to claim 1, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all N-type thin-film transistors.

6. The gate driving circuit according to claim 1, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all P-type thin-film transistors.

7. The gate driving circuit according to claim 1, characterized in that, The input voltage signal of the first-stage shift register unit is a pulse signal, and the input voltage signal of the remaining shift register units is the output voltage signal of the previous-stage shift register unit.

8. The gate driving circuit according to claim 1, characterized in that, The duty cycle of the first timing control signal, the duty cycle of the second timing control signal, and the duty cycle of the third timing control signal are all no greater than 1 / 3.

9. The gate driving circuit according to claim 8, characterized in that, The first timing control signal, the second timing control signal, and the third timing control signal are all square wave signals with the same output frequency, and are arranged sequentially in time.

10. A display device, characterized in that, Includes the gate drive circuit according to any one of claims 1 to 9.

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