Semiconductor structure and method for forming same

Abstract

A semiconductor structure and a method for forming same. The method for forming the semiconductor structure comprises: providing a substrate, wherein the substrate comprises a storage region and a boundary region that are adjacently arranged in sequence; forming an initial conductive layer on the substrate; patterning the initial conductive layer to form a plurality of initial bit line structures and an initial bit line contact layer, wherein the plurality of initial bit line structures extend in a first direction and are arranged at intervals in a second direction; forming an etching mask provided with a plurality of first openings; patterning the initial bit line structures and the initial bit line contact layer by using the etching mask as a mask, to form a plurality of bit line structures and a plurality of bit line contact pads; and forming a bit line isolation structure, wherein the bit line isolation structure comprises first isolation portions located between the bit line structures and second isolation portions located between the bit line contact pads, and a first width of the first isolation portions is greater than a second width of the second isolation portions. The above method for forming the semiconductor structure can improve the reliability of the semiconductor structure.

Description

Semiconductor structure and its formation method

[0001] This application claims priority to Chinese Patent Application No. 202411559807.9, filed on November 4, 2024, entitled "Semiconductor Structure and Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0003] With the development of the electronics industry and the demands of users, electronic devices have been designed to be small in size and high in performance. Therefore, the memory used in electronic devices also requires high integration and high performance.

[0004] To improve memory integration density, the linewidth of semiconductor patterns is gradually decreasing. However, increased integration density can lead to a deterioration in the reliability of semiconductor structures. Furthermore, with the rapid development of the electronics industry, the demand for highly reliable semiconductor structures is growing. Therefore, much research is underway to achieve highly reliable semiconductor structures. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising: providing a substrate, the substrate including sequentially adjacent memory regions and boundary regions, the memory regions including array regions and dummy regions; forming an initial conductive layer on the substrate; patterning the initial conductive layer of the memory regions to form a plurality of initial bit line structures, retaining the initial conductive layer of the boundary regions to form initial bit line contact layers, the plurality of initial bit line structures extending along a first direction and spaced apart along a second direction; forming an etching mask having a plurality of first openings, the plurality of first openings exposing portions of the initial bit line structures of the dummy regions and portions of the initial bit line contact layers of the boundary regions; patterning the initial bit line structures and initial bit line contact layers using the etching mask as a mask to form a plurality of bit line structures and a plurality of bit line contact pads; forming a bit line isolation structure, the bit line isolation structure including a first isolation portion located between the bit line structures and a second isolation portion located between the bit line contact pads, the first width of the first isolation portion being greater than the second width of the second isolation portion.

[0006] In some embodiments, the substrate further includes a peripheral region. When the initial conductive layer of the patterned memory region is used to form a plurality of initial bit line structures, the method further includes: patterning the initial conductive layer of the peripheral region to form a peripheral gate. After the initial conductive layer of the patterned memory region is used to form a plurality of initial bit line structures, the method further includes: forming a peripheral gate protection layer on the sidewall of the peripheral gate and forming a bit line protection layer on the sidewall of the initial bit line structure.

[0007] In some embodiments, the etching mask further includes a second opening that exposes a portion of the peripheral gate in the peripheral region. When the initial bit line structure and the initial bit line contact layer are patterned using the etching mask as a mask, the method further includes: patterning the peripheral gate using the etching mask as a mask to form two opposing peripheral sub-gates, wherein the arrangement direction of the two opposing peripheral sub-gates is the extension direction of the peripheral gate.

[0008] In some embodiments, after the initial conductive layer of the patterned memory region is used to form a plurality of initial bit line structures, the method further includes: forming a peripheral mask that covers a dummy region, a boundary region, and a peripheral region; using the peripheral mask as a mask, removing the bit line protection layer on the substrate of the array region to expose the substrate of the array region; removing the peripheral mask and filling the initial contact layer between the plurality of initial bit line structures.

[0009] In some embodiments, the method further includes: graphically representing an initial contact layer to form node contact layers spaced apart along a first direction, with node spacing grooves between adjacent node contact layers; and filling the node spacing grooves with node isolation structures.

[0010] In some embodiments, the method further includes: removing a portion of the node contact layer to form a node contact structure; forming plug grooves in the boundary region and the peripheral region; and simultaneously forming a contact pad structure above the node contact structure, a bit pad contact structure in the plug groove in the boundary region, and a peripheral contact structure in the plug groove in the peripheral region.

[0011] In some embodiments, the plurality of initial bit line structures include a first initial bit line structure and a second initial bit line structure arranged alternately along a second direction; the dummy region includes a first dummy region and a second dummy region located on both sides of the array region along a first direction; a first opening exposes the portion of the first initial bit line structure located in the first dummy region, and the first opening also exposes the portion of the second initial bit line structure located in the second dummy region; the plurality of bit line structures extend along the first direction and are spaced apart along the second direction, the plurality of bit line structures including a first bit line and a second bit line arranged alternately along the second direction, the first bit line being formed by the portion of the first initial bit line structure located in the array region and the second dummy region, and the second bit line being formed by the portion of the second initial bit line structure located in the array region and the first dummy region.

[0012] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate including a memory region and a boundary region sequentially adjacent to each other, the memory region including an array region and a dummy region; a plurality of bit line structures located in the memory region, the plurality of bit line structures extending along a first direction and spaced apart along a second direction, the plurality of bit line structures including first bit lines and second bit lines alternately arranged along the second direction; a plurality of bit line contact pads located in the boundary region, the plurality of bit line contact pads spaced apart along the second direction, the second bit lines extending to the dummy region and correspondingly connected to the bit line contact pads; and a bit line isolation structure located in the dummy region and the boundary region, the bit line isolation structure including a first isolation portion located between the second bit lines and a second isolation portion located between the bit line contact pads, the first width of the first isolation portion being greater than the second width of the second isolation portion.

[0013] In some embodiments, the dummy region includes a first dummy region and a second dummy region located on both sides of the array region along a first direction, and the boundary region includes a first boundary region and a second boundary region located on both sides of the storage region along a first direction; the first bit line extends to the second dummy region and is connected to the bit line contact pad located in the second boundary region; the second bit line extends to the first dummy region and is connected to the bit line contact pad located in the first boundary region.

[0014] In some embodiments, the substrate further includes a peripheral region, and the semiconductor structure further includes: two opposing peripheral sub-gates located in the peripheral region; a gate isolation structure located between opposing first sidewalls of the two opposing peripheral sub-gates, the gate isolation structure being made of the same material as the bit line isolation structure; and a peripheral gate protection layer located on the second sidewall of the two opposing peripheral sub-gates, the second sidewall being adjacent to the first sidewall, the peripheral gate protection layer being made of a different material than the gate isolation structure.

[0015] In some embodiments, the first width of the first isolation portion is equal to the spacing between adjacent second bit lines.

[0016] In some embodiments, the second width of the second isolation portion is equal to the bit line width of the bit line structure.

[0017] In some embodiments, the semiconductor structure further includes: a plurality of node contact structures located in the array region, the plurality of node contact structures being arranged in an array along a first direction and a second direction.

[0018] In some embodiments, the node contact structure located in the array region is embedded in the substrate and contacts the array active region in the substrate; the second isolation portion located in the dummy region is located on the substrate and is flush with the top surface of the substrate.

[0019] In this embodiment, an etching mask patterning process is used to obtain bit line structures and bit line contact pads to form a bit line isolation structure located in the dummy region and the boundary region. The bit line isolation structure has a first isolation portion located between the bit line structures and a second isolation portion located between the bit line contact pads. The first width of the first isolation portion is greater than the second width of the second isolation portion, which increases the effective area of ​​the bit line contact pads. This improves the alignment of the bit line contact pads and the bit line pad contact structure and avoids short circuits between the bit line pad contact structure and non-corresponding structures in the dummy region caused by alignment deviations, thereby improving the reliability of the semiconductor structure. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment;

[0022] Figures 2A to 11C are top views and cross-sectional views illustrating the formation process of a semiconductor structure according to embodiments of the present disclosure. Figures 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A to 11A are top views of the semiconductor structure, while Figures 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B to 11B and Figures 2C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C to 11C are cross-sectional views of the semiconductor structure.

[0023] Figure 12 is a top view schematic diagram of another semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0024] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0025] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0026] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0027] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0028] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0029] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0030] Taking Dynamic Random Access Memory (DRAM) as an example, DRAM is a type of volatile memory. DRAM typically consists of a memory region composed of memory cells and a peripheral region composed of logic control circuitry. A typical memory cell includes a switching structure (such as a transistor) and a memory structure (such as a capacitor). The logic control circuitry in the peripheral region can address each memory cell in the memory region through multiple word lines and bit lines passing through the memory region, and activate the switching structure to electrically connect with the memory structure to perform data reading, writing, or access. In advanced semiconductor manufacturing, by employing an architecture with embedded word lines, the chip size of DRAM can be significantly reduced. With this architecture, the active regions of the memory cells can be arranged at a denser spacing to achieve higher cell density.

[0031] As semiconductor structures, including logic control circuits and memory cells, shrink to even smaller sizes, the technical challenges of patterning processes are becoming increasingly significant. For example, in today's DRAM, due to the shrinking size of memory cells, it is difficult to establish good electrical contacts between bit lines and logic control circuits. For instance, to form an electrical connection between a bit line and a sense amplifier, structures such as bit line pad contacts are needed to connect the bit lines. Due to the close arrangement of bit lines, the bit line pad contact structure may not be able to effectively contact the corresponding bit line, causing a circuit break. Alternatively, due to alignment misalignment, the bit line pad contact structure may contact non-corresponding structures (such as node contacts, non-corresponding bit lines, etc.), causing a short circuit. Both open circuits and short circuits can lead to data read errors, reducing memory reliability.

[0032] In view of this, in order to solve the above problems, this disclosure provides a method for forming a semiconductor structure.

[0033] Figure 1 is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present disclosure; Figures 2A to 11C are top views and cross-sectional views illustrating a semiconductor structure formation process according to an embodiment of the present disclosure, wherein Figures 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A to 11A are top views of the semiconductor structure, Figures 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B and 11B are cross-sectional views of the semiconductor structure along sections A-A' and B-B' in the top view, and Figures 2C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C and 11C are cross-sectional views of the semiconductor structure along section C-C' in the top view; Figure 12 is a top view of another semiconductor structure according to an embodiment of the present disclosure. The method for forming a semiconductor structure according to the embodiments of this disclosure will be described in detail below with reference to Figures 1-12. It can be understood that in Figures 2A to 11A and Figure 12, the first direction D1, the second direction D2 and the third direction D3 are horizontal directions parallel to the plane where the substrate 110 is located, and the first direction D1 intersects the second direction D2. For example, the first direction D1 may be perpendicular to the second direction D2, and the third direction D3 is a direction that intersects both the first direction D1 and the second direction D2.

[0034] Referring to Figure 1, the method for forming a semiconductor structure includes at least the following steps:

[0035] S101: Provides a substrate, the substrate including sequentially adjacent memory regions and boundary regions, the memory regions including array regions and dummy regions;

[0036] S102: Form an initial conductive layer on the substrate;

[0037] S103: The initial conductive layer of the graphical memory region is used to form multiple initial bit line structures, and the initial conductive layer of the boundary region is retained to form an initial bit line contact layer. The multiple initial bit line structures extend along the first direction and are spaced apart along the second direction.

[0038] S104: Form an etching mask with multiple first openings, the multiple first openings exposing part of the initial bit line structure of the dummy region and part of the initial bit line contact layer of the boundary region;

[0039] S105: Using an etching mask as a mask, pattern the initial bit line structure and the initial bit line contact layer to form multiple bit line structures and multiple bit line contact pads;

[0040] S106: Form a bit line isolation structure, the bit line isolation structure including a first isolation portion located between bit line structures and a second isolation portion between bit line contact pads, the first width of the first isolation portion being greater than the second width of the second isolation portion.

[0041] It should be understood that the steps shown in Figure 1 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in the operation; the order of the steps shown in Figure 1 may be adjusted according to actual needs.

[0042] In the semiconductor structure formation method disclosed herein, firstly, by setting dummy regions and boundary regions to form bit line contact pads located in the boundary regions and bit line structures partially extending into the dummy regions, the arrangement density of bit line contact pads can be reduced, the effective contact area of ​​the bit line contact pads can be increased, and the alignment between the bit line contact pads and the subsequently formed bit line pad contact structures can be improved. Secondly, by etching the initial bit line structure and the initial bit line contact layer in one step using an etching mask with a first opening, the manufacturing process efficiency of the semiconductor structure can be effectively improved, and the electrical connection between the bit line structure and the corresponding bit line contact pad can be ensured. Thirdly, by forming a "convex"-shaped bit line isolation structure, the first isolation portion located between the bit line structures has a larger second width, which can effectively prevent short circuits between the bit line pad contact structure and non-corresponding structures, and the second isolation portion located between the bit line contact pads has a smaller first width, which can increase the space occupied by the bit line contact pads in the boundary regions and improve the process window of the bit line pad contact structure.

[0043] Referring to Figures 2A, 2B, and 2C, where Figure 2B includes cross-sectional views of the semiconductor structure taken along sections A-A' and B-B' in the top view shown in Figure 2A, and Figure 2C is a cross-sectional view of the semiconductor structure taken along section C-C' in the top view shown in Figure 2A. The substrate 110 can be divided into sequentially adjacent memory regions MR, boundary regions BR, and peripheral regions PR, wherein the boundary region BR is located at least one outer side of the memory region MR, and the peripheral region PR is located at least one outer side of the boundary region BR. For example, the boundary region BR surrounds the entire perimeter of the memory region MR, and the peripheral region PR surrounds the entire perimeter of the boundary region BR. The memory region MR can be divided into an array region AR and a dummy region DR located at least one outer side of the array region AR.

[0044] Referring to Figures 2A and 2B, the substrate 110 has an array of active regions 111 and shallow trench isolation structures 112 separating the active regions 111 in the storage region MR. The active regions 111 are arranged in an array along a first direction D1 and a second direction D2, and each active region 111 extends along a third direction D3 in the top view. The shallow trench isolation structure 112 is an integrated structure located in the storage region MR, the boundary region BR, and the peripheral region PR. The shallow trench isolation structures 112 located in different regions can have different depths. For example, the bottom surface of the shallow trench isolation structure 112 located in the peripheral region PR and the boundary region BR can be lower than the bottom surface of the shallow trench isolation structure 112 located in the storage region MR. The peripheral region PR in the substrate 110 is also provided with peripheral active regions 113 separated by the shallow trench isolation structure 112. The active regions 111 can be located in the array region AR and the dummy region DR of the storage region MR, or the active regions 111 can be located only in the array region AR of the storage region MR. The array region AR is the region used to form effective storage cells, and the dummy region DR is the region used to form dummy storage cells. Dummy storage cells refer to storage cells that are not used for actual operation. Dummy storage cells are used to reduce the impact of deviations in actual manufacturing processes.

[0045] The substrate 110 is made of semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. The shallow trench isolation structure 112 is made of one or more insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The shallow trench isolation structure 112 can be a single-layer structure or a multi-layer structure. For example, the shallow trench isolation structure 112 can be a multi-layer structure composed of silicon nitride-silicon oxide-silicon nitride (NON).

[0046] In some embodiments, the substrate 110 further includes a substrate protection layer located on the top surface of the array active region 111 and the shallow trench isolation structure 112. The substrate protection layer and the shallow trench isolation structure 112 are made of the same material.

[0047] Referring to Figures 2A and 2C, buried word lines 120 are also formed in the substrate 110. The buried word lines 120 are formed in the memory region MR, extending along the second direction D2 and spaced apart along the first direction D1, intersecting with the array active regions 111. Each array active region 111 intersects with two buried word lines 120. The buried word lines 120 are formed by forming word line trenches 120T in the substrate 110, and then sequentially forming a gate dielectric layer 121, a gate conductive layer, and a gate capping layer 124 within the word line trenches 120T. The gate conductive layer can be a single-layer structure or a multi-layer structure. For example, the gate conductive layer may include a first gate conductive layer 122 and a second gate conductive layer 123, wherein the work function of the second gate conductive layer 123 is lower than that of the first gate conductive layer 122, which can reduce gate-induced drain leakage current (GIDL). The gate conductive layer can be made of conductive materials including semiconductor materials (e.g., doped polycrystalline silicon), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). In one example, the first gate conductive layer 122 is made of metal, and the second gate conductive layer 123 is made of doped polycrystalline silicon. The gate dielectric layer 121 can be made of silicon oxide, silicon nitride, silicon oxynitride, etc., and can be formed on the bottom and sidewalls of the word line trench 120T using an in-situ steam generation (ISSG) process, or using atomic layer deposition, plasma vapor deposition, or rapid thermal oxidation (RTO) processes. The gate capping layer 124 is made of insulating materials such as silicon nitride and silicon oxynitride.

[0048] Bit line contact plugs 130 are also formed in the substrate 110. The bit line contact plugs 130 can be connected to the array active regions 111 one by one. The bit line contact plugs 130 are located in the middle of the array active regions 111, and the bottom surface of the bit line contact plugs 130 is lower than the top surface of the array active regions 111, while the top surface of the bit line contact plugs 130 can be flush with the top surface of the array active regions 111. The material of the bit line contact plugs 130 may include conductive materials such as doped polysilicon.

[0049] Referring to Figures 2A and 2C, an initial first conductive layer 212L may also be formed on the peripheral region PR of the substrate 110. The initial first conductive layer 212L may be formed simultaneously with the bit line contact plug 130. Before forming the initial first conductive layer 212L and the bit line contact plug 130, a peripheral dielectric layer 211 may be formed on the substrate 110. The material of the peripheral dielectric layer 211 may include high dielectric constant materials and silicon oxide, etc. The high dielectric constant materials are one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0050] Referring to Figures 3A, 3B, and 3C, where Figure 3B includes cross-sectional views of the semiconductor structure taken along sections A-A' and B-B' in the top view shown in Figure 3A, and Figure 3C is a cross-sectional view of the semiconductor structure taken along section C-C' in the top view shown in Figure 3A. An initial conductive layer 141L is formed on the storage region MR, boundary region BR, and peripheral region PR of the substrate 110. The material of the initial conductive layer 141L can be a semiconductor material, a metal, a conductive metal nitride, or a metal-semiconductor compound, etc. The initial conductive layer 141L can be a single-layer structure or a multi-layer structure. For example, the initial conductive layer 141L can be a multi-layer structure composed of a metal-semiconductor compound and a metal. The metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.) can reduce the contact resistance between the metal and the bit line contact plug 130. An initial capping layer 142L can also be formed on the initial conductive layer 141L. The material of the initial capping layer 142L is an insulating material such as silicon nitride.

[0051] Referring to Figures 4A, 4B, and 4C, Figure 4B includes cross-sectional views of the semiconductor structure taken along sections A-A' and B-B' in the top view shown in Figure 4A, and Figure 4C is a cross-sectional view of the semiconductor structure taken along section C-C' in the top view shown in Figure 4A. An initial conductive layer 141L of the patterned memory region MR is used to form multiple initial bit line structures 140a. Each initial bit line structure 140a may include a stacked initial bit line conductive layer 141a and an initial bit line capping layer 142a. The initial bit line conductive layer 141a is patterned from the initial conductive layer 141L, and the initial bit line capping layer 142a is patterned from the initial capping layer 142L. The initial conductive layer 141L and initial capping layer 142L of the boundary region BR are retained to form the initial bit line contact layer 151a and initial contact capping layer 152a. Multiple initial bit line structures 140a extend along a first direction D1 and are spaced apart along a second direction D2. The initial bit line contact layer 151a is connected to the end of the initial bit line conductive layer 141a of each initial bit line structure 140a. Multiple initial bit line structures 140a can be formed using a self-aligned double patterning (SADP) process.

[0052] Referring to Figures 4A and 4C, when the initial conductive layer 141L of the patterned memory region MR is used to form a plurality of initial bit line structures 140a, the method further includes: patterning the initial conductive layer 141L of the peripheral region PR to form a peripheral gate 210a, with the initial bit line contact layer 151a spaced apart from the peripheral gate 210a. The peripheral gate 210a may include a stacked first peripheral gate conductive layer 212, a second peripheral gate conductive layer 213, and a peripheral gate capping layer 214. The first peripheral gate conductive layer 212 is patterned from the initial first conductive layer 212L, the second peripheral gate conductive layer 213 is patterned from the initial conductive layer 141L, and the peripheral gate capping layer 214 is patterned from the initial capping layer 142L.

[0053] In some embodiments, a peripheral gate 210a may correspond to at least two peripheral active regions 113, that is, the projection of a peripheral gate 210a on the substrate 110 may intersect with the projections of at least two peripheral active regions 113 on the substrate 110, and a peripheral gate 210a is used to form at least two peripheral transistors.

[0054] Referring to Figures 5A, 5B, and 5C, where Figure 5B includes cross-sectional views of the semiconductor structure taken along sections A-A' and B-B' in the top view shown in Figure 5A, and Figure 5C is a cross-sectional view of the semiconductor structure taken along section C-C' in the top view shown in Figure 5A. After forming a plurality of initial bit line structures 140a and peripheral gates 210a with the initial conductive layer 141L of the patterned memory region MR, the method further includes: forming a peripheral gate protection layer 210p on the sidewall of the peripheral gate 210a, and forming a bit line protection layer 140p on the sidewall of the initial bit line structure 140a. The peripheral gate protection layer 210p and the bit line protection layer 140p are integrally formed and also cover a portion of the surface of the substrate 110.

[0055] In some embodiments, referring to Figures 5A, 5B, and 5C, after forming the peripheral gate protection layer 210p and the bit line protection layer 140p, the method further includes: forming a peripheral mask M1, which covers the dummy region DR, the boundary region BR, and the peripheral region PR; referring to Figures 6A, 6B, and 6C, wherein Figure 6B includes cross-sectional views of the semiconductor structure taken along sections A-A' and B-B' in the top view shown in Figure 6A, and Figure 6C is a cross-sectional view of the semiconductor structure taken along section C-C' in the top view shown in Figure 6A, using the peripheral mask M1 as a mask, the bit line protection layer 140p on the substrate 110 located in the array region AR is removed to expose the substrate 110 of the array region AR, and then the peripheral mask M1 is removed. The material of the peripheral mask M1 can be photoresist, used to protect the substrate 110 in other regions outside the array region AR. Since the outer mask M1 does not cover the array region AR, an etching process can be used to remove part of the bit line protection layer 140p and part of the substrate 110 between the initial bit line structures 140a on the array region AR to form a recess R. The recess R exposes the end of the array active region 111 in the substrate 110. The etching process includes dry etching or wet etching. Dry etching includes at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-density plasma etching (HDP). A dry etching process can be used to remove the bit line protection layer 140p located on the substrate 110 between the initial bit line structures 140a in the array region AR to expose the substrate 110, and simultaneously remove the bit line protection layer 140p located on top of the initial bit line structures 140a in the array region AR. Then, a wet etching process is used to form the recess R on the surface of the substrate 110. The portion of the initial bit line structure 140a located in the array region AR retains only the bit line protection layer 140p on the sidewalls, while the portion of the initial bit line structure 140a located in the dummy region DR retains the bit line protection layer 140p located on the sidewalls and top.

[0056] Referring to Figures 7A, 7B, and 7C, where Figure 7B includes cross-sectional views of the semiconductor structure taken along sections A-A' and B-B' in the top view shown in Figure 7A, and Figure 7C is a cross-sectional view of the semiconductor structure taken along section C-C' in the top view shown in Figure 7A. After removing the peripheral mask M1, a peripheral isolation layer 220 is filled in the gaps between peripheral gates 210a in the peripheral region PR, and an initial contact layer 160a is filled between the plurality of initial bit line structures 140a. The top surface of the initial contact layer 160a can be controlled to be flush with the initial bit line structure 140a by a planarization process. The material of the initial contact layer 160a includes conductive materials such as semiconductor materials (e.g., doped polysilicon) and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). In the array region AR, the initial contact layer 160a directly contacts the array active region 111 in the substrate 110 exposed by the recess R. The initial contact layer 160a in the array region AR is used to form a node contact structure that electrically connects the array active region 111 and the memory structure. In the dummy region DR, the initial contact layer 160a contacts the bit line protection layer 140p retained on the surface of the substrate 110 but is not electrically connected to the substrate 110. The initial contact layer 160a in the dummy region DR is used to form a dummy node contact structure. A memory structure may not be formed on the dummy region DR, or a memory structure that is not electrically connected to the substrate 110 may be formed. Typically, due to manufacturing process errors in structures such as the array active region 111, poor-performing memory cells are easily formed in the dummy region DR. By setting a dummy node contact structure in the dummy region DR, the impact of poor-performing memory cells on the semiconductor structure can be avoided.

[0057] Referring to Figures 8A, 8B, and 8C, where Figure 8B includes cross-sectional views of the semiconductor structure taken along sections A-A' and B-B' in the top view shown in Figure 8A, and Figure 8C is a cross-sectional view of the semiconductor structure taken along section C-C' in the top view shown in Figure 8A, an etching mask M2 with multiple first openings K1 is formed. The multiple first openings K1 expose a portion of the initial bit line structure 140a in the dummy region DR and a portion of the initial bit line contact layer 151a and initial contact capping layer 152a in the boundary region BR. The first width w1 of the first opening K1 in the dummy region DR is greater than the second width w2 of the first opening K1 in the boundary region BR.

[0058] In some embodiments, the first opening K1 is a U-shaped opening extending from the dummy region DR toward the boundary region BR. It can be formed by a first rectangular opening in the dummy region DR and a second rectangular opening in the boundary region BR, wherein the length of the first rectangular opening along the first direction D1 is greater than or equal to the length of the second rectangular opening along the first direction D1, and the first width w1 of the first rectangular opening along the second direction D2 is greater than the second width w2 of the second rectangular opening along the second direction D2. In some examples, the first width w1 of the portion of the first opening K1 located in the dummy region DR is equal to the spacing between the initial bitline structures 140a, i.e., equal to the width of one initial bitline structure 140a plus the width of two adjacent initial contact layers 160a. The portion of the first opening K1 located in the dummy region DR exposes the initial contact layers 160a located in the dummy region DR. The second width w2 of the portion of the first opening K1 located in the boundary region BR is substantially equal to the width of one initial bitline structure 140a; for example, the ratio of the second width w2 to the width of one initial bitline structure 140a ranges from 0.8 to 1.5.

[0059] Referring to Figures 9A, 9B, and 9C, where Figure 9B includes cross-sectional views of the semiconductor structure taken along sections A-A' and B-B' in the top view shown in Figure 9A, and Figure 9C is a cross-sectional view of the semiconductor structure taken along section C-C' in the top view shown in Figure 9A. The two end faces of the first opening K1 along the first direction D1 are respectively adjacent to the interface between the peripheral region PR and the boundary region BR, and the interface between the dummy region DR and the array region AR. Patterning the initial bit line structure 140a and the initial bit line contact layer 151a using an etching mask M2 includes: etching the initial bit line structure 140a along a first opening K1 to form multiple bit line structures 140, which alternately extend to the dummy region DR; etching the initial bit line contact layer 151a along the first opening K1 to cut it along a first direction D1, forming multiple bit line contact pads 150 spaced apart along a second direction D2; and further including: etching the initial contact layer 160a along the first opening K1 to remove the initial contact layer 160a in the dummy region DR. By removing the initial contact layer 160a in the dummy region DR, short circuits between the bit lines and the memory structure caused by positional misalignment of the subsequently formed bit line pad contact structures can be avoided. By not forming dummy node contact structures, abnormal electrical connections between the dummy node contact structures and the substrate caused by process errors can be avoided, further improving the process window of the bit line pad contact structures.

[0060] In some embodiments, the second opening K2 exposes a portion of the peripheral gate 210a in the peripheral region PR. When patterning the initial bit line structure 140a and the initial bit line contact layer 151a using the etching mask M2 as a mask, the method further includes: patterning the peripheral gate 210a using the etching mask M2 as a mask to form two opposing peripheral sub-gates 210, wherein the arrangement direction of the two opposing peripheral sub-gates 210 is the extension direction of the peripheral gate 210a. The extension direction of the peripheral gate 210a can be a first direction D1 or a second direction D2. In FIG. 9A, the extension direction of the peripheral gate 210a is taken as the first direction D1. The second opening K2 can be used to pattern multiple peripheral gates 210a arranged in parallel, and the extension direction of the second opening K2 is perpendicular to the extension direction of the peripheral gate 210a. For example, peripheral gates 210a extend along a first direction D1. Multiple peripheral gates 210a are etched through a second opening K2 extending along a second direction D2, so that each peripheral gate 210a is patterned into two opposing peripheral sub-gates 210 along the first direction D1. The width of the second opening K2 along the first direction D1 is less than the spacing between the two peripheral active regions 113 intersecting with the peripheral gates 210a. For example, the width of the second opening K2 along the first direction D1 is less than one-third of the spacing between the two peripheral active regions 113 intersecting with the peripheral gates 210a. By using an etching mask M2 with the second opening K2 to pattern the peripheral gates 210a, the end morphology of the peripheral sub-gates 210 can be optimized without increasing mask costs, avoiding the end rounding problem caused by one-step etching. This significantly reduces the spacing between the ends of the opposing peripheral sub-gates 210, thereby significantly improving the peripheral device integration density of the peripheral region PR.

[0061] Referring to Figures 10A, 10B, and 10C, Figure 10B includes cross-sectional views of the semiconductor structure taken along sections A-A' and B-B' in the top view shown in Figure 10A, and Figure 10C is a cross-sectional view of the semiconductor structure taken along section C-C' in the top view shown in Figure 10A. A bitline isolation structure 170 is filled in the space where parts of the initial bitline structure 140a, initial bitline contact layer 151a, and initial contact layer 160a have been removed. The bitline isolation structure 170 includes a first isolation portion 171 located between the bitline structures 140 and a second isolation portion 172 located between the bitline contact pads 150. The first width w1 of the first isolation portion 171 along the second direction D2 is greater than the second width w2 of the second isolation portion 172 along the second direction D2. The size and position of the bitline isolation structure 170 correspond to the size and position of the first opening K1 in the etching mask M2. The first isolation portion 171 fills the space corresponding to the first rectangular opening of the first opening K1, and the second isolation portion 172 fills the space corresponding to the second rectangular opening of the first opening K1. The first isolation portion 171 is used to isolate adjacent bitline structures 140 in the dummy region DR and contacts the bitline protection layer 140p on the sidewall of the bitline structure 140. The second isolation portion 172 is used to isolate adjacent bitline contact pads 150 in the boundary region BR and contacts the sidewall of the bitline contact pads 150.

[0062] In some embodiments, a gate isolation structure 230 is filled in the space where a portion of the peripheral gate 210a and the peripheral isolation layer 220 have been removed. The size and position of the gate isolation structure 230 correspond to the size and position of the second opening K2 in the etching mask M2. The gate isolation structure 230 is used to isolate the opposite ends of two opposing peripheral sub-gates 210 in the peripheral region PR. The gate isolation structure 230 is located between opposing first sidewalls s1 of the two opposing peripheral sub-gates 210. The gate isolation structure 230 and the bit line isolation structure 170 are formed synchronously and are made of the same material. The first sidewall s1 refers to the sidewalls of the two opposing peripheral sub-gates 210 facing each other. A peripheral gate protection layer 210p is located on the second sidewalls s2 of the two opposing peripheral sub-gates 210, and the second sidewall s2 is adjacent to the first sidewall s1. The peripheral gate protection layer 210p may also be located on the opposite sidewalls of the two opposing peripheral sub-gates 210. The peripheral gate protection layer 210p is made of a different material than the gate isolation structure 230. In one example, the peripheral gate protection layer 210p can be a multilayer structure, such as a multilayer structure composed of NON, to protect the sidewall morphology of the peripheral sub-gate 210; the gate isolation structure 230 is a single-layer structure, such as a single-layer structure composed of low dielectric constant materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxynitride, to reduce mutual interference and parasitic capacitance between the relative peripheral sub-gates 210.

[0063] Referring to Figures 11A, 11B, and 11C, where Figure 11B includes cross-sectional views of the semiconductor structure taken along sections A-A' and B-B' in the top view shown in Figure 11A, and Figure 11C is a cross-sectional view of the semiconductor structure taken along section C-C' in the top view shown in Figure 11A. The method for forming the semiconductor structure further includes: patterning an initial contact layer 160a to form node contact layers spaced at intervals along a first direction D1, with node spacing grooves 180T between adjacent node contact layers; and filling the node spacing grooves 180T with node isolation structures 180. A portion of the node contact layer is removed to form a node contact structure 160; plug grooves 311T and 312T are formed in the boundary region BR and the peripheral region PR; simultaneously, a contact pad structure 190 is formed above the node contact structure 160, a bit pad contact structure 311 is formed in the plug groove 311T in the boundary region BR, and a peripheral contact structure 312 is formed in the plug groove 312T in the peripheral region PR.

[0064] In some embodiments, the node contact structures 160 are arranged in a square layout along a first direction D1 and a second direction D2, meaning that the node contact structures 160 arranged along the first direction D1 are substantially aligned in the first direction D1, and the node contact structures 160 arranged along the second direction D2 are substantially aligned in the second direction D2. The contact pad structures 190 are arranged in a hexagonal layout along the first direction D1 and the second direction D2, meaning that each contact pad structure 190 has a substantially consistent distance from its five adjacent contact pad structures 190, and the five adjacent contact pad structures 190 form a regular hexagon. The contact pad structures 190 are used to connect subsequently formed memory structures and to achieve the densest stacking of the memory structures. The materials of the contact pad structures 190 include conductive materials such as metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0065] In some embodiments, an etching process is used to simultaneously form plug grooves 311T and 312T in the boundary region BR and the peripheral region PR, respectively. The plug groove 311T located in the boundary region BR can expose a portion of the surface of the bit line contact pad 150, and the plug groove 312T located in the peripheral region PR can expose a portion of the surface of the peripheral active region 113. The projection of the plug groove 311T located in the boundary region BR onto the substrate is located at the center of the projection of the bit line contact pad 150 onto the substrate, and the projection of the plug groove 312T located in the peripheral region PR onto the substrate is located at the center and both ends of the projection of the peripheral active region 113 onto the substrate.

[0066] In other examples, the plug groove 311T can be formed in the boundary region BR and the plug groove 312T in the peripheral region PR through different steps. For example, after forming the plug groove 312T in the peripheral region PR, a sacrificial layer is filled in the plug groove 312T in the peripheral region PR, then the plug groove 311T is formed in the boundary region BR, and the sacrificial layer filled in the plug groove 312T in the peripheral region PR is removed.

[0067] In some instances, after removing part of the node contact layer to form a node contact structure 160 and forming plug grooves 311T and 312T in the boundary region BR and the peripheral region PR respectively, the contact pad structure 190, bit pad contact structure 311 and peripheral contact structure 312 can be formed simultaneously by one-step deposition, thereby improving manufacturing process efficiency and reducing manufacturing costs.

[0068] Referring to Figures 5A, 6A, 7A, 8A, and 12, the plurality of initial bit line structures 140a include a first initial bit line structure BL1a and a second initial bit line structure BL2a alternately arranged along the second direction D2; the dummy region DR includes a first dummy region DR1 and a second dummy region DR2 located on both sides of the array region AR along the first direction D1; referring to Figures 8A and 12, the first opening K1 exposes the portion of the first initial bit line structure BL1a located in the first dummy region DR1, and the first opening K1 also exposes the portion of the second initial bit line structure BL1a located in the second dummy region DR2; referring to... As shown in Figures 9A and 12, multiple initial bit line structures 140 are obtained by patterning multiple initial bit line structures 140a based on the etching mask M2. These multiple bit line structures 140 extend along a first direction D1 and are spaced apart along a second direction D2. Each bit line structure 140 includes a first bit line BL1 and a second bit line BL2 alternately arranged along the second direction D2. The first bit line BL1 is formed by the portion of the first initial bit line structure BL1a located in the array region AR and the second dummy region DR2. The second bit line BL2 is formed by the portion of the second initial bit line structure BL2a located in the array region AR and the first dummy region DR1. The first bit line BL1 and the second bit line BL2 alternately extend to either the second dummy region DR2 or the first dummy region DR1, thereby reducing the layout density of the bit line structures 140 in the dummy region DR.

[0069] In some embodiments, referring to FIG12, the boundary region BR includes a first boundary region BR1 adjacent to the first dummy region DR1 and a second boundary region BR2 adjacent to the second dummy region DR2. The first boundary region BR1 and the second boundary region BR2 are located on both sides of the storage region MR along the first direction D1. The first bit line BL1 extends to the second dummy region DR2 and is connected one-to-one with the bit line contact pad 150 located in the second boundary region BR2; the second bit line BL2 extends to the first dummy region DR1 and is connected one-to-one with the bit line contact pad 150 located in the first boundary region BR1. The peripheral region PR may include a first peripheral region PR1 adjacent to the first boundary region BR1 and a second peripheral region PR2 adjacent to the second boundary region BR2. The bit line isolation structure 170 located in the first boundary region BR1 and the first dummy region DR1 is sandwiched between adjacent second bit lines BL2, and the bit line isolation structure 170 located in the second boundary region BR2 and the second dummy region DR2 is sandwiched between adjacent first bit lines BL1.

[0070] Based on the above-described method for forming a semiconductor structure, this disclosure also provides a semiconductor structure. Figures 11A, 11B, and 11C are schematic diagrams illustrating a semiconductor structure according to an embodiment of this disclosure.

[0071] Referring to Figures 11A, 11B, and 11C, the semiconductor structure includes: a substrate 110, which includes a memory region MR and a boundary region BR that are sequentially adjacent to each other. The memory region MR includes an array region AR and a dummy region DR; a plurality of bit line structures 140 located in the memory region MR, which extend along a first direction D1 and are spaced apart along a second direction D2. The plurality of bit line structures 140 include a first bit line BL1 and a second bit line BL2 that are alternately arranged along the second direction D2; and a boundary region BR. The system comprises multiple bit line contact pads 150, which are spaced apart along a second direction D2. The second bit line D2 extends to a dummy region DR and is connected to each bit line contact pad 150 in a one-to-one correspondence. A bit line isolation structure 170 is located between the dummy region DR and the boundary region BR. The bit line isolation structure 170 includes a first isolation portion 171 located between the second bit lines BL2 and a second isolation portion 172 located between the bit line contact pads 150. The first width w1 of the first isolation portion 171 is greater than the second width w2 of the second isolation portion 172. The first isolation portion 171 is located between the portions of the second bit line BL2 located in the dummy region DR. The first isolation portion 171 contacts the sidewall of the second bit line BL2 perpendicular to the second direction D2 and also contacts the end face of the second bit line BL2 perpendicular to the first direction D1.

[0072] In some embodiments, the ratio of the width of the bit line contact pad 150 along the second direction D2 to the bit line width of the bit line structure 140 ranges from 3 to 5. That is, the width of the bit line contact pad 150 is at least three times the bit line width to increase the effective contact area of ​​the bit line contact pad 150.

[0073] In some embodiments, the first width w1 of the first isolation portion 171 is substantially equal to the spacing between adjacent second bit lines BL2, or the first width w1 of the first isolation portion 171 is equal to the spacing between the linear structures formed by adjacent first bit lines BL1 and the two side bit line protection layers 140p.

[0074] In some embodiments, the second width w2 of the second isolation portion 172 is substantially equal to the bit line width of the bit line structure 140, or the second width w2 of the second isolation portion 172 is substantially equal to the width of the linear structure formed by the bit line structure 140 and the two side bit line protective layers 140p. For example, the ratio of the second width w2 to the width of an initial bit line structure 140a ranges from 0.8 to 1.5.

[0075] The substrate 110 also includes a peripheral region PR adjacent to the boundary region BR. An array of active regions 111 and shallow trench isolation structures 112 separating the array of active regions 111 are disposed in the memory region MR of the substrate 110. The array of active regions 111 are arranged in an array along a first direction D1 and a second direction D2, and each array of active regions 111 extends along a third direction D3. Buried word lines 120 are also formed in the substrate 110. The buried word lines 120 are formed in the memory region MR, extend along the second direction D2 and are spaced apart along the first direction D1, intersecting with the array of active regions 111. Each array of active regions 111 intersects with two buried word lines 120.

[0076] In some embodiments, referring to FIG12, the dummy region DR includes a first dummy region DR1 and a second dummy region DR2 located on both sides of the array region AR along the first direction, and the boundary region BR includes a first boundary region BR1 and a second boundary region BR2 located on both sides of the storage region MR along the first direction D1; the first bit line BL1 extends to the second dummy region DR2 and is connected to the bit line contact pad 150 located in the second boundary region BR2; the second bit line BL2 extends to the first dummy region DR1 and is connected to the bit line contact pad 150 located in the first boundary region BR1.

[0077] In some embodiments, referring to FIG12, the substrate 110 further includes a peripheral region PR, and the semiconductor structure further includes: two opposing peripheral sub-gates 210 located in the peripheral region PR; a gate isolation structure 230 located between opposing first sidewalls s1 of the two opposing peripheral sub-gates 210, the gate isolation structure 230 being made of the same material as the bit line isolation structure 140p; and a peripheral gate protection layer 210p located on the second sidewalls s2 of the two opposing peripheral sub-gates 230, the second sidewalls s2 being adjacent to the first sidewalls s1, the peripheral gate protection layer 210p being made of a different material than the gate isolation structure 230.

[0078] In some embodiments, referring to Figures 11B and 11C, the semiconductor structure further includes a plurality of node contact structures 160 located in the array region AR, the plurality of node contact structures 160 being arranged in an array along a first direction D1 and a second direction D2. A contact pad structure 190 is also formed above the node contact structures 160, the contact pad structure 190 being used to connect a memory structure, such as a capacitor.

[0079] In some embodiments, referring to Figures 11B and 11C, the node contact structure 160 located in the array region AR is embedded in the substrate 110 and contacts the array active region 111 in the substrate 110; the second isolation portion 172 located in the dummy region DR is located on the substrate 110, and the bottom surface of the second isolation portion 172 is flush with the top surface of the substrate 110.

[0080] In some embodiments, the substrate 110 further includes a substrate protective layer located on the top surface of the array active region 111 and the shallow trench isolation structure 112. A second isolation portion 172 located in the dummy region DR can contact the substrate protective layer but is isolated from the array active region 111. The top surface of the array active region 111 of the substrate 110 in the dummy region DR is flat, while the top surface of the array active region 111 of the substrate 110 in the array region AR has a recess R formed therein for accommodating the node contact structure 160.

[0081] In some embodiments, the semiconductor structure includes a memory, which may be a dynamic random access memory or a memory known in the art, such as a phase change memory or a ferroelectric memory.

[0082] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0083] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate (110) is provided, the substrate including sequentially adjacent memory regions (MR) and boundary regions (BR), the memory regions including array regions (AR) and dummy regions (DR); An initial conductive layer (141L) is formed on the substrate; An initial conductive layer of a graphical storage region is used to form a plurality of initial bit line structures (140a), and an initial conductive layer of a reserved boundary region is used to form an initial bit line contact layer (151a). The plurality of initial bit line structures extend along a first direction (D1) and are spaced apart along a second direction (D2). An etching mask (M2) with multiple first openings (K1) is formed, wherein the multiple first openings expose a portion of the initial bit line structure of the dummy region and a portion of the initial bit line contact layer of the boundary region; The initial bit line structure and the initial bit line contact layer are patterned using the etching mask as a mask to form a plurality of bit line structures (140) and a plurality of bit line contact pads (150); A bit line isolation structure (170) is formed, the bit line isolation structure including a first isolation portion (171) located between the bit line structures and a second isolation portion (172) located between the bit line contact pads, wherein the first width (w1) of the first isolation portion is greater than the second width (w2) of the second isolation portion.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The substrate further includes a peripheral region (PR). When the initial conductive layer of the patterned memory region is used to form a plurality of initial bit line structures, the substrate further includes: the initial conductive layer of the patterned peripheral region is used to form a peripheral gate (210a). After the initial conductive layer of the graphical memory region is formed to create multiple initial bit line structures, the following steps are also included: A peripheral gate protection layer (210p) is formed on the sidewall of the peripheral gate, and a bit line protection layer (140p) is formed on the sidewall of the initial bit line structure.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The etching mask further includes a second opening (K2) that exposes a portion of the peripheral gate in the peripheral region. When patterning the initial bit line structure and the initial bit line contact layer using the etching mask as a mask, the method further includes: The peripheral gate is patterned using the etching mask to form two opposing peripheral sub-gates (210), the arrangement direction of the two opposing peripheral sub-gates being the extension direction of the peripheral gate.

4. The method for forming a semiconductor structure according to claim 2, characterized in that, After the initial conductive layer of the graphical memory region is formed to create multiple initial bit line structures, the following steps are also included: A peripheral mask (M1) is formed, which covers the dummy region, the boundary region, and the peripheral region; Using the peripheral mask as a mask, the bit line protection layer on the substrate located in the array region is removed to expose the substrate of the array region; Remove the peripheral mask and fill the initial contact layer (160a) between the plurality of initial bit line structures.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, Also includes: The initial contact layer is graphically represented to form node contact layers spaced apart along the first direction, with node spacing grooves (180T) between adjacent node contact layers. The node spacing slots are filled with node isolation structures (180).

6. The method for forming a semiconductor structure according to claim 5, characterized in that, Also includes: Remove part of the node contact layer to form a node contact structure (160); Insertion grooves (311T, 312T) are formed in the boundary region and the peripheral region; Simultaneously, a contact pad structure (190) is formed above the node contact structure, a bit pad contact structure (311) is formed in the plug groove (311T) of the boundary region, and a peripheral contact structure (312) is formed in the plug groove (312T) of the peripheral region.

7. The method for forming a semiconductor structure according to any one of claims 1-6, characterized in that, The plurality of initial bit line structures include a first initial bit line structure (BL1a) and a second initial bit line structure (BL2a) arranged alternately along the second direction; the dummy region includes a first dummy region (DR1) and a second dummy region (DR2) located on both sides of the array region along the first direction. The first opening exposes a portion of the first initial bit line structure located in the first dummy region, and the first opening also exposes a portion of the second initial bit line structure located in the second dummy region; The plurality of bit line structures extend along a first direction and are spaced apart along a second direction. The plurality of bit line structures include a first bit line (BL1) and a second bit line (BL2) arranged alternately along the second direction. The first bit line is formed by the portion of the first initial bit line structure located in the array region and the second dummy region, and the second bit line is formed by the portion of the second initial bit line structure located in the array region and the first dummy region.

8. A semiconductor structure, characterized in that, include: A substrate (110) comprising sequentially adjacent memory regions (MR) and boundary regions (BR), wherein the memory regions include array regions (AR) and dummy regions (DR); The storage region contains a plurality of bit line structures (140) that extend along a first direction (D1) and are spaced apart along a second direction (D2). The plurality of bit line structures include a first bit line (BL1) and a second bit line (BL2) that are alternately arranged along the second direction. Multiple bit line contact pads (150) are located in the boundary region. The multiple bit line contact pads are arranged at intervals along the second direction. The second bit line extends to the dummy region and is connected to the bit line contact pads one by one. A bit line isolation structure (170) located in the dummy region and the boundary region, the bit line isolation structure including a first isolation portion (171) located between the second bit lines and a second isolation portion (172) located between the bit line contact pads, wherein the first width (w1) of the first isolation portion is greater than the second width (w2) of the second isolation portion.

9. The semiconductor structure according to claim 8, characterized in that, The virtual region includes a first virtual region (DR1) and a second virtual region (DR2) located on both sides of the array region along the first direction, and the boundary region includes a first boundary region (BR1) and a second boundary region (BR2) located on both sides of the storage region along the first direction. The first bit line extends to the second dummy region and is connected one-to-one with the bit line contact pad located in the second boundary region; The second bit line extends to the first dummy region and is connected one-to-one with the bit line contact pad located in the first boundary region.

10. The semiconductor structure according to claim 8, characterized in that, The substrate further includes a peripheral region (PR), and the semiconductor structure further includes: Two opposing peripheral sub-gates (210) located in the peripheral region; A gate isolation structure (230) is located between the opposing first sidewalls (s1) of the two opposing peripheral sub-gates, the gate isolation structure being made of the same material as the bit line isolation structure; A peripheral gate protection layer (210p) is located on the second sidewall (s2) of the two opposing peripheral sub-gates, the second sidewall being adjacent to the first sidewall, and the peripheral gate protection layer being made of a different material than the gate isolation structure.

11. The semiconductor structure according to any one of claims 8-10, characterized in that, The first width of the first isolation section is equal to the spacing between adjacent second bit lines.

12. The semiconductor structure according to any one of claims 8-10, characterized in that, The second width of the second isolation section is equal to the bit line width of the bit line structure.

13. The semiconductor structure according to any one of claims 8-10, characterized in that, The semiconductor structure also includes: Multiple node contact structures (160) are located in the array region, and the multiple node contact structures are arranged in an array along the first direction and the second direction.

14. The semiconductor structure according to claim 13, characterized in that, The node contact structure located in the array region is embedded in the substrate and contacts the array active region (111) in the substrate; The second isolation portion (172) located in the dummy region is located on the substrate and is flush with the top surface of the substrate.

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