Communication module and switch

Abstract

Disclosed in the present application are a communication module and a switch. The communication module comprises: a TSN switch chip module and a communication interface group, wherein the communication interface group is connected to the TSN switch chip module. A printed circuit of the communication module comprises a top layer, a first power / ground plane layer, a signal layer, a power plane, a second power / ground plane layer and a bottom layer which are arranged in sequence. A TSN switch chip is provided on the top layer; the communication interface is provided on the bottom layer; the TSN switch chip module is used for adjusting the clock frequency of a slave port in real time on the basis of the times at which a master port sends two consecutive synchronization messages and the time when the slave port receives the synchronization messages, so that the slave port resonates consistently with the master port; and the communication interface group is used for connecting to different external devices by means of different types of communication interfaces, so as to realize communication transmission between the TSN switch chip module and each external device.

Description

Communication modules and switches

[0001] This application claims priority to Chinese patent application No. 202411513228.0, filed on October 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a communication module and switch. Background Technology

[0003] With the development of industrial automation and the Internet of Vehicles, people have increasingly higher requirements for communication networks. While TSN technology is currently the next-generation Ethernet standard, existing TSN communication modules still have the following problems: 1. They cannot fundamentally meet the needs of dynamic real-time data transmission, or maintain stable low latency and low jitter under high load; 2. The transmission rate is not high, mostly concentrated on gigabit port communication, and packet loss occurs when using 10 gigabit speeds through the module connector; 3. They cannot simultaneously support multiple different types of interfaces, resulting in incompatibility with devices having different physical interfaces, making the module's application scenarios relatively limited and its versatility poor. Technical issues

[0004] In view of this, embodiments of this application provide a communication module and switch that can achieve real-time, accurate and reliable data transmission. Technical solutions

[0005] In a first aspect, embodiments of this application provide a communication module, including: a TSN switching chip module and a communication interface group, wherein the communication interface group is connected to the TSN switching chip module; wherein, the printed circuit of the communication module includes a top layer, a first power ground layer, a signal layer, a power layer, a second power ground layer and a bottom layer arranged sequentially; the TSN switching chip is disposed on the top layer; the communication interface is disposed on the bottom layer;

[0006] The TSN switching chip module is used to adjust the clock frequency of the slave port in real time according to the time of sending synchronization messages between two adjacent master ports and the time of receiving the synchronization messages by the slave port, so as to make the resonance of the slave port and the master port synchronized.

[0007] The communication interface group is used to connect different external devices through different types of communication interfaces to realize communication transmission between the TSN switching chip module and each of the external devices.

[0008] In some embodiments, the TSN switching chip module is specifically used for:

[0009] The master-slave frequency offset ratio is determined by the ratio of the time difference between two consecutive transmissions of the synchronization message by the master port to the time difference between two consecutive receptions of the synchronization message by the slave port.

[0010] The target clock frequency of the slave port is determined based on the ratio of the clock frequency of the master port to the master-slave frequency offset ratio.

[0011] Adjust the real-time frequency of the slave port to the target clock frequency.

[0012] In some embodiments, the communication module further includes a power management module;

[0013] The power management module is connected to the TSN switching chip module and is used to supply power to the TSN switching chip module and to implement timing control of the TSN switching chip module.

[0014] In some embodiments, the power management module includes a multi-channel DC-DC buck converter circuit and a timing control circuit;

[0015] Each of the DC-DC buck converter circuits is used to provide different operating voltages required in the communication module; each of the DC-DC buck converter circuits is connected to the timing control circuit, which is used to control the enable / disable state of each DC-DC buck converter circuit according to the output sequence of each operating voltage.

[0016] In some embodiments, the timing control circuit includes a first transistor and a second transistor cascaded together; the base of the first transistor is connected to a first voltage through a third resistor and a second resistor connected in series; the collector of the first transistor is connected to a third voltage through a first resistor; the base of the second transistor is connected to a second voltage through a fourth resistor; the collector of the second transistor is connected to the series node of the second resistor and the third resistor; the first voltage is used to power the entire TSN switching chip module;

[0017] The second voltage and the third voltage are used to power the corresponding circuits in the TSN switching chip module.

[0018] In some embodiments, the communication interface includes a first type of communication interface and a second type of communication interface;

[0019] The second type of communication interface is used to connect electrical interface devices, and the connector of the second type of communication interface is connected to the input terminal of the power management module;

[0020] The first type of communication interface is used to connect to optical interface devices.

[0021] In some embodiments, the communication module further includes a high-speed connector; the first type of communication interface communicates with the external device through the high-speed connector;

[0022] The impedance of the high-speed connector is 100 ohms;

[0023] The insertion loss of the high-speed connector is as follows: if the frequency f ≤ 4 GHz, the insertion loss is -0.5 dB; if the frequency is between 4 GHz < f < 8 GHz, the insertion loss is (- (0.25 * f + 0.5)) dB; if the frequency is between 8 GHz ≤ f < 10 GHz, the insertion loss is (- (0.75 * f + 4.5)) dB;

[0024] The crosstalk of the high-speed connector is as follows: if the frequency is less than 8 GHz, the crosstalk level is -32 dB; if the frequency range is 8 GHz < f < 10 GHz, the crosstalk level is -20 dB.

[0025] In some embodiments, the external device includes one or more combinations of a PLC, a sensor, a camera, and a bridge.

[0026] In some embodiments, the first triode and the second triode are NPN transistors.

[0027] In a second aspect, an embodiment of the present application provides a switch, and the switch includes the communication module as described above. Beneficial effects

[0028] In the embodiment of the present application, by adjusting the clock frequency of the slave port according to the time of the master port sending the Sync message twice adjacent and the time of the slave port receiving the Sync message, so that the resonance of the slave port is consistent with that of the master port, and by modifying and processing the timestamps of the incoming TSN data, the accuracy, real-time performance, and stability of data transmission can be achieved, thereby reducing the latency and jitter of data transmission, and further solving the technical problem that the existing standard Ethernet communication module cannot meet the transmission requirements of dynamic real-time data. Further, the communication interfaces of the present application include optical interfaces and electrical interfaces to achieve the versatility of the communication module. Furthermore, in the embodiment of the present application, through the stacked design of the printed circuit, the problem of no packet loss of the 10 Gigabit communication rate through the connector is ensured, meeting the design of the communication module for high-speed communication. Description of the drawings

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 shows a first structural schematic diagram of the communication module according to an embodiment of this application;

[0031] Figure 2 shows a second structural schematic diagram of the communication module according to an embodiment of this application;

[0032] Figure 3 illustrates a flowchart of adjusting the clock frequency of the slave port according to an embodiment of this application;

[0033] Figure 4 shows a schematic diagram of the master and slave port timestamps in an embodiment of this application;

[0034] Figure 5 shows a schematic diagram of the timing control circuit according to an embodiment of this application;

[0035] Figure 6 shows a schematic diagram of the printed circuit stack of the communication module according to an embodiment of this application. Embodiments of the present invention

[0036] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0037] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0038] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0039] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0040] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0041] Traditional Ethernet has limitations in terms of high bandwidth and low latency, especially in multi-node, high real-time network environments. Therefore, most Ethernet networks currently use TSN technology to improve data transmission stability. However, existing communication modules still have shortcomings in terms of integration, high bandwidth, and low latency, mainly reflected in:

[0042] High latency: Traditional Ethernet can only handle static data and is not suitable for dynamic real-time data transmission.

[0043] Low transmission rate: Most modules can only reach gigabit speeds, and packet loss is common at 10 gigabit speeds.

[0044] Limited interface: Existing modules do not support multiple interfaces, limiting application scenarios.

[0045] Based on this, this application proposes a communication module and switch based on a time-sensitive network switching chip. This communication module can achieve high bandwidth and low latency data transmission, ensuring the real-time performance, accuracy and reliability of data transmission. The modular and highly integrated design reduces the need for external components, reduces module complexity and cost design, and can adapt to the ever-changing network scale and different application scenarios.

[0046] The communication module will be described below with reference to some specific embodiments.

[0047] Figure 1 shows a schematic diagram of a communication module according to an embodiment of this application. Exemplarily, the communication module includes: a TSN switching chip module 100 and a communication interface group 200;

[0048] The TSN switching chip module 100 is used to process communication data with external device 300, and adjusts the clock frequency of the slave port in real time according to the time of sending synchronization messages (Sync messages) between two adjacent master ports and the time of receiving synchronization messages from the slave port, so as to make the resonance of the slave port and the master port consistent.

[0049] In some implementations, as shown in FIG2, the TSN switching chip module 100 is used to process communication data with external device 300, including but not limited to data packet scheduling and forwarding. The TSN switching chip module 100 includes but is not limited to TSN switching chip 110, DDR circuit 120, reset circuit 130, storage circuit 140 and crystal oscillator circuit 150.

[0050] The TSN switching chip 110 is the core of the TSN switching chip module 100 and the core of the communication module. It is used to process and transmit time-sensitive data, and to parse, identify and process the sent and received data. After receiving TSN data, it will parse and identify the timestamp, priority, etc. in the TSN data. When forwarding TSN data, it can prioritize forwarding data with higher priority. In addition, before forwarding data, the built-in processor of the TSN switching chip 110 will adjust the clock frequency of the slave port in real time to keep it consistent with the master port resonance, so as to improve the time accuracy of TSN stream data forwarding, thereby reducing latency and ensuring the real-time performance, accuracy and reliability of data transmission.

[0051] As shown in Figure 3, the steps of the TSN switching chip module 100 in this embodiment to adjust the clock frequency of the slave port in real time mainly include:

[0052] Step S100: Determine the master-slave frequency offset ratio based on the ratio of the time difference between two consecutive transmissions of synchronization messages on the master port to the time difference between two consecutive receptions of synchronization messages on the slave port.

[0053] Step S200: Determine the target clock frequency of the slave port based on the ratio of the master port's clock frequency to the master-slave frequency offset ratio.

[0054] Step S300: Adjust the real-time frequency of the port to the target clock frequency.

[0055] As shown in Figure 4, the slave port determines the time of the previous synchronization message sent by the master port based on the received synchronization message, denoted as t1_pred, and records the time it received the synchronization message as t2_pred. These two values ​​are continuously updated as the synchronization process progresses. Then, the slave port records the time it received the current synchronization message sent by the master port as t1, and records the time it received the current synchronization message as t2. Since the link delay is sufficiently stable, the actual time interval between the difference between the timestamps t1_pred and t1 recorded by the master port and the difference between the timestamps t2_pred and t2 recorded by the slave port from the last synchronization to the current synchronization is the same. Therefore, in this embodiment, the master-slave frequency offset ratio can be calculated based on t1_pred, t2_pred, t1, and t2.

[0056] The formula for calculating frequency offset is: rateRatio = (t1 - t1_pred) / (t2 - t2_pred); where rateRatio is the master-slave frequency offset ratio.

[0057] For the master port, its own clock frequency can be obtained from the master real-time clock. Then, based on the obtained master port clock frequency and the master-slave frequency offset ratio, the target clock frequency of the slave port can be determined. The formula for calculating the target clock frequency is: f_slave = f_master / rateRatio, where f_slave is the target clock frequency and f_master is the clock frequency of the master port.

[0058] After calculating the target clock frequency, the clock frequency of the slave port is adjusted to the target clock frequency. In this embodiment, the frequency of the real-time clock is continuously adjusted from the slave port to maintain resonance with the master port, thereby reducing errors caused by PTP protocol anomalies, improving the robustness of PTP clock network time synchronization, and improving the accuracy of master-slave synchronization.

[0059] DDR is a high-speed memory. In the TSN switching chip 110, DDR is mainly used as a high-speed cache memory to quickly store and retrieve data, thereby accelerating data processing. Its connection with the TSN switching chip 110 is reflected in the rapid exchange and processing of data. DDR can provide instant data access when the chip needs it, thereby improving the overall performance of the communication module.

[0060] The reset circuit 130 is a hardware or software logic circuit used to restore the communication module to its initial state when the communication module is started or under a specific error condition. In the TSN switching chip module 100, the reset circuit 130 ensures that all registers and processor states are restored to a predefined initial state when the communication module is started or needs to be reinitialized. This is crucial for ensuring the stable operation of the communication module under various conditions.

[0061] The storage circuit 140 is a Flash circuit. In the TSN switching chip module 100, the Flash circuit is used to store important data such as system startup code, configuration information, and firmware updates. When the communication module starts up, the Flash circuit provides the startup program to the communication module, ensuring that data can be saved even after power failure. Its connection with the TSN chip is to provide the basic environment for the communication module to start up and run.

[0062] The Crystal Oscillator Circuit 150 is a circuit that generates a precise clock signal, which is crucial for any communication module that requires a precise time reference, especially for time-sensitive communication protocols such as TSN. The TSN chip relies on a precise clock signal for accurate data transmission and timestamp processing. The connection between the Crystal Oscillator Circuit 150 and the TSN chip is to provide a stable clock signal to ensure the real-time performance and accuracy of data transmission.

[0063] The DDR, reset circuit 130, storage circuit 140 and crystal oscillator circuit 150 interact with the TSN switching chip 110 through circuit connection and data signal transmission, together forming an efficient and reliable communication module.

[0064] The TSN switching chip module 100 of this application integrates eight gigabit copper PHYs and four SerDes high-speed serializers / deserializers, and can be directly connected to a 10-gigabit optical module. Eight ports (eight gigabit copper PHYs) support 100 / 1000BASE-T, and four ports (four SerDes high-speed serializers) are SerDes interfaces, configurable as SGMII / 100BAS-FX / 1000BASE-X / 2500BASE-X / 5GBASE-R / 10GBASE-R1. The TSN switching chip 110 has a built-in dual-core ARM processor based on the Cortex A55 architecture with a frequency of 1.2GHz. It uses a 256Mb SPI FLASH to load the system boot program and an external 2Gb DDR3 SDRAM for program execution and data storage. The TSN switching chip 110 can be a DX15XX chip.

[0065] The communication module in this embodiment further includes a communication interface group 200, which is connected to the TSN switching chip module 100. This communication interface group is used to connect to different external devices 300 through different types of communication interfaces, and to enable communication transmission between the TSN switching chip module 100 and the external devices 300. The external devices 300 include, but are not limited to, terminal devices such as PLCs, sensors, cameras, and network bridges.

[0066] The communication interface group 200 includes a first type of communication interface 210 and a second type of communication interface 220; the second type of communication interface 220 is used to connect electrical interface devices, and the connector of the second type of communication interface 220 is connected to the input terminal of the power management module 400; the first type of communication interface 210 is used to connect optical interface devices.

[0067] It can be understood that the first type of communication interface 210 is connected to the 4 Serdes ports of the TSN switching chip module 100, providing high-speed data transmission with an external device 300. This interface supports a data transmission rate of at least 10 Gbps for 4 channels and can be externally connected to an SFP+ optical interface device. This communication interface is connected to the external device 300 through a high-speed connector. In this application, in order to ensure the data transmission rate and signal integrity, for the high-speed connector, parameters such as characteristic impedance, insertion loss, and crosstalk need to be strictly controlled. In the embodiment of this application, the impedance of the high-speed connector is 100 ohms; the insertion loss needs to meet the following conditions: if the frequency f ≤ 4 GHz, the insertion loss is -0.5 dB; if the frequency range is 4 GHz < f < 8 GHz, the insertion loss is (-0.25*f + 0.5) dB, that is, from 4 GHz to 8 GHz, the greater the frequency, the greater the insertion loss; if the frequency range is 8 GHz ≤ f < 10 GHz, the insertion loss is (-0.75*f + 4.5) dB, that is, from 8 GHz to 10 GHz, the greater the frequency, the greater the insertion loss; its crosstalk is: if the frequency is less than 8 GHz, the crosstalk level is -32 dB; if the frequency range is 8 GHz < f < 10 GHz, the crosstalk level is -20 dB.

[0068] The second type of communication interface 220 is connected to the 8 ports of the TSN switching chip module 100 that support 100 / 1000BASE-T, providing high-speed data transmission with an external device 300. This interface supports a data transmission rate of at least 1000 Mbps for 8 channels and can be externally connected to an RJ45 electrical interface device. This communication interface is connected to the external device 300 through a European-style connector. In addition, the second type of communication interface 220 also includes some control signals and power input signals, such as GPIO, I2C, RS232, etc., which are responsible for the status monitoring and fault diagnosis of the communication module. In the embodiment of this application, it can interact with the user through a user interface, allowing the user to set parameters and monitor the status of the communication module. These control signals are configured as output or input by the built-in processor of the TSN switching chip module 100 and are connected to the external device 300 through a European-style connector.

[0069] In some embodiments, the communication module of the embodiment of this application further includes a power management module 400. The power management module is connected to the TSN switching chip module 100, used to supply power to the TSN switching chip module 100 and implement timing control of the TSN switching chip module; the power management module includes a multi-channel DC-DC buck conversion circuit and a timing control circuit; each DC-DC buck conversion circuit is used to provide different working voltages required in the communication module.

[0070] By way of example, the TSN switching chip 110, DDR circuit 120, reset circuit 130, storage circuit 140 and crystal oscillator circuit 150 are all provided with a DC-DC buck converter circuit between themselves and the power management module; wherein, the DC-DC buck converter circuit is used to convert the output voltage of the power management module into the corresponding operating voltage of the TSN switching chip 110, DDR, reset circuit 130, storage circuit 140 and crystal oscillator circuit 150.

[0071] It is understood that the power management module 400 is used to provide power management for the entire communication module, including but not limited to voltage conversion and timing control. The input terminal of the power management module 400 is connected to the connector of the second type communication interface 220, and the output terminal is connected to the TSN switching chip module 100. The input voltage of the power management module 400 can be 3.3V, 5V, or 12V. When supplying power to the TSN switching chip 110, DDR, reset circuit 130, storage circuit 140, and crystal oscillator circuit 150, it can convert the voltage to the corresponding operating voltage value through a DC-DC step-down converter circuit according to the needs of the TSN switching chip 110, DDR, reset circuit 130, storage circuit 140, and crystal oscillator circuit 150, respectively, and provide voltage to the power-consuming circuits such as the TSN switching chip 110, DDR, reset circuit 130, storage circuit 140, and crystal oscillator circuit 150. In addition, in this embodiment of the application, a power timing control circuit is connected to each DC-DC buck converter circuit to control the on and off of the enable pin of each DC-DC buck converter circuit, thereby controlling the order of the output voltage of each DC-DC buck converter circuit.

[0072] As an example, as shown in Figure 5, the timing control circuit includes a first transistor Q1 and a second transistor Q2 cascaded together; the base of the first transistor Q1 is connected to a first voltage V1 through a third resistor R3 and a second resistor R2 connected in series; the collector of the first transistor Q1 is connected to a third voltage V3 through a first resistor R1; the base of the second transistor is connected to a second voltage V2 through a fourth resistor; and the collector of the second transistor Q2 is connected to the series node of the second resistor R2 and the third resistor R3.

[0073] The first voltage V1 supplies power to the entire TSN switching module; the second voltage V2 supplies power to the corresponding circuits within the TSN switching module; the third voltage V3 provides power to the DC-DC buck converter circuit; the emitters of the first transistor Q1 and the second transistor Q2 are both grounded. Both the first transistor Q1 and the second transistor Q2 are NPN transistors.

[0074] It can be understood that the first voltage V1 is used to power the entire TSN switching chip module 100, and the second voltage V2 is used to control the power-on of the third voltage V3, thereby controlling the order of the output voltages. Specifically, when the first voltage V1 is powered, it is connected to the base of the first transistor Q1 through the second resistor R2 and the third resistor R3. The emitter of the first transistor Q1 is connected to digital ground, and the collector of the first transistor Q1 is connected to the enable pin of the DC-DC buck converter circuit of the third voltage to be controlled. At this time, the PN junction of the first transistor Q1 is forward biased, the first transistor Q1 is turned on, the enable pin is connected to digital ground, and the voltage of the enable pin is lower than the start-up threshold of the DC-DC buck converter circuit of the third voltage V3, so the third voltage V3 cannot output; when the second voltage V2 is powered... When powered on, the base of the second transistor Q2 is connected through the fourth resistor R4, the emitter of the second transistor Q2 is connected to digital ground, and the collector of the second transistor Q2 is connected to the base of the first transistor Q1 through the third resistor R3, and is connected to the first voltage V1 through the second resistor R2. At this time, the PN junction of the second transistor Q2 is forward biased, and the second transistor Q2 is turned on, which causes the base voltage of the first transistor Q1 to decrease and the first transistor Q1 to turn off. The enable voltage of the third voltage V3 is pulled up, which is higher than the start-up threshold of the DC-DC buck converter circuit, so the third voltage V3 is powered normally.

[0075] This application embodiment ensures that all relevant power supply voltages are provided to different parts of the TSN switching chip module 100 at the appropriate time through power supply timing control. This avoids startup failures or erroneous behavior caused by improper power supply. Furthermore, power supply timing control also helps to enhance the stability of the entire communication module. When the power supply is interrupted or restored, proper timing control can prevent power interference from causing the communication module to crash, protecting data security and the normal operation of the module. In other words, power supply timing control can ensure that the communication module operates stably according to the predetermined working state, improving the reliability and performance of the device.

[0076] In some embodiments, as shown in Figure 6, the printed circuit of the communication module includes a top layer, a first power ground layer, a signal layer, a power layer, a second power ground layer, and a bottom layer arranged sequentially. The TSN switching chip is located on the top layer; the communication interface group is located on the bottom layer; the communication interface group wiring uses differential 100-ohm impedance matching; the power management module 400 is located on either the top or bottom layer. In this embodiment, the printed circuit of the communication module has two power ground layers (a first power ground layer and a second power ground layer). The first power ground layer is located between the top layer and the signal layer, and the second power ground layer is located between the power layer and the bottom layer. The signal layer and the power layer are adjacent, ensuring that each trace layer has a reference ground plane, thereby allowing for better control of the impedance of each trace layer. Both power ground layers can also effectively absorb magnetic field lines. Since each trace layer has an adjacent power ground layer, the power ground layers can provide a better return path for each signal layer (trace layer). Furthermore, to shorten the trace distance from the impedance transformation point to different communication interfaces and ensure signal quality, the four SerDes ports of the TSN switching chip module 100 can be positioned near the data transmission interface.

[0077] The communication module of this application provides a deterministic time-sensitive networking (TSN) technology through the TSN switching chip module 100. By modifying and processing the timestamps of incoming TSN data, the accuracy, real-time performance, and stability of data transmission can be achieved, thereby reducing data transmission latency and jitter. This solves the technical problem that existing standard Ethernet communication modules cannot meet the transmission requirements of dynamic real-time data. Furthermore, the implementation of this application, through the layered design of printed circuits, ensures that 10 Gigabit communication rates do not suffer packet loss through the connector, satisfying the design requirements of high-speed communication modules. Moreover, the communication interface of this application includes both optical and electrical interfaces to achieve the versatility of the communication module.

[0078] In some embodiments, this application also provides a switch, which includes the communication module described above.

[0079] It is understood that the options in the above embodiments also apply to this embodiment, so they will not be described again here.

[0080] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A communication module, wherein, The communication module includes a TSN switching chip module and a communication interface group, wherein the communication interface group is connected to the TSN switching chip module. The printed circuit of the communication module includes a top layer, a first power / ground layer, a signal layer, a power layer, a second power / ground layer, and a bottom layer arranged sequentially; the TSN switching chip is disposed on the top layer; and the communication interface is disposed on the bottom layer. The TSN switching chip module is used to adjust the clock frequency of the slave port in real time according to the time of sending synchronization messages between two adjacent master ports and the time of receiving the synchronization messages by the slave port, so as to make the resonance of the slave port and the master port synchronized. The communication interface group is used to connect different external devices through different types of communication interfaces to realize communication transmission between the TSN switching chip module and each of the external devices.

2. The communication module according to claim 1, wherein, The TSN switching chip module is specifically used for: The master-slave frequency offset ratio is determined by the ratio of the time difference between two consecutive transmissions of the synchronization message by the master port to the time difference between two consecutive receptions of the synchronization message by the slave port. The target clock frequency of the slave port is determined based on the ratio of the clock frequency of the master port to the master-slave frequency offset ratio. Adjust the real-time frequency of the slave port to the target clock frequency.

3. The communication module according to claim 1, wherein, The communication module also includes a power management module; The power management module is connected to the TSN switching chip module and is used to supply power to the TSN switching chip module and to implement timing control of the TSN switching chip module.

4. The communication module according to claim 3, wherein, The power management module includes a multi-channel DC-DC buck converter circuit and a timing control circuit; Each of the DC-DC buck converter circuits is used to provide different operating voltages required in the communication module; each of the DC-DC buck converter circuits is connected to the timing control circuit, which is used to control the enable / disable state of each DC-DC buck converter circuit according to the output sequence of each operating voltage.

5. The communication module according to claim 4, wherein, The timing control circuit includes a first transistor and a second transistor cascaded together; the base of the first transistor is connected to a first voltage through a third resistor and a second resistor connected in series; the collector of the first transistor is connected to a third voltage through a first resistor; the base of the second transistor is connected to a second voltage through a fourth resistor; and the collector of the second transistor is connected to the series node of the second resistor and the third resistor. The first voltage is used to power the entire TSN switching chip module; The second voltage and the third voltage are used to power the corresponding circuits in the TSN switching chip module.

6. The communication module according to claim 3, wherein, The communication interface includes a first type of communication interface and a second type of communication interface; The second type of communication interface is used to connect electrical interface devices, and the connector of the second type of communication interface is connected to the input terminal of the power management module; The first type of communication interface is used to connect to optical interface devices.

7. The communication module according to claim 6, wherein, The communication module further includes a high-speed connector; the first type of communication interface communicates with the external device through the high-speed connector. The impedance of the high-speed connector is 100 ohms; The insertion loss of the high-speed connector is as follows: if the frequency f ≤ 4 GHz, the insertion loss is -0.5 dB; if the frequency is between 4 GHz < f < 8 GHz, the insertion loss is (-0.25*f + 0.5) dB; if the frequency is between 8 GHz ≤ f < 10 GHz, the insertion loss is (-0.75*f + 4.5) dB. The crosstalk of the high-speed connector is as follows: if the frequency is less than 8 GHz, the crosstalk level is -32 dB; if the frequency range is 8 GHz < f < 10 GHz, the crosstalk level is -20 dB.

8. The communication module according to claim 1, wherein, The external device includes one or more combinations of a PLC, a sensor, a camera, and a bridge.

9. The communication module according to claim 5, wherein, The first triode and the second triode are NPN transistors.

10. A switch, wherein, The switch includes the communication module according to any one of claims 1-9.

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