Semiconductor device, semiconductor device preparation method, and electronic device

Abstract

The present application relates to the technical field of semiconductors, and provides a semiconductor device, an electronic device, and a semiconductor device preparation method. The semiconductor device comprises a P-type transistor, the P-type transistor comprises a first electrode, a second electrode, a channel, a gate, and a gate side wall, and the first electrode comprises boron; in addition, the semiconductor device further comprises a first film layer and a dielectric barrier layer, the first film layer is located on the first electrode, the first film layer comprises boron, and the boron content in the first film layer is greater than the boron content in the first electrode; and a surface of a substrate comprises a first region located at the periphery of the first electrode, the first region may correspond to the channel of the P-type transistor, and at least a part of the first region is covered by the dielectric barrier layer. The dielectric barrier layer can be used for inhibiting the boron in the first film layer from diffusing into the channel of the P-type transistor. In this way, the hole mobility of a channel layer can be improved, and a drive circuit of the P-type transistor can be improved.

Description

Semiconductor devices, methods for fabricating semiconductor devices, and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411514075.1, filed on October 28, 2024, entitled "Semiconductor Device, Method for Preparing Semiconductor Device and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, a semiconductor device packaging structure, an electronic device, and a method for fabricating a semiconductor device. Background Technology

[0003] With the development of integrated circuits, for example, embedded source-drain epitaxial silicon germanium is currently a core technology in 45nm and below processes.

[0004] Embedded source / drain epitaxial silicon-germanium can be understood as creating trenches in a substrate and epitaxially growing silicon-germanium inside and outside the trenches to form the source and drain electrodes. This technology utilizes the stress generated by the lattice mismatch between germanium (Ge) and silicon (Si) to improve hole mobility. Since the lattice constant of Ge is about 4% larger than that of Si, it generates lateral compressive stress in the channel, reducing the lattice constant of Si within the channel and decreasing the effective hole mass, thereby achieving the goal of improving hole mobility.

[0005] However, when using this technology to manufacture transistors, some substances diffuse into the transistor's channel, creating a short-channel effect that affects device performance. Summary of the Invention

[0006] This application provides a semiconductor device, a semiconductor device packaging structure, an electronic device including the semiconductor device packaging structure, and a method for fabricating the semiconductor device. The main objective is to suppress the short-channel effect of P-type transistors, improve carrier mobility, and enhance device performance.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] In one aspect, this application provides a semiconductor device, which may include a memory circuit, a logic circuit, or a digital circuit.

[0009] The semiconductor device includes a substrate and a P-type transistor. The P-type transistor includes a first electrode, a second electrode, a channel, a gate, and a gate sidewall. The substrate has the first electrode, the second electrode, and the channel of the P-type transistor. The channel is located between the first electrode and the second electrode. The gate is located on the channel. The gate sidewall is located on the peripheral side of the gate. The first electrode includes boron. In addition, the semiconductor device also includes a first film layer and a dielectric barrier layer. The first film layer is located on the first electrode. The first film layer includes boron, and the boron content in the first film layer is greater than the boron content in the first electrode. The surface of the substrate includes a first region located around the first electrode. The first region can correspond to the channel of the P-type transistor. At least a portion of the first region is covered by the dielectric barrier layer. The dielectric barrier layer is used to suppress the diffusion of boron in the first film layer into the substrate. For example, the dielectric barrier layer is used to suppress the diffusion of boron in the first film layer into the channel of the P-type transistor.

[0010] In the semiconductor device provided in this application, a first film layer with a high boron content is provided on the first electrode of a P-type transistor. This first film layer can reduce the resistance in the circuit and optimize the device performance. However, in some fabrication processes, after the first film layer with a high boron concentration is obtained, the boron in the first film layer may diffuse into the channel of the P-type transistor, resulting in a short-channel effect. This application provides a dielectric barrier layer around the first electrode, that is, the channel surrounding the first electrode is at least partially covered by the dielectric barrier layer. The dielectric barrier layer can suppress the diffusion of boron in the first film layer into the channel. In this way, the short-channel effect can be suppressed, the hole mobility can be improved, and the device performance can be optimized.

[0011] In one possible implementation, the material of the gate sidewall is the same as the material of the dielectric barrier layer; alternatively, the material of the gate sidewall may be different from the material of the dielectric barrier layer.

[0012] For example, the dielectric barrier layer includes at least one of silicon oxide, silicon nitride, silicon dioxide, and silicon carbide.

[0013] For example, the gate sidewall includes at least one of silicon oxide and silicon nitride.

[0014] In one possible implementation, the first pole includes: an embedded portion located in a substrate, and a protruding portion protruding from the surface of the substrate, the first region surrounding the protruding portion; a peripheral side surface of the protruding portion is covered by a dielectric barrier layer; the dielectric barrier layer located on the peripheral side surface of the protruding portion extends to and covers the first region.

[0015] Since the dielectric barrier layer located on the peripheral side of the protrusion extends to a first region on the substrate surface, which corresponds to the channel of the transistor, that is, part of the channel in the substrate is covered by the dielectric barrier layer, the diffusion of high concentrations of boron in the first film layer into the channel can be suppressed.

[0016] In one possible implementation, the peripheral side of the protrusion near the gate sidewall is inclined away from the gate sidewall.

[0017] This allows for the fabrication of the first electrode using epitaxial growth technology, a simple and easily implemented process.

[0018] In one possible implementation, the gate sidewall includes: a first gate sidewall and a second gate sidewall, the first gate sidewall and the second gate sidewall being stacked sequentially on the peripheral side surface of the gate; the peripheral side surface of the dielectric barrier layer is in contact with the second gate sidewall.

[0019] In one example, the materials of the first gate sidewall and the second gate sidewall can be the same or different.

[0020] In some other examples, the materials of the second gate sidewall and the dielectric barrier layer can be the same or different.

[0021] In one possible implementation, the semiconductor device further includes a second film layer; the second film layer is present between the dielectric barrier layer and the first film layer, and the second film layer is present between the first electrode and the first film layer; the first film layer and the first electrode further include silicon; the second film layer includes pure silicon; or; the second film layer includes silicon and boron; wherein the boron content in the second film layer is less than the boron content in the first film layer, and the silicon content in the second film layer is greater than the silicon content in the first film layer; and the boron content in the second film layer is less than the boron content in the first electrode, and the silicon content in the second film layer is greater than the silicon content in the first electrode.

[0022] In some structures, pure silicon is used as the second film layer. The high concentration of silicon can suppress the diffusion of high boron content from the first film layer into the transistor channel. In other structures, a second film layer containing both silicon and boron is used. Because the silicon content in the second film layer is greater than the boron content in the first film layer and the first electrode, and the boron content in the second film layer is less than the boron content in the first film layer and the first electrode, the diffusion of high boron content from the first film layer into the transistor channel can be effectively suppressed.

[0023] In addition, the second film layer can be made using pure silicon or materials containing silicon and boron. The process is easy to implement, compatible with the fabrication process of P-type transistors, does not increase the process steps, and has a relatively low manufacturing cost.

[0024] In one possible implementation, the first electrode further includes silicon and germanium, and the first electrode includes: a stacked first sub-electrode layer and a second sub-electrode layer, the first sub-electrode layer being closer to the channel than the second sub-electrode layer; the germanium content in the second sub-electrode layer being greater than the germanium content in the first sub-electrode layer; and the boron content in the second sub-electrode layer being greater than the boron content in the first sub-electrode layer.

[0025] The first sub-electrode layer can be considered as a buffer layer, and the second sub-electrode layer can be considered as a stress application layer. The stress applied to the channel by the second sub-electrode layer can be increased through the second film layer, thereby further improving the channel carrier mobility and increasing the drive current of the P-type transistor.

[0026] In one possible implementation, the second film layer comprises silicon and boron, wherein the boron content in the second film layer is less than the boron content in the second sub-electrode layer, and the silicon content in the second film layer is greater than the silicon content in the second sub-electrode layer.

[0027] When the second film layer contains silicon and boron, the second film layer can suppress the diffusion of boron from the first film layer into the channel by having a lower boron content in the second sub-electrode layer and a higher silicon content in the second film layer than in the second sub-electrode layer.

[0028] In one feasible manner, the radial dimension of the first pole first increases and then decreases from the bottom to the top surface of the first pole.

[0029] In some feasible processes, trenches can be formed in the substrate, with the radial dimension of the trench first increasing and then decreasing from the bottom surface to the opening direction. Such a trench structure can be called a sigma trench. Filling the sigma trench with a first electrode can cause the germanium-silicon first electrode of the structure to apply stress to the channel.

[0030] Secondly, this application also provides a semiconductor device packaging structure, which includes a substrate and a semiconductor device as described in any of the above implementations, wherein the semiconductor device is disposed on the substrate.

[0031] In the semiconductor device packaging structure provided in this application, at least a portion of the first region surrounding the first electrode of the semiconductor device integrated on the substrate is covered by a dielectric barrier layer, that is, the channel is covered by the dielectric barrier layer. The dielectric barrier layer can suppress the diffusion of boron in the first film layer into the channel, thereby suppressing the short-channel effect, improving hole mobility, optimizing device performance, and improving the performance of the semiconductor device packaging structure.

[0032] Thirdly, this application also provides an electronic device, which includes a circuit board and a semiconductor device packaging structure as described in any of the above implementations, wherein the semiconductor device packaging structure is disposed on the circuit board.

[0033] The electronic device provided in this application includes a semiconductor device in any of the above implementations. By using a dielectric barrier layer, the diffusion of boron in the first film layer into the channel can be suppressed. In this way, the short-channel effect can be suppressed, the hole mobility can be improved, and the device performance can be optimized.

[0034] Fourthly, this application also provides a method for fabricating a semiconductor device, the method comprising:

[0035] Trenches are formed in the electrode region of the substrate, and the electrode region is used to form the first electrode of the P-type transistor;

[0036] The first electrode of a P-type transistor is formed within the trench, and the first electrode includes boron;

[0037] A dielectric barrier layer is formed, wherein at least a portion of the substrate surface and the area surrounding the first electrode is covered by the dielectric barrier layer;

[0038] A first film layer is formed on the first electrode. The first film layer includes boron, and the boron content in the first film layer is greater than the boron content in the first electrode.

[0039] When using this method to fabricate a P-type transistor in a semiconductor device, a dielectric barrier layer is first fabricated before the first film layer containing a high boron content is fabricated, and the corresponding channel region of the substrate is covered by the dielectric barrier layer. In this way, after the first film layer is fabricated, the high boron content in the first film layer will not diffuse into the channel, thus preventing a short-channel effect from occurring in the channel.

[0040] In one feasible approach, the fabrication method further includes, before creating a trench in the electrode region of the substrate used to form the first electrode of the P-type transistor:

[0041] A first mask layer and a second mask layer are formed. The first mask layer includes silicon oxide. The electrode region surface of the substrate is covered by the first mask layer. The second mask layer is located on the side of the first mask layer away from the substrate.

[0042] After creating trenches in the electrode region of the substrate used to form the first electrode of the P-type transistor, the fabrication method further includes:

[0043] The inner wall of the trench is cleaned, and the portion of the first mask layer near the trench is cleaned away, exposing the surface of the substrate near the trench.

[0044] For example, after trenches are created, silicon dioxide will be generated on the inner wall of the trenches due to natural oxidation. Therefore, the silicon dioxide in the trenches needs to be cleaned. During the cleaning process, part of the first mask layer containing the silicon dioxide layer will also be cleaned away.

[0045] In one feasible approach, cleaning the inner wall surface of the trench includes:

[0046] The inner wall of the trench is cleaned with a gas containing ammonia and hydrogen fluoride, which removes the silicon oxide on the inner wall of the trench and the silicon oxide of the first mask layer near the trench.

[0047] In one feasible manner, the dielectric barrier layer is fabricated by:

[0048] A dielectric barrier layer is formed on the first electrode and on the exposed area of ​​the substrate near the trench surface;

[0049] An anisotropic etching process is used, with etching stopping at the surface of the first electrode, leaving the dielectric barrier layer exposed on the surface of the substrate near the trench.

[0050] This can be understood as follows: when the dielectric barrier layer is fabricated, it covers the surface of the first electrode and the exposed surface of the substrate. The exposed surface of the substrate corresponds to the channel of the transistor. In this way, the channel of the transistor can be covered by the dielectric barrier layer, which suppresses the diffusion of high-concentration boron into the channel in subsequent processes.

[0051] In one feasible manner, after forming the dielectric barrier layer and before forming the first film layer, the preparation method further includes: forming a second film layer; wherein the first film layer and the first electrode further include silicon; the second film layer includes pure silicon; or; the second film layer includes silicon and boron; the boron content in the second film layer is less than the boron content in the first film layer, and the silicon content in the second film layer is greater than the silicon content in the first film layer; and the boron content in the second film layer is less than the boron content in the first electrode, and the silicon content in the second film layer is greater than the silicon content in the first electrode.

[0052] The second film layer prepared in this example can also be a barrier layer, which can also inhibit the diffusion of high concentrations of boron in the first film layer into the channel of the transistor.

[0053] In one feasible manner, forming the first electrode of a P-type transistor within the trench includes:

[0054] The first sub-electrode layer is formed within the trench;

[0055] A second sub-electrode layer is fabricated on the first sub-electrode layer. The germanium content in the second sub-electrode layer is greater than that in the first sub-electrode layer, and the boron content in the second sub-electrode layer is greater than that in the first sub-electrode layer.

[0056] The first sub-electrode layer can be considered as a buffer layer, and the second sub-electrode layer can be considered as a stress application layer. The buffer layer can increase the stress value applied to the channel by the second sub-electrode layer, further improving the channel carrier mobility and increasing the drive current of the P-type transistor. Attached Figure Description

[0057] Figure 1 is a partial structural diagram of an electronic device according to an example of this application;

[0058] Figure 2 is a partial structural diagram of a semiconductor device provided in an embodiment of this application;

[0059] Figure 3 is a partial structural diagram of a P-type transistor in a semiconductor device provided in an embodiment of this application;

[0060] Figure 4 is a top view of the first electrode of a P-type transistor in a semiconductor device provided in an embodiment of this application;

[0061] Figures 5 to 15 are process structure diagrams corresponding to some steps in the fabrication process of a semiconductor device provided in the embodiments of this application;

[0062] Figure 16 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0063] Figure 17 is a structural diagram of a trench for filling the first electrode of a P-type transistor according to an embodiment of this application;

[0064] Figure 18 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0065] Figure 19 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0066] Figure 20 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0067] Figure 21 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0068] Figure 22 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application.

[0069] Reference numerals: 100-Circuit board; 200-Substrate; 300-Semiconductor device; 400-Electrical connection structure; 11-First electrode; 12-Second electrode; 13-Channel; 14-Gate; 15-First film layer; 16-Dielectric barrier layer; 17-First gate sidewall; 18-Second gate sidewall; 111-First sub-electrode layer; 112-Second sub-electrode layer; 11A-Embedded portion; 11B-Protruding portion; 19-Second film layer;

[0070] 20 - Silicon oxide layer; 21 - Polycrystalline silicon hard mask layer; 22 - Hard mask silicon oxide layer; 23 - Hard mask silicon nitride layer; 24 - Trench; 25 - Notch. Detailed Implementation

[0071] The following embodiments of this application will be described in conjunction with the accompanying drawings.

[0072] The technical solutions of this application can be applied to various electronic devices employing semiconductor devices. For example, the electronic devices in the embodiments of this application can be mobile phones, tablets, laptops, smart home devices, smart wearable devices (e.g., smartwatches, smart bracelets, smart glasses, smart helmets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, etc. The electronic devices can also be handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices, electronic devices in 5G networks, or electronic devices in future evolved public land mobile networks (PLMNs), etc. The embodiments of this application are not limited in this regard.

[0073] As shown in Figure 1, the aforementioned electronic device may include a circuit board 100, such as a printed circuit board (PCB), on which a semiconductor device package structure is disposed. The semiconductor device package structure can be electrically connected to the circuit board 100 via an electrical connection structure 400, thereby enabling the semiconductor device package structure to achieve signal interconnection with other chips or other electronic modules on the circuit board 100.

[0074] In alternative implementations, the electrical connection structure 400 may include a plurality of solder balls, such as a ball grid array (BGA), or a plurality of metal pillars.

[0075] In some examples, as shown in Figure 1, the semiconductor device package structure includes multiple semiconductor devices 300 disposed on a substrate 200, such as on a package substrate. The substrate 200 is disposed on a circuit board 100 via an electrical connection structure 400.

[0076] The semiconductor device 300 shown in Figure 1 can be a single chip or multiple chips stacked in three dimensions.

[0077] In some implementation structures, the semiconductor device 300 may include memory, logic circuits, system on chip (SOC), or analog chips, digital chips, etc.

[0078] The semiconductor device shown above may contain multiple transistors. For example, when the semiconductor device is a memory, the memory cell may be a 6T memory cell, or it may be a 4T2C memory cell.

[0079] A semiconductor device may include a plurality of electrically connected P-type transistors; or, a plurality of electrically connected N-type transistors; or, a plurality of electrically connected P-type transistors and N-type transistors.

[0080] For example, in a P-type transistor, the application of compressive stress along the channel length can reduce the lattice constant of silicon in the channel, decrease the effective hole mass, thereby increasing the hole mobility, which will increase the drive current of the P-type transistor and optimize circuit performance.

[0081] However, during the fabrication of P-type transistors, some materials in the film structure diffuse into the channel of the P-type transistor, resulting in a short-channel effect and degrading the performance of the P-type transistor.

[0082] This application provides several methods for applying compressive stress to the channel of a P-type transistor and suppressing the diffusion of certain materials into the channel. Specific implementation methods are described below.

[0083] Figure 2 is a partial structural schematic diagram of a semiconductor device according to an embodiment of this application. The semiconductor device includes a substrate and a plurality of transistors; in the example of Figure 2, one P-type transistor (PMOS) and two N-type transistors (NMOS) are shown. Figure 2 is one example, but of course, more transistors may be included.

[0084] As shown in Figure 2, the P-type transistor of this application includes a first electrode 11, a second electrode 12, a channel 13, and a gate 14. For example, one of the first electrode 11 and the second electrode 12 can be the drain and the other can be the source.

[0085] The first electrode 11, the second electrode 12 and the channel 13 are located in the substrate, the channel 13 is located between the first electrode 11 and the second electrode 12, and the gate 14 is located on the channel 13. For example, the gate 14 can be fabricated by epitaxial growth technology.

[0086] In the P-type transistor of this application example, the first electrode 11 may include boron B, for example, it may include silicon Si, germanium Ge, and boron B, such as a SiGe material containing boron B. The second electrode 12 may also include silicon Si, germanium Ge, and boron B, such as a SiGe material containing boron B.

[0087] Due to the lattice constant of germanium (Ge) The lattice constant of silicon (Si) The increase of about 4% will generate a transverse compressive stress F on the channel 13 as shown in Figure 2, which will reduce the Si lattice constant in the channel 13 and reduce the effective hole mass, thereby achieving the purpose of improving the hole mobility.

[0088] Figure 3 shows a detailed schematic diagram of the structure of the first electrode 11, the gate 14, and other films in a P-type transistor. At least a portion of the first electrode 11 is located in the substrate, and the P-type transistor also includes a first film 15 located on the first electrode 11.

[0089] The first film layer 15 includes boron (B), for example, silicon (Si) and boron (B). The boron (B) content in the first film layer 15 is greater than the boron (B) content in the first electrode 11. The first film layer 15 is electrically coupled to the first electrode 11. Because the first film layer 15 has a higher content (or concentration) of boron (B), the resistance of the circuit containing the P-type transistor can be effectively reduced, thus optimizing the circuit performance.

[0090] In some examples of this application, the boron content in the first film layer 15 is greater than the boron content in the first electrode 11. This can be understood as follows: in the first film layer, the boron content = the number of boron B atoms / (the number of boron B atoms + the number of silicon Si atoms); in the first electrode, the boron content = the number of boron B atoms / (the number of boron B atoms + the number of silicon Si atoms + the number of germanium Ge atoms).

[0091] In some examples, the boron content in the first film layer 15 is greater than the boron content in the first electrode 11. This can be understood as: the proportion of boron atoms in the first film layer 15 is greater than the proportion of boron atoms in the first electrode 11; or, the boron concentration in the first film layer 15 is greater than the boron concentration in the first electrode 11.

[0092] See Figure 3, which shows the approximate extent of the channel 13 of the P-type transistor in the substrate with a dashed box. Of course, Figure 3 is an example.

[0093] As shown in Figures 3 and 4, Figure 4 shows a top view of the first electrode 11 and the first region in Figure 3. The surface of the substrate includes a first region located around the first electrode 11, which can be understood as the first region surrounding the first electrode 11 circumferentially, as shown in Figure 3. In the substrate, the channel 13 of the P-type transistor corresponds to the location of the first region. In this application example, as shown in Figure 3, the first region has a dielectric barrier layer 16, which can be understood as at least a portion of the first region being covered by the dielectric barrier layer 16.

[0094] The dielectric barrier layer 16 is used to suppress the diffusion of boron B in the first film layer 15 into the substrate. For example, the dielectric barrier layer 16 is used to suppress the diffusion of boron B in the first film layer 15 into the channel 13 of the P-type transistor.

[0095] The dielectric barrier layer 16 can suppress the diffusion of boron (B) from the first film layer 15 into the channel 13 of the P-type transistor. This can be understood as follows: in some structures, the dielectric barrier layer 16 can completely suppress the diffusion of boron (B) from the first film layer 15 into the channel 13 of the P-type transistor, and there will be virtually no boron (B) in the channel 13; or, in other structures, the dielectric barrier layer 16 can have a strong suppression effect, and there will be a small amount of boron (B) in the channel 13, and this small amount of boron (B) will not cause short-channel effect.

[0096] The following explanation, in conjunction with the accompanying drawings, explains how to fabricate the structure shown in FIG3 and how to use the dielectric barrier layer 16 to suppress the diffusion of boron B in the first film layer 15 into the substrate.

[0097] As shown in Figure 5, a gate 14 and a first gate sidewall 17 are fabricated on a substrate, with the first gate sidewall 17 formed on the peripheral side surface of the gate 14.

[0098] For example, if the substrate is a silicon substrate, it will naturally oxidize into a silicon oxide layer 20 on the substrate surface.

[0099] Among the available materials, the gate 14 can be a conductive material, such as a metallic material. In alternative embodiments, it can be one or more of the following conductive materials: TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0100] Among a number of selectable materials, the first gate sidewall 17 may be a dielectric material, such as a dielectric material with a high dielectric constant. Examples include insulating materials such as silicon nitride and silicon oxide.

[0101] The first gate sidewall 17 can have a protective function, controlling the distance from the channel when ions are implanted into the substrate to form the channel, thereby suppressing the short-channel effect.

[0102] In some optional processes, as shown in Figure 5, a polysilicon hard mask layer 21 of a certain thickness can be formed on top of the gate 14. The polysilicon hard mask layer 21 acts as a sacrificial layer to protect the gate 14 in subsequent processes.

[0103] As shown in Figure 6, a hard mask silicon oxide layer 22 and a hard mask silicon nitride layer 23 are formed. For example, the hard mask silicon oxide layer 22 and the hard mask silicon nitride layer 23 are fabricated using epitaxial growth technology.

[0104] The hard mask silicon oxide layer 22 serves as a buffer layer between the hard mask silicon nitride layer 23 and the first sidewall 17, allowing for better fabrication of the hard mask silicon nitride layer 23. For example, a hard mask silicon oxide layer 22 with a thickness of 1 nm to 6 nm can be deposited using CVD.

[0105] In some processes, a hard mask silicon nitride layer with a thickness of 5 nm to 30 nm can be deposited using a furnace tube.

[0106] As shown in Figure 6, the silicon oxide layer on the substrate surface includes the naturally oxidized silicon oxide layer 20 shown in Figure 5, and the hard mask silicon oxide layer 22 formed in Figure 6.

[0107] As shown in Figure 7, trenches 24 are formed in the source and drain regions of the substrate for forming P-type transistors. For example, trenches 24 can be formed by dry etching or wet etching.

[0108] For example, dry etching can use at least one of the following gases: chlorine, hydrogen chloride, hydrogen bromide, carbon tetrafluoride, and nitrogen trifluoride. The etching time can be 50-150 seconds.

[0109] For another example, wet etching can use tetramethylammonium hydroxide. The etching time can be 100s-400s.

[0110] As shown in Figure 7, when etching trench 24, the hard mask silicon nitride layer 23 and silicon oxide layer (including hard mask silicon oxide layer 22 and naturally oxidized silicon oxide layer 20) located on the substrate surface will be etched away.

[0111] As shown in Figure 8, after the trench 24 is etched as shown in Figure 7, for example, when the substrate is a silicon substrate, the inner wall surface of the trench 24 will be oxidized to form silicon oxide.

[0112] To improve the performance of the P-type transistor, the inner wall of the trench 24 needs to be cleaned before the source and drain are fabricated in the trench 24 to remove the silicon oxide adhering to the wall of the trench 24.

[0113] As shown in Figure 9, clean the inner wall of the trench 24.

[0114] In some alternative processes, gases containing hydrogen fluoride (HF) and ammonia (NH3) can be used to remove silicon oxide from the inner wall surface of trench 24.

[0115] As shown in Figure 9, when cleaning the silicon oxide on the inner wall of trench 24, the side of the silicon oxide layer in contact with the substrate is exposed. Consequently, the silicon oxide layer at the bottom of the hard mask silicon nitride layer 23 that is in contact with the substrate is also cleaned away, thus forming the notch 25 shown in Figure 9. The formation of the notch 25 exposes part of the substrate surface.

[0116] The exposed substrate may correspond to the channel 13 of the P-type transistor. If the source and drain of the P-type transistor and the first film layer 15 are fabricated using the method shown in Figure 10, there will be some technical problems.

[0117] As shown in Figure 10, a first electrode 11 of a P-type transistor is formed in the trench 24, and a first film layer 15 is formed on the first electrode 11.

[0118] Because the first film layer 15 has a high boron content, the high boron content will diffuse into the substrate through the notch 25, for example, into the channel 13 of the P-type transistor, resulting in a short-channel effect and degrading the transistor performance.

[0119] In order to suppress the diffusion of high boron content into the substrate through the notch 25, the method shown in Figures 11 and 12 can be used in this application example.

[0120] As shown in Figure 11, a first electrode 11 of a P-type transistor is formed in the trench 24, and a dielectric barrier layer 16 is formed on the first electrode 11.

[0121] The dielectric barrier layer 16 covers the substrate surface, which can be understood as: at least the exposed area of ​​the substrate located outside the first electrode 11 (that is, the first area in Figures 3 and 4 above) is covered by the dielectric barrier layer 16.

[0122] In some examples, the dielectric barrier layer 16 may be made of at least one of dielectric materials such as silicon oxide, silicon nitride, silicon oxide, and silicon carbide.

[0123] As shown in Figure 12, an anisotropic dry etching process can be used to stop the etching on the surface of the first electrode 11.

[0124] As shown in Figure 13, a first film layer 15 is formed on the first electrode 11. The first film layer 15 at least covers the surface of the first electrode 11. In other examples, the first film layer 15 may cover the surface of the first electrode 11 and may also cover the surface of the dielectric barrier layer 16.

[0125] Because a dielectric barrier layer 16 is formed before the first film layer 15 is formed, and the dielectric barrier layer 16 covers some exposed areas of the substrate surface, the high boron content (B) in the first film layer 15 will not diffuse into the substrate or into the channel of the P-type transistor. Therefore, in the fabrication of the P-type transistor in this application example, as shown in FIG9, the presence of the notch 25 will not expose the channel in the substrate, preventing the boron (B) in the first film layer 15 from diffusing into the channel of the P-type transistor.

[0126] In some processes, the polysilicon hard mask layer 21, the hard mask silicon oxide layer 22, and the hard mask silicon nitride layer 23 are removed to obtain the structure shown in Figure 14.

[0127] For example, wet etching can use phosphoric acid treatment for 200s-500s to remove the hard mask silicon nitride layer 23 and polysilicon hard mask layer 21; wet etching can use HF to remove the hard mask silicon oxide layer 22.

[0128] As shown in Figure 15, a second gate sidewall 18 is formed on the side of the first gate sidewall 17.

[0129] Among a number of selectable materials, the second gate sidewall 18 may be a dielectric material, such as a dielectric material with a high dielectric constant. Examples include insulating materials such as silicon nitride and silicon oxide.

[0130] The materials of the first gate sidewall 17 and the second gate sidewall 18 can be the same or different.

[0131] As shown in Figure 16, which illustrates another P-type transistor structure, the first electrode 11 of this example may include an embedded portion 11A located in a substrate and a protruding portion 11B protruding from the substrate surface. The peripheral side surface of the protruding portion 11B is covered by a dielectric barrier layer 16; and the dielectric barrier layer 16 located on the peripheral side surface of the protruding portion 11B extends to the substrate surface, for example, to a first region of the substrate (the region surrounding the periphery of the protruding portion 11B), and the dielectric barrier layer 16 covers the first region.

[0132] When the first electrode 11 shown in FIG16, which includes an embedded portion 11A and a protruding portion 11B, is manufactured, the embedded portion 11A and the protruding portion 11B can be manufactured by an epitaxial growth process.

[0133] Continuing with Figure 16, the protruding portion 11B of the first electrode 11 is inclined in a direction away from the gate 14 near the peripheral side of the gate 14.

[0134] As shown in Figure 16, the dielectric barrier layer 16 is in contact with the gate sidewall located around the gate 14. For example, in Figure 16, the dielectric barrier layer 16 is in contact with the second gate sidewall 17.

[0135] In some examples, the material of the gate sidewall can be the same as the material of the dielectric barrier layer 16. Alternatively, in other examples, the material of the gate sidewall can be different from the material of the dielectric barrier layer 16.

[0136] For example, in Figure 16, the gate sidewall includes a first gate sidewall 17 and a second gate sidewall 18. The first gate sidewall 17 is located on the side of the gate 14, and the second gate sidewall 18 is stacked on the first gate sidewall 17. The dielectric barrier layer 16 is in contact with the second gate sidewall 18.

[0137] In some examples, the materials of the first gate sidewall 17 and the second gate sidewall 18 are different, and the materials of the second gate sidewall 18 and the dielectric barrier layer 16 are different. In other examples, the materials of the first gate sidewall 17 and the second gate sidewall 18 are the same, and the materials of the second gate sidewall 18 and the dielectric barrier layer 16 are different. In still other examples, the materials of the first gate sidewall 17 and the second gate sidewall 18 are different, and the materials of the second gate sidewall 18 and the dielectric barrier layer 16 are the same.

[0138] Continuing with Figure 16, the side of the dielectric barrier layer 16 is in contact with the second gate sidewall 18, and the side of the first film layer 15 is in contact with the second gate sidewall 18.

[0139] In some possible implementations, the shape of the trench used to accommodate the first pole 11 can be varied, for example, it can be a rectangular trench; or, for example, it can be the trench structure shown in Figure 17.

[0140] In the trench 24 structure shown in Figure 17, the radial dimension of the trench 24 (e.g., the dimension along the L direction) first increases and then decreases from the bottom surface of the trench 24 to the opening direction (e.g., along the P direction).

[0141] For example, trench 24 has opposing first inner walls S1 and second inner walls S2, and opposing third inner walls S3 and fourth inner walls S4. The first inner wall S1 and third inner wall S3 are connected, and the second inner wall S2 and fourth inner wall S4 are connected. From the bottom surface of trench 24 to the opening direction (e.g., along the P direction), the first inner wall S1 and second inner wall S2 are inclined towards the outside of trench 24, while the third inner wall S3 and fourth inner wall S4 are inclined towards the inside of trench 24. Such a trench structure can be referred to as a sigma-shaped trench. The sigma-shaped trench shape facilitates the application of stress from the germanium-silicon of the first electrode to the channel, improving the carrier mobility of the channel. For example, the on-state current of the semiconductor device can be increased by 50%.

[0142] Thus, the radial dimension of the first pole 11 formed from the bottom surface to the top surface (as shown in the P direction of Figure 17) first increases and then decreases.

[0143] In some feasible structures, as shown in Figure 18, the first electrode 11 of the P-type transistor may include a stacked first sub-electrode layer 111 and a second sub-electrode layer 112, wherein the first sub-electrode layer 111 is closer to the channel 13 of the P-type transistor than the second sub-electrode layer 112. In the fabrication process, the first sub-electrode layer 111 can be fabricated first, and then the second sub-electrode layer 112 can be fabricated on the first sub-electrode layer 111.

[0144] The first sub-electrode layer 111 includes silicon (Si), germanium (Ge), and boron (B); the second sub-electrode layer 112 includes silicon (Si), germanium (Ge), and boron (B).

[0145] The germanium (Ge) content in the second sub-electrode layer 112 is greater than the germanium (Ge) content in the first sub-electrode layer 111, and the boron (B) content in the second sub-electrode layer 112 is greater than the boron (B) content in the first sub-electrode layer 111.

[0146] The germanium (Ge) content in the first sub-electrode layer 111 is less than that in the second sub-electrode layer 112, and the boron (B) content in the first sub-electrode layer 111 is less than that in the second sub-electrode layer 112. The first sub-electrode layer 111 can be considered a buffer layer, and the second sub-electrode layer 112 can be considered a stress-applying layer. The buffer layer can increase the stress applied to the channel by the second sub-electrode layer 112, further improving the channel carrier mobility and increasing the drive current of the P-type transistor. For example, the on-state current of the semiconductor device can be increased by 50%.

[0147] Referring again to Figure 18, the substrate surface may have a second sub-electrode layer 112, the peripheral side of which is covered by a dielectric barrier layer 16; and the dielectric barrier layer 16 extends to the substrate surface, for example, to a first region of the substrate.

[0148] As shown in Figure 19, which illustrates another type of P-type transistor structure, the first electrode 11 in this example may include an embedded portion 11A located in the substrate. This can be understood as the surface of the first electrode 11 being substantially flush with the substrate surface and not protruding from it.

[0149] The area on the substrate surface and surrounding the first electrode 11 is considered the first region, which is at least partially covered by the dielectric barrier layer 16.

[0150] Continuing with Figure 19, the first electrode 11 is separated from the channel in the substrate by a dielectric barrier layer 16. This can suppress the diffusion of boron B in the first film layer 15 into the channel in the substrate and suppress the short-channel effect.

[0151] As shown in Figure 20, which illustrates another type of P-type transistor structure, this example includes not only a dielectric barrier layer 16 but also a second film layer 19, which is stacked between the first electrode 11 and the first film layer 15 of the transistor.

[0152] In some examples, as shown in Figure 20, the second film layer 19 may cover the first electrode 11 and the dielectric barrier layer 16.

[0153] The second film layer 19 is used to suppress the diffusion of boron from the first film layer 15 into the channel of the P-type transistor. In this example, the use of the dielectric barrier layer 16 and the second film layer 19 can further suppress the diffusion of boron from the first film layer 15 into the channel of the P-type transistor, suppress the short-channel effect, improve hole mobility, and optimize device performance.

[0154] In this application example, the second membrane layer 19 can be made of a variety of materials.

[0155] For example, the second film layer 19 can be made of metal. A second film layer 19 made of metal can achieve electrical coupling between the first electrode 11 and the first film layer 15.

[0156] For example, the second film layer 19 is pure silicon. Pure silicon can be understood as having a silicon content that is close to 100%, or at least 98% or higher. In some structures, the second film layer 19 covering the first electrode 11 can be relatively thin, thus enabling electrical coupling between the first electrode 11 and the first film layer 15. For example, the thickness of the second film layer 19 covering the first electrode 11 can be 2 nm or more.

[0157] For example, the second film layer 19 includes silicon (Si) and boron (B). The second film layer 19, which includes silicon (Si) and boron (B), is conductive, allowing the first electrode 11 to be electrically coupled to the first film layer 15.

[0158] When the second film layer 19 comprises silicon (Si) and boron (B), the boron content in the second film layer 19 is less than the boron content in the first film layer 15, and the silicon content in the second film layer 19 is greater than the silicon content in the first film layer 15; and the boron content in the second film layer 19 is less than the boron content in the first electrode 11, and the silicon content in the second film layer 19 is greater than the silicon content in the first electrode 11.

[0159] In this example, in the second film layer 19, the boron B content = number of boron B atoms / (number of boron B atoms + number of silicon Si atoms), and the silicon Si content = number of silicon Si atoms / (number of boron B atoms + number of silicon Si atoms); in the first film layer, the boron B content = number of boron B atoms / (number of boron B atoms + number of silicon Si atoms), and the silicon Si content = number of silicon Si atoms / (number of boron B atoms + number of silicon Si atoms); in the first electrode, the boron B content = number of boron B atoms / (number of boron B atoms + number of silicon Si atoms + number of germanium Ge atoms), and the silicon Si content = number of silicon Si atoms / (number of boron B atoms + number of silicon Si atoms + number of germanium Ge atoms).

[0160] In some examples, the boron content in the second film layer 19 is less than the boron content in the first film layer 15. This can be understood as: the proportion of boron atoms in the second film layer 19 is less than the proportion of boron atoms in the first film layer 15, or the boron concentration in the second film layer 19 is less than the boron concentration in the first film layer 15.

[0161] Figure 21 illustrates another P-type transistor structure. In this example, the first electrode 11 includes a stacked first sub-electrode layer 111 and a second sub-electrode layer 112. When the second film layer 19 comprises silicon and boron, the boron (B) content in the second film layer 19 is less than the boron content in the second sub-electrode layer 112, and the silicon content in the second film layer 19 is greater than the silicon content in the second sub-electrode layer 112. Thus, the second film layer 19 does not affect the function of the first electrode 11, and the second film layer 19 also serves to suppress the diffusion of boron from the first film layer 15 into the channel.

[0162] Semiconductor devices with different structures based on the above examples, and their corresponding fabrication methods, can be fabricated according to the process flow diagram shown in Figure 22.

[0163] Step S1: Create trenches in the electrode region of the substrate. The electrode region is used to form the first electrode of the P-type transistor.

[0164] The first electrode can be either the source or the drain of a P-type transistor.

[0165] In some selectable processes, trenches can be obtained by etching the source and drain regions of the substrate using either dry or wet etching.

[0166] For example, the trench can be a Sigma trench, which is beneficial for the first electrode of the P-type transistor to apply stress to the channel.

[0167] In some processes, the fabrication method may also include the following steps before creating trenches in the electrode region of the substrate:

[0168] The gate of a P-type transistor is fabricated on a substrate;

[0169] A first mask layer and a second mask layer are formed. The first mask layer includes silicon oxide. The electrode region surface of the substrate is covered by the first mask layer. The second mask layer is located on the side of the first mask layer away from the substrate. The surface and side of the gate are also covered by the first mask layer and the second mask layer. The second mask layer may include silicon nitride.

[0170] In some structures, when the substrate is a silicon substrate, after trenches are opened in the electrode region of the substrate, silicon oxide will be formed on the inner wall of the trench. Therefore, the silicon oxide on the inner wall of the trench can be removed by epitaxial in situ pre-cleaning process.

[0171] For example, a gas containing ammonia and hydrogen fluoride can be used to clean the inner wall of the trench, thereby removing the silica from the inner wall of the trench.

[0172] In addition, the portion of the first mask layer of silicon oxide near the trench will also be washed away, exposing the surface of the substrate near the trench.

[0173] Step S2: Form the first electrode of the P-type transistor within the trench. The first electrode includes boron. For example, the first electrode includes silicon, germanium, and boron.

[0174] When performing step S2, the process may include: forming a first sub-electrode layer in the trench; forming a second sub-electrode layer on the first sub-electrode layer, wherein the germanium content in the second sub-electrode layer is greater than the germanium content in the first sub-electrode layer, and the boron content in the second sub-electrode layer is greater than the boron content in the first sub-electrode layer.

[0175] The first sub-electrode layer acts as a buffer layer, allowing the second sub-electrode layer to better apply stress to the channel.

[0176] The first electrode is fabricated using an epitaxial growth process. The first electrode protrudes from the substrate surface, forming a protruding portion on the substrate surface.

[0177] Step S3: A dielectric barrier layer is formed, wherein at least a portion of the substrate surface and the area surrounding the first electrode is covered by the dielectric barrier layer.

[0178] When the substrate surface has a protrusion, the dielectric barrier layer covers the peripheral side of the protrusion and extends from the peripheral side of the protrusion to the substrate surface, thus covering the substrate surface corresponding to the channel.

[0179] In some optional processes, a dielectric barrier layer can be formed on both the first electrode and the substrate surface, and then an anisotropic dry etching process can be used to etch until the etching stops on the surface of the first electrode, leaving the dielectric barrier layer on the substrate surface and located on the periphery of the first electrode.

[0180] Step S4: A first film layer is formed on the first electrode. The first film layer includes boron, and the boron content in the first film layer is greater than the boron content in the first electrode.

[0181] When fabricating a P-type transistor in a semiconductor device using the method described in this application, although the area corresponding to the channel of the substrate will be exposed when cleaning the silicon oxide on the inner wall of the trench, the exposed area can be covered by adding a dielectric barrier layer, thus preventing the high boron content in the subsequent first film layer from diffusing into the channel.

[0182] After the dielectric barrier layer is formed and before the first film layer is formed, the preparation method may further include: forming a second film layer on the first electrode, the second film layer may be pure silicon, or the second film layer may include silicon (Si) and boron (B); and then forming the first film layer on the second film layer.

[0183] The P-type transistor fabricated using this method includes a dielectric barrier layer and a second film layer. Both film layer structures can suppress the diffusion of high concentrations of boron (B) from the first film layer into the channel of the P-type transistor. This further suppresses the short-channel effect and improves device performance.

[0184] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0185] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A P-type transistor includes a first electrode, a second electrode, a channel, a gate, and a gate sidewall. The first electrode, the second electrode, and the channel are located in the substrate. The channel is located between the first electrode and the second electrode. The gate is located on the channel. The gate sidewall is located on the peripheral side of the gate. The first electrode includes boron. A first membrane layer is located on the first electrode, and the first membrane layer includes boron, wherein the boron content in the first membrane layer is greater than the boron content in the first electrode. A dielectric barrier layer, wherein the surface of the substrate includes a first region located at the periphery of the first electrode, and at least a portion of the first region is covered by the dielectric barrier layer.

2. The semiconductor device according to claim 1, characterized in that, The first electrode includes: an embedded portion located in the substrate, and a protruding portion protruding from the surface of the substrate, the first region surrounding the protruding portion; The peripheral side of the protruding portion is covered by the dielectric barrier layer; The dielectric barrier layer located on the peripheral side of the protrusion extends into the first region and covers the first region.

3. The semiconductor device according to claim 2, characterized in that, The circumferential side of the protruding portion near the gate sidewall is inclined away from the gate sidewall.

4. The semiconductor device according to any one of claims 1-3, characterized in that, The gate sidewall includes a first gate sidewall and a second gate sidewall, wherein the first gate sidewall and the second gate sidewall are stacked sequentially on the peripheral side surface of the gate. The peripheral side of the dielectric barrier layer is in contact with the second gate sidewall.

5. The semiconductor device according to any one of claims 1-4, characterized in that, The material of the gate sidewall is the same as the material of the dielectric barrier layer.

6. The semiconductor device according to any one of claims 1-5, characterized in that, The dielectric barrier layer includes at least one of silicon oxide, silicon nitride, silicon oxide, and silicon carbide.

7. The semiconductor device according to any one of claims 1-6, characterized in that, The semiconductor device further includes: a second film layer; A second film layer is provided between the dielectric barrier layer and the first film layer, and a second film layer is provided between the first electrode and the first film layer; The first film layer and the first electrode also include silicon; The second film layer comprises pure silicon; or; The second film layer comprises silicon and boron; The boron content in the second film layer is less than the boron content in the first film layer, and the silicon content in the second film layer is greater than the silicon content in the first film layer; and, The boron content in the second film layer is less than the boron content in the first electrode, and the silicon content in the second film layer is greater than the silicon content in the first electrode.

8. The semiconductor device according to claim 7, characterized in that, The first electrode also includes silicon and germanium; The first electrode includes: a stacked first sub-electrode layer and a second sub-electrode layer, wherein the first sub-electrode layer is closer to the channel than the second sub-electrode layer; The germanium content in the second sub-electrode layer is greater than the germanium content in the first sub-electrode layer; and, The boron content in the second sub-electrode layer is greater than the boron content in the first sub-electrode layer.

9. The semiconductor device according to claim 8, characterized in that, The second film layer comprises silicon and boron, wherein the boron content in the second film layer is less than the boron content in the second sub-electrode layer, and the silicon content in the second film layer is greater than the silicon content in the second sub-electrode layer.

10. The semiconductor device according to any one of claims 1-9, characterized in that, From the bottom surface to the top surface of the first pole, the radial dimension of the first pole first increases and then decreases.

11. A semiconductor device packaging structure, characterized in that, include: The semiconductor device as described in any one of claims 1-10; A substrate on which the semiconductor device is disposed.

12. An electronic device, characterized in that, include: Circuit board; The semiconductor device packaging structure as described in claim 11; The semiconductor device packaging structure is disposed on the circuit board.

13. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A trench is formed in the electrode region of the substrate, the electrode region being used to form the first electrode of a P-type transistor; The first electrode of the P-type transistor is formed within the trench, and the first electrode comprises boron; A dielectric barrier layer is formed, wherein at least a portion of the substrate surface and the area surrounding the first electrode is covered by the dielectric barrier layer; A first film layer is formed on the first electrode, the first film layer comprising boron, and the boron content in the first film layer being greater than the boron content in the first electrode.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, Before forming the trench in the electrode region of the substrate, the fabrication method further includes: A first mask layer and a second mask layer are formed. The first mask layer includes silicon oxide. The electrode region surface of the substrate is covered by the first mask layer. The second mask layer is located on the side of the first mask layer away from the substrate. After forming the trench in the electrode region of the substrate, the fabrication method further includes: The inner wall of the trench is cleaned, and the portion of the first mask layer near the trench is cleaned away, exposing the surface of the substrate near the trench.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The dielectric barrier layer is prepared by: The dielectric barrier layer is formed on the first electrode and on the exposed area of ​​the substrate near the trench surface; An anisotropic etching process is used, and the etching stops at the surface of the first electrode, leaving the dielectric barrier layer on the exposed area of ​​the substrate near the trench.

16. The method for fabricating a semiconductor device according to any one of claims 13-15, characterized in that, After obtaining the dielectric barrier layer and before obtaining the first film layer, the preparation method further includes: The second film layer was obtained; The first film layer and the first electrode further include silicon; The second film layer comprises pure silicon; or; The second film layer comprises silicon and boron; The boron content in the second film layer is less than the boron content in the first film layer, and the silicon content in the second film layer is greater than the silicon content in the first film layer; and, The boron content in the second film layer is less than the boron content in the first electrode, and the silicon content in the second film layer is greater than the silicon content in the first electrode.

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