Computer-implemented method and device for an automated topology selection for power electronics circuits

Abstract

The invention relates to a computer-implemented method for determining an optimal topology for a power electronics circuit, in particular a voltage converter, an inverter, or a power driver, wherein the topology of the power electronics circuit can be represented by a network using a network list, the method having the steps of: - providing (S2) a plurality of topologies, each of which has a respective circuit network comprising active and passive components, the active components comprising semiconductor switches and / or diodes; - providing (S1) requests to the power electronics circuit, the requests specifying user-defined operating points (om m=1…M); - determining respectively optimized component values of the active and / or passive components for the plurality of topologies on the basis of a target function (F) which assesses the fulfillment of the requests, - determining (S10) a respective function value of a specified decision target function (V) for the plurality of topologies on the basis of the assigned optimized component values; and - selecting the topology from the plurality of topologies on the basis of the associated function value of the decision target function (V).

Description

[0001] R. 406567

[0002] 1

[0003] Description

[0004] title

[0005] Computer-implemented method and device for automated topology selection for power electronic circuits

[0006] Technical field

[0007] The invention relates to the selection of a circuit topology in power electronic hardware, such as voltage converters, inverters, or driver circuits. The invention particularly relates to the topology selection for a power electronic circuit at the beginning of a design process for power electronic hardware.

[0008] Technical background

[0009] The selection of a suitable topology for a specific power electronics application has so far been based on expert knowledge, intuitively or based on experience, taking into account the cost, volume, and efficiency of the power electronics hardware to be manufactured. However, it is often difficult for an expert to evaluate a topology with regard to new requirements before its implementation in hardware.

[0010] It is therefore desirable to provide an automated process for finding a suitable topology for a power electronic circuit that is optimized in terms of requirements and cost.

[0011] Disclosure of the invention

[0012] According to the invention, a computer-implemented method for determining R. 406567

[0013] 2 of an optimal topology for a power electronic circuit according to claim 1 and a corresponding device according to the dependent claim.

[0014] Further details are specified in the dependent claims.

[0015] According to a first aspect, a computer-implemented method for determining an optimal topology for a power electronic circuit, in particular a voltage converter, an inverter or a power driver, is provided, wherein the topology of the power electronic circuit can be represented by a circuit network using a netlist, with the steps:

[0016] Providing a variety of topologies with a respective circuit network of active and passive components, wherein the active components include semiconductor switches and / or diodes;

[0017] Providing requirements for the power electronic circuit, where the requirements specify user-defined operating points;

[0018] Determining optimized component values ​​of the active and / or passive components for the multitude of topologies depending on an objective function that evaluates the fulfillment of the requirements; determining a respective function value of a given decision objective function for the multitude of topologies depending on the assigned optimized component values;

[0019] - Selecting the topology from the multitude of topologies depending on the associated function value of the decision objective function.

[0020] Furthermore, the following steps can be performed for each of the multitude of topologies: o Determining a set of realizable switch configurations of the active components, where the set of realizable switch configurations is each a set of realizable

[0021] Switch configurations for continuous current or

[0022] Voltage behavior (continuous operation) and a set of realizable switch configurations for discontinuous current or voltage behavior (intermittent operation) includes, or determining an associated “equivalent” network from R. 406567

[0023] 3 original network T orgthe topology, which is triggered purely externally by ideal switches, where all diodes are replaced by ideal switches and each passive component associated with a switch configuration SD™ for discontinuous current or voltage behavior is provided with an additional artificial switch; o Determining a set of all realizable switching sequences SSpea for realizable switch configurations Spea, where the realizable switching sequences SSpea are periodic, and each switch is turned on and off at most once within a switching period; o Analyzing the equivalent network by determining, for a given set of initial component values ​​pi ini , i = 1... I of the active and / or passive components of the equivalent network for each of the predefined user-defined operating points o m , m=1... M an optimal realizable switching sequence SS m opt , m=1... M with associated optimal

[0024] Switching time interval vectors At m opt , m=1... M of the realizable switch configurations Spea and associated best initial state vectors zo m opt , m=1... M for internal states of the passive components in the equivalent network is determined from the set of realizable switching sequences, taking into account the given objective function F, in order to determine a function value of the objective function for each operating point; o Determining the optimized component values ​​Pi opt , i=1... l of the passive components using a predefined decision objective function V depending on the function value of the objective function F determined for each operating point and a corresponding value of the decision objective function V.

[0025] The typical development process for power electronic hardware consists of several phases, starting with the selection of suitable topologies of power electronic circuits that meet the technical requirements and can be manufactured cost-effectively, and ending with concrete hardware prototypes of the power electronic circuit.

[0026] Initially, a large number of topologies are created, which are of interest. R. 406567

[0027] 4

[0028] Candidates for a suitable solution are identified, and those topologies that meet the requirements of the desired application are selected. Subsequently, the costs, advantages, and disadvantages of the remaining candidates are determined, and the appropriate topologies are selected based on these findings. The basis for determining the suitability of a topology according to the requirements and costs is solely information about the signal waveforms of physical quantities, such as voltage, current, magnetomotive force, and magnetic flux, as well as the component values ​​of the circuit network components, such as the capacitances C of capacitors, the inductances L of coils, the reluctances R of magnetic paths, and the number of windings N in transformers.

[0029] The aim of the above method is to automate the topology selection at the beginning of the development process of a hardware module with a power electronic circuit by taking technical requirements and costs into account as effectively as possible. The power electronic circuit can be a voltage converter, an inverter, or a power driver (H-bridge circuit, B6 circuit, and the like).

[0030] Selecting a suitable topology first requires formulating the requirements by defining them, i.e., the boundary conditions under which the analysis and selection of the topology are to take place. In particular, the requirements for the power electronic circuit are defined by a number of power terminals, each with an electrical voltage and current, using two-port or multi-port parameters.

[0031] For this purpose, the required voltages and currents, as well as the averaged currents and voltages over a switching period, are specified for each power port at the relevant steady-state operating points of the circuit. Using the multiport model, it is determined whether the circuit is capable of fulfilling the requirements, for example, in a loss- and cost-optimized manner. The behavior of the two-port or multiport can be advantageously described in simulations using the corresponding state equations in the time domain. R. 406567

[0032] 5

[0033] Furthermore, the requirements can specify the manner in which the stationary transmission of the average electrical power P is carried out. m avg , m = 1 . . M is to be performed at a specific operating point. The set of specific operating points o m , m = 1 ... M under the given requirements can be achieved by different time-constant input variables x m, m = 1 ... M and different output variables y averaged over a switching period m avg , m = 1 . . M can be defined. The type of input or output variables is determined by defining the source characteristic (current source / voltage source). The source characteristic specifies how current and voltage are related in the component in question. For a current source, the current is fixed and the voltage is arbitrary (it is determined by the electrical network in response to the given current). For a voltage source, the voltage is fixed and the current is arbitrary (it is determined by the electrical network in response to the given voltage).

[0034] Power electronic circuits, such as DC / DC converters in electromobility, comprise electrical (non-isolated) or electromagnetic (isolated) circuit networks in which passive electrical and magnetic energy storage devices are connected to active switches to enable a predetermined electrical energy exchange between two or more electrical ports. In addition to bidirectional (ideal) switches, unidirectional (real) switches with bypass diodes and purely isolated diodes are also used. While the binary state (open (0) or closed (1)) of ideal switches can be controlled externally with independent signals freely selectable by the designer, the switching state of real switches or diodes depends partly or even entirely on the currents or voltages flowing through or across the respective switch.

[0035] The decision variables correspond to the variables that influence the average power transfer for input variations. The topology is defined by the topology information T, which is mathematically characterized by the associated topological matrices (e.g., incidence or adjacency matrices; see, for example, [Chua, U., Ling, P., "Computer-Aided Analysis of Electronic Circuits", Prentice-Hall, Englewood Cliffs, NJ, 1975]) and indicates how one component in the circuit is connected to another component. R. 406567

[0036] 6

[0037] The component values ​​define the parameter vector p T = (pi . . pi . . pi) with i=1..l , I equals the number of components in the circuit network and e {C, L, R, N}. Preferably, a component value describes at least one element of a parameter vector p. T, whose elements each describe a physical parameter of a component, e.g., the inductance of a coil, its dimensions, or the capacitance of a capacitor, or similar for other active or passive components. Since the components are determined by the specific design of the power electronic circuit and the implementation of the components within that circuit, they are identical for all operating points within the given requirements.

[0038] For a given topology T and given parameter value vector p, the variation of the power transfer and thus the transition from one steady-state operating point to another is influenced by the switching sequence SS as a sequence of specific switch configurations S in the circuit.

[0039] The switch configurations S are typically defined by binary vectors whose length corresponds to the number of switches in the topology and whose elements specify the switching state. Consequently, the switching sequence SS is a sequence of binary vectors, which can then be encoded accordingly in the form of a binary matrix. The dimensions of the matrix are then given, on the one hand, by the length of the switching vectors and, on the other hand, by the length of the sequence of switching vectors.

[0040] For a given topology T, given parameter value vector p and a given switching sequence SS, the switching time interval vector At determines T= (Ati . . Atj . . Ati) with I equal to the number of switching intervals in the period 1 / f in combination with the associated initial state vector zo (these are currents for inductors, voltages for capacitances and fluxes for magnetic reluctances) of the energy-storing components in the circuit the power transfer.

[0041] Based on the definition of the influencing factors and their order of action, the goal for selecting the most suitable topology can be defined in order to obtain a defined sequence of topologies to be investigated. See R. 406567.

[0042] 7. The topologies T with the most cost-effective (optimal) component values ​​p will be selected. opt for those stationary operating conditions o w Each component that places the highest demands (loads) on the component in question, in the circuit under its best control conditions, which are achieved through the optimal switching sequence SS. optwith the associated optimal switching time interval vector At opt and the associated optimal initial state vector zo opt The topology is determined and ordered. From the ordered list, the most suitable topology with the lowest value of a given decision objective function V can then be selected.

[0043] The decision objective function is an estimate of the generalized effort required to implement the topology in question. This estimate is based on information available at the topology level regarding signal waveforms, component values, and their limiting loads (maximum values, etc.). For example, the cost of an inductor can be determined based on the maximum energy that can be stored in the component.

[0044] The process is based on a number of possible topologies, from which one or more suitable topologies are selected based on the given requirements and costs.

[0045] First, the requirements for the power electronic circuit are formulated. This relates, on the one hand, to the number and source characteristics of the ports (voltage source / current source) and, on the other hand, to the operating points to be defined. m , m = 1 . . M.

[0046] Subsequently, the topologies suitable for analysis will be specified as netlists, comprising diodes and transistors (or active components as switches) as well as passive components. The switches are assumed to be binary switches that can be either open or closed.

[0047] The switch configurations that will be considered further in the subsequent procedure are determined. For this purpose, all switches in the original network T are first identified. org real switches and diodes located there are replaced by ideal R. 406567

[0048] 8

[0049] Switches are replaced. For the resulting idealized network Tid with exclusively ideal switches and passive components, the set SAH of all possible 2 K Switch configurations are formed with K as the number of switches in the idealized network.

[0050] From this set, all switch configurations valid for the idealized network are filtered out and subdivided into the subsets Scon for continuous operation and SD™ for discontinuous operation. The discontinuous operation subset can be further subdivided into Sidm and SEdm, depending on whether the discontinuous operation is generated by a purely internally triggered diode or by an externally triggered real or ideal switch. The procedure for filtering out the relevant switch configurations is based on the fundamental intersections and mesh equations of the idealized network, which can be derived from the network's topological description in the form of its incidence matrix using methods from electrical network theory. See, for example, [Chua, U., Ling, P., "Computer-Aided Analysis of Electronic Circuits", Prentice-Hall, Englewood Cliffs, NJ, 1975],

[0051] Finally, irrelevant valid switch configurations of the idealized network are identified for the original network. Switch configurations are irrelevant if they differ from the ideal switches in the original network T due to the different behavior of diodes and real switches. org These switching configurations can never occur. They are included in the set of a priori irrelevant switching configurations Si rr collected.

[0052] To determine these switch configurations, it is suitable to analyze the intersections and mesh equations that result from the fundamental intersections and mesh equations by eliminating all passive components in the intersections and meshes. The set of all valid switch configurations Spea for the original network then results from the intersection of the union of the subsets Scon for gapless operation and SD™ for gapped operation and the complement of the irrelevant switch configurations Sirr.

[0053] The idealized network is then transformed into the original network R. 406567.

[0054] 9

[0055] Torg's assigned "equivalent" network T eqThis is done by identifying, for each valid switch configuration, from the set of Spea that results in intermittent operation in the original network, those passive components whose respective states are forced to zero due to the intermittent operation.

[0056] The identification of the relevant passive components in the network is carried out by classical network analysis and subsequent detection of the network elements that result in intermittent operation. See, for example, [Chua, II., Ling, P., "Computer-Aided Analysis of Electronic Circuits", Prentice-Hall, Englewood Cliffs, NJ, 1975 and Föllinger, O., "Regelungstechnik", Hüthig Buch Verlag Heidelberg, 1992],

[0057] For these components, an artificial ideal auxiliary switch is arranged in series in the case of a capacitor, and in parallel in the case of an inductor or a controlled current source. The auxiliary switch ensures that the state of the respective component is maintained in the equivalent network when the switching event occurs. In the case of an inductor, for example, this results in a constant circulating current flowing when the auxiliary switch closes.

[0058] In this case, the state of the equivalent network differs from the state of the original network in that, while the state in the original network is also constant, it must also necessarily be zero. Therefore, the term "equivalent network" is initially only a label and not an inherent property of the derived network. The advantage gained by creating the equivalent network is achieved because all switch configurations that result in gapless operation in the original (and idealized) network result in gapless operation in the equivalent network.

[0059] With the extension of the network to include artificial auxiliary switches, the switching configurations S must also be extended accordingly to include auxiliary switch states. This is done by inserting a 0 (open switch) for each auxiliary switch of an inductor or controlled current source in the case of an originally gapless configuration and a 1 (closed switch) in the case of the originally gapping configuration in question. This is further accomplished by specifying for R. 406567

[0060] 10. Each auxiliary switch of a capacitor is assigned a 1 (closed switch) in the case of an originally gapless configuration and a 0 (open switch) in the case of the originally gapping configuration in question.

[0061] The class of networks that arises due to the presence of purely ideal switches, passive linear components, and the absence of discontinuous operation (due to ideal auxiliary switches) can be mathematically described by a purely externally controlled sequence of linear subsystems for which analytical partial solutions to the corresponding state equations are possible. The step-by-step procedure for deriving these analytical partial solutions is based on well-known principles of linear network and system theory and is implemented using transition matrices, which are well-known for linear systems in state space. See, for example, [Chua, U., Ling, P., "Computer-Aided Analysis of Electronic Circuits", Prentice-Hall, Englewood Cliffs, NJ].[ , 1975 and Föllinger, O, “Regelungstechnik“, Hüthig Buch Verlag Heidelberg, 1992], This enables the construction of an efficient, accurate, and robust network simulator for calculating the network parameters current, voltage, magnetic flux, and magnetomotive force as a function of the given input parameters and decision variables. The decision variables can include the respective component vector p as well as the switching sequence SS with the associated switching time interval vector At and the associated initial state vector zo.

[0062] The required agreement between the solutions of the original network and the equivalent network is achieved in a final step by making solutions of the equivalent network with non-zero states unattractive in the case of discontinuous operation of the original network during optimization of the objective function F. This is done using penalty function terms, so that these solutions are automatically eliminated when searching for an optimal solution. For inductors and controlled sources, the current through the relevant auxiliary switch is suitable as the basis for constructing such penalty function terms, while for capacitors, the voltage across the relevant auxiliary switch is appropriate. The penalty function term itself is derived, for example, from the average weighted power loss of the auxiliary switch, which the auxiliary switch generates by assigning an artificial line resistance value. By successively increasing this resistance value, the R...406567.

[0063] 11

[0064] As part of the optimization process, the switch current or the switch voltage is successively reduced towards zero until it lies below a predetermined residual fault limit.

[0065] The underlying objective function F can, for example, be the average power loss occurring in the equivalent network, which occurs during the transmission of the average power P. avg from the input gates to the output gates at a specific stationary operating point in the network. In this case, the objective function F can be divided into, for example, three components.

[0066] F = Fq + F s + F p divide. F describes this. q for example, the proportion of current conduction losses occurring in the passive and active components as well as the voltage-induced losses, F s the proportion of switching losses occurring in the switches and F pArtificially generated penalty losses due to the violation of constraints to be met in the solution of the equivalent networks.

[0067] One such constraint is, for example, that auxiliary switch currents for inductors and controlled current sources, and auxiliary switch voltages for capacitors in the equivalent network, must always be zero, meaning less than a predefined residual fault limit. Another constraint is, for example, the requirement that the currents and voltages of an ideal switch in the equivalent network, which replaces a real or diode switch in the original network, do not violate the current-voltage characteristic curve, which is restricted by the presence of real or diode switches in the original network. Furthermore, it is also conceivable to penalize exceeding limits for the currents, voltages, magnetic fluxes, and magnetomotive forces of the components.Whether penalty function terms take effect in the underlying objective function F can be determined by a user-adjustable multiplicative coefficient, which is greater than zero when the penalty term is activated and equal to zero otherwise. These coefficients must be specified for all penalty terms in the objective function definition in the netlist. R. 406567.

[0068] 12

[0069] When minimizing the underlying objective function F, the system simulation required to calculate the objective function must also consider constraints. These constraints, given a component parameter vector p and a switching sequence SS, guarantee the periodicity of the solutions, the average power to be transmitted at the operating point, the positivity of the switching time intervals, and the fact that the sum of all switching time intervals equals the period. These constraints can be described as equational and inequality constraints, depending on the relevant decision variables for the underlying optimization problem: the switching time interval vector At and the associated initial state vector zo.This allows the underlying minimization of the average power loss in the equivalent network as a function of the relevant decision variables At and zo to be expressed mathematically by a nonlinear program (NP), the solution of which represents a standard optimization procedure, see for example in [Papageorgiou, M, “Optimierung, Statische,dynamisch und stochastic Verfahren für die Anwendung“, Oldenbourg Verlag, München Wien , 1991],.

[0070] In a subsequent step, based on the previously determined set of valid, i.e., realizable switch configurations Spea, the set of all possible realizable switching sequences SSAII is generated.

[0071] In this context, a switching sequence is considered feasible if it consists only of the sequence of feasible switching configurations Spea, is periodic, and each switch is turned on and off at most once within a switching period. This limits the number of all possible feasible switching sequences SSAII to a finite number.

[0072] The optimal achievable switching sequence SS for a specific operating point Opt This then results from the optimized value of the underlying objective function F. opt , if all feasible switching sequences in the previously performed optimization problem are specified as fixed switching sequences.

[0073] The effort required to determine the optimal, achievable switching sequence SS Opt This can be significantly reduced if, instead of all feasible switching sequences SSAII, only the dominant switching sequences SSoom are specified in the procedure. R. 406567

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[0075] A switching sequence is considered dominant if it is realizable and not part of another realizable switching sequence. Thus, a dominant switching sequence cannot be created by reducing (removing one or more realizable switching configurations) another realizable switching sequence. Conversely, the set of dominant switching sequences contains all realizable switching sequences as subsequences.

[0076] This means that it suffices to specify the dominant switching sequences when solving the underlying optimization problem and to determine whether the switching time intervals occurring in the optimal solution, which are assigned to the switching configurations within the switching sequence, are equal to zero in the sense of falling below a predefined limit. In this case, the relevant switching configurations can be removed from the switching sequence and the optimization repeated with the reduced switching sequence. This procedure is repeated until no further reductions are indicated by the assigned switching time intervals At.

[0077] The underlying optimization problem uses the network model to determine the optimal switching time intervals or the optimal timing, including the optimal switching time interval vector At. opt and the associated optimal initial state zo optThe circuit is optimized for a given switching sequence SS. The optimization optimizes the underlying objective function F (losses) as a function of the decision variables At and zo.

[0078] Then, for a given set of initial component values ​​p, ini the passive and active components and for all specified operating points o m , m=1... M the corresponding optimal switching sequences SS m opt with the associated optimal switching time intervals At m opt and initial states opt This is determined starting from the set of all realizable switching sequences SSAII or dominant switching sequences SSoom, based on the procedure described above. The solution to the previously described underlying optimization problem yields the corresponding optimal values ​​At. m opt and zom optThe analytical simulation model used in the context of the underlying optimization for the equivalent network T eq This is generated automatically. R. 406567

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[0080] Besides the optimal solution SS m opt ', At m opt and so m opt The next best solutions (K) are also considered, provided they generate a subordinate objective function value F that lies above the optimal objective function value within a predefined limit. The most promising switching sequences thus determined are then included in the set of most promising switching sequences SS. m prom In summary, the parameter K can also be specified and helps define the set SS. m prom to limit it to a practical level.

[0081] Then, based on a found optimal solution, SS m opt ', At m optand zom opt and the number of the most promising switching sequences SS m prom and the given set of initial component values ​​p ini for all specified operating points o m , m=1... M optimized values ​​of the passive and active components were determined.

[0082] For this purpose, the higher-level scalar decision objective function V is used, which represents a cost measure depending on the active and passive component values ​​and enables the ranking of different topologies in terms of increasing costs for the active and passive component values.

[0083] In the overarching optimization problem, the decision objective function V is minimized as a function of the component values ​​p. To achieve this, the optimization algorithm varies the overarching decision variable p in a suitable manner to progress to the minimum. Since the variation of the component values ​​also determines the optimal solutions SS m opt', At m opt and so m opt Since the subordinate optimization problem is affected, the switching sequences with their associated switching time intervals and initial states must be recalculated for each change (variation) of the component values ​​(calculated in the sense of a renewed subordinate optimization of the objective function F (e.g., losses) of the decision variables SS, At, and zo when p is changed). To reduce the effort involved, instead of the set of all realizable switching sequences SSAII or the dominant switching sequences SSoom, only the most promising switching sequences SS can be considered at this point. m prom , m=1... M are taken into account. This measure only slightly impairs the quality of the solutions, but significantly reduces the computational effort.

[0084] Calculating the optimal solutions SS m opt ', At m opt and so m optHowever, R. 406567 also remains.

[0085] 15 then a very computationally intensive procedure, so the calculation of the decision objective function V for the optimization of the component values ​​should be performed as infrequently as possible.

[0086] The optimization with the objective function F and the optimization of the component values ​​with the decision objective function V are two different optimizations that are nested within each other. The underlying optimization of the objective function F (e.g., based on losses) returns the optimized switching sequence SS as its return values. opt , the associated optimized switching time intervals At opt and the associated optimal initial state zo optThis underlying optimization is parameterized by the component values. If these change, the underlying optimum also changes, and thus the optimal subordinate decision variables. The superimposed optimization of the decision objective function V (e.g., costs) is directly determined via the superimposed decision variable p (component values) and via the optimal subordinate decision variables SS, which depend on p. opt (p), At opt (p) and zo opt (p) indirectly led to the optimum by the optimizer.

[0087] For such optimization problems, the state of the art provides very powerful methods based on so-called adaptive surface response techniques. For further details, see, for example, the Matlab 2019b, “Global Optimization” documentation.

[0088] In a subsequent step, the result for the equivalent network is translated into a result for the original network.

[0089] The translation is achieved by using the optimal switching sequence SS. opt All columns that may be associated with diode switches and auxiliary switches in the equivalent network are removed.

[0090] Subsequently, in an optional final step, the results for the original network can be validated using an independent external simulation tool with internally triggered diode switches. For this purpose, the optimal solutions (all optimal time signals in the equivalent network) of the method described here are simulated with the external R. 406567.

[0091] 16

[0092] The simulation tool was used to recreate the simulations in the original network and the results were compared. For optimization, the deviations for all signals must remain below a predefined residual error limit.

[0093] The network is simulated using the component values ​​for the set of optimal decision variables of the overall problem. That is, for the optimal p opt (Component values) SS opt (p opt ) (Sequence sequence), At opt (p opt ) (time switching intervals) and zo opt (p opt ) (Initial states).

[0094] Brief description of the drawings

[0095] The embodiments are explained in more detail below with reference to the accompanying drawings. These show:

[0096] Figure 1 is a flowchart illustrating the process of a procedure for automatically determining an optimal topology of a power electronic circuit;

[0097] Figure 2 schematically shows the definition of requirements for a network regarding the gates and power transmission;

[0098] Figure 3 shows an exemplary topology of a buck converter;

[0099] Figure 4 illustrates a process of switching configuration analysis;

[0100] Figure 5 shows a representation of the basic network theory concepts for classical network analysis;

[0101] Figure 6 shows a division of the considered network classes into tree and connecting branch components and the introduction of an ordering system based on the given numbering for the different component types as well as the associated fundamental intersections and mesh equations in matrix form;

[0102] Figure 7 shows a classification of unphysical and undesired operating modes for given switch configurations using the topological R. 406567

[0103] 17

[0104] Submatrices from the fundamental intersection and mesh equations;

[0105] Figure 8 shows a classification of desired and undesired modes for gapless operation for given switch configurations using the topological submatrices from the fundamental intersection and mesh equations;

[0106] Figure 9 shows a reduction of the fundamental intersections and mesh equations by removing all terms containing energy storage.

[0107] Figure 10 shows a compilation and rearrangement of the remaining intersection and mesh equations so that they can be checked for contradiction when the corresponding bi- and unidirectional characteristics of the original components are inserted.

[0108] Figure 11 shows a comparison of an original network and an equivalent network with associated optimal switching sequence matrices;

[0109] Figure 12 shows a process for creating a state space model for the given class of valid networks, on the basis of which equivalent networks can be created.

[0110] Description of embodiments

[0111] Figure 1 shows a flowchart illustrating the process of a method for automatically determining the optimal topology of a power electronic circuit. The method is computer-implemented and supports the development of hardware with a power electronic circuit.

[0112] In step S1, requirements for the power electronic circuit are formulated. These requirements can be determined by defining the boundary conditions under which the subsequent topology selection is to take place. In particular, the requirements for the power electronic circuit are defined in R. 406567.

[0113] 18

[0114] A circuit is defined by a number of power connections, each with an electrical voltage and current, using two-port or multi-port parameters. The behavior of the two-port or multi-port can be advantageously described in simulations by the corresponding state equations in the time domain.

[0115] Figure 2 illustrates, for a network, a formulation of the requirements by defining the boundary conditions under which the analysis and selection of the topology are to take place, in order to select a suitable topology. In particular, the requirements for the power electronic circuit are defined by a number of power connections, each with an electrical voltage and current, using two-port or multi-port parameters. The behavior of the two-port or multi-port can be advantageously described in simulations by the associated state equations in the time domain.

[0116] For example, the following requirements can be specified for a topology with two ports.

[0117] PortDef(1).Type = [0];

[0118] PortDef(2).Type = [0];

[0119] OpPoint(1).lnputVec = [-300;-200];

[0120] OpPoint(1).AvgOutputVec = [13,4;-20];

[0121] OpPoint(2).lnputVec = [-400;-100];

[0122] OpPoint(2).AvgOutputVec = [10;-40]

[0123] The first two lines describe, by way of example, the type of input and output ports, of which there are two in this example. 0, for instance, describes a voltage source and 1 a current source. Line 3 describes the value of the source voltages or source currents at the ports in operating point 1, where, for example, the consumer reference arrow system is also used for sources. Line 4 describes the value of the reaction voltages or currents averaged over one period at the ports in operating point 1. The product of the time-constant source value and the averaged reaction value then yields the average power flowing into (negative product) or out of (positive product) the port. Lines 5 and 6 describe the requirements of the second operating point accordingly. R. 406567

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[0125] The requirements for an application are specified by the user in the form of source characteristics and a list of relevant steady-state operating points, and are therefore part of the specification. Typically, the source variables are voltages and the corresponding response variables at the gates are the averaged currents. Here, the possible topologies are specified and defined with regard to the number and characteristics (voltage source / current source) of the gates.

[0126] For example, if a DC / DC converter is to be implemented for a voltage conversion from 400 V to 100 V for a maximum power transmission of 4 kW, the requirement is a two-port power converter with voltage source characteristics at both ports and an average current at the ports of 10 A and 40 A. The inclusion of further operating points with, for example, different voltage or power levels in the requirements list is the responsibility of the circuit designer and depends on the application.

[0127] Furthermore, the requirements can specify the manner in which the stationary transmission of the average electrical power P is carried out. m avg , m = 1 . . M at a specific operating point, include. The set of specific operating points for the given requirements can be defined by different time-constant input variables x. m , m = 1 . . M and different output variables y averaged over a switching period mavg The values ​​of m = 1 .. M are defined. The type of input and output variables is determined by defining the source characteristics (current source / voltage source). In principle, any number of operating points can be defined. However, due to the resulting increase in computation time, it is advisable to limit oneself to the characteristic operating points.

[0128] In step S2, a multitude of possible topologies are provided, which can be retrieved, for example, from a database. The topologies can be specified as netlists containing diodes and transistors or active components as switches, as well as passive components such as capacitors, inductors, resistors, and transformers. The topologies generally only specify the interconnection of the components and not the component values. The switches are represented here as binary switches R. 406567.

[0129] 20 assumed, which can either be open or closed.

[0130] The topology is defined by the topology information T, which is mathematically characterized by the associated topological matrices (e.g., incidence or adjacency matrices) and specifies how one component in the circuit is connected to another. The topology information T is part of the netlist and is further processed algebraically using incidence matrices, which are well-known from computer-aided circuit description.

[0131] For example, the topology-describing part of a netlist can be used for a

[0132] The subtractors according to Figure 3 are given as follows: par.EleNet(1).VS(1).CompNum = 1 ; par.EleNet(1).VS(1).Branch = 1 ; par.EleNet(1).VS(1).NodeSource = 4; par.EleNet(1).VS(1).NodeSink = 1 ; par.EleNet(1).VS(2).CompNum = 2; par.EleNet(1).VS(2).Branch = 2; par.EleNet(1).VS(2).NodeSource = 4; par.EleNet(1).VS(2).NodeSink = 3; par.EleNet(1).S(1).CompNum = 1 ; par.EleNet(1).S(1).Branch = 3; par.EleNet(1).S(1).NodeSource = 1 ; par.EleNet(1).S(1). NodeSink = 2; par.EleNet(1).S(2).CompNum = 2; par. EleNet(1).S(2). Branch = 4; par.EleNet(1).S(2).NodeSource = 4; par.EleNet(1).S(2). NodeSink = 2; par.EleNet(1).L(1).CompNum = 1 ; par. EleNet(1).L(1). Branch = 5; par.EleNet(1).L(1).NodeSource = 2; par.EleNet(1).L(1). NodeSink = 3;

[0133] The references VS, S and L stand for voltage sources, switches and inductances.

[0134] The provided topologies are evaluated in the following steps. R. 406567

[0135] 21

[0136] In step S3, the switch configurations that will be considered further in the subsequent procedure are determined. This procedure is explained in conjunction with Figure 4.

[0137] To automatically determine and classify valid switch configurations, it is necessary to ascertain which possible switch configurations exist for a given power electronic circuit. Switches, which can be formed by transistors or diodes, for example, generally have two states: "0" for an open switch and "1" for a closed switch. Switch types can be distinguished as externally triggered and internally triggered switches.

[0138] Externally triggered switches are ideal switches (e.g., transistors, MOSFETs, etc.) that can be controlled, at least predominantly, by independent external control signals. Internally triggered switches are typically diodes, where the switch states are controlled by the current and / or voltage state in the circuit network, which depends on the continuous dynamics of the circuit network. Switch configurations in the original network that result in infinitely large currents or voltages are considered physically unrealizable. Switch configurations are undesirable if they lead to physically realizable but unsuitable circuit behavior. The undesirable switch configurations and the physically unrealizable switch configurations correspond to the unrealizable switch configurations.

[0139] The realizable switching configurations in the original network that always result in a defined current path or voltage loop are called realizable continuous switching configurations. Realizable switching configurations that force currents or voltages of a passive element to the specific value of 0, since in this case no defined current path or voltage loop exists, are called realizable discontinuous switching configurations. If the realizable discontinuous switching configurations are caused by an internally triggered switching state, e.g., caused by a diode, they are called realizable internally triggered switching configurations. R. 406567

[0140] 22

[0141] Switch configurations caused by an externally triggered switching state of an ideal switch are referred to as realizable externally triggered switch configurations.

[0142] To avoid manually determining the feasible switch configurations, the possible switch configurations in a network can be determined automatically.

[0143] First, all data in the original T network will be processed. org The real switches and diodes present are replaced by ideal switches. For the resulting idealized network Tid with exclusively ideal switches and passive components, the set SAH of all possible 2 KSwitch configurations are formed with K as the number of switches in the idealized network. From this set, all valid switch configurations for the idealized network are filtered and divided into the subsets Scon for continuous operation and SD™ for discontinuous operation. The subset for discontinuous operation can be further subdivided into the subsets Sidm and SEdm, depending on whether the discontinuous operation is generated by a purely internally triggered diode or by an externally triggered real or ideal switch.

[0144] The following section aims to automatically determine all feasible switch configurations of a topology.

[0145] The procedure for filtering out the feasible switch configurations from all possible switch configurations (SAH) is based on the fundamental intersections and mesh equations of the idealized network, which can be derived from the network's topological description in the form of its incidence matrix using methods from electrical network theory. See, for example, [Chua, U., Ling, P., "Computer-Aided Analysis of Electronic Circuits", Prentice-Hall, Englewood Cliffs, NJ, 1975],

[0146] This is illustrated in Figure 5a using the example of the electrical network of a simple bidirectional DC / DC converter with two capacitors, two inductors and four switches, which in the given switch configuration (S1 open, S2 closed, S3 open and S4 closed) are provided by ideal voltage sources (switches R. 406567).

[0147] Figure 5b illustrates how the input and output gates are represented by closed gates (23) and open switches (current sources). In this example, the input and output gates have voltage source characteristics. After entering the nodes N1-N6 into the network, a directed graph can be assigned to it, as shown in Figure 5b. In this graph, the nodes represent the network nodes, and the branches correspond to the connections (components) between the nodes. The direction of the branches in the graph is initially chosen arbitrarily and corresponds to the direction of current and voltage in the components. Since the direction of current and voltage is the same regardless of the component, the method is based on the consumer direction system. The graph can be divided into two sets: the set of tree branches and the set of connecting branches. The set of tree branches connects all nodes of the graph without forming a closed loop or circuit.In the example shown in Figure 5b, the tree branches are represented by dashed arrows. The connecting branches form the remainder of the graph. They are represented by solid (black) arrows in the example shown in Figure 5b. By adding the connecting branches to the tree, closed loops or meshes are created. Each branch can be assigned a branch voltage and a branch current, which can be summarized in the branch voltage vector u and the branch current vector i. The dimension of the vectors is determined by the number of branches B in the graph. The complete incidence matrix A. orgThe incidence matrix of the directed graph has N rows, where N is the number of nodes in the graph, and B columns. It contains zero entries everywhere except at the points where a branch originates from or terminates at a node. If a node is the starting node for a branch, a 1 is entered at the corresponding position in the matrix; in the case of a termination node, a -1 is entered. Since the complete incidence matrix is ​​overdetermined by one degree of freedom, deleting a row generates the reduced incidence matrix A. We further assume that the last row, and thus the node with the highest number, is always removed. We also assume, by convention, that this is the reference node for the ground potential in the electrical network.Using the incidence matrix, B - N + 1 independent mesh equations and N - 1 independent intersection equations can now be formulated, which are known as Kirchhoff's mesh and node equations and must be satisfied as constraints by every electrical network. In compact vector notation, these equations can be expressed by R. 406567.

[0148] 24 o = Bu or o = Di with the mesh matrix B and the intersection matrix D. Network theory provides tree-finding methods for determining a tree in the network graph, which are described in detail in [Chua, II., Ling, P., "Computer-Aided Analysis of Electronic Circuits", Prentice-Hall, Englewood Cliffs, NJ, 1975]. This allows the incidence matrix to be expressed in the form

[0149] A = (A T|AJ) to transform, where the submatrix AT describes the tree and Aj the connecting branches. Since the submatrix AT is invertible, it can be transformed by left multiplication with the inverse submatrix AT'. 1 the fundamental intersection matrix

[0150] D = (l T | Dj). This is called fundamental because the submatrix DT associated with the tree is a diagonal matrix IT. Thus, each row of the fundamental intersection matrix corresponds to a section through the network such that the intersection contains exactly one tree branch and otherwise only connecting branches. This is shown by way of example in Figure 5c. The fundamental mesh matrix is ​​derived from the fundamental intersection matrix by

[0151] B = (B T | IJ) = (-Dj T | lj).

[0152] This is called fundamental because the submatrix Bj, which is assigned to the connecting branches, is a diagonal matrix Ij. Thus, each row of the fundamental mesh matrix corresponds to a circuit in the network such that the mesh contains exactly one connecting branch and otherwise only tree branches. This is shown by way of example in Figure 5d. R. 406567

[0153] 25

[0154] If one further selects the ordering system shown in Figure 6a for the numbering of the branches ZW in the tree and co-tree JB (connecting branches) of the subnetworks, which result when one interprets closed switches in the idealized network as voltage sources with a source voltage of 0 V and open switches as current sources with a source current of 0 A (tree branches with voltage sources are numbered consecutively first, then the closed switches etc. follow), a fine structure of the fundamental intersection equations and fundamental mesh equations according to Figure 6b and c results.

[0155] The topological submatrices Fj appearing in this fine structure according to Figure 6b and c xx(where x represents a placeholder for the components occurring in the network: 0 for voltage source, S for closed switch, C for capacitance, L for inductance, K for controlled current source, G for open switch, and H for current source) The entries in the connection branches reveal which components are connected to the corresponding component in the tree branch. For example, the topological submatrix FJLL with non-zero entries describes an intersection with an inductor in the tree branch ITL and further inductors in the connection branches FJLL. This allows the subnetworks to be checked for specific critical component interconnection configurations that result in non-physical or undesirable transmission behavior by analyzing the submatrix entries in conjunction with the corresponding identity submatrix (e.g., ITL).For undesired switch configurations, which are referred to as critical in the following, the fundamental intersection equations with the dashed topological submatrices and the fundamental mesh equations with the solid outlined submatrices are relevant according to Figure 6b and c.

[0156] Figures 7 and 8 show, on the right, the critical element configurations resulting from the critical fundamental intersection equations, and on the left, the critical element configurations resulting from the critical fundamental mesh equations. The first column denotes the respective critical element configuration, and the second column the corresponding conditions for the topological submatrices for the occurrence of R. 406567

[0157] The third column describes the interpretation of such a configuration, and the fourth column describes the designation of the critical switch configuration or mode. Non-physical critical configurations are marked with a cross, undesirable critical configurations with an index finger, and tolerable critical configurations with a check mark. All other switch configurations are non-critical and correspond to physically meaningful continuous operating modes.

[0158] The intersections and mesh equations derived from the fundamental intersections and mesh equations by eliminating all passive components within the intersections and meshes are then analyzed to determine whether they lead to unsatisfiable mesh or node equations in the original network when ideal switches are replaced by the original real switches or diode switches. If such contradictions occur, the corresponding switch configuration in the equivalent network is irrelevant to the original network and therefore need not be considered further. Thus, all switch configurations of the derived circuit that cannot occur a priori in the original network and are therefore irrelevant in the derived circuit from the outset can be determined.For each switch configuration in the derived circuit, it is checked whether the sign of the intersection currents of closed ideal switches contradicts the switching state of the corresponding diodes in the original circuit, and whether the sign of the loop voltage when the switch is open contradicts the switching state of the corresponding diodes or real switches in the original network. After this step, the realizable continuous switching states, the internally triggered realizable discontinuous switching states, and the externally triggered realizable switching states are identical in both the derived circuit and the original network.

[0159] Figures 9 and 10 show the procedure steps for determining the set of irrelevant switch configurations. The starting point is again the fundamental intersection and mesh equations of the subnetworks (left). The aim of the procedure is to construct all intersections in the subnetworks that do not contain components in the form of capacitors, inductors, and controlled current sources. These intersections are independent of R. 406567

[0160] 27. The dynamic state of the subnetworks allows for a priori analysis of potential contradictions. To this end, all fundamental intersection and mesh equations are first rearranged according to Figures 9a and 9b, and all fundamental intersections and meshes containing capacitances, inductances, and controlled current sources in the tree and connecting branches according to Figures 9c and 9d are eliminated, since not all capacitances, inductances, or controlled current sources can be eliminated from these equations using elementary algebraic transformations. Furthermore, all intersection and mesh equations containing only independent sources can be removed, as these are identical in the original network and the derived idealized network. The remaining intersection and mesh equations must then be analyzed for any contradictions between the original network and the idealized network.According to Figure 9 e and f, contradictions can occur in the original network only with diodes when switches are closed, and with both diodes and real switches when switches are open.

[0161] In the remaining intersection and mesh equations, all capacitances, inductances, and controlled current sources can now be eliminated by elementary algebraic transformations, leaving the intersection and mesh equations shown in Figures 10a and 10b. The corresponding topological submatrices have become zero matrices due to these transformations. This allows all capacitance, inductance, and controlled current source currents and voltages to be eliminated from the system of equations. Furthermore, the third and first subsystems of equations in the intersection and mesh equations, respectively, are irrelevant for the analysis for the following reason.

[0162] These systems of partial equations describe fundamental intersections or meshes with only current sources and open switches, or with only voltage sources and closed switches. These equations are either also satisfied in the original network, meaning that diodes or real switches are open or closed under the given conditions, or they are not satisfied, meaning that diodes or real switches are closed or open under the given conditions. In the first case, there is no contradiction, and in the second case, the comparison is not made using this system of partial equations, but rather using the remaining ones. R. 406567

[0163] 28

[0164] Systems of partial equations with closed or open switches instead of open or closed switches.

[0165] The two remaining systems of intersection and mesh equations are divided according to Figures 10c and d, and the currents of closed switches and the voltages of open switches are divided into bidirectional and unidirectional components, depending on whether the switch in question is an ideal switch (0), a real switch (1), or an isolated diode (2) in the original network. It is then checked whether the intersection and mesh equations can still be satisfied under the signs specified by the original network.

[0166] Once it has been clarified which of the valid switch configurations of the idealized network determined in this way are irrelevant for the original network, these switch configurations are included in the set of a priori irrelevant switch configurations Si rrcollected. The set of all valid (realizable) switch configurations Spea for the original network is then obtained from the intersection of the union of Scon and Sam and the complement of Si. rr .

[0167] In step S4, the idealized network Tid is transformed into the “equivalent” network T assigned to the original network Torg. eq educated.

[0168] For each valid switch configuration, from the set Spea that results in discontinuous operation in the original network and can therefore be denoted by Sam, those passive components are identified whose state is forced to zero due to the discontinuous operation. For these components, an artificial ideal switch is then inserted in series in the case of a capacitor and in parallel in the case of an inductor or a controlled current source. This ensures that the state of the respective component is maintained when the corresponding switching event occurs in the equivalent network. In the case of an inductor, for example, this leads to the flow of a constant circulating current when the auxiliary switch is closed.

[0169] This procedure is shown in Figure 11 using the example of inductor L12. With switches S13 and S14 open simultaneously in the original network a), the R is 406567.

[0170] 29

[0171] The inductor is currentless because there is no longer a closed current path containing this component. This current-gap operation is avoided in the equivalent network b) by the fact that the additional artificial auxiliary switch S17 allows the inductor current, which is present at the switching time, to continue circulating in the loop when it closes precisely at that moment.

[0172] In this case, the state of the equivalent network differs from the state of the original network in that, while the state in question is also constant in the original network, it must also be equal to zero. The advantage of creating the equivalent network becomes apparent because, as a result, all switch configurations that lead to gapless operation in the original (and idealized) network result in gapless operation in the equivalent network.

[0173] With the extension of the network to include artificial auxiliary switches, the switching configurations S must also be extended accordingly to include auxiliary switch states. This is done by inserting a 0 (open switch) for each auxiliary switch of an inductor or controlled current source in the case of an originally gapless configuration and a 1 (closed switch) in the case of the corresponding originally gapless configuration. This is further accomplished by inserting a 1 (closed switch) for each auxiliary switch of a capacitor in the case of an originally gapless configuration and a 0 (open switch) in the case of the corresponding originally gapless configuration.

[0174] The class of networks that arises due to the presence of purely ideal switches, passive linear components, and the absence of discontinuous operation due to ideal auxiliary switches can be mathematically described by a purely externally controlled sequence of linear subsystems for which the derivation of analytical partial solutions to the associated state equations is possible. The step-by-step procedure for deriving these analytical partial solutions is shown in Figure 12. It is based on well-known principles of linear network and system theory and is implemented using transition matrices, which are well-known for linear systems in state space. See, for example, [Chua, II., Ling, P., "Computer-Aided Analysis of Electronic Circuits", Prentice-Hall, Englewood Cliffs, NJ, 1975 and Föllinger, R. 406567].

[0175] 30

[0176] O, “Control Engineering”, Hüthig Buch Verlag Heidelberg, 1992],

[0177] This enables the construction of an efficient, accurate and robust network simulator for calculating the network parameters current, voltage, magnetic flux and magnetomotive force as a function of the given input parameters and decision variables.

[0178] The required agreement between the solutions of the original network and the equivalent network is achieved in a final step by making solutions of the equivalent network with non-zero states unattractive in the case of discontinuous operation of the original network during optimization of the objective function F. This is done using penalty function terms, so that these solutions are automatically eliminated when searching for an optimal solution. For inductors and controlled sources, the current through the relevant auxiliary switch is suitable as the basis for constructing corresponding penalty terms, while for capacitors, the voltage across the relevant auxiliary switch is appropriate. The penalty term itself is derived, for example, from the average weighted power loss of the auxiliary switch, which the auxiliary switch generates by assigning an artificial line resistance value. By successively increasing this resistance value, the switch current or the voltage across the auxiliary switch is reduced.The switch voltage was successively reduced towards zero during optimization until it was below a predetermined residual fault limit.

[0179] The underlying objective function F can, for example, be the average power loss occurring in the equivalent network, which occurs during the transmission of the average power P. avg from the input gates to the output gates at a specific stationary operating point in the network. In this case, the objective function F can be divided into, for example, three components.

[0180] F = Fq + F s + F p divide. F describes this. q for example, the proportion of current conduction losses occurring in the passive and active components as well as the voltage-induced losses, F s the proportion of switching losses occurring in the switches and F pArtificially generated penalty losses due to the violation of required constraints in the solution of the equivalent R. 406567

[0181] 31

[0182] Networks.

[0183] One such constraint is, for example, that auxiliary switch currents for inductors and controlled current sources, and auxiliary switch voltages for capacitors in the equivalent network, must always be zero, meaning less than a predefined residual fault limit. Another constraint is, for example, the requirement that the currents and voltages of an ideal switch in the equivalent network, which replaces a real or diode switch in the original network, do not violate the current-voltage characteristic curve, which is restricted by the presence of real or diode switches in the original network. Furthermore, it is also conceivable to penalize exceeding limits for the currents, voltages, magnetic fluxes, and magnetomotive forces of the components.Whether penalty function terms take effect in the underlying objective function F is determined by a user-configurable multiplicative coefficient, which is greater than zero when the penalty term is activated and equal to zero otherwise. These coefficients must be specified for all penalty terms in the objective function definition in the netlist.

[0184] When minimizing the underlying objective function F, the system simulation required to calculate the objective function must also consider constraints. These constraints, given component parameters p and a switching sequence SS, guarantee the periodicity of the solutions, the average power to be transmitted at the operating point, the positivity of the switching time intervals, and that the sum of all switching time intervals equals the period. These constraints can be described as equational and inequality constraints, depending on the relevant decision variables for the underlying optimization problem: the switching time interval vector At and the associated initial state vector zo.This allows the underlying minimization of the average power loss F in the equivalent network as a function of the relevant decision variables At and zo to be expressed mathematically by a nonlinear program (NP), the solution of which represents a standard optimization procedure; see, for example, [Papageorgiou, M, “Optimierung, Statische,dynamisch und stochastic Verfahren für die Anwendung“, Oldenbourg Verlag, München Wien , 1991], R. 406567.

[0185] 32

[0186] In a subsequent step S5, the set of all possible realizable switching sequences SSAII is generated based on the set of realizable switch configurations Spea determined in step S3. In this context, a switching sequence is considered realizable if it consists only of the sequence of realizable switching configurations Spea, is periodic, and each switch is turned on and off at most once within a switching period. This limits the number of all possible realizable switching sequences SSAII to a finite number.

[0187] The optimal achievable switching sequence SS for a specific operating point Opt This then results from the best underlying objective function value F opt , if all feasible switching sequences in the optimization problem described in step S4 are specified as fixed switching sequences.

[0188] The effort required to determine the optimal, achievable switching sequence SSOpt The number of possible switching sequences can be significantly reduced if, instead of all realizable switching sequences SSAII, only the dominant switching sequences SSoom generated in step S6 are specified in the procedure. A switching sequence is considered dominant if it is realizable and not part of another realizable switching sequence. Thus, a dominant switching sequence cannot be generated by reducing (removing one or more realizable switching configurations) another realizable switching sequence. On the other hand, the set of dominant switching sequences contains all realizable switching sequences as subsequences.

[0189] This means that it suffices to specify the dominant switching sequences when solving the underlying optimization problem and to check whether the switching time intervals appearing in the optimal solution, which are assigned to the switching configurations within the switching sequence, are equal to zero in the sense of falling below a predefined limit. In this case, the relevant switching configurations can be removed from the switching sequence and the optimization repeated with the reduced switching sequence. This procedure is repeated until no further reductions are indicated by the assigned switching time intervals At.

[0190] In a subsequent step S7, for a given set of initial component values ​​p, ini the passive and active components and for all specified operating points o m , m=1... M the corresponding optimal R. 406567

[0191] 33

[0192] Switching sequences SS m opt with the associated optimal switching time intervals At m opt and initial states zo m opt This is determined based on the set of all realizable switching sequences SSAII or dominant switching sequences SSoom determined in step S5, using the procedure described in step S5, which is carried out in step S7.

[0193] The solution to the underlying optimization problem described in step S4 is determined in step S8, yielding the corresponding optimal values ​​At. m opt and zom opt The analytical simulation model for the equivalent network T, used within the framework of the underlying optimization and described in step S4, eq This process is automatically generated and executed in step S9.

[0194] Besides the optimal solution SS m opt ', At m opt and so mopt The next best solutions (maximum K) are also considered, provided they generate a subordinate objective function value F that lies above the optimal value within a predefined limit. The most promising switching sequences thus determined are then included in the set of most promising switching sequences SS. m prom In summary, the parameter K can also be specified and helps define the set SS. m prom to limit it to a practical level.

[0195] In step S10, based on a found optimal solution SS m opt ', At m opt and zom opt and the number of the most promising switching sequences SS m prom for all specified operating points o m , m=1... M and the given set of initial component values ​​p ini Optimized values ​​were determined for the passive and active components.

[0196] For this purpose, the higher-level scalar decision objective function V is formed, which represents a cost measure depending on the active and passive component values ​​and the signal patterns in the network and enables the ranking of different topologies in terms of increasing costs (in terms of manufacturing costs, component costs and / or effort and the like).

[0197] Since the variation of the component values ​​also determines the optimal solutions SS m opt ', At m opt and zom opt Since the switching sequences are affected, the associated switching time intervals and initial states must be re-optimized for each change in component values. This is done for all permissible switching sequences, R. 406567.

[0198] 34 alternatively only for the dominant permissible switching sequences and in step S11 for the switching time intervals and associated initial states. The simulation models required for optimization are automatically created in each case in step S12.

[0199] To reduce the effort required for re-optimization, instead of considering the set of all feasible switching sequences SSAII or the dominant switching sequences SSoom, only the most promising switching sequences SS can be considered at this point. m prom , m=1... M are taken into account. This measure presumably only slightly impairs the quality of the solutions, but significantly reduces the computational effort. The calculation of the optimal solutions SS m opt ', At m opt and so m optHowever, this remains a computationally very complex procedure, so the calculation of the decision objective function V should be performed as infrequently as possible when optimizing the component values.

[0200] For such optimization problems, the state of the art provides very powerful methods based on so-called adaptive surface response techniques. For further details, see, for example, the Matlab 2019b, “Global Optimization” documentation.

[0201] In step S13, the result for the equivalent network is translated into a result for the original network. Figures 11c and 11d illustrate the procedure for the topology shown in Figures 11a and 11b. In this case, the optimal switching sequence in the equivalent network consists of six consecutive realizable switching combinations s1 to s6. Each switching combination in the equivalent network consists of seven bits for the switches Sn to S17. The ideal switches S13 and S15 in the original network according to Figure 11a are purely internally triggered diode switches, and S17, according to Figure 11b, is an artificial auxiliary switch to eliminate discontinuous operation when, for example, S13 and S14 are open simultaneously. Since these switches do not exist in the original network or have no control connections, the corresponding columns are simply removed from the matrix of the optimal switching sequence.

[0202] Subsequently, the results for the original network can be validated in an optional step S14 using an independent external simulation tool with internally triggered diode switches. R. 406567

[0203] 35

[0204] For this purpose, the optimal solutions (all optimal time signals in the equivalent network) of the method described here are simulated in the original network using the external simulation tool and compared one-to-one. The deviations for all signals must remain below a predefined residual error limit.

Claims

R. 406567 36 Claims 1. Computer-implemented method for determining an optimal topology for a power electronic circuit, in particular a voltage converter, an inverter or a power driver, wherein the topology of the power electronic circuit can be represented by a network using a netlist, comprising the steps: Providing (S2) a variety of topologies with a respective circuit network of active and passive components, wherein the active components include semiconductor switches and / or diodes; Providing (S1) requirements for the power electronic circuit, wherein the requirements are user-defined operating points (o m specify m=1... M); Determining optimized component values ​​of the active and / or passive components for the multitude of topologies depending on an objective function (F) that evaluates the fulfillment of the requirements; Determining (S10) a respective function value of a given decision objective function (V) for the multitude of topologies depending on the assigned optimized component values; - Selecting the topology from the multitude of topologies depending on the associated function value of the decision objective function (V).

2. The method of claim 1, wherein the requirements are defined by a number of power connections, each with an electrical voltage and a current, using two-port parameters, and by the manner in which the steady-state transfer of the averaged electrical power (P) is carried out. avg ) at a specific operating point (o m m=1... M) is defined.

3. A method according to claim 1 or 2, wherein for each of the plurality of topologies the following steps are performed: o Determining (S3) a set of realizable switch configurations of the active components, wherein the set of realizable switch configurations is each one R. 406567 37 The set of realizable switch configurations (Scon) for "continuous" current or voltage behavior (gapless operation) and a set of realizable switch configurations So™ for "discontinuous" current or voltage behavior (gapless operation) includes: o Determining (S4) an equivalent network from the network of the topology that is triggered purely externally by ideal switches, where all diodes are replaced by ideal switches and each passive component associated with a switch configuration (SD™) for discontinuous current or voltage behavior is provided with an additional artificial switch; o Determining (S6) a set of all realizable switching sequences (SSpea) for realizable switching configurations (Sf ea), where the realizable switching sequences (SSpea ) are periodic, and each of the switches is turned on and off at most once within a switching period, o Analyzing (S7) the equivalent network by for a given set of initial component values ​​( in i) the active and / or passive components of the equivalent network for each of the specified user-defined operating points (o m m=1... M) an optimal realizable switching sequence (SS m opt , m=1... M) with associated optimal switching time intervals (At m opt , m=1... M) of the realizable switch configurations (Spea) and the associated best initial state values ​​(zo m opt , m=1... M) for internal states of the passive components in the equivalent network from the set of realizable switching sequences (SS m opt, m=1... M) is determined taking into account the given objective function (F) in order to determine for each operating point (o m m=1... M) to determine a function value of the objective function (F); o Determining (S8) the optimized component values ​​of the passive components using a given decision objective function (V) depending on the function value of the objective function (F) determined for each operating point and a corresponding value of the decision objective function (V). R. 406567 38 4. Method according to claim 3, wherein only dominant realizable switching sequences are considered as realizable switching sequences, the realizable Switching configurations (Spea) that are not part of any other feasible switching sequence.

5. Method according to claim 3 or 4, wherein the objective function is defined with a penalty function term when the equivalent network is augmented by an artificial switch.

6. Method according to any one of claims 1 to 5, wherein the power electronic circuit is implemented according to the selected topology.

7. Device for carrying out one of the methods according to one of claims 1 to 5.

8. Computer program product comprising instructions which, when the program is executed by at least one data processing device, cause it to perform the steps of the method according to any one of claims 1 to 5.

9. Machine-readable storage medium comprising instructions which, when executed by at least one data processing device, cause it to execute the steps of the method according to any one of claims 1 to 5.

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