Offload server and offload control method

Abstract

An offload server (100) comprises: a replacement function detection part (113) that detects a calculation portion suitable for a quantum computer; a replacement processing part (114) that replaces the calculation portion with a quantum computer processing portion implemented in an open source framework; and a control part (110) that selects, for a plurality of types of accelerators including a quantum computer (5), the highest-performance pattern from among patterns for offloading one of a calculation processing portion suitable for the quantum computer, a functional block in which a source code of a software program can be executed by an accelerator, and a loop statement of the software program.

Description

Offloading Server and Offloading Control Method

[0001] The present invention relates to an offloading server and an offloading control method for offloading a software processing program processed by a normal CPU (Central Processing Unit) to be processed at high speed in an environment where accelerators such as a quantum computer, a GPU (Graphics Processing Unit), an FPGA (Field Programmable Gate Array), and a multi-core CPU coexist.

[0002] In recent years, the deceleration of Moore's Law, which expected the speed increase of CPUs, has been predicted. From such a situation, not only CPUs but also the use of hardware such as GPUs and FPGAs in systems has been increasing. For example, Amazon (the trademark of "Amazon") provides GPU and FPGA servers as cloud instances. Also, Microsoft (the trademark of "Microsoft") has made efforts to improve Bing search efficiency using FPGAs. Also, not only GPUs and FPGAs but also IoT terminals are increasing. Furthermore, as new hardware, quantum computers, DPUs (Data Processing Unit), etc. have also emerged.

[0003] In order to speed up the system using hardware other than CPUs with the normal number of cores, it is a prerequisite to create and set programs while taking into account the nature of the hardware, and programming skills such as C language extensions such as OpenMP (OpenMulti-Processing) (registered trademark), CUDA (Compute Unified Device Architecture) (registered trademark), and OpenCL (Open Computing Language) (registered trademark) are required. Therefore, for most programmers whose mainstream development is in script languages such as Python (registered trademark) and Javascript (the trademark of "Javascript"), the hurdle is high.

[0004] Systems utilizing heterogeneous hardware such as GPUs, FPGAs, quantum computers, and DPUs, in addition to CPUs with a standard number of cores, are expected to increase in the future due to the potential for power reduction and other benefits. However, realizing these systems presents a significant skill barrier. Therefore, to remove this skill barrier and enable the full utilization of hardware other than CPUs with a standard number of cores, a platform is becoming crucial that allows programmers to write software with the same processing logic as a standard program, and then convert, configure, and adapt it to the environment in which it is deployed (GPU, FPGA, quantum computer, etc.).

[0005] Therefore, the inventors have proposed environment-adaptive software that automatically performs conversion and resource configuration for GPUs and FPGAs, enabling existing software code to be utilized on GPUs and FPGAs in the deployment environment, thereby enabling high-speed application operation. In addition, as elements of environment-adaptive software, methods have been proposed for automatically offloading loop statements and functional blocks of existing software code to GPUs and FPGAs, and for reconfiguring offloaded processing in response to changes in the operational situation (Non-Patent Documents 1-2).

[0006] A quantum computer is a computer that applies the principles of quantum mechanics to computation. While D-Wave and others use the quantum annealing method, the development of quantum computers using the more versatile quantum gate method is becoming mainstream, and many companies such as Amazon, Microsoft, Google ("Google" is a registered trademark), and IBM ("IBM" is a registered trademark) are working on this. Amazon Braket and Azure Quantum ("Azure" is a registered trademark) are offered as part of Amazon's AWS cloud and Microsoft's Azure cloud, respectively, and are available as cloud services for a limited time. By using these quantum computer clouds, the initial hardware costs of the quantum computer itself are not required.

[0007] However, in reality, quantum algorithms for solving NP (Non-deterministic Polynomial) problems such as the Traveling Salesperson Problem and prime factorization using quantum computers are researched and devised one by one by experts, making them difficult for laypeople to use. A DPU is a programmable computer processor that tightly integrates a general-purpose CPU and network interface hardware, such as NVIDIA's BlueField. DPUs are used as a replacement for conventional NICs (Network Interface Cards) and are used to offload complex network processing and other infrastructure processing from the main CPU.

[0008] Y. Yamato, "Study and Evaluation of Improved Automatic GPU Offloading Method," International Journal of Parallel, Emergent and Distributed Systems, Taylor and Francis, DOI: 10.1080 / 17445760.2021.1941010, June 2021.Y. Yamato, "Automatic Offloading Method of Loop Statements of Software to FPGA," International Journal of Parallel, Emergent and Distributed Systems, Taylor and Francis, DOI: 10.1080 / 17445760.2021.1916020, Apr. 2021. M. Mykhailova, "Teaching Quantum Computing using Microsoft Quantum Development Kit and Azure Quantum." 2023 IEEE International Conference on Quantum Computing and Engineering (QCE), Vol. 3. 2023.

[0009] However, verification using the technologies described in Non-Patent Documents 1 and 2 has so far mainly focused on conversion, configuration, and reconfiguration using existing accelerators such as GPUs and FPGAs, and has not considered automatic offloading to newly emerging hardware such as quantum computers and DPUs. In other words, the automation of offloading to individual hardware such as FPGAs, GPUs, and quantum computers has been the mainstream, and appropriate offloading to mixed environments of these hardware components has not been considered.

[0010] Quantum computers are currently offered by numerous companies, including D-Wave, Amazon, Microsoft, and IBM, and are being applied to non-deterministic polynomial (NP) problems. Some companies, such as Amazon and Microsoft, offer quantum computers on a cloud-based, hourly rental basis, making them accessible without the need for massive initial investments.

[0011] In view of these points, the present invention has been made, and its objective is to provide an offload server and offload control method that targets automatic offloading to appropriate hardware in a mixed environment where conventional CPUs, multi-core CPUs, GPUs, FPGAs, and quantum computers exist.

[0012] To solve the aforementioned problems, the following is provided: a storage unit that registers the code of the computation part suitable for a quantum computer and stores in a database the processing part for using the quantum computer with the quantum algorithm corresponding to that code; a code analysis unit that performs syntactic analysis of the source code of a software program and analyzes the computation part of a structure that can be executed by the quantum computer from the source code; a replacement function detection unit that compares the computation part of the structure analyzed by the code analysis unit with the information registered in the storage unit to detect the computation part suitable for the quantum computer; a replacement processing unit that reads the computation processing part suitable for the quantum computer detected by the replacement function detection unit from the storage unit and replaces it with a quantum computer processing part implemented with an open-source framework; an executable file creation unit that creates a quantum computer processing executable file to be executed by the quantum computer based on the quantum computer processing part replaced by the replacement processing unit; and the created quantum computer processing executable file to be turned off the quantum computer. The offload server is characterized by comprising: a quantum computer processing execution unit for loading; a processing pattern creation unit that creates patterns for offloading functional blocks of the source code of a software program that can be executed by an accelerator to one of the accelerators, and for offloading loop statements of the software program to one of the accelerators; a performance measurement unit that measures the total processing time and the quantum computer-side processing time when processing is offloaded to the quantum computer, and measures the performance of each of the patterns for offloading the functional blocks or loop statements to the accelerators by deploying them to a verification environment; and a control unit that selects the highest-performing pattern from among the processing parts of calculations suitable for the quantum computer, or the patterns for offloading functional blocks of the source code of a software program that can be executed by an accelerator, or the loop statements of the software program, for multiple types of accelerators including the quantum computer.

[0013] According to the present invention, it is possible to provide an offload server and offload control method that target automatic offloading to appropriate hardware in a mixed environment where conventional CPUs, multi-core CPUs, GPUs, FPGAs, and quantum computers exist.

[0014] This figure shows an example configuration of a network system equipped with an offload server according to an embodiment of the present invention. This is a functional block diagram showing an example configuration of an offload server according to an embodiment of the present invention. This is a hardware configuration diagram showing an example of a computer that realizes the functions of the offload server according to an embodiment of the present invention. This figure illustrates the offloading process of the offload server according to an embodiment of the present invention to a quantum computer. This figure illustrates the automatic offloading of the offload server according to an embodiment of the present invention to a mixed environment including a quantum computer. This is a flowchart of the process of constructing a quantum computer code pattern DB in the control unit of the offload server according to an embodiment of the present invention. This is a flowchart of the offloading process to a quantum computer when the control unit of the offload server according to an embodiment of the present invention operates as an environment adaptation function unit. This is a flowchart of the process of selecting patterns to offload to an accelerator. This is a flowchart of the process of selecting patterns to offload to an accelerator. This is a flowchart of the process of offloading functional blocks. This is a flowchart of the process of offloading loop statements. This figure shows the automatic offloading process of the offload server according to an embodiment of the present invention. This figure shows a search image of the control unit of the offload server according to an embodiment of the present invention using a simple genetic algorithm. This figure shows the gene sequence mapping of loop statements to a multi-core CPU. This is a flowchart of the process of selecting patterns to offload functional blocks to an accelerator. This is a flowchart of the process of selecting patterns to offload functional blocks to an accelerator. This figure shows the gene sequence mapping of loop statements to the GPU. This is a flowchart for selecting patterns to offload loop statements to the GPU. This is a flowchart for selecting patterns to offload loop statements to the GPU. This is a flowchart for selecting patterns to offload loop statements to the FPGA. This is a flowchart for selecting patterns to offload loop statements to the FPGA. This figure shows a table illustrating the performance measurement environment and specifications for offloading to a multi-core CPU, FPGA, GPU, and quantum computer in a network system of an offload server according to an embodiment of the present invention.This figure shows, in a table format, the processing time, performance improvement, and cost performance when the four applications of the offload server according to the embodiment of the present invention are offloaded to a mixed environment, with the normal CPU VM set to "1".

[0015] The following describes an offload server in an embodiment of the present invention (hereinafter referred to as "this embodiment") with reference to the drawings. This embodiment targets automatic offloading to appropriate hardware in a mixed environment where conventional CPUs, multi-core CPUs, FPGAs, GPUs, and quantum computers exist.

[0016] [Network System] Figure 1 shows an example of the configuration of a network system equipped with an offload server according to an embodiment of the present invention. As shown in Figure 1, the network system 1 includes a client PC 2 (client), a network 3, the Internet 4, a quantum computer 5 located on an external cloud 6 via the Internet 4, an offload server 100, and a verification machine 10. The placement of the offload server 100 or the verification machines 10, 11 is not limited and may be placed anywhere on the network 3. Furthermore, the verification machines 10, 11 may be located within the offload server 100 (Figure 2), or conversely, the verification machine 10 or verification machine 11 may have the offload server 100.

[0017] Client PC 2 runs user application 2a. Client PC 2 is connected to network 3 and can communicate with quantum computer 5 on external cloud 6 via the Internet 4. Client PC 2 can run applications such as the Traveling Salesperson Problem on quantum computer 5 on external cloud 6. Network 3 can be any of the following: wired LAN (Local Area Network), wireless LAN, LPWA (Low Power Wide Area), 4G, 5G, etc. Quantum computer 5 is configured to be applied to NP problems. External cloud 6 is, for example, Azure Cloud.

[0018] <Quantum Computer 5> Quantum computers 5 are computers that apply the principles of quantum mechanics to computation, and are offered by numerous companies such as D-Wave, Amazon, Microsoft, and IBM. While D-Wave and others use the quantum annealing method, the development of quantum computers using the more versatile quantum gate method is becoming mainstream, and many companies such as Amazon, Microsoft, Google, and IBM are working on this.

[0019] Quantum computers include Amazon Braket and Azure Quantum. Amazon Braket and Azure Quantum are offered as part of Amazon's AWS cloud and Microsoft's Azure cloud, respectively. Quantum computers are available for use as cloud services from companies like Amazon and Microsoft, eliminating the need for initial hardware costs for the quantum computer itself.

[0020] Quantum computer V is well-suited for calculations such as the traveling salesman problem, the knapsack problem, and prime factorization, leveraging the parallelism of quantum mechanics. However, in reality, quantum algorithms for solving NP problems like the traveling salesman problem and prime factorization using quantum computer V are being researched and devised one by one by experts, making them difficult for laypeople to use.

[0021] [Offload Server 100] Figure 2 is a functional block diagram showing an example configuration of the offload server 100. Figure 2 shows an example configuration in which the offload server 100 has verification machines 10 and 11. The offload server 100 is an environment-adaptive device that automatically offloads specific processing of an application to accelerators such as quantum computers, GPUs, FPGAs, and multi-core CPUs. As shown in Figure 2, the offload server 100 is composed of a control unit 110 (environment-adaptive function unit), an input / output unit 12, a storage unit 13, and verification machines 10 and 11.

[0022] The verification machines 10 and 11 are equipped with accelerators such as GPUs, FPGAs, and multi-core CPUs as verification environments for environment-adaptive software. As shown in Figure 1, verification machine 10 is equipped with gcc 10a, a PGI compiler 10b, CUDA 10c, a multi-core CPU 10d, and a GPU 10e. Verification machine 11 is equipped with an Intel Acceleration Stack 11a, a CPU 11b, and an FPGA 11c.

[0023] Returning to Figure 2, the input / output unit 12 consists of a communication interface 950 (Figure 3) for sending and receiving information with each device, and an input / output interface 960 (Figure 3) for sending and receiving information with input devices such as touch panels and keyboards, and output devices such as monitors.

[0024] The storage unit 13 is composed of a hard disk, flash memory, RAM (Random Access Memory), etc. The storage unit 13 stores a test case DB 131, a quantum computer code pattern DB 132 (the "storage unit" in the claim), and a mixed code pattern DB 133, as well as programs (offload programs) for executing each function of the control unit 110, and information necessary for processing by the control unit 110, such as a quantum computer processing execution file 134 and an intermediate language file 135, which are temporarily stored there.

[0025] <Test Case DB131> Test Case DB131 stores data for test items corresponding to the software under verification. For example, for a database system such as MySQL, this would include transaction testing such as TPC-C. Mixed Code Pattern DB133 stores replaceable accelerator libraries or accelerator IP cores corresponding to library names.

[0026] <Quantum Computer Code Pattern DB132> The Quantum Computer Code Pattern DB132 registers (stores) codes for computational parts suitable for quantum computers (for example, computational parts that handle the Traveling Salesperson Problem, the Knapsack Problem, prime factorization, etc.), and also stores in a database the processing parts (equivalent to libraries) for using quantum computers with the quantum algorithms corresponding to those codes.

[0027] <Mixed Code Pattern DB 133> The mixed code pattern DB 133 stores records of executable files and OpenCL, etc., that can be accelerated. The offload server 100 uses the called library as a key to retrieve executable files and OpenCL, etc., that can be accelerated from the records registered in the mixed code pattern DB 133.

[0028] <Quantum computer processing executable file 134> The quantum computer processing executable file 134 is an executable file to be executed by quantum computer processing and is implemented as quantum computer processing corresponding to the application code (Qiskit, Cirq, etc.).

[0029] <Intermediate Language File 135> The intermediate language file 135 is an executable file derived from the intermediate language. The intermediate language file 135 is placed (deployed) on the verification machine 10 equipped with a many-core CPU and GPU, or on the verification machine 11 equipped with an FPGA.

[0030] <Control Unit 110> The control unit 110 is an automatic offloading function that controls the entire offload server 100. The control unit 110 is realized, for example, when the CPU 910 in Figure 3 loads an application program (offload program) stored in the memory unit 13 into RAM and executes it.

[0031] The control unit 110 includes a code specification unit 111, a code analysis unit 112, a replacement function detection unit 113, a replacement processing unit 114, a quantum computer executable file creation unit 115, a quantum computer processing execution unit 116, a processing specification unit 117, a processing pattern creation unit 118, a performance measurement unit 119, an executable file creation unit 120, a production environment deployment unit 121, a performance measurement test extraction and execution unit 122, and a user provision unit 123.

[0032] The control unit 110 selects the most powerful option (for example, the fastest option or the most efficient option when applied to the relevant accelerator) from among several types of accelerators, including a quantum computer (for example, a multi-core CPU, GPU, FPGA), which are either the computation processing part suitable for the quantum computer 5, or a pattern that offloads either a functional block of the software program source code that can be executed by the accelerator, or a loop statement of the software program. The control unit 110 then works in conjunction with each of the above functional units to execute a series of processes.

[0033] <Code Specification Unit 111> The code specification unit 111 specifies the input source code (for example, source code in C, Java, or Python). Specifically, the code specification unit 111 passes the source code written in the received file to the code analysis unit 112 as a matching application code.

[0034] <Code Analysis Unit 112> The code analysis unit 112 performs syntactic analysis of the source code of the software program and analyzes the computational parts of structures that can be executed by a quantum computer (for example, computational parts of classes, structures, etc.) from the source code ("discovery of computational parts"). Specifically, the code analysis unit 112 uses Clang, Java Parser, Lark, etc. The computational parts of classes, structures, etc. analyzed by the code analysis unit 112 are executable by quantum computers, etc. The code analysis unit 112 analyzes the source code of the software program and identifies loop statements such as for / do-while / while, and functional blocks such as FFT libraries, matrix operations, and random number generation. These loop statements and functional blocks are executable by accelerators.

[0035] <Substitution Function Detection Unit 113> The substitution function detection unit 113 compares the computational parts such as classes and structures analyzed by the code analysis unit 112 with the information registered in the quantum computer code pattern DB 132 to detect computational parts suitable for a quantum computer. Specifically, the substitution function detection unit 113 uses a similarity detection tool to detect whether there are quantum algorithms that can be offloaded to the computational parts such as classes and structures detected by the code analysis unit 112.

[0036] Similarity detection tools, such as Deckarrd and CloneDigger, enable the detection of similar code, such as code that has been copied and modified. Similarity detection uses methods such as abstract syntax trees, vocabulary, lines, program dependency graphs, and fingerprints. For example, Deckarrd uses abstract syntax trees to analyze Java and C language code. In many cases, it is thought that a computational part suitable for quantum computing cannot be found. In such cases, one can proceed to acceleration using evolutionary computation methods on GPUs and other hardware in a verification environment.

[0037] <Substitution Processing Unit 114> The substitution processing unit 114 reads the processing part (equivalent to a library) suitable for quantum computing from the quantum computer code pattern DB 132 and replaces it with the quantum computer processing part (number and type of arguments and return values ​​expected by the host program) implemented with an open-source framework ("quantum computer processing"). If the substitution processing unit 114 finds a computation part suitable for quantum computing, it replaces the corresponding part of the user program with the processing part registered in the quantum computer code pattern DB 132 and associated with it, implemented with Qiskit.

[0038] <Quantum Computer Executable File Creation Unit 115> The quantum computer executable file creation unit 115 creates a quantum computer processing executable file 132 to be executed by the quantum computer based on the quantum computer processing portion replaced by the substitution processing unit 114.

[0039] <Quantum Computer Processing Execution Unit 116> The quantum computer processing execution unit 116 performs a verification test to offload the quantum computer processing execution file 134 created by the quantum computer execution file creation unit 115 to the quantum computer 5.

[0040] <Processing Specification Unit 117> The processing specification unit 117 compiles each functional block by replacing it with processing to be offloaded to the accelerator, and compiles each loop statement by specifying a parallel processing specification statement to be offloaded to the accelerator. The processing specification unit 117 includes an offload range extraction unit 117a and an intermediate language file output unit 117b.

[0041] The offload range extraction unit 120a identifies processes that can be offloaded to a multi-core CPU, GPU, or FPGA, such as loop statements like for / do-while / while, and functional blocks like FFT, matrix operations, and random number generation, and extracts the offload range. The intermediate language file output unit 117b outputs an intermediate language file 135 of the extracted offloadable processes. Intermediate language extraction is not a one-time process; it is repeated to try execution and optimize in order to find an appropriate offload region.

[0042] <Processing pattern creation unit 118> Based on the extracted offload range, the processing pattern creation unit 118 creates a pattern for offloading functional blocks and loop statements to the accelerator.

[0043] When the GPU is used as the accelerator for a loop statement, the processing pattern creation unit 118 excludes loop statements (iteration statements) that cause compilation errors from the offload target, and creates a parallel processing pattern for specifying whether to perform parallel processing for loop statements that do not cause compilation errors.

[0044] <Performance measurement unit 119> The performance measurement unit 119 has two functions: a performance measurement function when processing is offloaded to the quantum computer 5 and a performance measurement function when processing is offloaded to an accelerator other than the quantum computer 5. - Performance measurement function when processing is offloaded to the quantum computer 5 The performance measurement unit 119 measures the overall processing time and the processing time on the quantum computer side when processing is offloaded to the quantum computer 5.

[0045] - Performance measurement function when processing is offloaded to the accelerator The performance measurement unit 119 compiles the source code of the processing pattern, deploys (places) it on the verification machines 10 and 11, and executes the performance measurement processing when offloaded to the accelerator. The performance measurement unit 119 includes an execution file deployment unit 119a. The execution file deployment unit 119a deploys (places) the intermediate language file 135 derived from the intermediate language on the verification machine 10 equipped with a multi-core CPU and a GPU or the verification machine 11 equipped with an FPGA.

[0046] The performance measurement unit 119 executes the placed binary file, measures the performance when offloaded, and returns the performance measurement result to the processing pattern creation unit 118. In this case, the processing pattern creation unit 118 creates another offload pattern. The performance measurement unit 119 attempts to measure the performance of the created another offload pattern.

[0047] <Execution File Creation Unit 120> The Execution File Creation Unit 120 selects an offloading pattern with the highest processing performance from a plurality of offloading patterns based on the performance measurement results repeated a predetermined number of times, and compiles the offloading pattern with the highest processing performance to create an execution file.

[0048] <Production Environment Deployment Unit 121> The Production Environment Deployment Unit 121 deploys the created execution file to the production environment for users ("deployment of the final binary file to the production environment"). The Production Environment Deployment Unit 121 determines a pattern specifying the final offloading area and deploys it to the production environment for users.

[0049] <Performance Measurement Test Extraction Execution Unit 122> After the execution file is deployed, the Performance Measurement Test Extraction Execution Unit 122 extracts performance test items from the test case DB 131 and executes performance tests ("deployment of the final binary file to the production environment"). After the execution file is deployed, the Performance Measurement Test Extraction Execution Unit 122 extracts performance test items from the test case DB 131 to show performance to the user, and automatically executes the extracted performance tests.

[0050] <User Provision Unit 123> The User Provision Unit 123 has the following two user provision functions. - User provision function when processing is offloaded to the quantum computer 5. The User Provision Unit 123 presents information such as price and performance to the user based on the performance test results ("provision of information such as price and performance to the user"). In the test case DB 131, data on test items corresponding to the verification target software is stored. The User Provision Unit 123 presents data such as performance data obtained by implementing the test items stored in the test case DB 131 and price information of resources (virtual machines, GPUs, etc.) where the user software is deployed to the user. The user determines the start of charging for the service based on the presented information such as price and performance.

[0051] - When processing is offloaded to the accelerator, the user-provided function user-provided unit 123 presents the user with information such as price and performance based on the performance test results ("Provision of price and performance information to the user"). The test case DB 131 stores data on test items corresponding to the software under verification. The user-provided unit 123 presents the user with data such as performance obtained by performing the test items stored in the test case DB 131, and data such as price information for resources (virtual machines, GPUs, etc.) on which the user software will be deployed. The user decides whether to start using the service for which billing is required, based on the presented price and performance information.

[0052] [Application of Genetic Algorithm] The offload server 100 can use a genetic algorithm to optimize offloading. The configuration of the offload server 100 when using a genetic algorithm is as follows: The processing specification unit 117 sets the number of loop statements (repeated statements) as the gene length based on the genetic algorithm. The processing pattern creation unit 118 maps the possibility of accelerator processing to the gene pattern, setting either 1 or 0 to indicate whether accelerator processing is performed, and the other 0 or 1 to indicate whether it is not performed.

[0053] The processing pattern creation unit 118, when using a genetic algorithm, prepares a specified number of gene patterns by randomly creating each gene value to either 1 or 0. The performance measurement unit 119 compiles source code specifying parallel processing in the accelerator according to each individual and places it on the verification machines 10 and 11. The performance measurement unit 119 executes performance measurement processing on the verification machines 10 and 11.

[0054] Here, when using a genetic algorithm, if a gene with the same parallel processing pattern as before is generated in an intermediate generation, the performance measurement unit 119 does not compile or measure the performance of the source code corresponding to that parallel processing pattern, but uses the same value as the performance measurement value. In addition, for source code that results in compilation errors, and source code for which performance measurement does not finish within a predetermined time, the performance measurement unit 119 treats it as a timeout and sets the performance measurement value to a predetermined time (long period).

[0055] The executable file creation unit 120 performs performance measurements on all individuals and evaluates them so that individuals with shorter processing times have higher fitness scores. The executable file creation unit 120 selects individuals from all individuals whose fitness scores are higher than a predetermined value (for example, the top n% of the total number of individuals, or the top m individuals of the total number of individuals: n and m are natural numbers) as high-performance individuals, and performs crossover and mutation processing on the selected individuals to create the next generation of individuals. After processing a specified number of generations, the executable file creation unit 120 selects the parallel processing pattern with the best performance as the solution.

[0056] Figure 3 is a hardware configuration diagram showing an example of a computer that implements the functions of the offload server 100. The computer 900 has a CPU 910, RAM 920, ROM 930, HDD 940, communication interface 950, input / output interface 960, and media interface 970.

[0057] The CPU 910 operates based on programs stored in the ROM 930 or HDD 940, and controls various parts. The ROM 930 stores boot programs executed by the CPU 910 when the computer 900 starts up, as well as programs that depend on the computer 900's hardware.

[0058] The HDD 940 stores programs executed by the CPU 910, as well as data used by such programs. The communication interface 950 receives data from other devices via the communication network 80 and sends it to the CPU 910, and transmits data generated by the CPU 910 to other devices via the communication network 80.

[0059] The CPU 910 controls output devices such as displays and printers, and input devices such as keyboards and mice, via the input / output interface 960. The CPU 910 acquires data from input devices via the input / output interface 960. The CPU 910 also outputs the generated data to output devices via the input / output interface 960.

[0060] The media interface 970 reads a program or data stored in the recording medium 980 and provides it to the CPU 910 via the RAM 920. The CPU 910 loads the program from the recording medium 980 onto the RAM 920 via the media interface 970 and executes the loaded program. The recording medium 980 is, for example, an optical recording medium such as a DVD (Digital Versatile Disc), a magneto-optical recording medium such as an MO (Magneto Opticaldisk), a tape medium, a magnetic recording medium, or a semiconductor memory.

[0061] For example, when the computer 900 functions as the offload server 100 according to this embodiment, the CPU 910 of the computer 900 realizes the functions of each part of the offload server 100 by executing programs loaded on the RAM 920. The HDD 940 stores data from each part of the offload server 100. The CPU 910 of the computer 900 reads and executes these programs from the recording medium 980, but as another example, these programs may be obtained from other devices via the communication network 80.

[0062] The automatic offload operation of the offload server 100 configured as described above will be explained below.

[0063] <Quantum Computer Characteristics and Basic Considerations> Quantum computers almost always require low temperatures using dilution refrigerators to exhibit quantum effects, and purchasing such equipment in-house would cost over 100 million yen. To use a quantum computer without initial costs, one can consider using quantum computers provided as cloud services such as Amazon Braket or Azure Quantum.

[0064] For example, Azure Quantum performance computing costs around $90 USD per hour. Therefore, these cloud-based quantum computers are used, but even though there are no upfront costs, the hourly cost is higher compared to VMs (Verification machines) equipped with regular CPUs or GPUs. GPUs and FPGAs use evolutionary computation methods to find faster patterns through repeated testing in a verification environment. However, it is financially difficult to occupy a quantum computer for extended periods for verification, so when offloading to a quantum computer, it is necessary to offload only the effective calculations in a single run without repeated testing.

[0065] We consider offloading computations that are effective for quantum computers. In the case of quantum computers using the quantum gate method, NP problems, such as the traveling salesman problem, the knapsack problem, and prime factorization, which have a huge number of possible combinations, are said to be solved much faster than with a conventional CPU. The solution methods involve experts who understand quantum mechanics designing quantum algorithms suitable for each problem.

[0066] This invention focuses particularly on quantum computers as a form of automated offloading to new hardware. The invention identifies computational portions of code that are effectively handled by quantum computers within the code the user wishes to offload, and then automatically offloads those computational portions by utilizing cloud quantum computing according to a quantum algorithm devised by experts.

[0067] Quantum computer algorithms, such as methods for solving the Traveling Salesperson Problem using quantum computers, are outside the scope of this invention. The present invention aims to find and replace problems suitable for quantum computers, such as the Traveling Salesperson Problem.

[0068] [Offloading to a Quantum Computer] Figure 4 illustrates the offloading process to a quantum computer. The control unit 110 (environmental adaptation function unit) analyzes the existing application to be offloaded, discovers specific computational processes such as the traveling salesman problem as suitable for a quantum computer ("discovery of suitable computational parts for offloading"), and realizes automatic offloading by replacing those parts with processes that utilize a quantum computer ("quantum computer processing").

[0069] First, let's discuss "discovering suitable computational components for off-road use." This can be further divided into A. discovery of computational components and B. discovery of computational components suitable for quantum computing. These will be explained in order below.

[0070] <Discovering suitable calculation parts for off-road use> A. The calculation part discovery control unit 110 (environmental adaptation function unit) performs syntactic analysis of the code provided by the user (step S11 "1. Code Analysis" in Figure 4) and detects calculation parts such as classes and structures from the source code. The type of problem is unknown without actually looking at the contents, such as the Traveling Salesperson Problem, but the calculation part is detected first.

[0071] B. Discovery of computational parts suitable for quantum computers In advance, code for processing problems such as the traveling salesman problem, the knapsack problem, and prime factorization, which are suitable computational parts for quantum computers, is stored in the quantum computer code pattern DB132 (Figure 2). Furthermore, the processing part (equivalent to a library) for using quantum computer 5 with the quantum algorithm corresponding to that code is also stored in the quantum computer code pattern DB132.

[0072] The substitution function detection unit 113 of the control unit 110 (Figure 2) detects a computation part suitable for a quantum computer by comparing it with information registered in the quantum computer code pattern DB 132 (Step S12 in Figure 4, "2. Searching for a computation part suitable for a quantum computer"). The substitution function detection unit 113 of the control unit 110 uses a similarity detection tool to detect whether there is a quantum algorithm that can be offloaded to the computation part such as a class or structure detected in A. Discovery of the computation part.

[0073] The substitution processing unit 114 of the control unit 110 determines, using a tool threshold or the like, whether the computational parts suitable for the quantum computer 5, registered in the quantum computer code pattern DB 132, have a high degree of similarity. Since it is clear that the range that can be covered by similarity detection is not 100%, the application of deep learning recognition of artificial intelligence processing can be considered as a future application. However, even in the case of artificial intelligence processing, it is difficult to make the machine understand the intent of the code, so classes, structures, etc., that are newly and independently created will not be subject to offloading to the quantum computer.

[0074] When a computation portion suitable for the quantum computer 5 is found, the quantum computer processing execution unit 116 of the control unit 110 offloads the processing portion (equivalent to a library) for using the quantum computer 5 with the quantum algorithm corresponding to that code, which is registered in the quantum computer code pattern DB 132, to the quantum computer 5. This concludes section B. Discovery of computation portions suitable for quantum computers.

[0075] <Quantum Computer Processing> Next, we will explain quantum computer processing. For computational parts such as classes and structures, a search is performed to determine if the computation is suitable for a quantum computer. If it is suitable, the processing part (equivalent to a library) is replaced on the host side and implemented. Since quantum computers differ from one development company to another, it is basically necessary to implement the processing using the tools provided by each company. However, there are frameworks that can be used in common by each company. Qiskit is a quantum computer framework open-sourced by IBM. Cirq is a quantum computer framework open-sourced by Google. Furthermore, Q# is a quantum computer programming language proposed by Microsoft.

[0076] This section describes examples of the use of similarity detection tools and quantum computer processing. For example, given a user application that includes the Traveling Salesperson Problem, Deckard (a similarity detection tool) is used to discover quantum algorithms implemented with Qiskit (a framework) from the quantum computer code pattern DB132 (Figure 2). The control unit 110 (environmental adaptation function unit) outputs a quantum computer processing execution file using Qiskit (Step S13 "3. Output of Quantum Computer Processing Execution File" in Figure 4). The control unit 110 offloads processing for a specific computation part to the quantum computer 5 in the external cloud 6 (Step S14 "4. Deployment and Performance Measurement" in Figure 4).

[0077] Here, in order to find the part of the computation that will be processed by the quantum computer (equivalent to a library) for a specific computational part, it is necessary to generate an interface part, etc. Also, since the suitability of the computation for quantum computing is determined by similarity, there is no guarantee that the number and types of arguments and return values ​​expected by the Qiskit implementation and the host program will match. If the number and types of expected arguments and return values ​​do not match, since the quantum algorithm implementation cannot be changed frequently, the user requesting offloading will be asked to confirm whether they will change the number and types of arguments and return values ​​in the original code to match the quantum computer processing part, and after confirmation and approval, an offload verification test will be attempted.

[0078] If the type difference can be resolved simply by casting between float and double, then verification testing can proceed without specific user confirmation. Also, if the number of arguments or return values ​​differs between the original program and the quantum computer processing part (for example, if arguments 1 and 2 are required and argument 3 is optional in the CPU program, and arguments 1 and 2 are required in the quantum computer processing part), and it is acceptable to omit them without causing problems, then optional arguments may be automatically treated as none without user confirmation.

[0079] In this way, the control unit 110 of the offload server 100 detects computational parts suitable for a quantum computer from the code that the user requests to be offloaded, using similarity detection technology (similarity detection tool), and replaces them with quantum computer processing parts implemented with an open-source framework (replaced with Qiskit), thereby performing automatic offloading to the quantum computer. This makes it possible for general users to use the quantum computer 5.

[0080] [Automatic Offloading to Mixed Environments Including Quantum Computers] First, we will discuss automatic offloading to individual hardware other than quantum computers. A fundamental challenge in automatic offloading to individual hardware is that it is difficult for compilers to find loop statements that are suitable for GPU parallel processing. With this in mind, we automatically find appropriate loop statements to offload to the GPU using a genetic algorithm (GA), an evolutionary computation method. For a group of parallelizable loop statements, we generate them by assigning 1 to GPU execution and 0 to CPU execution, and then repeatedly perform performance verification trials in a verification environment to search for the appropriate region. The method of searching for appropriate loop statements in GA can also be used for multi-core CPUs.

[0081] Automatic offloading to FPGAs has the following characteristics: Since it takes several hours or more to compile and run OpenCL on an FPGA, it is not possible to repeatedly measure performance using a GA. Therefore, an arithmetic strength analysis tool is used to narrow down candidate loop statements that seem appropriate based on arithmetic strength, loop count, and resource usage. Then, performance measurements of multiple patterns are performed in a verification environment, and a fast offload pattern is selected, enabling automatic offloading.

[0082] Next, we will discuss automatic offloading to quantum computers. Quantum computers are said to be able to solve problems with a vast number of combinations, such as the knapsack problem, at high speed. Therefore, we will discover functional blocks that are effective on quantum computers and offload them according to expert quantum algorithms. First, we will use a similarity detection tool to find out if there are any offloadable functional blocks. If found, we will automate quantum computer offloading by replacing the corresponding processing part for using the quantum computer, which is registered in the database. This method of discovering functional blocks using similarity detection and replacing them with the corresponding processing part (equivalent to a library) can also be used on multi-core CPUs, GPUs, and FPGAs other than quantum computers.

[0083] Figure 5 illustrates automatic offloading to mixed environments, including quantum computers. In Figure 5, 2a is C / C++ code, S1 is quantum computer offloading, S2 is functional block offloading to a multicore CPU, S3 is functional block offloading to a GPU, S4 is functional block offloading to an FPGA, S5 is loop statement offloading to a multicore CPU, S6 is loop statement offloading to a GPU, S7 is loop statement offloading to an FPGA, S8 is a cost-performance comparison, and S9 is the selection of appropriate offload destination hardware.

[0084] First, quantum computer offloading is attempted (Step S1 in Figure 5). Since quantum computer offloading involves functional block offloading, a search is conducted to see if there are any equivalent libraries available for use with the multi-core CPU, GPU, and FPGA after the quantum computer. If found, functional block offloading is performed and performance is measured (Steps S2 to S4 in Figure 5). Regardless of whether functional block offloading is possible or not, after the functional block offloading attempt, loop statement offloading is attempted in the order of multi-core CPU, GPU, and FPGA (this order can be changed, but FPGA should be the last (see below) (Steps S5 to S7 in Figure 5)), and performance is measured using the final solution of the evolutionary computation. Since performance measurement results for all patterns are obtained, cost performance is calculated based on the usage fees of each hardware, and the appropriate hardware is selected (Steps S8 to S9 in Figure 5). Automatic offloading to mixed environments including quantum computers will be explained in more detail below.

[0085] <Functional Block Offload Trial> In the functional block offload trial, a functional block offload trial is performed on each piece of hardware, including the quantum computer 5. A similarity detection tool is used to find out if there are any functional blocks that can be offloaded to each piece of hardware. The similarity detection tool is a tool that enables the detection of similar code, such as code that has been copied and modified. Similarity detection uses similarities such as abstract syntax trees, vocabulary, lines, program dependency graphs, and fingerprints, but the analysis is performed using a tool that looks at abstract syntax trees. If the control unit 110 (Figure 2) finds a functional block that can be offloaded, it replaces it with the processing part (equivalent to a library) for using the hardware corresponding to that code, which is registered in the quantum computer code pattern DB 132 or the mixed code pattern DB 133, and offloads it to the corresponding accelerator.

[0086] When using Quantum Computer 5, the implementation is based on quantum algorithms and uses one of the following: Qiskit is a quantum computing framework open-sourced by IBM, Cirq is a quantum computing framework open-sourced by Google, and Q# is a quantum computing programming language proposed by Microsoft. When using a multi-core CPU instead of Quantum Computer 5, the OpenMP file specifying the multi-core CPU library is replaced; when using a GPU, the OpenACC file specifying the GPU library is replaced; and when using an FPGA, the OpenCL file that becomes the FPGA IP core is replaced. When an offload function block is found and can be replaced in the processing part, the processing time with offloading and the processing time when executed with a normal CPU are measured again to obtain the degree of performance improvement with offloading.

[0087] <Loop Statement Offload Trial> In the loop statement offload trial, the code analysis unit 112 of the control unit 110 (Figure 2) performs the loop statement offload trial for each hardware. The user application is analyzed using a syntax analysis library to understand the structure of the for statements. For multiple for statements, patterns are created to determine whether or not to offload to the hardware, and the fast offload pattern is found through iterative performance measurement in the verification environment. This is common to all hardware. The verification order is basically multi-core CPU, GPU, and FPGA. This is because FPGAs, in particular, take a long time from compilation to actual measurement, so if reasonably good results are obtained in the multi-core CPU and GPU offload trials, which take a similar amount of time, FPGAs can be skipped.

[0088] In the trials in the verification environment, the processing specification unit 117 of the control unit 110 (Figure 2) uses a genetic algorithm of evolutionary computation to measure multiple patterns of whether or not for loop offloading is possible for multi-core CPUs and GPUs, and finds the fastest pattern. For FPGAs, candidate loop statements are narrowed down based on arithmetic strength, loop count, and resource amount, and then the performance of multiple patterns is measured in the verification environment to find the fastest offload pattern. The final solution is an OpenMP file for multi-core CPUs, an OpenACC file for GPUs, and an OpenCL file for FPGAs. Performance measurements are repeated throughout the process, but the processing time when offloading is performed with the final solution and the processing time when executed with a normal CPU are measured again to obtain the degree of performance improvement when offloading is performed.

[0089] <Hardware Selection Based on Cost Performance> This section discusses hardware selection based on cost performance. There are cases where no process can be offloaded and therefore cannot be replaced, or where offloading does not improve performance. However, as mentioned above, there are up to seven patterns available, including patterns where functional blocks are offloaded to quantum computers, multi-core CPUs, GPUs, and FPGAs, and patterns where loop statements are offloaded to multi-core CPUs, GPUs, and FPGAs. Basically, functional block offloading replaces the processing part (equivalent to a library) with a dedicated processing part, so the degree of speed improvement is often large. For example, replacing the Fourier transform processing on the CPU with the GPU library cuFFT resulted in a 730 times performance improvement. Therefore, when functional block offloading is possible, selecting hardware corresponding to the processing part becomes a strong candidate.

[0090] On the other hand, if functional block offloading is not possible and only loop statement offloading is available, it is necessary to determine which hardware is appropriate for offloading. In the case of processing performed on a quantum computer, the problems are mainly those that cannot be solved by a CPU in the first place, and a normal CPU would time out, so the degree of improvement does not need to be considered. Specifically, the degree of improvement for each offload pattern is divided by the usage fee of the offload hardware (monthly usage fee in the case of a cloud instance, etc.) to determine the cost performance. If the cost performance is higher than that of a normal CPU and is the highest value for all patterns, then that hardware is appropriate, and it is selected as the system and proposed to the user. For example, if a normal CPU VM costs 60 USD / Month, a GPU VM costs 200 USD / Month, and an FPGA VM costs 700 USD / Month, and a certain application performs 10 times better with GPU offloading and 20 times better with FPGA offloading, the cost performance is calculated. In this case, GPU offloading is determined to be appropriate, and it is proposed to the user.

[0091] <Predicting the appropriate hardware to some extent> This section describes predicting the appropriate hardware to some extent. Basically, performance is measured on all hardware that can be offloaded, and the hardware with good cost performance is selected. In particular, searching for an appropriate offload loop statement requires a long time for iterative performance measurement, and to shorten the time, it is desirable not to measure on many pieces of hardware. Therefore, in this embodiment, when entering the loop statement search, it is possible to predict to some extent which hardware is appropriate. For example, if it is predicted that offloading is suitable for a GPU, offloading can be attempted on the GPU first, and if the expected performance is met, trials on multi-core CPUs and FPGAs can be omitted. To make a prediction to some extent, the measurement order of GPUs and multi-core CPUs is considered using the arithmetic strength of the loop statement.

[0092] Arithmetic intensity is an indicator of computational complexity, measured in FLOPs / Byte. The arithmetic intensity is the number of floating-point operations per data point in a loop, and the arithmetic intensity for each for loop can be obtained using arithmetic intensity analysis tools such as the ROSE framework. For example, the Polybench 3mm matrix calculation is faster on a GPU, while the NASA benchmark BT block tridiagonal solver calculation is faster on a multi-core CPU. One reason for the faster NASA benchmark BT on a multi-core CPU is the large amount of data used; GPU-CPU memory transfer becomes a bottleneck for GPUs. Therefore, by analyzing the arithmetic intensity of loop statements, it's possible to predict the measurement order in advance, for example, using a GPU for arithmetic intensities of "5" or higher, a multi-core CPU for "1-5," and a standard CPU for "1" or lower. However, since performance involves multiple factors, it's necessary to measure actual performance and select appropriate offload hardware.

[0093] [Implementation] The implementation will be described below.

[0094] <Tools Used> The application to be tested will be a C / C++ application. However, it can also be used with Python.

[0095] Quantum computer 5 (Figure 1) utilizes Azure Quantum, a quantum gate-based computing service, as a function of Microsoft Azure cloud services. As mentioned above, even the hourly use of the cloud incurs considerable costs. For this reason, repeated use in verification is often difficult for users, and trial and error using evolutionary computation methods will not be performed. The multi-core CPU 10d (Figure 1) will be an AMD Ryzen Threadripper 2990WX (32 cores). The GPU 10e (Figure 1) will be an NVIDIA GeForce RTX 2080 Ti (CUDA cores: 4352, Memory: GDDR6 11GB). Note that the Ryzen Threadripper 2990WX and GeForce RTX 2080 Ti will be mounted on the same node. The FPGA 11c (Figure 1) will be an Intel PAC D5005 (Intel Stratix 10GX FPGA). The machine used for compilation is a DELL EMC PowerEdge R740 (CPU: Intel Xeon Bronze 3206R, RAM: 32GB RDIMM).

[0096] Multicore CPU 10d processing uses gcc 10.1 (gcc 10a in Figure 1). gcc is a compiler that supports a wide range of functions and is compatible with OpenMP. GPU 10e (Figure 1) processing uses the CUDA toolkit 10.1 and the PGI compiler 19.10. The PGI compiler 10b (Figure 1) is a compiler that interprets OpenACC. The PGI compiler 10b can also process calls to CUDA libraries such as cuFFT.

[0097] FPGA11c (Figure 1) processing uses Intel Acceleration Stack 2.0 (Intel FPGA SDK for OpenCL, Intel Quartus Prime). Intel AccelerationStack is capable of high-level synthesis. Intel AccelerationStack interprets OpenCL code that describes the kernel program to be processed by the FPGA and the host program to be processed by the CPU 11b (Figure 1), outputs information such as resource usage, performs wiring work on FPGA11c, and enables operation on FPGA11c.

[0098] For parsing C / C++ languages, the LLVM / Clang 6.0 parsing library (libClang's Python binding) is used. For Python parsing, Lark is used. For C / C++ languages, Deckard 2.0 is used as the similarity detection tool. Deckard uses the modified computation portion of existing code as the target of comparison and determines the abstract syntax tree similarity of the code registered in the mixed code pattern DB133 (Figure 2) using a threshold. For Python, CloneDigger is used.

[0099] The code pattern database used for matching (mixed code pattern DB 133 in Figure 2) uses MySQL 8. The code for the computational part used for matching, along with the associated hardware processing implementation, is also stored. In the case of quantum computer 5 (Figure 1), this is a Qiskit framework implementation, and in the case of GPU 10e (Figure 1), it is a CUDA library implementation such as cuFFT. The quantum computer framework uses Qiskit, which was open-sourced by IBM, and is implemented as Qiskit SDK 1.1.2. The ROSE framework is used for arithmetic strength analysis (described later) during loop statement offloading trials to FPGA 10c (Figure 1). In this embodiment, the implementation is done in Python 3.

[0100] <Implementation Operation> First, as a preliminary step, the matching code and hardware usage portion are registered in the MySQL code pattern database (Mixed code pattern database 133 in Figure 1). This code pattern database contains C / C++ code for matching that includes eigenvalue analysis problems and Fourier transforms, etc. The hardware usage portion contains processing parts implemented with algorithms corresponding to these.

[0101] The code pattern databases (Quantum Computer Code Pattern DB 132 and Mixed Code Pattern DB 133 in Figure 1) are Qitkit implementations for Quantum Computer 5 (Figure 1) and CUDA library implementations for GPU 10e (Figure 1), etc. These matching codes and processing parts will be prepared in advance by the cloud provider. The cloud provider will also prepare verification environments, commercial environments, etc.

[0102] This section outlines the implementation's operation (details are provided later in Figure 9, etc.). All verification is performed in a verification environment. Implementation begins with code analysis upon request for application use. First, a functional block offload attempt is made. If functional block offloading is possible, the hardware processing portion is replaced, and performance is measured. Next, a loop statement offload attempt is made, and performance is measured using the final solution. Finally, cost-effectiveness is determined based on the improvement over the standard CPU, and the hardware that is better than the standard CPU and offers the highest value is selected. The selected hardware is proposed to the user, and after approval, it is deployed in the commercial environment.

[0103] - Key points of functional block offload implementation: When a request is made to use a C / C++ application, the program structure, including defined classes and structures, is understood using code analysis with Clang.

[0104] The implementation uses Deckard to detect the similarity between the detected partial code (classes, structures, etc.) and the comparison code registered in the database. Functional blocks exceeding a threshold are identified, along with corresponding Qiskit implementations for quantum computers, GPU libraries, FPGA IP cores, etc., using an abstract syntax tree similarity threshold of 95%. In particular, if the interface (arguments, return values, types, etc.) of the source code and the library to be replaced differ, the system confirms with the user who requested the offloading whether it is acceptable to modify the interface to match the target library, etc., and creates the executable file after confirmation.

[0105] If a functional block that can be offloaded to hardware is found, the processing part implemented in the code pattern DB (mixed code pattern DB 133 in Figure 1), which is associated with the code pattern, is replaced with the corresponding part of the user program. When using quantum computer 5 (Figure 1), in addition to the Qiskit implementation, the address information of the Azure Quantum to be used is also obtained from the code pattern DB (quantum computer code pattern DB 132 in Figure 1) and set in the user program. When using a multi-core CPU 10d (Figure 1), OpenMP with the multi-core CPU 10d library is set; when using a GPU 10e (Figure 1), OpenACC with the GPU 10e library is set; and when using an FPGA 11c (Figure 1), OpenCL, which is the IP core of the FPGA 11c, is set. If functional block offloading is successful, the application is executed and the processing time is measured to obtain the degree of performance improvement for each offload compared to a normal CPU. However, in the case of quantum computer 5, the problems are mainly those that cannot be solved by CPU 11b (Figure 1) in the first place, and the regular CPU would time out, so no improvement is sought.

[0106] - Implementing Loop Statement Offload: Regardless of whether functional block offloading is possible, loop statement offloading will be attempted. In code analysis using Clang, particular attention will be paid to understanding the program structure, such as the location and hierarchy of loop statements (for statements). The order of loop statement offloading attempts will be multi-core CPU, GPU, and FPGA.

[0107] Multicore CPU offloading trials are performed by iteratively measuring OpenMP using gcc. Since `#pragma omp parallel for` is a multicore CPU processing instruction, the `for` statement is genetically modified, with "1" representing multicore CPU processing and "0" representing normal CPU processing. Performance is then measured in a verification environment, and the genetic algorithm is used to repeatedly recombine the genes for the fastest patterns. The OpenMP file representing the highest-performing pattern in the final generation is the final solution.

[0108] GPU offload trials are performed by iteratively measuring OpenACC with the PGI compiler. Since `#pragma acc kernels` is a GPU processing instruction, the `for` statement is genetically modified, with "1" representing GPU processing and "0" representing normal CPU processing. Performance is measured in a verification environment, and the performance measurement is repeated while rearranging the genes for the fastest patterns using a genetic algorithm. The OpenACC file of the highest-performing pattern in the final generation is the final solution.

[0109] FPGA offload trials are performed by measuring OpenCL performance using the Intel Acceleration Stack. Since compiling and routing an FPGA takes about eight hours, multiple measurements using genetic algorithms are not feasible. Therefore, the ROSE framework is used to narrow down candidate loop statements based on arithmetic strength, loop count, and resource usage for all loop statements. Then, performance measurements are performed on multiple patterns in a verification environment, and the fastest offload pattern is selected. The OpenCL file of the highest-performing pattern is the solution. Once the final solution is determined for each hardware after loop statement offloading, the application is executed and processing time is measured to obtain the performance improvement for each offload compared to a normal CPU.

[0110] - Key points for selecting and implementing offload hardware: To date, we have obtained data on the performance improvement compared to a standard CPU using functional block offloading and loop statement offloading. For implementation, the performance improvement for each offload pattern is divided by the monthly cloud instance usage fee for the hardware to determine cost-effectiveness. If the cost-effectiveness is higher than that of a standard CPU and is the highest across all patterns, then offloading to that hardware is the most cost-effective option and it is selected. The selected offload hardware is proposed to the user along with its monthly usage fee. After user approval, the offloaded application is deployed to the commercial environment and actual use begins.

[0111] As shown in Figure 5, the first attempt is to offload the processing to the quantum computer 5 (step S1 in Figure 5). The offloading process to the quantum computer 5 will be explained below with reference to Figures 6A and 6B.

[0112] [Flowchart for Offloading Processing to a Quantum Computer] Figure 6A is a flowchart showing the process of constructing the quantum computer code pattern DB 132 in the control unit 110. Figure 6B is a flowchart showing the offloading processing to a quantum computer when the control unit 110 operates as an environment adaptation function unit. In step S20 shown in Figure 6A, the control unit 110 registers the code for the calculation part suitable for a quantum computer and pre-constructs the quantum computer code pattern DB 132, which is a database of the processing part for using the quantum computer with the quantum algorithm corresponding to that code.

[0113] In step S21 shown in Figure 6B, the code specification unit 111 specifies the input source code (for example, source code in C, Java, or Python). Specifically, the code specification unit 111 passes the source code described in the received file to the code analysis unit 112 as a matching application code.

[0114] In step S22, the code analysis unit 112 performs syntactic analysis of the source code of the software program and analyzes the computational parts such as classes and structures from the source code ("discovery of computational parts"). Specifically, the code analysis unit uses Clang, Java Parser, Lark, etc. The computational parts such as classes and structures detected by the code analysis unit 112 are executable by a quantum computer or the like.

[0115] In step S23, the substitution function detection unit 113 compares the computational parts such as classes and structures analyzed by the code analysis unit 112 with the information registered in the quantum computer code pattern DB 132 to detect computational parts suitable for a quantum computer. Specifically, the substitution function detection unit 113 uses a similarity detection tool to detect whether there are quantum algorithms that can be offloaded to the computational parts such as classes and structures analyzed by the code analysis unit 112.

[0116] In step S24, the substitution processing unit 114 reads a computational part (equivalent to a library) suitable for quantum computing from the quantum computer code pattern DB 132 and replaces it with a quantum computer processing part (number and type of arguments and return values ​​expected by the host program) implemented with an open-source framework ("quantum computer processing"). If the substitution processing unit 114 finds a computational part suitable for quantum computing, it replaces the corresponding part of the user program with the processing part registered in the quantum computer code pattern DB 132 and associated with it, implemented with Qiskit.

[0117] In step S25, the quantum computer executable file creation unit 115 creates a quantum computer processing executable file 134 (Figure 2) to be executed by the quantum computer processing based on the quantum computer processing portion replaced by the replacement processing unit 114.

[0118] In step S26, the quantum computer processing execution unit 116 performs a verification test to offload processing to the quantum computer 5. In step S27, the performance measurement unit 119 measures the total processing time and the quantum computer-side processing time when processing is offloaded to the quantum computer 5.

[0119] In step S28, the user provision unit 123 presents the user with information such as price and performance based on the performance test results ("Provision of price and performance information to the user") and terminates the processing of this flow.

[0120] [Implementation] This section describes the implementation to verify the effectiveness of the proposed technology.

[0121] <Tools Used> To verify the effectiveness of quantum computer offloading, the target applications will be those written in C / C++ and Python, which are numerous in number. For C / C++ parsing, the LLVM / Clang 6.0 parsing library (libClang's Python binding) will be used. For Python parsing, Lark will be used.

[0122] For the similarity detection tool, Deckard v2.0 is used for C / C++ languages. Deckard uses a threshold to determine the abstract syntax tree similarity of the code registered in the quantum computer code pattern DB132 (Figure 2) to the computation portion of the existing code that has been modified for quantum computer offloading of specific computation parts. CloneDigger is used for Python.

[0123] The quantum computer code pattern DB132 used for matching stores data using MySQL8. The quantum computer code pattern DB132 holds not only the computation code used for matching, but also the Qiskit framework implementation part of the quantum computer processing unit associated with it.

[0124] The quantum computing framework used is the Qiskit SDK v1.1.2, open-sourced by IBM. Quantum computer 5 (Figures 2 and 4) utilizes Azure Quantum, a quantum gate-based system, as a feature of the Microsoft Azure cloud service. Note that the cost of using quantum computer 5, even on a time-based cloud usage basis, is substantial. Therefore, repeated use of quantum computer 5 during the verification phase would be burdensome for the user, and evolutionary computation methods cannot be used. The implementation will be done in Python 3.

[0125] <Implementation Operation> The implementation will perform the following processing operations: ・Preparation As preparation, the matching code and the quantum computer utilization portion will be registered in MySQL's quantum computer code pattern DB132 (Figure 2). The matching code will be C / C++ or Python code describing the Traveling Salesperson Problem, the Knapsack Problem, etc. The quantum computer utilization portion will be processing parts implemented in Qiskit using the corresponding quantum algorithms. These matching codes and quantum computer utilization portions will be prepared in advance by the cloud service provider or other service provider.

[0126] • Code Reception and Syntax Analysis First, the offload server 100 (Figures 1 and 2) receives the application code that the user wants offloaded. The application is in C / C++ or Python. Depending on the language used, Clang is used for C / C++ and Lark for Python for syntax analysis. Syntax analysis identifies units of computation, such as classes and structures.

[0127] - Similarity Detection Next, Deckard is used to detect whether there are any quantum algorithms that can be offloaded to the computational parts of the detected classes, structures, etc. Since differences in parameter values ​​do not affect the abstract syntax tree, the search is performed with a similarity threshold of 95% for the abstract syntax tree. If nothing is found at this stage, the techniques described in Non-Patent Documents 1 and 2 can be used to attempt to speed up the process by offloading to a GPU or the like.

[0128] - If a computational portion suitable for the replacement quantum computer 5 (Figure 1) is found in the user program, the processing portion implemented with Qiskit, which is registered in the quantum computer code pattern DB132 and associated with it, is replaced and implemented in the user program. Since the quantum computer 5 to be used is determined to be Azure Quantum, in addition to the Qiskit processing portion, the Azure Quantum address information is also obtained from the quantum computer code pattern DB132 and set in the user program.

[0129] If there is a discrepancy between the Qiskit implementation and the host program's expected number and types of arguments and return values, the user will be asked to confirm whether they want to modify the original code's arguments and return values ​​to match the quantum computer processing part. If the type difference can be resolved simply by casting between float and double, then user confirmation is not necessary.

[0130] Once the parameters for offloading processing to the quantum computer are configured, a verification test is performed to confirm that processing is offloaded to the quantum computer, and the total processing time and the processing time on the quantum computer side are measured. The measurement results and the usage fee (the sum of the hourly price of the host VM and the hourly price of the Azure Quantum quantum computer) are presented to the user, and if the user agrees, the actual service will start.

[0131] [Evaluation] The effectiveness of this embodiment will be evaluated. The evaluation will focus on confirming that automatic processing offloading from a user-specified application to a quantum computer is possible and that the quantum computer processing time is appropriate.

[0132] <Evaluation Criteria> The evaluation target will be eigenvalue analysis problems. There is no computational procedure that can exactly represent eigenvalues ​​in a matrix of higher-order real or complex numbers using a finite number of algebraic operations. Therefore, it has been conventional to always use iterative methods for the numerical analysis of eigenvalue problems. The quantum superposition properties of quantum computers make it possible to speed up the process. The essence of the problem is to find the eigenvalues ​​of the accompanying matrix of a general n-th order algebraic equation, and each problem differs in its parameters. The "eigenvalue analysis problems" used will be those with Qiskit implementations. Since Qiskit implementations are available using quantum algorithms, solutions using quantum computers are also possible. Here, quantum algorithms are also being researched for solving NP problems such as the knapsack problem and prime factorization using quantum computers. Eigenvalue analysis problems, which are general-purpose problems with a wide range of applications for general users, will be targeted for offloading.

[0133] • Evaluation Method: A user is assumed to request the offloading of an application that includes the Traveling Salesperson Problem. Upon receiving the request, the service provider's platform analyzes the application, searches for the offloaded computation portion using a similarity detection tool, and if found, replaces it with the quantum computer-based portion and offloads it to the quantum computer. The processing time during the offloading process is measured, and the measurement results and usage price are presented to the user. The experimental conditions are as follows.

[0134] Offloaded computation part: A predetermined eigenvalue analysis problem Offload destination: Azure Quantum Offloaded computation part discovery method: The computation part included in the application code is compared with the code included in code pattern DB131 using the similarity detection tool Deckard. Performance measurement: The sample parameters of the predetermined eigenvalue analysis problem are kept the same, and the processing time on the quantum computer is measured. For small sizes, the calculation can be completed in a realistic time even on a normal CPU, but for large sizes, the calculation cannot be completed. In this evaluation, in order to confirm quantum computer offloading, measurements for large sizes that cannot be completed even on a normal CPU are not performed.

[0135] The above describes the offloading process to quantum computer 5. Next, we will explain the six offloading methods (steps S2 to S7 in Figure 5) that are attempted after offloading to quantum computer 5, as shown in Figure 5, which consist of a multi-core CPU, GPU, FPGA, functional blocks, and loop statements. After the six offloading attempts, the degree of improvement compared to a normal CPU is measured for all seven offloading patterns, including the quantum computer. The improvement for each offloading pattern is divided by the usage fee of the offloading hardware (monthly usage fee in the case of a cloud instance, etc.) to determine the cost performance. If the cost performance is higher than that of a normal CPU and is the highest value for all patterns, then that hardware is appropriate, and it is selected as the system and proposed to the user.

[0136] [Flowchart for Offloading to Multicore CPU, GPU, and FPGA] Figures 7A and 7B are flowcharts for selecting patterns to offload to accelerators (multicore CPU, GPU, and FPGA). The offload server 100 considers automatic offloading to the three destination environments—multicore CPU, GPU, and FPGA—using two methods: functional blocks and loop statements.

[0137] When C / C++ source code is input (S200), the processing specification unit 117 of the control unit 110 executes a series of offload pattern selection processes. The control unit 110 calls the selection processes shown in Figures 8A and 8B to check the offloading of functional blocks to the multi-core CPU (S201) and determines whether the desired performance has been obtained (S202). If the desired performance has been obtained (Yes), the control unit 110 selects the highest performance pattern from all measurements (S208) and terminates the process shown in this figure. If the desired performance has not been obtained (No), the control unit 110 proceeds to step S203.

[0138] In step S203, the processing specification unit 117 of the control unit 110 calls the selection processes shown in Figures 8A and 8B to check the offloading of functional blocks to the GPU. The control unit 110 then determines whether the desired performance has been obtained (S204). If the desired performance has been obtained (Yes), the control unit 110 selects the most cost-effective pattern from all measurements (S207) and terminates the process shown in this figure. If the desired performance has not been obtained (No), the control unit 110 proceeds to step S205.

[0139] In step S205, the processing specification unit 117 of the control unit 110 calls the selection processes shown in Figures 8A and 8B to check the offloading of functional blocks to the FPGA. The control unit 110 then determines whether the desired performance has been obtained (S206). If the desired performance has been obtained (Yes), the control unit 110 selects a cost-performance pattern from all measurements (S207) and terminates the process shown in this figure. If the desired performance has not been obtained (No), the control unit 110 proceeds to step S209 in Figure 7B. Through these steps S201 to S207, functional blocks can be automatically made more efficient even in environments where multiple types of accelerators are mixed. Furthermore, the control unit 110 can efficiently search for patterns that can be accelerated by trying multi-core CPUs, GPUs, and FPGAs in that order.

[0140] In step S209, the processing specification unit 117 of the control unit 110 calls the selection processes shown in Figures 12A and 12B to check the offloading of loop statements to the multi-core CPU. The control unit 110 then determines whether the desired performance has been obtained (S210). If the desired performance has been obtained (Yes), the control unit 110 selects the highest performance pattern from all measurements (S208) and terminates the process shown in this figure. If the desired performance has not been obtained (No), the control unit 110 proceeds to step S211.

[0141] In step S211, the processing specification unit 117 of the control unit 110 calls the selection processes shown in Figures 14A and 14B to check for offloading loop statements to the GPU. The control unit 110 then determines whether the desired performance has been obtained (S212). If the desired performance has been obtained (Yes), the control unit 110 selects the highest performance pattern from all measurements (S208) and terminates the process shown in this figure. If the desired performance has not been obtained (No), the control unit 110 proceeds to step S213.

[0142] In step S213, the processing specification unit 117 of the control unit 110 calls the selection processes shown in Figures 15A and 15B to check for offloading loop statements to the FPGA. The control unit 110 then determines whether the desired performance has been achieved (S214). If the desired performance has been achieved (Yes), the control unit 110 selects a cost-effective pattern from all measurements (S207) and terminates the process shown in this figure. If the desired performance has not been achieved (No), the control unit 110 selects a cost-effective pattern from the verifications for each migration destination (S215) and terminates the process shown in this figure.

[0143] Through the processing in steps S209 to S215, the loop statement can be automatically optimized for high performance even in an environment where multiple types of accelerators are mixed. Furthermore, the control unit 110 can efficiently search for patterns that can be accelerated by trying the multi-core CPU, GPU, and FPGA in that order. The control unit can efficiently search for patterns that can be accelerated by trying the loop statement after trying the functional block as an offload target to the accelerator.

[0144] Figures 8A and 8B are flowcharts of the process for selecting patterns for offloading functional blocks to accelerators. First, the code analysis unit 112 performs offload analysis of the C / C++ source code (S30). Specifically, the code analysis unit 112 uses a syntax analysis tool such as Clang to analyze library calls and functional processing contained in the code.

[0145] The offload range extraction unit 117a detects external library calls in this source code (S31) and retrieves replaceable accelerator libraries or accelerator IP cores from the mixed code pattern DB 133 using the library name as the key (S32). Here, an accelerator is one of a multi-core CPU, GPU, or FPGA. Specifically, the offload range extraction unit 117a retrieves executable files or OpenCL, etc. that can be accelerated from the records registered in the mixed code pattern DB 133 using the called library as the key.

[0146] Here, the offload range extraction unit 117a obtains replaceable accelerator libraries or accelerator IP cores by matching the identified external library calls with the mixed code pattern DB 133 using the called library name as the key. Here, an accelerator library is an executable file for multi-core CPUs or GPUs. An accelerator IP core is OpenCL, etc.

[0147] Furthermore, the search for libraries or IP cores that can speed up functional blocks involves not only name matching of libraries and other components but also detection using similarity detection tools. Similarity detection tools are software engineering tools such as Deckard, used to detect copied code and code that has been copied and then modified. Similarity detection tools determine code similarity by looking at abstract syntax tree similarity, and can detect processes that would be written similarly when calculated on the CPU, or cases where reference code from others has been copied and modified.

[0148] The processing pattern creation unit 118 replaces the source code's processing description with a processing description for a multi-core CPU or GPU library, or an FPGA IP core, to match the target accelerator (S33). Furthermore, the processing pattern creation unit 118 offloads the replaced accelerator library or accelerator IP core processing description to the accelerator as an offloadable functional block (S34). At this time, it is not known whether the offloaded processing will actually lead to speed improvements or whether the cost-effectiveness is sufficient, so the system automatically extracts the offload pattern that will result in higher speeds by trying out offloading and not offloading through performance measurements in a verification environment.

[0149] The processing pattern creation unit 118 describes interface processing for calling accelerator libraries and accelerator IP cores (S35). This interface processing is, for example, OpenCLAPI for FPGAs. Next, the executable file creation unit 120 compiles the created pattern (S36). The performance measurement unit 119 measures the performance of the created pattern in a verification environment (S37). This is the first performance measurement.

[0150] After the first performance measurement, the executable file creation unit 120 creates combination patterns for the patterns that were sped up during the first measurement (S38), and compiles the created combination patterns (S39). Then, the performance measurement unit 119 performs a performance measurement of the created combination patterns in the verification environment (S40). This is the second performance measurement.

[0151] After the second performance measurement, the production environment deployment unit 121 selects the pattern with the highest performance from the first and second measurements (S41), and terminates the processing of this flow.

[0152] Compared to offloading individual loop statements, offloading a tuned functional block, which processes functional blocks containing multiple loop statements in units, yields a greater degree of speed improvement when used with accelerators that handle such blocks individually.

[0153] <Implementation> The offload server 100 uses code analysis to understand the program structure, including the libraries being called and the defined classes and structures.

[0154] Next, the offload server 100 detects GPU libraries, FPGA IP cores, etc., that can speed up the called library. Using the called library as a key, the offload server 100 retrieves executable files, OpenCL, etc., that can be accelerated from the records registered in the mixed code pattern DB 133. If a replacement function that can be accelerated is detected, the offload server 100 creates the executable file.

[0155] For multi-core CPUs and GPU libraries, the original code is deleted and replaced with a replacement library (such as the CUDA library) to call the replacement library. For FPGA IP cores, the acquired OpenCL code is deleted from the host code before being replaced with the kernel code. After the replacement is complete, the code is compiled using gcc for multi-core CPUs, the PGI compiler for GPUs, and Intel Acceleration Stack 11a (Figure 1) for FPGAs.

[0156] The process described above applies to library calls, but the process also runs in parallel when similarity detection is used. Deckard is used to detect the similarity between the detected partial code (classes, structures, etc.) and the comparison code registered in the database. Functional blocks whose similarity exceeds a threshold are then identified, along with the corresponding GPU libraries and FPGA IP cores. In particular, if the interface of the source code and the replacement library or IP core differs in terms of arguments, return values, types, etc., the offload server 100 confirms with the user who requested the offload whether it is acceptable to modify the interface to match the replacement library or IP core, and then creates the executable file.

[0157] Here, the offload server 100 creates an executable file that can be used to measure performance on the GPU or FPGA of the verification environment. In functional block offloading, the offload server 100 measures the performance of whether or not to offload each replacement functional block to confirm whether it can be sped up.

[0158] [Automatic Offload Operation] The offload server 100 in this embodiment is an example of applying the technology of automatically offloading user application logic to an accelerator as an elemental technology of an environment-adaptive software system.

[0159] Figure 9 shows the automatic offloading process of the offload server 100. As shown in Figure 9, the offload server 100 is applied to the elemental technology of an environment-adaptive software system. The offload server 100 includes a control unit 110, a test case DB 131, an intermediate language file 135, and verification machines 10 and 11. The offload server 100 obtains the source code 130 to be used by the user.

[0160] The user utilizes resource 15. Resource 15 includes, for example, device 151, device 152 having a CPU and GPU, device 153 having a CPU and FPGA, and device 154 having a CPU. The offload server 100 automatically offloads functional processing to the accelerators of device 152 having a CPU and GPU, and device 153 having a CPU and FPGA.

[0161] The operation of each part will be explained below with reference to the step numbers in Figure 9. <Step S61: Specifying the source code> In step S61, the code specification unit 111 (see Figure 2) identifies the processing function (image analysis, etc.) of the service provided to the user. Specifically, the code specification unit 111 specifies the input source code.

[0162] <Step S62: Source Code Analysis> In step S62, the code analysis unit 112 (see Figure 2) analyzes the source code of the processing function and understands the structure, such as loop statements and FFT library calls.

[0163] <Step S63: Extraction of Offload Range> In step S63, the processing specification unit 117 (see Figure 2) identifies loop statements included in the application's source code and compiles each loop statement by specifying a parallel processing specification statement for the accelerator. Specifically, the offload range extraction unit 117a (see Figure 2) extracts the range that can be offloaded to the GPU / FPGA, such as loop statements and FFT.

[0164] <Step S64: Output of intermediate language file> In step S64, the processing specification unit 117 (see Figure 2) outputs an intermediate language file 135 using the intermediate language file output unit 117b. The output of the intermediate language is not a one-time event, but is repeated to try execution and optimize it in order to find an appropriate offload area.

[0165] <Step S65: Processing in case of compilation error> In step S65, the processing pattern creation unit 118 (see Figure 2) creates a parallel processing pattern that excludes loop statements that produce compilation errors from offloading, and specifies whether or not to perform parallel processing on loop statements that do not produce compilation errors.

[0166] <Step S71: Deployment of executable files> In step S71, the executable file deployment unit 119a (see Figure 2) deploys the executable files derived from the intermediate language to the verification machines 10 and 11, which are equipped with a multi-core CPU, a GPU, and an FPGA.

[0167] <Step S72: Performance Measurement> In step S72, the performance measurement unit 119 (see Figure 2) executes the placed file and measures the performance when offloaded. To make the offload area more appropriate, this performance measurement result is returned to the processing pattern creation unit 118, which creates another offload pattern. The performance measurement unit 119 then measures the performance of the other offload pattern (see reference numeral e in Figure 9).

[0168] As shown by arrow e in Figure 9, the control unit 110 repeatedly executes the processes from step S62 to step S72.

[0169] The automatic offload function of the control unit 110 can be summarized as follows: The processing specification unit 117 identifies loop statements in the source code, specifies a parallel processing specification statement for each loop statement, and compiles it. The processing pattern creation unit 118 then excludes loop statements that produce compilation errors from offloading and creates a parallel processing pattern that specifies whether or not to perform parallel processing on loop statements that do not produce compilation errors. The performance measurement unit 119 then compiles the source code of the corresponding parallel processing pattern, places it on the verification machines 10 and 11, and executes the performance measurement process on the verification machines 10 and 11. The executable file creation unit 120 selects the pattern with the best processing performance from among multiple parallel processing patterns based on the performance measurement results that have been repeated a predetermined number of times, compiles the selected pattern, and creates an executable file.

[0170] <Step S73: Deployment to the production environment> In step S73, the production environment deployment unit 121 determines a pattern that specifies the final offload area and deploys it to the production environment for users.

[0171] <Step S74: Performance Measurement Test and Execution> In step S74, the performance measurement test extraction and execution unit 122 extracts performance test items from the test case DB 131 in order to show the performance to the user after the execution file has been placed, and automatically executes the extracted performance tests.

[0172] <Step S75: Providing price and performance information to the user> In step S75, the user provision unit 123 presents the user with information on price, performance, etc., based on the performance test results. The user decides to start using the service based on the presented price and performance information.

[0173] Steps S61 to S75 described above are performed in the background while the user is using the service, and are intended to be performed, for example, during the first day of trial use.

[0174] As described above, when applied to the elemental technologies of an environment-adaptive software system, the control unit 110 of the offload server 100 extracts the areas to be offloaded from the source code of the application used by the user and outputs intermediate language for the purpose of offloading functional processing (S61-S75). The control unit 110 places and executes the executable file derived from the intermediate language on the verification machines 10 and 11 to verify the offload effect (S71-S72). After repeating the verification and determining the appropriate offload areas, the control unit 110 deploys the executable file to the actual production environment that will be provided to the user and provides it as a service (S73-S75).

[0175] [Automatic Loop Offloading Using Genetic Algorithms] Automatic loop offloading to GPUs and multi-core CPUs is a process that repeats steps S62 to S72 in Figure 9, ultimately obtaining the offload code to be deployed in step S73.

[0176] GPUs generally do not guarantee latency, but they are devices well-suited to increasing throughput through parallel processing. There are many different types of applications that are well-suited to GPUs. Typical examples include data encryption, image processing for camera video analysis, and machine learning processing for analyzing large amounts of sensor data, all of which involve a lot of repetitive processing. Therefore, the offload server 100 aims to speed up processing by automatically offloading loop statements contained in the application's source code to the GPU.

[0177] However, as described in the previous technology section, appropriate parallel processing is necessary for speeding up. In particular, when using a GPU, performance is often not achieved unless the data size and loop count are large due to memory transfers between the CPU and GPU. Also, depending on the timing of memory data transfers, the combination of individual loop statements (repetition statements) that can be sped up in parallel may not be the fastest. For example, if there are 10 loop statements (repetition statements) and three of them (1st, 5th, and 10th) can be sped up compared to the CPU, the combination of these three (1st, 5th, and 10th) may not necessarily be the fastest.

[0178] To specify the appropriate parallel processing area, there is an attempt to optimize the parallelization of loop statements through trial and error using the PGI compiler 10b (Figure 1). However, this trial and error process is time-consuming, which delays user access and increases costs when providing it as a service.

[0179] Therefore, in this embodiment, appropriate offload areas are automatically extracted from a general-purpose program that is not intended for parallelization. For this purpose, the offload server 100 checks the offload of functional blocks in the order of multi-core CPU → GPU → FPGA, and then checks the offload of loop statements in the order of multi-core CPU → GPU → FPGA. By checking functional blocks with high offload effect before loop statements, and by checking in the order of multi-core CPU → GPU → FPGA, which is the order of lowest verification cost, it is possible to efficiently search for patterns that can be accelerated.

[0180] [Image of the search for the control unit 110 using a simple genetic algorithm] Figure 10 shows an image of the search for the control unit 110 of the offload server using a simple genetic algorithm. A genetic algorithm is one of the combinatorial optimization methods that mimics the evolutionary process of living organisms. The flowchart of the genetic algorithm is initialization → evaluation → selection → crossover → mutation → termination determination.

[0181] In this embodiment, a simplified genetic algorithm is used within the genetic algorithm. The simplified genetic algorithm uses only genes with values ​​of 1 and 0, and is a simplified genetic algorithm that uses methods such as roulette selection, one-point crossover, and mutation by reversing the value of one gene.

[0182] <Initialization> During initialization, the parallelizability of all loop statements in the source code is checked, and then the parallelizable loop statements are mapped to gene sequences. Set to 1 if GPU processing is required, and 0 if GPU processing is not required. A specified number of individuals M are prepared for the genes, and 1 and 0 are randomly assigned to each loop statement.

[0183] Specifically, the control unit 110 (see Figure 2) obtains the source code 130 (see Figure 9) used by the user and checks whether the loop statements can be parallelized from the code pattern 141 of the source code 130. As shown in Figure 11, if three loop statements are detected from the code pattern 141d, one digit is randomly assigned to each loop statement; in this case, three digits of 1 or 0 are assigned to the three loop statements. For example, 0 is assigned when processing on a single-core CPU, and 1 is assigned when outputting to a multi-core CPU. However, at this stage, 1 or 0 is assigned randomly. The code corresponding to the gene length is three digits, and the code for a three-digit gene length is 2 ３ This results in 8 patterns, for example, 100, 110, ... Note that in Figure 10, the circles (○ marks) in code pattern 141 are shown as images of the codes.

[0184] <Evaluation> In step S300, the evaluation involves deployment and performance measurement. Specifically, the performance measurement unit 119 (see Figure 2) compiles the code corresponding to the gene, deploys it to the verification machines 10 and 11, and executes it. The performance measurement unit 119 performs benchmark performance measurement. The fitness of the gene for the pattern with good performance (parallel processing pattern) is increased.

[0185] <Selection> In step S301, a high-performance code pattern is selected based on fitness. The performance measurement unit 119 (see Figure 2) selects a specified number of high-fitness genes based on fitness. In this embodiment, a roulette selection and elite selection of the highest-fitness genes are performed according to fitness. Figure 10 shows the search image, indicating that the number of circles (○ marks) in the selected code pattern 142 has been reduced to three.

[0186] <Crossover> In crossover, a certain number of genes are exchanged at a specific point between selected individuals at a fixed crossover rate Pc, creating a new individual with different genes. Roulette selects a pattern (parallel processing pattern) and crossovers the genes of other patterns. The position of the single-point crossover is arbitrary; for example, the crossover can be performed at the second digit of the three-digit code mentioned above.

[0187] <Mutation> In mutation, the values ​​of each gene in an individual are changed from 0 to 1 or from 1 to 0 at a constant mutation rate Pm. Mutation is also introduced to avoid local optima. However, to reduce computational complexity, mutation may not be performed. Then, as shown in step S302, each of these crossover and mutation-treated codes is used as the next generation code.

[0188] <Termination Criteria> Generates next-generation coding patterns after crossover and mutation. In the termination criteria, the process is terminated after a specified number of generations (T times), and the gene with the highest fitness is taken as the solution. For example, performance is measured, and three individuals with fast processing speeds are selected, for example, individuals with genes 110,010,001. These three are then recombined using a genetic algorithm in the next generation to create a new pattern (parallel processing pattern) 011 (one example). At this time, mutations such as changing 0 to 1 are introduced into the recombined pattern. The above is repeated until the pattern with the fastest processing speed is found. A specified number of generations (for example, 20 generations) is set, and the pattern remaining in the final generation is taken as the final solution.

[0189] <Deployment> The parallel processing pattern corresponding to the gene with the highest fitness and processing performance is redeployed to the production environment and provided to users.

[0190] <Supplementary Explanation> This section explains the case where a significant number of loop statements (repeating statements) cannot be offloaded to the GPU. For example, even if there are 200 loop statements, only about 30 can be offloaded to the GPU. Here, we exclude those that result in errors and perform a genetic algorithm on these 30.

[0191] OpenACC includes a compiler that allows GPU offloading by extracting and executing bytecode for the GPU using the directive "#pragmaacckernels". By writing a loop statement command in this "#pragma", it is possible to determine whether that loop statement will run on the GPU or not.

[0192] For example, when using C / C++, the C / C++ code is analyzed to detect loop statements. Once loop statements are detected, OpenACC uses the parallel processing syntax "#pragmaacckernels" to write to them. In detail, each loop statement is placed into an empty "#pragmaacckernels" and compiled. If an error occurs, that loop statement cannot be processed by the GPU in the first place and is excluded. In this way, the remaining loop statements are detected. The loops that do not produce errors are then defined as having a length (gene length). If there are five error-free loop statements, the gene length is 5; if there are 10 error-free loop statements, the gene length is 10. Note that loops that cannot be processed in parallel are those that depend on data, such as using the previous process for the next process. This completes the preparation stage. Next, the genetic algorithm processing is performed.

[0193] A code pattern is obtained with a gene length corresponding to the number of loop statements. Initially, parallel processing patterns such as 10010, 01001, 00101, etc. are assigned randomly. Genetic algorithm processing is performed and compiled. At this time, errors may occur even if the loop statements can be offloaded. This occurs when the loop statements are hierarchical (either one can be specified for GPU processing). In this case, the loop statements that caused the error can be kept. Specifically, one method is to increase the processing time and cause a timeout.

[0194] The system is deployed on verification machines 10 and 11 (Figure 9), and benchmarks are performed, for example, using image processing. The shorter the processing time, the higher the fitness is evaluated. For example, the fitness of an individual that takes 10 seconds to process is set to 1. The fitness of an individual that takes 100 seconds to process is set to 0.1. The fitness of an individual that takes 1 second to process is set to 10.

[0195] The offload server 100 selects those with high fitness. For example, the offload server 100 selects 3 to 5 from 10 individuals and rearranges them to create a new code pattern. During the creation process, it may be possible to create the same thing as before. In this case, there is no need to perform the same benchmark, so the offload server 100 uses the data with the same fitness as before. In this embodiment, the offload server 100 stores the code pattern and its processing time in the storage unit 13.

[0196] This concludes the explanation of the search image for the control unit 110 using a simple genetic algorithm.

[0197] Figure 11 shows the gene sequence mapping of loop statements to a multicore CPU. Code pattern 141d contains three loop statements. Here, one binary digit is assigned to each loop statement, and three digits of 1 or 0 are randomly assigned to the three loop statements.

[0198] The first for loop statement in code pattern 141d has the directive "#pragmaompparallelfor" attached to it. In this case, the first for loop statement is compiled to be offloaded to the multicore. Furthermore, the gene sequence 100 of code pattern 141d is shown to the left of code pattern 141d.

[0199] Figures 12A and 12B are flowcharts of the process for selecting a pattern for offloading loop statements to a multi-core CPU. First, the code analysis unit 112 analyzes the loop statements in the C / C++ source code (S90). The processing specification unit 117 identifies the loop statements and reference relationships in the C / C++ source code (S91).

[0200] The processing specification unit 117 runs a benchmark tool to determine the number of loops for each loop statement, and then, after assigning each loop to a threshold (S92), it checks the possibility of parallel processing for each loop statement (S93).

[0201] Furthermore, the PGI compiler used for automatic offloading to the GPU would output an error when parallelization was not possible. However, with OpenMP compilers such as gcc, such errors are the programmer's responsibility. Therefore, to automate this process, the processing performed by the OpenMP directive is simplified to only whether or not to parallelize the loop statement on a multi-core CPU. In addition, a check is performed during performance measurement to verify whether the final calculation result is correct when parallelized, so that only patterns that produce correct calculation results remain in the evolutionary computation.

[0202] Next, the processing specification unit 117 counts the number of loop statements that can be processed in parallel and sets it as the gene length (S94), and prepares a specified number of gene sequences as initial values ​​(S95). Here, the processing specification unit 117 creates a predetermined number of gene sequences to which 0s and 1s are randomly assigned.

[0203] The processing specification unit 117 maps the C / C++ source code to genes and prepares patterns for a specified number of individuals (S96). Specifically, depending on the prepared gene sequence, the processing specification unit 117 inserts a directive into the C / C++ code that specifies parallel processing if the gene value is 1 (see, for example, the #pragma directive in Figure 11).

[0204] The control unit 110 repeats the processing in steps S100 to S108 for a specified number of generations. Furthermore, within the repetition of the specified number of generations, the processing in steps S101 to S104 is repeated for a specified number of individuals. In other words, within the repetition of the specified number of generations, the repetition for the specified number of individuals is processed in a nested manner.

[0205] During the repetition of the specified number of individuals, the processing pattern creation unit 118 (see Figure 2) compiles the C / C++ source code with directives specified according to the gene pattern, i.e., each offload pattern, using the gcc compiler (S102). In other words, the processing pattern creation unit 118 compiles the created C / C++ code using the gcc compiler on the verification machines 10 and 11 equipped with multi-core CPUs. Here, compilation errors may occur, for example, when specifying parallel processing for multiple nested loop statements. In this case, it is treated the same as when the processing time times out during performance measurement.

[0206] The performance measurement unit 119 (see Figure 2) deploys the compiled offload pattern executable file, i.e., the compiled offload pattern, to the multi-core CPU-equipped verification machines 10 and 11 (Figure 9) (S103), executes the deployed executable file, and measures the benchmark performance when offloaded (S104).

[0207] Here, for genes with the same pattern as before in intermediate generations, we do not measure them, but use the same values. In other words, if the same gene pattern as before is generated during the genetic algorithm processing, we do not compile or measure the performance of that individual, but use the same measurement values ​​as before.

[0208] In step S105, if the control unit 110 has not completed repeating the specified number of individuals, it returns to the process in step S101. If it has repeated all the specified number of individuals, it proceeds to step S106.

[0209] Next, in step S106, the executable file creation unit 120 (see Figure 2) evaluates the fit of each individual so that the shorter the processing time, the higher the fit, and selects the individual with the best performance. The executable file creation unit 120 (see Figure 2) evaluates the difference between the calculation result of each individual and the calculation result of the single-core CPU, and selects the individual that falls within an acceptable range (S107). During performance measurement, the executable file creation unit 120 compares the final calculation result with the result obtained when the original code is processed with a normal CPU to ensure that the result is the same as when parallel processing is not performed. If the difference is unacceptably large, the fit of that pattern is set to 0 and it is not selected for the next generation. The executable file creation unit 120 also checks whether the final calculation result obtained when parallel processing is performed during performance measurement, so that it can narrow down the evolutionary calculation to patterns that produce the correct calculation result.

[0210] The executable file creation unit 120 performs crossover and mutation processing on the selected individuals to create the next generation of individuals (S108). This is because compilation, performance measurement, fitness setting, selection, crossover, and mutation processing are performed on the next generation of individuals.

[0211] In other words, the executable file creation unit 120 measures the benchmark performance for all individuals and sets the fitness level of each gene sequence according to the benchmark processing time. The executable file creation unit 120 selects the individuals to keep according to the set fitness levels. The executable file creation unit 120 then performs genetic algorithm processing on the selected individuals using crossover, mutation, and direct copying to create the next generation population.

[0212] In step S109, if the control unit 110 has not completed the specified number of generations, it returns to the process in step S100. If it has completed all the specified number of generations, it proceeds to step S110.

[0213] In step S110, the executable file creation unit 120 terminates the process shown in Figure 12B after completing the genetic algorithm processing for the specified number of generations and selecting the C / C++ code (highest performance parallel processing pattern) corresponding to the highest performance gene sequence as the solution. In this way, even if the destination environment is a multi-core CPU, it is possible to search for a pattern that can efficiently speed up the loop statement.

[0214] Like GPUs, multi-core CPUs accelerate processing by parallelizing operations using their numerous computing cores. The difference from GPUs is that, since multi-core CPUs share memory, the overhead caused by data transfer between CPU and GPU memory, which was often a problem with GPU offloading, does not need to be considered. Furthermore, the OpenMP specification is frequently used for parallelizing program processing on multi-core CPUs. OpenMP is a specification that allows programmers to specify parallel processing using directives such as "#pragmaompparallelfor". The OpenMP programmer is responsible for parallelizing processing with OpenMP; if a process that cannot be parallelized is attempted, the compiler does not output an error, but rather the calculation result is incorrectly output.

[0215] Based on these considerations, in this embodiment, the automatic offloading of loop statements for multicore CPUs employs an evolutionary computation method that gradually speeds up the process by creating multiple patterns in which the parallel processing capability of the loop is specified using "#pragma" in OpenMP, and repeatedly measuring the actual performance in a verification environment.

[0216] <Implementation> The offload server 100 analyzes the C / C++ source code to find loop statements and understands the program structure, including the variable data used within the loop statements and the processing of those variables.

[0217] Since loop statements that cannot be processed in parallel must be excluded, the offload server 100 attempts to insert a directive to process each loop statement using the GPU, and loop statements that produce errors are excluded from the genetic algorithm. Here, the number of loop statements that do not produce errors becomes the gene length.

[0218] Next, the offload server 100 prepares a specified number of gene sequences as initial values. Each gene value is randomly assigned between 0 and 1. Depending on the prepared gene sequence, the offload server 100 inserts a directive into the C / C++ code that specifies GPU or multi-core CPU processing if the gene value is 1.

[0219] The offload server 100 compiles the C / C++ code with the inserted directives using gcc, deploys the compiled executable file, and measures its performance. In performance measurement, the offload server 100 checks whether the calculation results, when processed in parallel using, for example, the PCAST ​​function of the PGI compiler, differ significantly from the original code, along with the processing time. If the results are outside the acceptable range, it sets the fitness score to 0.

[0220] The offload server 100 measures the performance of all individuals and then sets the fitness score for each individual according to the processing time. Based on the set fitness score, it selects the individuals to keep. For the selected individuals, it performs genetic algorithm processing using crossover, mutation, and direct copying to create the next generation population.

[0221] The offload server 100 further performs instruction insertion, compilation, performance measurement, fitness setting, selection, crossover, and mutation processing on the next generation of individuals, and repeats this for the specified number of generations. After the genetic algorithm processing for the specified number of generations is completed, the offload server 100 uses the C / C++ code with directives corresponding to the highest-performing gene sequence as the solution.

[0222] Figure 13 shows the gene sequence mapping of a loop statement to the GPU. The first for loop statement in code pattern 141e is annotated with "#pragmaacckernels". In this case, the first for loop statement is compiled to be offloaded to the GPU. Furthermore, the gene sequence 100 of code pattern 141e is shown to the left of code pattern 141e.

[0223] Figures 14A and 14B are flowcharts showing the process for selecting a pattern for offloading loop statements to the GPU. The offload server 100 performs the following processing using the OpenACC compiler for C / C++.

[0224] The code analysis unit 112 (see Figure 2) analyzes loop statements by analyzing the C / C++ source code (S120). Then, the processing specification unit 117 (see Figure 2) identifies the loop statements and their reference relationships in the C / C++ source code (S121), runs a benchmark tool to determine the number of loop iterations for each loop statement, and distributes them according to thresholds (S122). Finally, the processing specification unit 117 checks the possibility of parallel processing for each loop statement (S123).

[0225] Next, the control unit 110 repeats the processing in steps S124 to S127 for the number of loop statements. The processing specification unit 117 compiles each loop statement with parallel processing specified (S125). As shown in Figure 13, the specification for parallel processing in OpenACC is "#pragmaacckernels". If a compilation error occurs, the processing specification unit 117 deletes the parallel processing specification and excludes the loop statement from offloading (S126). Then, after the control unit 110 has repeated the processing for all loop statements, it proceeds to step S128.

[0226] The processing specification unit 117 counts the number of loop statements that do not produce compilation errors and uses this as the gene length (S128), then prepares the gene sequences for the specified number of individuals. Here, it creates gene sequences for the specified number of individuals, with 0 and 1 randomly assigned as initial values. Next, the processing specification unit 117 maps the C / C++ source code to the genes and prepares the patterns for the specified number of individuals (S129). Specifically, depending on the prepared gene sequences, the processing specification unit 117 inserts a directive into the C / C++ code that specifies parallel processing if the gene value is 1 (see, for example, the #pragma directive in Figure 13).

[0227] The control unit 110 repeats the process in steps S130 to S137 for a specified number of generations. Furthermore, within the repetition of the specified number of generations, the process in steps S131 to S134 is repeated for a specified number of individuals. In other words, within the repetition of the specified number of generations, the repetition for the specified number of individuals is processed in a nested manner.

[0228] During the repetition of the specified number of individuals, the processing pattern creation unit 118 (see Figure 2) compiles the C / C++ source code with directives specified according to the gene pattern, i.e., each offload pattern, using the PGI compiler (S132). In other words, the processing pattern creation unit 118 compiles the created C / C++ code using the PGI compiler on the verification machines 10 and 11 equipped with GPUs. Here, compilation errors may occur, such as when multiple nested loop statements are specified in parallel. In this case, it is treated the same as when the processing time times out during performance measurement.

[0229] The performance measurement unit 119 (see Figure 2) deploys the compiled offload pattern executable file, i.e., the compiled offload pattern, to the verification machines 10 and 11 equipped with a CPU and GPU (S133), executes the deployed executable file, and measures the benchmark performance when offloaded (S134).

[0230] Here, for genes with the same pattern as before in intermediate generations, we do not measure them, but use the same values. In other words, if the same gene pattern as before is generated during the genetic algorithm processing, we do not compile or measure the performance of that individual, but use the same measurement values ​​as before.

[0231] In step S135, if the control unit 110 has not completed repeating the specified number of individuals, it returns to the process in step S131. If it has repeated all the specified number of individuals, it proceeds to step S136.

[0232] In step S136, the executable file creation unit 120 (see Figure 2) evaluates individuals so that those with shorter processing times have higher fitness scores, and selects individuals with high performance. The executable file creation unit 120 then performs crossover and mutation processing on the selected individuals to create the next generation of individuals (S137). This is because compilation, performance measurement, fitness setting, selection, crossover, and mutation processing are performed on the next generation of individuals. In other words, after measuring benchmark performance for all individuals, the executable file creation unit 120 sets the fitness score for each gene sequence according to the benchmark processing time. The executable file creation unit 120 then selects individuals to keep according to the set fitness scores. The executable file creation unit 120 then performs crossover, mutation, and direct copy genetic algorithm processing on the selected individuals to create the next generation of individuals.

[0233] In step S138, if the control unit 110 has not completed the specified number of generations, it returns to the process in step S130. If all of the specified generations have been repeated, it proceeds to step S139.

[0234] In step S139, after the genetic algorithm processing for the specified number of generations is completed, the executable file creation unit 120 uses the C / C++ code (highest performance parallel processing pattern) corresponding to the highest performance gene sequence as the solution and terminates the process shown in Figure 14B.

[0235] As a fundamental challenge, while a compiler can identify the limitation that this loop statement cannot be processed in parallel on the GPU, it is difficult to identify the suitability of this loop statement for GPU parallel processing.

[0236] Generally, loops with a higher number of loop iterations are said to be more suitable for GPU offloading. However, it is difficult to predict the actual performance gains from offloading to the GPU without actual measurement. Therefore, it is common practice to manually instruct the system to offload the loop to the GPU and then perform trial-and-error performance measurements.

[0237] This paper proposes automatically finding appropriate loop statements to offload to the GPU using a genetic algorithm, a type of evolutionary computation method. Starting with a general-purpose program designed for a standard CPU that is not intended for GPU processing, the paper first checks for parallelizable loop statements. Then, it genetically models these parallelizable loop statements, assigning values ​​of 1 for GPU execution and 0 for CPU execution. Performance verification is then repeatedly performed in a verification environment to search for the appropriate region.

[0238] By focusing on parallelizable loop statements and maintaining and rearranging speed-enhancing parallel processing patterns in the form of genes, the system efficiently searches for patterns that can be sped up from the vast number of possible parallel processing patterns.

[0239] In addition to appropriately extracting loop statements, regarding variables used within nested loop statements, when offloading loop statements to the GPU, if CPU-GPU transfers occur at the lower level of the nesting, transfers occur for each lower-level loop, which is inefficient. Therefore, we propose transferring variables that can be transferred at the higher level collectively at the higher level. Automatic GPU offloading of loop statements is made possible by optimization using evolutionary computation methods and reduction of CPU-GPU transfers.

[0240] Figures 15A and 15B are flowcharts of the process for selecting a pattern to offload loop statements to the FPGA. First, the code analysis unit 112 analyzes the source code to be offloaded (S150), and analyzes information on loop statements and variables according to the language of the source code.

[0241] Then, the offload range extraction unit 117a identifies the loop statements and reference relationships in the source code (S151), and narrows down the candidates for whether or not to try FPGA offloading for the identified loop statements. Arithmetic strength is one indicator of whether or not there is an offload effect for a loop statement.

[0242] The offload range extraction unit 117a calculates the arithmetic strength of the application's loop statements using an arithmetic strength analysis tool (S152). Arithmetic strength is an indicator that increases with a large number of calculations and decreases with a large number of accesses. Processes with high arithmetic strength are heavy processes for the processor. Therefore, the offload range extraction unit 117a analyzes the arithmetic strength of the loop statements using the arithmetic strength analysis tool and narrows down the loop statements with high arithmetic strength to offload candidates.

[0243] Even highly arithmetic-intensive loop statements can be problematic if they consume excessive FPGA resources when processed on an FPGA. Therefore, this section describes how to calculate the resource requirements when processing highly arithmetic-intensive loop statements on an FPGA.

[0244] The process of compiling to an FPGA involves converting high-level languages ​​such as OpenCL to hardware description levels such as HDL, and then performing actual wiring and other processing based on this. While the wiring and other processing takes a considerable amount of time, the process up to the intermediate stage of HDL only takes a few minutes. Even at the intermediate stage of HDL, the resources to be used by the FPGA, such as FlipFlops and LookUpTables, can be determined. Therefore, by looking at the intermediate stage of HDL, the amount of resources to be used can be determined in a short time, even before compilation is complete.

[0245] Therefore, in this embodiment, the processing pattern creation unit 118 first converts the target loop statement into a high-level language such as OpenCL and calculates the amount of resources. Also, since the arithmetic intensity and the amount of resources when the loop statement is offloaded are determined, the resource efficiency is defined as arithmetic intensity / resource amount or arithmetic intensity × number of loops / resource amount. Then, loop statements with high resource efficiency are further narrowed down as offload candidates.

[0246] Let's return to the flow chart in Figure 15A and continue the explanation. The processing pattern creation unit 118 uses profiling tools such as gcov and gprof to measure the number of loops in the application's loop statements (S153), and narrows down the loop statements to those with high arithmetic intensity and a high number of loops (S154).

[0247] The processing pattern creation unit 118 creates OpenCL to offload each of the narrowed-down loop statements to the FPGA (S155).

[0248] Here, we will provide some supplementary explanation regarding the OpenCL implementation of loop statements. Specifically, when implementing loop statements using OpenCL or a similar high-level language, two processes are necessary. First, the CPU processing program is divided into kernel (FPGA) and host (CPU) according to the syntax of the high-level language such as OpenCL. Second, techniques for speeding up the process are incorporated during this division. Generally, techniques for speeding up using FPGAs include local memory caching, stream processing, multiple instantiation, loop statement unpacking, nested loop merging, and memory interleaving. While these do not always have an absolute effect depending on the loop statement, they are commonly used as methods for speeding up the process.

[0249] Next, several resource-efficient loop statements are selected, and the required number of offload patterns are created using these to measure performance. FPGA acceleration can be achieved by concentrating FPGA resources on a single process, or by distributing FPGA resources across multiple processes. The offload server 100 creates a certain number of selected single-loop statement patterns and precompiles them as a preliminary step before they run on the actual FPGA.

[0250] The processing pattern creation unit 118 precompiles the created OpenCL and calculates the amount of resources to be used (S156), and narrows down the loop statements to those with high resource efficiency (S157).

[0251] Then, the executable file creation unit 120 compiles OpenCL to offload the narrowed-down loop statements (S158). The performance measurement unit 119 measures the performance of the compiled program (S159). This is the first performance measurement.

[0252] The processing pattern creation unit 118 lists the loop statements that have shown improved performance compared to the CPU during performance measurement (S160), and creates OpenCL to offload by combining the loop statements in the list (S161). The processing pattern creation unit 118 calculates the amount of resources to be used by precompiling the combined offload OpenCL (S162). This is the second calculation of the amount of resources. Alternatively, the processing pattern creation unit 118 may use the sum of the amount of resources from precompilation before the first measurement without precompilation. In this way, the number of precompilations can be reduced.

[0253] The executable file creation unit 120 compiles the combined offload OpenCL (S163). The performance measurement unit 119 measures the performance of the compiled program (S164). This is the second performance measurement.

[0254] The production environment deployment unit 121 selects the pattern with the best performance from the first and second measurements (S165) and terminates the processing of this flow.

[0255] Thus, FPGA automatic offloading of loop statements focuses on loop statements with high arithmetic strength and loop count, and high resource efficiency, creating offload patterns and performing high-speed pattern search through actual measurements in a verification environment.

[0256] When considering offloading time-consuming loop statements to an FPGA to speed up processing, predicting which loops will be most efficient is difficult. Therefore, we propose automatically measuring performance in a verification environment, similar to how it's done with GPUs. However, since it takes several hours or more to compile OpenCL and run it on an FPGA, repeatedly measuring performance using a genetic algorithm for GPU automatic offloading would result in an enormous processing time, making it impractical.

[0257] Therefore, in this embodiment, the candidate loop statements to be offloaded to the FPGA are narrowed down before conducting performance measurement trials. Specifically, first, loop statements with high arithmetic intensity are extracted from the discovered loop statements using an arithmetic intensity analysis tool such as the ROSE framework. Furthermore, loop statements with a large number of loop iterations are also extracted using profiling tools such as gcov or gprof.

[0258] Then, loop statements with high arithmetic intensity and a large number of loop iterations are selected as candidates and converted to OpenCL. The created OpenCL is precompiled for the offload candidate loop statements with high arithmetic intensity and a large number of loop iterations to find loop statements with high resource efficiency. This is because the resources such as FlipFlop and LookUpTable to be created are known during the compilation process, allowing for further narrowing down to loop statements that use fewer resources.

[0259] Several loop statements have been selected, and their performance will be measured. FPGA acceleration can be achieved by concentrating FPGA resources on a single process, or by distributing FPGA resources across multiple processes. Therefore, the selected single loop statements are compiled to run on an actual FPGA and their performance is measured. For single loop statements that have been further accelerated, combination patterns are also created, and a second performance measurement is performed. The offload server 100 selects the fastest pattern from among the multiple patterns whose performance was measured in the verification environment as the solution.

[0260] For FPGA automatic offloading of loop statements, candidate loop statements are narrowed down using arithmetic strength, loop count, and resource usage, and then performance measurements of multiple patterns are performed in a verification environment to enable automatic offloading.

[0261] <Implementation> The offload server 100 analyzes the C / C++ source code to find loop statements and understand the program structure, including the variable data used within the loop statements. Next, the offload server 100 executes ROSE to obtain the arithmetic strength of each loop statement and uses gcov to obtain the number of loop iterations for each loop statement.

[0262] Next, the offload server 100 generates OpenCL code that offloads individual loop statements with high arithmetic intensity and high loop counts to the FPGA. The OpenCL code divides the loop statement into an FPGA kernel and the remainder into a CPU host program.

[0263] Next, the offload server 100 precompiles the created OpenCL code and calculates the amount of resources, such as FlipFlops, to be used. The amount of resources used is displayed as a percentage of the total resources. At this point, the offload server 100 selects a loop statement with high arithmetic strength, high loop count, and low resource usage (high resource efficiency) based on the arithmetic strength, loop count, and resource usage.

[0264] Next, the offload server 100 creates and compiles a test pattern using the selected loop statements as candidates. The offload server 100 measures the performance of each selected loop statement when offloaded to check if it can be sped up. If multiple loop statements can be sped up as a result, the offload server 100 also creates an OpenCL of that combination and measures its performance to check if it can be sped up compared to the individual loop statements. However, since FPGAs have limited resources, the offload server 100 will not create the patterns if the amount of resources required for multiple offloads exceeds the upper limit. Finally, the offload server 100 selects the fastest pattern from the multiple measurement patterns as the solution.

[0265] [Evaluation] Four applications specified by the user are offloaded to a mixed environment of a quantum computer 5 (Figure 1), a multi-core CPU 10d (Figure 1), a GPU 10e (Figure 1), and an FPGA 11c (Figure 1). The effectiveness is evaluated by confirming that cost-effective hardware has been selected. The evaluation conditions are divided into <Evaluation Target>, <Evaluation Method>, and <Evaluation Environment>.

[0266] <Evaluation Targets> The first evaluation target is the eigenvalue analysis problem. In the case of high-dimensional complex matrices, there is no computational procedure that can accurately represent eigenvalues ​​with a finite number of algebraic operations. For this reason, iterative methods have traditionally been used for the numerical analysis of eigenvalue problems. This can be accelerated by utilizing the superposition properties of quantum states in quantum computers. The essence of the problem is to find the eigenvalues ​​of the related matrices of a general nth-order algebraic equation, and each problem is determined by differences in parameters. Solutions to eigenvalue analysis problems on quantum computers are also implemented in Qiskit using quantum algorithms.

[0267] The second item to be evaluated is NAS.BT, a block-diagonal solver. A block-diagonal solver is a numerical method for solving partial differential equations. There are various types and implementations of numerical computation, but here we will use NAS.BT (NASA block triangular solver) as an example of a medium-scale numerical computation application with more than 100 loop statements. The parameters are set to CLASSA, with a grid size of 64*64*64, 200 iterations, and a time step of 0.0008.

[0268] The third item to be evaluated is the Himeno benchmark. The Himeno benchmark is benchmark software used to measure the performance of incompressible fluid analysis, and it solves the Poisson equation using the Jacobi iterative method. It is frequently used for manual acceleration with accelerators, and will be used to confirm that acceleration is also possible with the proposed automated method. The data size used will be LARGE (512*256*256).

[0269] The fourth item to be evaluated is MRI-Q. MRI-Q is an MRI image processing algorithm that calculates the Q matrix, which represents the scanner settings for calibration. MRI-Q is used in 3D MRI reconstruction algorithms in non-carthean space. MRI-Q is used in many fields, including IoT. Image processing using MRI-Q is necessary for things like automated monitoring of camera images, and offloading is important to improve image processing throughput. MRI-Q performs 3D MRI image processing, and the processing time is measured using data of size 64*64*64.

[0270] <Evaluation Method> The user requests the offloading of the four applications mentioned above. The service provider platform uses the offload server 100 to analyze the requested applications and performs functional block offloading and loop statement offloading on the quantum computer, multi-core CPU, GPU, and FPGA. Usage fees: Quantum computer: 90 USD / hour, Standard CPU VM: 60 USD / Month, Multi-core CPU VM: 140 USD / Month, GPU VM: 200 USD / Month, FPGA VM: 700 USD / Month. These fees are based on usage fees for public cloud services.

[0271] The functional block offload trial will be conducted as follows: Functional blocks: Eigenvalue analysis problem, NAS.BT, Himeno benchmark, MRI-Q Functional block discovery method: Functional blocks contained in the code will be compared with codes contained in the code pattern DB using the similarity detection tool Deckar.

[0272] Loop statement offloading trials are performed as follows. A genetic algorithm is used for multi-core CPUs and GPUs. Offload targets and number of loop statements: Eigenvalue analysis problem 0, NAS.BT120, Himeno benchmark 13, MRI-Q 12. Number of individuals M: Less than or equal to the number of loop statements (NAS.BT 20, Himeno benchmark 10, MRI-Q 10). Number of generations T: Less than or equal to the number of loop statements (NAS.BT 20, Himeno benchmark 10, MRI-Q 10). Goodness of fit: (Processing time) 1 / 2 Shorter processing times result in higher fitness. Furthermore, using the (-1 / 2) power prevents excessively high fitness for specific individuals with short processing times, thus narrowing the search range. Additionally, if performance measurement does not complete within a certain time (e.g., 3 minutes), a timeout is triggered, and fitness calculations are performed assuming an infinite processing time. Selection: Roulette selection is used. However, elite conservation is also performed, where the highest-fitting gene in a generation is preserved in the next generation without crossover or mutation. Crossover rate Pc: 0.9 Mutation rate Pm: 0.05

[0273] FPGAs perform filtering before measurement. Arithmetic strength filtering: Filters to the top 5 loop statements in arithmetic strength analysis. Resource efficiency filtering: Filters to the top 3 loop statements in resource efficiency analysis (selecting the top 3 loop statements with high arithmetic strength / resource amount). Number of measured offload patterns: 4 (the first time, the top 3 loop statement offload patterns are measured, and the second time, a combination pattern of the two loop statement offloads that performed well in the first time is measured). Performance measurement: Processing time is measured with the sample parameters as they are. Under the above conditions, functional block offload trials and loop statement offload trials are performed, the processing time when offloading is performed is measured, and the measurement results and usage fees for 4 applications are presented to the user.

[0274] <Evaluation Environment> Figure 16 is a table showing the performance measurement environment and specifications for the multi-core CPU, FPGA, GPU, and offload to the quantum computer in the network system 1 of Figure 1. The quantum computer 5 (Figure 1) used is Azure Quantum on an external cloud 6. The offload server 100 (Figure 1) is processed via the internet 4 through a Qiskit implementation for quantum computers. The multi-core CPU 10d (Figure 1) used is an AMD Ryzen ThreadrIPper 2990WX (32 cores), and OpenMP processing uses gcc 10.1. The GPU 10e (Figure 1) used is an NVIDIA GeForce RTX 2080 Ti (CUDA core: 4352, Memory: GDDR6 11GB), and OpenACC processing uses the PGI compiler 19.10 and CUDAToolkit 10.1. The Ryzen and GeForce are installed on the same node. The FPGA 11c (Figure 1) uses an Intel PACD5005 (Intel Stratix 10GXFPGA). The compilation machine (PGI compiler 10b) (Figure 1) is a DELL EMC PowerEdge R740 (CPU: Intel Xeon Bronze3206R *2, RAM: 32GB RDIMM *4), and OpenCL is compiled using Intel AccelerationStack 2.0.

[0275] Here, the user specifies the C / C++ language application they will be using from client PC 2 (Client Notebook PC) (Figure 1) (C / C++ code 2a) (Figure 1), and the Verification Machine uses Deckard to compare and search against the database on the same node. The processing time is measured by the Verification Machine, etc., appropriate hardware is determined, and it is deployed to the commercial environment used by actual users.

[0276] [Results] Figure 17 is a table showing the processing time, performance improvement, and cost-effectiveness when the four applications were offloaded to a mixed environment, with the normal CPU VM set to "1". The four applications automatically select the hardware with the highest cost-effectiveness.

[0277] First, eigenvalue analysis problems are often unsolvable by conventional CPUs, but by offloading the problem to quantum computer 5 (Figure 1), the processing is completed in about 15 seconds (Figure 17). Next, NAS.BT automatically selects a multi-core CPU as the appropriate offload destination based on the results of loop statement offloading trials, demonstrating more than five times the performance and 2.3 times the cost-effectiveness of a conventional CPU.

[0278] Next, the Himeno benchmark, after attempting loop statement offloading, automatically selects the appropriate GPU as the offload destination, demonstrating more than 20 times the performance and 6.6 times the cost-effectiveness of a typical CPU.

[0279] Next, MRI-Q automatically selected an FPGA as the appropriate offload destination based on the results of loop statement offloading trials, demonstrating performance more than 11 times faster than a typical CPU and 1.01 times better cost performance (generally, FPGA instances often cost about 10 times more than typical CPU VMs, so their cost performance is not that high).

[0280] The time it takes to offload varies; functional block offload attempts complete in seconds, while loop statement offload attempts require more time. For multi-core CPUs and GPUs, the time depends on the number of measurements in the genetic algorithm. For NAS.BT and other systems with many for loops and a high number of measurements, it can take around 8 hours. Similarly, for FPGAs, compiling OpenCL and performing a single measurement takes about 8 hours, so the time increases significantly with a higher number of measurements.

[0281] Without using quantum computers, offloading loop statements to the GPU involves measuring the performance of multiple offload patterns in a test environment and selecting the fastest pattern. For example, even in large-scale applications like Darknet, which have over 100 for loops, automatic offloading to the GPU has resulted in a 3x speedup. However, depending on the application type, there were many cases where the GPU could not provide sufficient speedup. This embodiment enables cost-effective processing of many applications by offloading to the appropriate hardware in a mixed environment of multi-core CPUs, GPUs, and FPGAs, including quantum computers.

[0282] [Effects] As described above, the offload server 100 (Figure 1) according to the embodiment includes: a storage unit (quantum computer code pattern DB 132) (Figure 2) that registers the code of the computation part suitable for the quantum computer 5 (Figures 2 and 4) and stores in a database the processing part for using the quantum computer with the quantum algorithm corresponding to that code; a code analysis unit 112 (Figure 2) that performs syntactic analysis of the source code of the software program and analyzes the computation part of the structure that can be executed by the quantum computer 5 from the source code; a replacement function detection unit 113 (Figure 2) that compares the computation part of the structure analyzed by the code analysis unit 112 with the information registered in the storage unit (quantum computer code pattern DB 132) and detects the computation part suitable for the quantum computer 5; a replacement processing unit 114 (Figure 2) that reads the computation processing part suitable for the quantum computer 5 detected by the replacement function detection unit 113 from the storage unit (quantum computer code pattern DB 132) and replaces it with the quantum computer processing part implemented with an open-source framework; and a quantum processing unit 114 that uses the quantum computer processing part replaced by the replacement processing unit 114 to perform quantum A quantum computer executable file creation unit 115 creates a quantum computer processing executable file 132 (Figure 2) to be executed by computer processing; a quantum computer processing execution unit 116 offloads the created quantum computer processing executable file 132 to the quantum computer 5; a processing pattern creation unit 118 creates patterns that offload functional blocks of the software program source code that can be executed by an accelerator to one of the accelerators, and also creates patterns that offload loop statements of the software program to one of the accelerators; a performance measurement unit 119 measures the total processing time and the quantum computer-side processing time when processing is offloaded to the quantum computer 5, and measures the performance by deploying each pattern that offloads functional blocks or loop statements to an accelerator to a verification environment; and for multiple types of accelerators including the quantum computer 5 (multicore CPU, GPU, FPGA), the processing part of the calculation suitable for the quantum computer 5, or the source code of the software program, functional blocks that can be executed by an accelerator, orThe system includes a control unit 110 that selects the most high-performance pattern (for example, the fastest pattern or the most efficient pattern when applied to the accelerator in question) from among the patterns for offloading any of the loop statements in the software program.

[0283] In this way, the offload server 100 can automatically improve performance even when migrating to an environment where multiple types of accelerators, including the quantum computer 5, are mixed. In particular, it can automatically offload computational parts suitable for the quantum computer 5 to the quantum computer 5 for processing, allowing users to utilize the quantum computer even without specialized knowledge. For example, problems that become unsolvable on a normal CPU machine due to their size, such as the traveling salesman problem, as well as the knapsack problem and prime factorization, can be processed by offloading them to the quantum computer.

[0284] In the offload server 100 (Figure 1), the control unit 110 attempts to offload to the quantum computer 5, then attempts to offload a functional block to an accelerator, followed by the loop statement, and then attempts to offload the functional block and / or the loop statement to an accelerator in the following order: multicore CPU, GPU, FPGA.

[0285] In this way, the offload server 100 can efficiently search for patterns that can accelerate processing in an environment where multiple types of accelerators, including the quantum computer 5, are mixed. That is, since it is financially difficult to occupy a quantum computer for a long time for verification, when offloading to a quantum computer, it is necessary to offload only the calculations that are effective in a single run without repeated testing. For this reason, the first attempt is to offload to the quantum computer 5.

[0286] Furthermore, if a GPU is predicted to be suitable, offload testing can be performed on the GPU first. If the expected performance is met, testing on a multi-core CPU or FPGA can be omitted. In particular, since FPGAs take a long time from compilation to actual hardware measurement, if reasonably good results are obtained with multi-core CPU or GPU offload testing that takes a similar amount of time, FPGAs can be skipped.

[0287] In the offload server 100 (Figure 1), the control unit 110, if the performance measured by the performance measurement unit 119 for offloading a functional block to one of the accelerators is not as desired, creates a pattern by the processing pattern creation unit 118 for offloading the loop statement of the software program to one of the accelerators, and the performance measurement unit 119 deploys each pattern to the verification environment and measures its performance.

[0288] In this way, the offload server 100 can automatically improve its performance even when migrating to an environment where multiple types of accelerators, including the quantum computer 5, are mixed together.

[0289] Furthermore, the Qiskit used in this embodiment can be used with quantum computers other than Azure Quantum. It can also be applied to new hardware such as DPUs, not just quantum computers.

[0290] Furthermore, among the processes described in the above embodiments, all or part of the processes described as being performed automatically can be performed manually, or all or part of the processes described as being performed manually can be performed automatically by known methods. In addition, the processing procedures, control procedures, specific names, and information including various data and parameters shown in the above documents and drawings can be arbitrarily changed unless otherwise specified. Moreover, each component of each illustrated device is a functional concept and does not necessarily have to be physically configured as shown. In other words, the specific forms of distribution and integration of each device are not limited to those shown, and all or part of them can be functionally or physically distributed and integrated in any unit according to various loads and usage conditions.

[0291] Furthermore, each of the above configurations, functions, processing units, and processing means may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. Alternatively, each of the above configurations and functions may be implemented in software for the processor to interpret and execute programs that realize each function. Information such as programs, tables, and files that realize each function can be stored in memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC (Integrated Circuit) card, an SD (Secure Digital) card, or an optical disc.

[0292] 1 Network System 2a User Application 2 Client PC (Client) 3 Network 4 Internet 5 Quantum Computer 6 External Cloud 10, 11 Verification Machine 12 Input / Output Unit 13 Storage Unit 100 Offload Server 110 Control Unit (Environmental Adaptation Function Unit) 111 Code Specification Unit 112 Code Analysis Unit 113 Replacement Function Detection Unit 114 Replacement Processing Unit 115 Quantum Computer Executable File Creation Unit 116 Quantum Computer Processing Execution Unit 117 Processing Specification Unit 117a Offload Range Extraction Unit 117b Intermediate Language File Output Unit 118 Processing Pattern Creation Unit 119 Performance Measurement Unit 119a Executable File Placement Unit 120 Executable File Creation Unit 121 Production Environment Placement Unit 122 Performance Measurement Test Extraction Execution Unit 123 User Provision Unit 131 Test Case DB 132 Quantum Computer Code Pattern DB 133 Mixed Code Pattern Database 134 Quantum Computer Processing Executable File 135 Intermediate Language File

Claims

1. A storage unit that registers the code of the computation part suitable for a quantum computer and stores in a database the processing part for using the quantum computer with the quantum algorithm corresponding to that code; a code analysis unit that performs syntactic analysis of the source code of a software program and analyzes the computation part of a structure that can be executed by the quantum computer from the source code; a replacement function detection unit that compares the computation part of the structure analyzed by the code analysis unit with the information registered in the storage unit and detects the computation part suitable for the quantum computer; a replacement processing unit that reads the computation processing part suitable for the quantum computer detected by the replacement function detection unit from the storage unit and replaces it with a quantum computer processing part implemented with an open-source framework; an executable file creation unit that creates a quantum computer processing executable file to be executed by the quantum computer based on the quantum computer processing part replaced by the replacement processing unit; and a quantum computer processing execution unit that offloads the created quantum computer processing executable file to the quantum computer. An offload server comprising: a processing pattern creation unit that creates patterns for offloading functional blocks of a software program's source code that can be executed by an accelerator to one of the accelerators, and for offloading loop statements of the software program to one of the accelerators; a performance measurement unit that measures the total processing time and the quantum computer's processing time when the processing is offloaded to the quantum computer, and measures the performance of each of the patterns that offload the functional blocks or loop statements to the accelerators by deploying them to a verification environment; and a control unit that selects the highest-performing pattern from among the patterns that offload the processing part of the calculation suitable for the quantum computer, or the functional blocks or loop statements, for a plurality of types of accelerators, including the quantum computer.

2. The offload server according to claim 1, characterized in that the control unit attempts to offload to the quantum computer, then attempts to offload the functional block to the accelerator, then attempts to offload the loop statement, and attempts to offload the accelerator to which the functional block and / or the loop statement is to a multi-core CPU, a GPU, and an FPGA in that order.

3. The offload server according to claim 1 or 2, characterized in that, if the performance measured by the performance measurement unit for offloading the functional block to any of the accelerators is not as desired, the control unit creates a pattern for offloading the loop statement of the software program to any of the accelerators, and the performance measurement unit deploys each of the patterns to the verification environment and measures the performance.

4. Offload control method for an offload server, wherein the offload server includes a storage unit that registers the code of the computation part suitable for a quantum computer and stores in a database the processing part for using the quantum computer with the quantum algorithm corresponding to the code, the method comprising: parsing the source code of a software program and analyzing the computation part of a structure that can be executed by the quantum computer from the source code; comparing the computation part of the analyzed structure with the information registered in the storage unit to detect the computation part suitable for the quantum computer; reading the detected computation processing part suitable for the quantum computer from the storage unit and replacing it with a quantum computer processing part implemented with an open-source framework; creating a quantum computer processing executable file to be executed by the quantum computer based on the replaced quantum computer processing part; offloading the created quantum computer processing executable file to the quantum computer; creating a pattern in which the source code of the software program offloads functional blocks that can be executed by an accelerator to one of the accelerators, and creating a pattern in which the loop statements of the software program offload to one of the accelerators, An offload control method characterized by the steps of: measuring the total processing time and the processing time on the quantum computer side when the processing is offloaded to the quantum computer; deploying each of the patterns that offload the functional block or the loop statement to the accelerator to a verification environment and measuring its performance; and selecting the highest-performing pattern from among a plurality of accelerators, including the quantum computer, that offloads either the processing part of the calculation suitable for the quantum computer, or a functional block of the source code of the software program that can be executed by the accelerator, or a loop statement of the software program.

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