Ad converting device and method for correcting ad conversion value

Abstract

According to the present invention, errors between interleaved AD converters are reduced while eliminating the need to generate an analog input signal using a DA converter.　This AD converting device comprises: a plurality of AD converters; a multiphase clock generator that generates multiphase clocks for the plurality of AD converters on the basis of a reference clock; a multiplexer that combines AD conversion values of the plurality of AD converters; a phase interpolator (PI) that adjusts the phase of the reference clock; a delay adjusting circuit that adjusts the delay of the multiphase clock for each AD converter; and a switching unit that switches the inputs of the plurality of AD converters between the reference clock and an analog input signal.

Description

AD Conversion Device and AD Conversion Value Correction Method

[0001] This technology relates to an AD conversion device and an AD conversion value correction method. Specifically, this technology relates to an AD conversion device and an AD conversion value correction method that are accelerated based on the interleaved operation of a plurality of AD converters.

[0002] As a method for accelerating the AD conversion speed, there is a time-interleaved method. This combines a plurality of AD converters and applies a polyphase clock to each AD converter, so that each AD converter operates at a low AD conversion speed while achieving an overall increase in the AD conversion speed. For example, in an AD conversion device that drives a plurality of AD converters at a clock frequency corresponding to the number of converters, a technique is disclosed in which the output of each AD converter is subjected to FFT processing, and the offset error, gain error, and phase error between the reference AD converter and other AD converters are calculated from the calculation results (see, for example, Patent Document 1).

[0003] Japanese Unexamined Patent Application Publication No. 2012-15615

[0004] However, in the above-mentioned conventional technology, a sine wave generation circuit is used to generate a reference analog input signal. The DAC used in the sine wave generation circuit requires a sufficiently high accuracy compared to the AD converter for which error correction is performed, which may lead to an increase in power consumption and circuit area.

[0005] This technology was created in view of such a situation, and aims to reduce the error between interleaved AD converters while eliminating the need to generate an analog input signal using a DAC.

[0006] This technology was developed to solve the aforementioned problems, and its first aspect is an AD conversion device comprising: a plurality of AD converters; a multiphase clock generator that generates multiphase clocks for the plurality of AD converters based on a reference clock; a multiplexer that synthesizes the AD conversion values ​​of the plurality of AD converters; a Phase Interpolator (PI) that adjusts the phase of the reference clock; a delay adjustment circuit that adjusts the delay of the multiphase clock for each of the AD converters; and a switching unit that switches the input of the plurality of AD converters between the reference clock and an analog input signal. This eliminates the need to generate an analog input signal using a DA converter, while reducing errors between interleaved AD converters.

[0007] Furthermore, in the first aspect, the delay adjustment circuit may correct the timing mismatch between the plurality of AD converters based on the phase detection results of the plurality of AD converters. This eliminates the need to generate an analog input signal using a DA converter while correcting the timing mismatch between the plurality of AD converters.

[0008] Furthermore, in the first aspect, a correction circuit may be provided that corrects the offset mismatch and gain mismatch between the plurality of AD converters based on the amplitude detection results of the plurality of AD converters. This eliminates the need to generate an analog input signal using a DA converter, while correcting the offset mismatch and gain mismatch between the plurality of AD converters.

[0009] Furthermore, in the first aspect, the system may include an error detection circuit for detecting errors in the AD conversion values ​​of the multiple AD converters. This results in the correction of errors in the AD conversion values ​​of the multiple AD converters based on the errors in the AD conversion values ​​of the multiple AD converters.

[0010] Furthermore, in the first aspect, the error detection circuit may detect the error in the AD conversion values ​​of the plurality of AD converters based on the FFT (Fast Fourier Transform) result of the AD conversion values ​​of the plurality of AD converters when the phase of the reference clock is set. This results in the detection of the error in the AD conversion values ​​of the plurality of AD converters based on the AD conversion values ​​of the plurality of AD converters.

[0011] Furthermore, in the first aspect, the system may include a switching unit that selectively outputs the AD conversion values ​​of each of the multiple AD converters, and a storage unit that stores correction values ​​for the errors in the AD conversion values ​​of the AD converters. This allows the errors in the AD conversion values ​​of the multiple AD converters to be corrected without requiring the AD conversion device to have a built-in correction value calculation function.

[0012] Furthermore, in the first aspect, the system may include a processor that calculates a correction value for the error of the AD conversion values ​​of the multiple AD converters based on the AD conversion values ​​of each of the multiple AD converters and stores it in the storage unit. This allows the correction value for the error of the AD conversion values ​​of the multiple AD converters to be calculated without connecting a tester to the AD converter.

[0013] Furthermore, the second aspect is an AD conversion value correction method comprising the steps of: driving a plurality of AD converters based on a multiphase clock generated from a reference clock with set phase, obtaining the AD conversion value of the reference clock from the plurality of AD converters; detecting an error in the AD conversion value of the reference clock; calculating a correction value for the error of the AD conversion value of the AD converters based on the detection result of the error in the AD conversion value of the reference clock; and correcting the error of the AD conversion value of the AD converters based on the correction value for the error of the AD conversion value of the AD converters. This eliminates the need to generate an analog input signal using a DA converter and reduces errors between interleaved AD converters.

[0014] Furthermore, in a second aspect, the phase may be set to one of several phases between 0° and 360°. This results in the separation of timing mismatch, offset mismatch, and gain mismatch.

[0015] Furthermore, in a second aspect, the error in the AD conversion value may include timing errors, offset errors, and gain errors. This results in the correction of timing mismatches, offset mismatches, and gain mismatches based on the detection result of the error in the AD conversion value of the reference clock.

[0016] This is a block diagram showing an example configuration of the AD converter according to the first embodiment. This is a diagram showing a method for correcting timing errors in the AD converter according to the first embodiment. This is a diagram showing the AD conversion result when there is no timing error in the AD converter according to the first embodiment. This is a diagram showing the AD conversion result when the PI phase is set when there is no timing error in the AD converter according to the first embodiment. This is a diagram showing the AD conversion result when the PI phase is set when there is no timing error in the AD converter according to the first embodiment. This is a diagram showing the AD conversion result when the PI phase is set when there is no timing error in the AD converter according to the first embodiment. This is a diagram showing the AD conversion result when the PI phase is set when there is no timing error in the AD converter according to the first embodiment. This is a diagram showing the AD conversion result when there is a timing error in the AD converter according to the first embodiment. This is a diagram showing the AD conversion result when the PI phase is set when there is a timing error in the AD converter according to the first embodiment. This is a diagram showing the AD conversion result when the PI phase is set when there is a timing error in the AD converter according to the first embodiment. This is a diagram showing the AD conversion result when the PI phase is set when there is a timing error in the AD converter according to the first embodiment. This figure shows the AD conversion result when the PI phase is set in the case of a timing error in the AD converter according to the first embodiment. This figure shows the FFT (Fast Fourier Transform) calculation result when there is a timing error in the AD converter according to the first embodiment. This figure shows the FFT calculation result when there is no offset error and gain error in the AD converter according to the first embodiment. This figure shows the FFT calculation result when there is an offset error and gain error in the AD converter according to the first embodiment. This block diagram shows an example of the configuration of the AD converter according to the second embodiment during testing. This block diagram shows an example of the configuration of the AD converter according to the second embodiment at the time of shipment. This block diagram shows an example of the configuration of the AD converter according to the third embodiment. This block diagram shows an example of the configuration of the AD converter according to the fourth embodiment. This block diagram shows an example of the configuration of the AD converter according to the fifth embodiment. This block diagram shows an example of the configuration of the AD converter according to the sixth embodiment. This block diagram shows a schematic example of the configuration of the vehicle control system.This is an explanatory diagram showing an example of the installation location of the imaging unit.

[0017] The following describes the embodiments for implementing this technology (hereinafter referred to as embodiments). The description will be in the following order: 1. First embodiment (an example in which multiple AD converters are driven based on a multiphase clock generated from a reference clock with set phase, and the error in the AD conversion value of the AD converter is corrected based on the detection result of the error in the AD conversion value of the reference clock obtained from the multiple AD converters) 2. Second embodiment (an example in which a tester connected to the AD converter calculates the correction value for the error in the AD conversion value of the AD converter and stores it in the AD converter) 3. Third embodiment (an example in which a processor provided in the AD converter calculates the correction value for the error in the AD conversion value of the AD converter and stores it in the AD converter) 4. Fourth embodiment (an example in which an AD converter that corrects the error in the AD conversion value of the AD converter based on the detection result of the error in the AD conversion value of the reference clock obtained from multiple AD converters is applied to a serial interface) 5. Fifth Embodiment (An example in which an AD converter that corrects the error in the AD conversion value of an AD converter based on the detection result of the error in the AD conversion value of a reference clock acquired from multiple AD converters is applied to a serial interface, and the PI is driven based on a two-phase signal with a phase shift of 90°) 6. Sixth Embodiment (An example in which an AD converter that corrects the error in the AD conversion value of an AD converter based on the detection result of the error in the AD conversion value of a reference clock acquired from multiple AD converters is applied to a serial interface, and the reference clock generated by the PLL is divided and input to the AD converter) 7. Application Examples to Mobile Devices

[0018] <1. First Embodiment> Figure 1 is a diagram showing an example of the configuration of an AD converter according to the first embodiment. In the following description, the interleaved operation of four AD converters AD1 to AD4 is used as an example, but it may also be applied to the interleaved operation of N (where N is an integer of 2 or more) AD converters.

[0019] In the figure, the AD conversion device 10 includes a switching unit 11, AD converters AD1 to AD4, a PI (Phase Interpolator) 13, a multiphase clock generator 14, an error detection circuit 15, delay adjustment circuits PA1 to PA4, correction circuits HS1 to HS4, and a multiplexer 16.

[0020] The switching unit 11 switches the input from each AD converter AD1 to AD4 using a reference clock CLK and an analog input signal SIN. The analog input signal SIN is, for example, a sensing signal detected by a sensor. The sensing target is, for example, light, vibration, pressure, temperature, flow rate, radiation, etc. The output from the switching unit 11 is input in parallel to each AD converter AD1 to AD4 via the buffer 12. The reference clock CLK may be a sine wave or a square wave.

[0021] Each AD converter, AD1 to AD4, digitizes an analog signal. The analog signal is selected from the analog input signal SIN and the reference clock CLK. Each AD converter, AD1 to AD4, can perform AD conversion in parallel.

[0022] PI13 adjusts the phase of the reference clock CLK. Here, when the inputs of each A / D converter AD1 to AD4 are switched to the reference clock CLK, PI13 can change the phase of the reference clock CLK between 0° and 360°. At this time, PI13 can adjust the phase of the reference clock CLK based on the phase setting information (PI control code) PCD. On the other hand, when the inputs of each A / D converter AD1 to AD4 are switched to the analog input signal SIN, PI13 can set the phase of the reference clock CLK to an optimal value. The optimal value may be the point where the center of the eye pattern is widest.

[0023] The multiphase clock generator 14 generates multiphase clocks CK1 to CK4 for each AD converter AD1 to AD4 based on a reference clock CLK. At this time, each AD converter AD1 to AD4 is driven based on the multiphase clocks CK1 to CK4.

[0024] The multiplexer 16 synthesizes the AD conversion values ​​Ch1 to Ch4 from each AD converter AD1 to AD4. At this time, the multiplexer 16 can output a digital value DOUT which combines the AD conversion values ​​Ch1 to Ch4 from each AD converter AD1 to AD4 into a single system.

[0025] The error detection circuit 15 detects the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4. At this time, the error detection circuit 15 can detect the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 based on the FFT (Fast Fourier Transform) result of the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 when the phase of the reference clock CLK is set. The error in the AD conversion values ​​Ch1 to Ch4 may include timing error (also called skew error), offset error EO, ​​and gain error EG.

[0026] Here, the error detection circuit 15 calculates timing correction values ​​HV1, HV2, HV3, and HV4 for each AD converter AD1 to AD4 based on the timing error, and outputs them from the delay adjustment circuit PA1 to PA4.

[0027] The delay adjustment circuits PA1 to PA4 adjust the delay of the multiphase clocks CK1 to CK4 for each AD converter AD1 to AD4. At this time, the delay adjustment circuits PA1 to PA4 can correct the timing mismatch between AD converters AD1 to AD4 based on the phase detection results of each AD converter AD1 to AD4. For example, the delay adjustment circuits PA1 to PA4 can adjust the delay of the multiphase clocks CK1 to CK4 based on the timing correction values ​​HV1, HV2, HV3, and HV4 calculated by the error detection circuit 15.

[0028] The correction circuits HS1 to HS4 correct the offset mismatch and gain mismatch between AD converters AD1 to AD4 based on the detection results of the amplitudes of the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4. For example, the correction circuits HS1 to HS4 can correct the offset mismatch and gain mismatch between AD converters AD1 to AD4 based on the offset error EO and gain error EG detected by the error detection circuit 15.

[0029] Here, when an error is detected in each AD converter from AD1 to AD4, the inputs from each AD converter from AD1 to AD4 are switched to the reference clock CLK. Also, based on the phase setting information PCD input to PI13, the phase of the reference clock CLK is changed between 0° and 360°.

[0030] Then, in the multiphase clock generator 14, multiphase clocks CK1 to CK4 are generated for each phase of the reference clock CLK, and each AD converter AD1 to AD4 is driven by the multiphase clocks CK1 to CK4. At this time, each delay adjustment circuit PA1 to PA4 can bypass the adjustment of the delay of the multiphase clocks CK1 to CK4.

[0031] The AD conversion values ​​Ch1 to Ch4 from each AD converter AD1 to AD4 are input to the error detection circuit 15, and the error of each AD converter AD1 to AD4 is detected. Here, the error detection circuit 15 can calculate and store the timing correction values ​​HV1, HV2, HV3, and HV4 for each AD converter AD1 to AD4 based on the timing error. The error detection circuit 15 can also detect and store the offset error EO and the gain error EG.

[0032] On the other hand, during normal operation of each A / D converter AD1 to AD4, the inputs of each A / D converter AD1 to AD4 are switched to the analog input signal SIN. In addition, the phase of the reference clock CLK is set to the optimal value.

[0033] Then, in the multiphase clock generator 14, multiphase clocks CK1 to CK4 are generated for each phase of the reference clock CLK, and each AD converter AD1 to AD4 is driven by the multiphase clocks CK1 to CK4. At this time, in each delay adjustment circuit PA1 to PA4, the delay of the multiphase clocks CK1 to CK4 is adjusted based on the timing correction values ​​HV1, HV2, HV3, and HV4 calculated by the error detection circuit 15 before being input to each AD converter AD1 to AD4.

[0034] Then, the AD conversion values ​​Ch1 to Ch4 from each AD converter AD1 to AD4 are input to the multiplexer 16 via correction circuits HS1 to HS4. At this time, each correction circuit HS1 to HS4 corrects the offset error EO and gain error EG detected by the error detection circuit 15 to correct the offset mismatch and gain mismatch between AD converters AD1 to AD4 before inputting them to the multiplexer 16.

[0035] Figure 2 is a diagram showing a method for correcting timing errors in an AD converter according to the first embodiment. In the figure, a is a diagram showing the relationship between the analog input signal SIN and the multiphase clocks CK1 to CK4 before timing correction. In the figure, b is a diagram showing the relationship between the analog input signal SIN and the multiphase clocks CK1 to CK4 after timing correction.

[0036] In figure a, it is assumed that there is no timing error in the AD conversion values ​​Ch1, Ch2, and Ch4 of each AD converter AD1, AD2, and AD4, and that there is a timing error in the AD conversion value Ch3 of AD converter AD3.

[0037] At this time, there is no timing error at the sampling points P1, P2, and P4 of each AD converter AD1, AD2, and AD4, but a timing error occurs at the sampling point P3 of AD converter AD3. Here, the error detection circuit 15 detects the timing error of AD converter AD3 based on the sampling point P3 of AD converter AD3 and calculates the timing correction value HV3. Then, as shown in b of the figure, the delay adjustment circuit PA3 adjusts the delay of the multiphase clock CK3 based on the timing correction value HV3.

[0038] FIG. 3 is a diagram showing an AD conversion result when there is no timing error in the AD conversion device according to the first embodiment.

[0039] In this figure, when there is no timing error, the output codes of the AD conversion values Ch1 to Ch4 of the AD converters AD1 to AD4 coincide with each other.

[0040] FIGS. 4 to 7 are diagrams showing AD conversion results at the time of PI phase setting when there is no timing error in the AD conversion device according to the first embodiment. In this figure, examples in which the phase of the reference clock CLK is changed to 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315° are shown.

[0041] In this figure, when there is no timing error, there is no phase shift between the AD conversion values Ch1 to Ch4 of the AD converters AD1 to AD4 at each phase of the reference clock CLK.

[0042] FIG. 8 is a diagram showing an AD conversion result when there is a timing error in the AD conversion device according to the first embodiment. In this figure, an example in which a phase shift occurs in the AD conversion value Ch3 of the AD converter AD3 is shown.

[0043] In this figure, when there is a timing error, a phase difference appears between the AD conversion values Ch1 to Ch4 of the AD converters AD1 to AD4.

[0044] At this time, the error detection circuit 15 performs an FFT of the AD conversion values Ch1 to Ch4 with respect to the phase (PI control code) for each of the AD conversion values Chl to Ch4 of the AD converters AD1 to AD4. The FFT calculation result has the PI control code on the horizontal axis. For example, when the PI control code is 128, the horizontal axis takes values from 0 to 64. At this time, the horizontal axis 0 is the frequency f0 and indicates DC. The horizontal axis 1 is the frequency f1 and indicates a sine wave for one cycle.

[0045] Then, the error detection circuit 15 extracts the phase component of the frequency f1 from the FFT calculation result. At this time, the relative deviation component of the phases of the AD conversion values Ch1 to Ch4 becomes the timing error. Each delay adjustment circuit PA1 to PA4 can correct the timing error by delaying and adjusting this timing error difference.

[0046] Note that it is not necessary to calculate all frequencies for the FFT, and it may be performed only for the frequency f1. The reference clock CLK may be a rectangular wave in addition to a sine wave. Since a rectangular wave is the sum of the reference frequency and its odd harmonics, the odd harmonics may be ignored from the FFT calculation result. At this time, there may be distortion in the AD converters AD1 to AD4 and the buffer 12. This timing error detection method is not affected by the offset error and gain error of each of the AD converters AD1 to AD4.

[0047] Figs. 9 to 12 are diagrams showing the AD conversion results at the time of PI phase setting when there is a timing error in the AD conversion device according to the first embodiment. In the figure, an example in which the phase of the reference clock CLK is changed to 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315° is shown.

[0048] In the figure, when there is a timing error, a phase shift occurs between the AD conversion values Ch1 to Ch4 of each of the AD converters AD1 to AD4 at each phase of the reference clock CLK. In the figure, an example in which a phase shift occurs in the AD conversion value Ch3 of the AD converter AD3 is shown.

[0049] Fig. 13 is a diagram showing the FFT calculation result when there is a timing error in the AD conversion device according to the first embodiment. In the figure, a shows the relationship between the frequency and amplitude for each FFT of the AD conversion values Ch1 to Ch4. b in the figure shows the relationship between the frequency and phase for each FFT of the AD conversion values Ch1 to Ch4.

[0050] In figure b, the phases of the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 are reflected in the phases TM1 to TM4 at frequency f1 of the FFT calculation results for the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4. For example, if a phase shift occurs in the AD conversion value Ch3 of AD converter AD3, it is reflected in the phase TM3 at frequency f1 of the FFT calculation result for the AD conversion value Ch3. Therefore, the error detection circuit 15 can detect the relative phase shift component of the AD conversion value Ch3 from the phase component at frequency f1 of the FFT calculation result.

[0051] Figure 14 shows the FFT calculation results for the AD converter according to the first embodiment when there is no offset error and gain error. In the figure, a shows the relationship between frequency and amplitude for each FFT of AD conversion values ​​Ch1 to Ch4. In the figure, b shows the relationship between frequency and phase for each FFT of AD conversion values ​​Ch1 to Ch4.

[0052] In figure a, the offset between the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 is reflected in the amplitudes OF1 to OF4 at frequency f0 of the FFT calculation results of the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4. If there is no offset mismatch between the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4, the amplitudes OF1 to OF4 at frequency f0 of the FFT calculation results of the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 will match.

[0053] The gains of the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 are reflected in the amplitudes GA1 to GA4 at frequency f1 of the FFT calculation results for the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4. If there is no gain mismatch between the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4, the amplitudes GA1 to GA4 at frequency f1 of the FFT calculation results for the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 will match.

[0054] Figure 15 shows the FFT calculation results for the AD converter according to the first embodiment when there is an offset error and a gain error. In the figure, a shows the relationship between frequency and amplitude for each FFT of AD conversion values ​​Ch1 to Ch4. In the figure, b shows the relationship between frequency and phase for each FFT of AD conversion values ​​Ch1 to Ch4.

[0055] In the figure, at point a, if there is an offset mismatch between the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4, a shift occurs in the amplitude OF1 to OF4 at frequency f0 of the FFT calculation result of the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4. For example, if an offset mismatch occurs in the AD conversion value Ch1 of AD converter AD1, it is reflected in the amplitude OF1 at frequency f0 of the FFT calculation result of the AD conversion value Ch1. Therefore, the error detection circuit 15 can detect the relative shift component of the offset of the AD conversion value Ch1 from the amplitude component at frequency f0 of the FFT calculation result.

[0056] At this time, the error detection circuit 15 performs an FFT on the phase (PI control code) of each AD conversion value Ch1 to Ch4 from each AD converter AD1 to AD4. The error detection circuit 15 then extracts the amplitude component of frequency f0 from the FFT calculation result. At this time, the relative deviation component of the amplitude of frequency f0 of the AD conversion values ​​Ch1 to Ch4 becomes the offset error EO. Each correction circuit HS1 to HS4 can correct the offset mismatch between AD converters AD1 to AD4 based on this offset error EO.

[0057] If there is a gain mismatch between the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4, a shift will occur in the amplitudes GA1 to GA4 at frequency f1 of the FFT calculation results for the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4. For example, if a gain mismatch occurs in the AD conversion value Ch2 of AD converter AD2, this will be reflected in the amplitude OF2 at frequency f1 of the FFT calculation result for the AD conversion value Ch2. Therefore, the error detection circuit 15 can detect the relative shift component of the gain of the AD conversion value Ch2 from the amplitude component at frequency f1 of the FFT calculation result.

[0058] At this time, the error detection circuit 15 performs an FFT on the phase (PI control code) of each AD conversion value Ch1 to Ch4 of each AD converter AD1 to AD4. The error detection circuit 15 then extracts the amplitude component of frequency f1 from the FFT calculation result. At this time, the relative deviation component of the amplitude of frequency f1 of the AD conversion values ​​Ch1 to Ch4 becomes the gain error EG. Each correction circuit HS1 to HS4 can correct the gain mismatch between AD converters AD1 to AD4 based on this gain error EG.

[0059] As described above, in the first embodiment, the AD converters AD1 to AD4 are driven based on the multiphase clocks CK1 to CK4 generated from a phase-set reference clock CLK, and the errors in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 are corrected based on the error detection result of the AD conversion values ​​Ch1 to Ch4 of the reference clock CLK obtained from each AD converter AD1 to AD4. This makes it possible to reduce errors between the interleaved AD converters AD1 to AD4 without requiring the generation of analog input signals using a DA converter. For this reason, it is possible to correct the errors in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 without requiring a DA converter that requires sufficiently high accuracy for each AD converter AD1 to AD4, thereby suppressing increases in power consumption and circuit area.

[0060] At this time, based on the FFT calculation results of the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 when the phase of the reference clock is set, the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 can be detected. This makes it possible to correct not only the timing error of the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4, but also the offset error and gain error.

[0061] <2. Second Embodiment> In the first embodiment described above, the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 was corrected based on the detection result of the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4, which are driven based on the multiphase clocks CK1 to CK4 generated from the phase-set reference clock CLK. In this second embodiment, a tester connected to the AD converter calculates the error correction value of the AD conversion value of the AD converter and stores it in the AD converter.

[0062] Figure 16 is a block diagram showing an example of the configuration of the AD converter according to the second embodiment during testing.

[0063] In the figure, the AD converter 20 has a storage unit 21 and a switching unit 22 added to the AD converter 10 of the first embodiment described above. Also, the error detection circuit 15 is removed from the AD converter 10 of the first embodiment described above in the AD converter 20. In this case, the AD converter 20 can be connected to the tester 23 when detecting an error in each AD converter AD1 to AD4. The other configurations of the AD converter 20 are the same as those of the AD converter 10 of the first embodiment described above.

[0064] The switching unit 22 switches the output of each AD converter AD1 to AD4 between each correction circuit HS1 to HS4 and the tester 23. The switching unit 22 also switches the memory unit 21 between each delay adjustment circuit PA1 to PA4 and the tester 23. At this time, when an error is detected in each AD converter AD1 to AD4, the switching unit 22 switches the output of each AD converter AD1 to AD4 to the tester 23, and during normal operation of the AD converter 20, it switches the output of each AD converter AD1 to AD4 to each correction circuit HS1 to HS4.

[0065] The memory unit 21 stores the timing correction values ​​HV1, HV2, HV3, HV4, offset error EO, ​​and gain error EG calculated by the tester 23. At this time, the memory unit 21 is connected to the tester 23 when errors are detected in each AD converter AD1 to AD4, and is connected to each delay adjustment circuit PA1 to PA4 and each correction circuit HS1 to HS4 during the normal operation of the AD converter 20.

[0066] The tester 23 detects the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 based on the output of each AD converter AD1 to AD4. The tester 23 also inputs phase setting information PCD to PI13 when detecting an error in each AD converter AD1 to AD4. At this time, the tester 23 can change the phase of the reference clock CLK between 0° and 360° based on the phase setting information PCD. Then, the tester 23 can detect the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 based on the FFT results of the AD conversion values ​​Ch1 to Ch4 when the phase of the reference clock CLK is set. Furthermore, the tester 23 can calculate the timing correction values ​​HV1, HV2, HV3, and HV4 for each AD converter AD1 to AD4 based on the timing error and store them in the storage unit 21. In addition, the tester 23 can calculate the offset error EO and gain error EG of the AD conversion values ​​Ch1 to Ch4 for each AD converter AD1 to AD4 and store them in the storage unit 21.

[0067] Figure 17 is a block diagram showing an example of the configuration of the AD converter according to the second embodiment at the time of shipment.

[0068] In the figure, when the AD converter 20 is shipped, the AD converter 20 is disconnected from the tester 23. At this time, the switching unit 22 switches the output of each AD converter AD1 to AD4 from each correction circuit HS1 to HS4. The switching unit 22 also switches the output destination of the timing correction values ​​HV1, HV2, HV3, and HV4 stored in the memory unit 21 from each delay adjustment circuit PA1 to PA4. The switching unit 22 also switches the output destination of the offset error EO and gain error EG stored in the memory unit 21 from each correction circuit HS1 to HS4.

[0069] During normal operation of the AD converter 20, each delay adjustment circuit PA1 to PA4 adjusts the delay of the multiphase clocks CK1 to CK4 based on the timing correction values ​​HV1, HV2, HV3, and HV4 stored in the memory unit 21 before inputting them to each AD converter AD1 to AD4. In addition, each correction circuit HS1 to HS4 corrects the offset mismatch and gain mismatch of the AD conversion values ​​Ch1 to Ch4 of the AD converters AD1 to AD4 based on the offset error EO and gain error EG stored in the memory unit 21 before inputting them to the multiplexer 16.

[0070] Thus, in the second embodiment described above, the tester 23 connected to the AD converter 20 calculates the error correction value for the AD conversion values ​​Ch1 to Ch4 from each AD converter AD1 to AD4, and stores it in the AD converter 20. This allows the error in the AD conversion values ​​Ch1 to Ch4 to be corrected without detecting the error in the AD conversion values ​​Ch1 to Ch4 within the AD converter 20, thereby reducing the load on the AD converter 20.

[0071] <3. Third Embodiment> In the second embodiment described above, a tester 23 connected to the AD converter 20 calculated the error correction value for the AD conversion values ​​Ch1 to Ch4 from each AD converter AD1 to AD4 and stored it in the AD converter 20. In this third embodiment, a processor 33 provided in the AD converter 30 calculates the error correction value for the AD conversion values ​​Ch1 to Ch4 from each AD converter AD1 to AD4 and stores it in the AD converter 30.

[0072] Figure 18 is a block diagram showing an example configuration of an AD conversion device according to the third embodiment.

[0073] In the figure, this AD converter 30 includes a storage unit 31 and a switching unit 32 instead of the storage unit 21 and switching unit 22 of the second embodiment described above. Furthermore, this AD converter 30 has a processor 33 added to the AD converter 20 of the second embodiment described above. The other configurations of this AD converter 30 are the same as those of the AD converter 20 of the second embodiment described above.

[0074] The switching unit 32 switches the output of each AD converter AD1 to AD4 between each correction circuit HS1 to HS4 and the processor 33. The switching unit 32 also switches the memory unit 31 between each delay adjustment circuit PA1 to PA4 and the processor 33. At this time, when an error is detected in each AD converter AD1 to AD4, the switching unit 32 switches the output of each AD converter AD1 to AD4 to the processor 33, and during normal operation of the AD converter 30, it switches the output of each AD converter AD1 to AD4 to each correction circuit HS1 to HS4.

[0075] The memory unit 31 stores the timing correction values ​​HV1, HV2, HV3, HV4, offset error EO, ​​and gain error EG calculated by the processor 33. At this time, the memory unit 31 is connected to the processor 33 when an error is detected in each AD converter AD1 to AD4, and is connected to each delay adjustment circuit PA1 to PA4 and each correction circuit HS1 to HS4 during the normal operation of the AD converter 30.

[0076] The processor 33 detects errors in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 based on the outputs of each AD converter AD1 to AD4. The processor 33 also inputs phase setting information PCD to PI13 when detecting errors in each AD converter AD1 to AD4. At this time, the processor 33 can change the phase of the reference clock CLK between 0° and 360° based on the phase setting information PCD. The processor 33 can then detect errors in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 based on the FFT results of the AD conversion values ​​Ch1 to Ch4 when the phase of the reference clock CLK is set. Furthermore, the processor 33 can calculate timing correction values ​​HV1, HV2, HV3, and HV4 for each AD converter AD1 to AD4 based on the timing errors and store them in the storage unit 31. Furthermore, the processor 33 can calculate the offset error EO and gain error EG of the AD conversion values ​​Ch1 to Ch4 from each AD converter AD1 to AD4 and store them in the storage unit 31. The processor 33 may be a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). The processor 33 may be a single-core processor or a multi-core processor. The processor 33 may include hardware circuits such as accelerators that perform part of the processing (for example, an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit)).

[0077] During normal operation of the AD converter 30, each AD converter AD1 to AD4 is disconnected from the processor 33. At this time, the switching unit 32 switches the output of each AD converter AD1 to AD4 from each correction circuit HS1 to HS4. The switching unit 32 also switches the output destination of the timing correction values ​​HV1, HV2, HV3, and HV4 stored in the memory unit 31 from each delay adjustment circuit PA1 to PA4. Furthermore, the switching unit 32 switches the output destination of the offset error EO and gain error EG stored in the memory unit 31 from each correction circuit HS1 to HS4.

[0078] Then, each delay adjustment circuit PA1 to PA4 adjusts the delay of the multiphase clocks CK1 to CK4 based on the timing correction values ​​HV1, HV2, HV3, and HV4 stored in the memory unit 31, and then inputs them to each AD converter AD1 to AD4. In addition, each correction circuit HS1 to HS4 corrects the offset mismatch and gain mismatch of the AD conversion values ​​Ch1 to Ch4 of the AD converters AD1 to AD4 based on the offset error EO and gain error EG stored in the memory unit 31, and then inputs them to the multiplexer 16.

[0079] As described above, in the third embodiment, the processor 33 provided in the AD converter 30 calculates the error correction value for the AD conversion values ​​Ch1 to Ch4 from each AD converter AD1 to AD4 and stores it in the AD converter 30. This allows the processor 33 provided in the AD converter 30 to detect the error in the AD conversion values ​​Ch1 to Ch4, eliminating the need for a dedicated device to detect the error in the AD conversion values ​​Ch1 to Ch4, while correcting the error in the AD conversion values ​​Ch1 to Ch4.

[0080] <4. Fourth Embodiment> In the first embodiment described above, the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 was corrected based on the detection result of the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4, which are driven based on the multiphase clocks CK1 to CK4 generated from a phase-set reference clock CLK. In this fourth embodiment, an AD converter 40 that corrects the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 based on the detection result of the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 is applied to the serial interface.

[0081] Figure 19 is a block diagram showing an example configuration of an AD conversion device according to the fourth embodiment.

[0082] In the figure, the AD converter 40 includes switches 43 and 44 as the switching unit 11 of the first embodiment described above. In addition, the AD converter 40 has a resistor R, a PGA (Programmable Gain Amplifier) ​​41, a CTLE (Continuous Time Linear Equalizer) 42, a PLL (Phase Lock Loop) 45, a DFE (Decision Feedback Equalizer) / FFE (Feed Forward Equalizer) 46, a storage unit 47, a PD (Phase detector) 48, and a selector 49 added to the AD converter 10 of the first embodiment described above. In this case, the AD converter 40 can be used as a receiver. Furthermore, the AD converter 40 can be integrated into a semiconductor chip. The other configurations of the AD converter 40 are the same as those of the AD converter 10 of the first embodiment described above.

[0083] Switches 43 and 44 are turned on and off based on the mode selection signal MOD. The mode selection signal MOD selects between error detection mode and normal operation mode. When the error detection mode is selected by the mode selection signal MOD, switch 43 turns off and switch 44 turns on. On the other hand, when the normal operation mode is selected by the mode selection signal MOD, switch 43 turns on and switch 44 turns off. The error detection mode can be selected when the power is started up, when idling, or at the time of shipment.

[0084] PGA41 adjusts the gain of the analog input signal SIN and inputs it to CTLE42. The input of PGA41 is grounded via resistor R. Resistor R can be set to, for example, 50Ω.

[0085] The CTLE42 reduces ISI (Intersymbol Interference) jitter by compensating for the inverse characteristics of the insertion loss characteristics of the transmission line with a high-pass filter. In this case, the CTLE42 can boost the high-frequency components of the analog input signal SIN.

[0086] The PLL 45 generates a reference clock CLK based on phase synchronization and inputs it to the PI 13 and also to the buffer 12 via the switch 44.

[0087] DFE / FFE46 reduces intersymbol interference in frequency-selective channels based on digital processing.

[0088] The memory unit 47 stores the timing correction values ​​HV1, HV2, HV3, HV4, offset error EO, ​​and gain error EG calculated by the error detection circuit 15 when an error is detected in the AD converter 40. Then, during the normal operation of the AD converter 40, the memory unit 47 outputs the timing correction values ​​HV1, HV2, HV3, and HV4 from the delay adjustment circuit PA1 to PA4, and outputs the offset error EO and gain error EG from the correction circuit HS1 to HS4.

[0089] PD48 sets the phase of the reference clock CLK to an optimal value. The optimal value may be the point where the center of the eye pattern is widest. In this case, PD48 may optimize the phase of the reference clock CLK based on CDR (Clock Data Recovery).

[0090] The selector 49 selects either the output of the error detection circuit 15 or the output of PD48 and inputs it to PI13 based on the mode selection signal MOD. Here, if the error detection mode is selected by the mode selection signal MOD, the output of the error detection circuit 15 is selected. On the other hand, if the normal operation mode is selected by the mode selection signal MOD, the output of PD48 is selected.

[0091] Thus, in the fourth embodiment described above, an AD converter 40 is applied to the serial interface that corrects the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 based on the detection result of the error in the AD conversion values ​​Ch1 to Ch4 of the reference clock CLK obtained from each AD converter AD1 to AD4. This makes it possible to achieve high speed while improving the accuracy of AD conversion of the serial interface.

[0092] <5. Fifth Embodiment> In the fourth embodiment described above, an AD converter 40 that corrects the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 based on the detection result of the error in the AD conversion values ​​Ch1 to Ch4 of the reference clock CLK acquired from each AD converter AD1 to AD4 is applied to the serial interface. In this fifth embodiment, an AD converter 40 that corrects the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 based on the detection result of the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 is applied to the serial interface, and the PI13 is driven based on a two-phase signal with a phase shift of 90°.

[0093] Figure 20 is a block diagram showing an example configuration of an AD conversion device according to the fifth embodiment.

[0094] In the figure, the AD converter 50 includes PI53 and PLL55 instead of PI13 and PLL45 in the fourth embodiment described above. The other configurations of the AD converter 40 are the same as those of the AD converter 10 in the first embodiment described above.

[0095] PI53 adjusts the phase of the reference clock CLK1. At this time, PI53 can adjust the phase of the reference clock CLK1 based on reference clocks CLK1 and CLK2, which are out of phase by 90° from each other. Here, when the input from each AD converter AD1 to AD4 is switched to the reference clock CLK1, PI53 can change the phase of the reference clock CLK1 between 0° and 360°. At this time, PI53 can adjust the phase of the reference clock CLK1 based on phase setting information (PI control code) PCD. On the other hand, when the input from each AD converter AD1 to AD4 is switched to the analog input signal SIN, PI53 can set the phase of the reference clock CLK1 to an optimal value.

[0096] The PLL 55 generates reference clocks CLK1 and CLK2, which are 90° out of phase with respect to each other based on phase synchronization, and inputs them to the PI 13. It also inputs reference clock CLK1 to the buffer 12 via the switch 44.

[0097] Thus, in the fifth embodiment described above, an AD converter 40 that corrects the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 is applied to the serial interface, and the PI13 is driven based on a two-phase signal with a phase shift of 90°. This makes it possible to achieve high speed while improving the accuracy of AD conversion of the serial interface, and also stabilize the operation of the PI13.

[0098] <6. Sixth Embodiment> In the fourth embodiment described above, an AD converter 40 that corrects the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 was applied to the serial interface. In this sixth embodiment, an AD converter 40 that corrects the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 is applied to the serial interface, and the reference clock CLK generated by the PLL is divided and input to each AD converter AD1 to AD4.

[0099] Figure 21 is a block diagram showing an example configuration of an AD conversion device according to the sixth embodiment.

[0100] In the figure, the AD converter 60 has a frequency divider circuit 61 added to the AD converter 40 of the fourth embodiment described above. The other configurations of the AD converter 60 are the same as those of the AD converter 40 of the fourth embodiment described above.

[0101] The frequency divider circuit 61 divides the reference clock CLK generated by the PLL 45 and inputs it to the buffer 12 via the switch 44.

[0102] As described above, in the sixth embodiment, an AD converter 40 that corrects the error in the AD conversion values ​​Ch1 to Ch4 of each AD converter AD1 to AD4 is applied to the serial interface, and the reference clock CLK generated by the PLL 45 is divided and input to each AD converter AD1 to AD4. This makes it possible to achieve high speed while improving the accuracy of AD conversion of the serial interface, and to optimize the frequency of the reference clock CLK input to each AD converter AD1 to AD4.

[0103] <7. Examples of Application to Mobile Devices> The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0104] Figure 22 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0105] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 22, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0106] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0107] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0108] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0109] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0110] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0111] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0112] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0113] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0114] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 22, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0115] Figure 23 shows an example of the installation position of the imaging unit 12031.

[0116] In Figure 23, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0117] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0118] Figure 23 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0119] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0120] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0121] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0122] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0123] The above describes an example of a vehicle control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the driver state detection unit 12041 and the imaging unit 12031 of the configuration described above. Specifically, for example, each of the AD conversion devices 10 to 60 of the above embodiment can be applied to the driver state detection unit 12041 and the imaging unit 12031. By applying the technology of this disclosure to the vehicle control system 12000, it is possible to improve the accuracy and speed of AD conversion while suppressing increases in power consumption and circuit area.

[0124] The embodiments described above are merely examples for realizing the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. Furthermore, the effects described herein are merely examples and are not limiting, and other effects may also exist.

[0125] Furthermore, this technology can also take the following configurations: (1) An AD conversion device comprising: a plurality of AD converters; a multiphase clock generator that generates multiphase clocks for the plurality of AD converters based on a reference clock; a multiplexer that synthesizes the AD conversion values ​​of the plurality of AD converters; a PI (Phase Interpolator) that adjusts the phase of the reference clock; a delay adjustment circuit that adjusts the delay of the multiphase clock for each of the AD converters; and a switching unit that switches the input of the plurality of AD converters between the reference clock and an analog input signal. (2) The AD conversion device according to (1), wherein the delay adjustment circuit corrects the timing mismatch between the plurality of AD converters based on the detection results of the phases of the plurality of AD converters. (3) The AD conversion device according to (1) or (2), further comprising a correction circuit that corrects the offset mismatch and gain mismatch between the plurality of AD converters based on the detection results of the amplitudes of the plurality of AD converters. (4) The AD converter according to any one of (1) to (3), further comprising an error detection circuit for detecting errors in the AD conversion values ​​of the plurality of AD converters. (5) The AD converter according to (5), wherein the error detection circuit detects errors in the AD conversion values ​​of the plurality of AD converters based on the FFT (Fast Fourier Transform) results of the AD conversion values ​​of the plurality of AD converters when the phase of the reference clock is set. (6) The AD converter according to any one of (1) to (6), further comprising a switching unit for selectively outputting each of the AD conversion values ​​of the plurality of AD converters, and a storage unit for storing a correction value for the error of the AD conversion values ​​of the AD converters. (7) The AD converter according to (6), further comprising a processor for calculating a correction value for the error of the AD conversion values ​​of the AD converters based on each of the AD conversion values ​​of the plurality of AD converters and storing it in the storage unit.(8) A method for correcting an AD conversion value, comprising the steps of: driving a plurality of AD converters based on a multiphase clock generated from a reference clock with set phase, and obtaining an AD conversion value of the reference clock from the plurality of AD converters; detecting an error in the AD conversion value of the reference clock; calculating a correction value for the error of the AD conversion value of the AD converters based on the detection result of the error in the AD conversion value of the reference clock; and correcting the error of the AD conversion value of the AD converters based on the correction value for the error of the AD conversion value of the AD converters. (9) The method for correcting an AD conversion value according to (8), wherein the phase is set to a plurality of phases between 0° and 360°. (10) The method for correcting an AD conversion value according to (8), wherein the error in the AD conversion value includes a timing error, an offset error, and a gain error.

[0126] 10 AD converter 11 Switching unit 12 Buffer 13 PI 14 Multiphase clock generator 15 Error detection circuit 16 Multiplexer AD1 to AD4 AD converter PA1 to PA4 Delay adjustment circuit HS1 to HS4 Correction circuit

Claims

1. An AD conversion device comprising: a plurality of AD converters; a multiphase clock generator that generates multiphase clocks for the plurality of AD converters based on a reference clock; a multiplexer that synthesizes the AD conversion values ​​of the plurality of AD converters; a Phase Interpolator (PI) that adjusts the phase of the reference clock; a delay adjustment circuit that adjusts the delay of the multiphase clock for each of the AD converters; and a switching unit that switches the inputs of the plurality of AD converters between the reference clock and an analog input signal.

2. The AD conversion device according to claim 1, wherein the delay adjustment circuit corrects the timing mismatch between the plurality of AD converters based on the phase detection results of the plurality of AD converters.

3. The AD converter according to claim 1, further comprising a correction circuit that corrects offset mismatch and gain mismatch between the plurality of AD converters based on the amplitude detection results of the plurality of AD converters.

4. The AD conversion device according to claim 1, further comprising an error detection circuit for detecting errors in the AD conversion values ​​of the plurality of AD converters.

5. The AD conversion device according to claim 5, wherein the error detection circuit detects the error in the AD conversion values ​​of the plurality of AD converters based on the Fast Fourier Transform (FFT) result of the AD conversion values ​​of the plurality of AD converters when the phase of the reference clock is set.

6. The AD conversion device according to claim 1, further comprising: a switching unit that selectively outputs the AD conversion values ​​of each of the plurality of AD converters; and a storage unit that stores a correction value for the error of the AD conversion values ​​of the AD converters.

7. The AD conversion device according to claim 6, further comprising a processor that calculates a correction value for the error of the AD conversion value of the AD converters based on the AD conversion value of each of the plurality of AD converters and stores it in the storage unit.

8. A method for correcting an AD conversion value, comprising: driving a plurality of AD converters based on a multiphase clock generated from a reference clock with set phase, and obtaining an AD conversion value of the reference clock from the plurality of AD converters; detecting an error in the AD conversion value of the reference clock; calculating a correction value for the error of the AD conversion value of the AD converters based on the detection result of the error in the AD conversion value of the reference clock; and correcting the error of the AD conversion value of the AD converters based on the correction value for the error of the AD conversion value of the AD converters.

9. The AD conversion value correction method according to claim 8, wherein the phase is set to one of several phases between 0° and 360°.

10. The AD conversion value correction method according to claim 8, wherein the error in the AD conversion value includes timing error, offset error, and gain error.

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