Power conversion device

Abstract

The present invention reduces recovery loss occurring during recovery of a diode in a power conversion device using an RC-IGBT comprising an IGBT having two independently drivable gates. This power conversion device includes a power conversion circuit in which an upper arm and a lower arm are connected in series, and a drive circuit that drives the power conversion circuit. The upper arm and the lower arm each comprise an RC-IGBT provided with an IGBT having a first gate and a second gate that can be driven independently, and a diode having a diode gate to which a voltage can be applied independently of the first and second gates of the IGBT. The drive circuit applies an ON signal (G2') to the second gate of a paired arm before applying an ON signal (G1') to the first gate of the paired arm, and applies an ON signal (DG) to the diode gate of its own arm before or at the same time as applying the ON signal (G2') to the second gate of the paired arm.

Description

Power conversion device

[0001] The present invention relates to a power conversion device.

[0002] An RC-IGBT (RC: Reverse-Conducting, reverse-conducting IGBT) incorporating an IGBT (Insulated Gate Bipolar Transistor) and a diode within the same chip has the advantage of reducing the chip size because the termination regions of the IGBT and the diode can be shared. Further, since the operating timings of the IGBT and the diode are different from each other, heat generated due to losses occurring in either the IGBT region or the diode region is dispersed to the other, and heat can be dissipated across the entire chip, thus also having the advantage of reducing the thermal resistance.

[0003] As a prior art related to RC-IGBTs, for example, there is Patent Document 1. In FIG. 1 of Patent Document 1, trenches (3) are formed in the diode region (22) in the same manner as in the IGBT region (21), and a structure in which a dummy electrode (6) is provided inside the trench (3) of the diode region (22) is described. And in paragraph 0025 of Patent Document 1, it is described that, for example, an emitter potential (E) is supplied to the dummy electrode (6), but it is not limited thereto, and other potentials such as a gate potential (G) may be used.

[0004] Further, although not an RC-IGBT, as a technology related to IGBTs, an IGBT having two independently drivable gates within one IGBT (sometimes called a double gate IGBT, a dual gate IGBT, etc.) is known, and for example, there is Patent Document 2.

[0005] Figures 1 to 3 and the abstract of Patent Document 2 state that "The power conversion switching element (100) has a first gate electrode (6), a p-type channel layer (2) having an n-type emitter region (3), a second gate electrode (13), and a p-type floating layer (15) arranged in a repeating sequence on the surface side of an n-type semiconductor substrate (1). The spacing a between the two gates (6, 13) sandwiching the p-type channel layer (2) is smaller than the spacing b between the two gates (13, 6) sandwiching the p-type floating layer (15), and a drive signal with a time difference in drive timing is supplied to each of the first gate electrode (6) and the second gate electrode (13)."

[0006] Furthermore, paragraph 0015 of Patent Document 2 states that it is possible to reduce losses during turn-off and improve the controllability of the time rate of change (dv / dt) of the output voltage during turn-on.

[0007] Japanese Patent Publication No. 2023-172272, International Publication No. 2014 / 038064

[0008] In an RC-IGBT, the anode potential (A) is the same as the emitter potential (E). As shown in Patent Document 1, in an RC-IGBT, a trench (3) is also formed in the diode region (22), and when the emitter potential (E) or gate potential (G) is applied to the dummy electrode (6) inside the trench (3) of the diode region (22), the potential of the dummy electrode (6) becomes the same as the anode potential (A) at the timing when the diode operates, whether the diode is conducting or recovering. Therefore, the dummy electrode (6) does not affect the operation of the diode.

[0009] Furthermore, in the diode region of an RC-IGBT, if the concentration of holes injected before diode recovery is high, there is a problem in that the reverse current increases during recovery, leading to increased recovery losses.

[0010] Furthermore, with RC-IGBTs, since the IGBT and diode are fabricated on the same chip, there is a challenge in that simultaneous optimization of the IGBT and diode is difficult.

[0011] Patent Document 2 describes how an IGBT having two independently driveable gates can reduce losses during IGBT turn-off and improve the controllability of the time rate of change (dv / dt) of the IGBT output voltage during turn-on; however, it does not describe its application to RC-IGBTs.

[0012] The problem that this invention aims to solve is to provide a power conversion device that uses an RC-IGBT equipped with two independently driveable IGBTs, and that can reduce the recovery loss that occurs during diode recovery.

[0013] To solve the above-mentioned problems, the present invention provides a power conversion device comprising a power conversion circuit in which an upper arm and a lower arm are connected in series, and a drive circuit for driving the power conversion circuit, wherein the upper arm has a first semiconductor device having an IGBT and a diode on the same chip, and the lower arm has a second semiconductor device having an IGBT and a diode on the same chip, and the IGBT in the first and second semiconductor devices each comprises an emitter, a collector, a first trench, a second trench, a first gate provided inside the first trench, and a second gate provided inside the second trench to which a voltage can be applied independently of the first gate, and the diode in the first and second semiconductor devices each comprises an anode electrically connected to the emitter, a cathode electrically connected to the collector, and a wire that penetrates the anode and reaches the cathode The first semiconductor device has a third trench reaching a certain point, an in-trench insulating film provided inside the third trench, and a diode gate provided inside the third trench and facing the anode and cathode via the in-trench insulating film, wherein the diode gate of the first semiconductor device can be voltage-applied independently of the first gate and the second gate of the IGBT of the first semiconductor device, and the diode gate of the second semiconductor device can be voltage-applied independently of the first gate and the second gate of the IGBT of the second semiconductor device, and the drive circuit is characterized in that it applies an ON signal to the second gate of the first semiconductor device before applying an ON signal to the first gate of the first semiconductor device, and applies an ON signal to the diode gate of the second semiconductor device before or simultaneously with applying an ON signal to the second gate of the first semiconductor device.

[0014] According to the present invention, in a power conversion device using an RC-IGBT equipped with two independently driveable IGBTs, the recovery loss that occurs during diode recovery can be reduced.

[0015] A circuit diagram showing an example of the power converter of Example 1. A cross-sectional view showing an example of the semiconductor device of Example 1. A cross-sectional view illustrating an example of the operation of the semiconductor device of Example 1 when the diode conducts just before the diode performs a recovery operation. A cross-sectional view illustrating an example of the operation of the semiconductor device of Example 1 when the diode conducts under normal conditions other than just before the diode performs a recovery operation. A timing chart illustrating an example of the driving method of the power converter of Example 1. A circuit diagram showing an example of the power converter of Example 2. A timing chart illustrating an example of the driving method of the power converter of Example 2.

[0016] The embodiments of the present invention will be described below with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0017] In this embodiment, a power conversion device using an RC-IGBT having two independently driveable n-type IGBTs is described as an example. The impurity concentration of the semiconductor layer increases in the order n- < n < n+ and p- < p < p+. Note that the impurity concentration of the semiconductor layer in this embodiment is just an example, and can be appropriately changed within a range that allows the intended operation in this embodiment to be achieved.

[0018] Figure 1 is a circuit diagram showing an example of the power conversion device of Embodiment 1.

[0019] The power converter 200 of this embodiment includes a power conversion circuit 201 in which an upper arm 202 and a lower arm 203 are connected in series, and a drive circuit 206 that drives the power conversion circuit 201. The upper arm 202 and the lower arm 203 are each composed of RC-IGBTs. The upper arm 202 has a first semiconductor device 100A having an IGBT 204 and a diode 205 on the same chip, and the lower arm 203 has a second semiconductor device 100B having an IGBT 204 and a diode 205 on the same chip. The IGBT 204 of this embodiment has two independently driveable gates. The diode 205 of this embodiment has a diode gate. In reality, there is no circuit symbol like the one shown in Figure 1, but it is shown in Figure 1 as a symbol to simulate this structure. The diode gate of diode 205 of the first semiconductor device 100A can be voltage-applied independently of the first and second gates of IGBT 204 of the first semiconductor device 100A, and the diode gate of diode 205 of the second semiconductor device 100B can be voltage-applied independently of the first and second gates of IGBT 204 of the second semiconductor device 100B.

[0020] The drive circuit 206 drives the power conversion circuit 201 based on a control signal from a control circuit (not shown). The drive circuit 206 includes an amplification circuit 209, which amplifies the control signal and outputs it as a drive signal.

[0021] The drive circuit 206 of this embodiment includes a delay circuit 207 and wiring 208. The delay circuit 207 of this embodiment includes a first delay circuit 207A, a second delay circuit 207B, a third delay circuit 207C, and a fourth delay circuit 207D. The wiring 208 of this embodiment includes a first wiring 208A and a second wiring 208B.

[0022] Specifically, the drive circuit 206 of this embodiment includes a first delay circuit 207A that delays the input first drive signal and outputs it to the first gate of the first semiconductor device 100A, a second delay circuit 207B that delays the first drive signal by a shorter time than the first delay circuit 207A and outputs it to the second gate of the first semiconductor device 100A, and a first wiring 208A that inputs the first drive signal to the diode gate of the diode 205 of the second semiconductor device 100B. One end of the first wiring 208A is connected to node N1 between the amplification circuit 209 and the second delay circuit 207B. With this configuration, the first drive signal can be directly applied to the diode gate of the diode 205 of the second semiconductor device 100B.

[0023] Furthermore, the drive circuit 206 of this embodiment includes a third delay circuit 207C that delays the input second drive signal and outputs it to the first gate of the second semiconductor device 100B, a fourth delay circuit 207D that delays the second drive signal by a shorter time than the third delay circuit 207C and outputs it to the second gate of the second semiconductor device 100B, and a second wiring 208B that inputs the second drive signal to the diode gate of the diode 205 of the first semiconductor device 100A. One end of the second wiring 208B is connected to node N2 between the amplification circuit 209 and the fourth delay circuit 207D. With this configuration, the second drive signal can be directly applied to the diode gate of the diode 205 of the first semiconductor device 100A.

[0024] The power converter 200 is connected to a DC power supply (not shown), with the upper arm 202 connected to the high-potential side of the DC power supply and the lower arm 203 connected to the low-potential side of the DC power supply. The power converter 200 converts the DC power input from the DC power supply into AC power by driving the IGBT 204 and diode 205 at predetermined timings using the drive circuit 206, and outputs the AC power to the load 210 from the connection node between the upper arm 202 and the lower arm 203. In this embodiment, only one phase of the power converter circuit 201 is shown, but the power converter circuit 201 may have two or more phases.

[0025] The first semiconductor device 100A and the second semiconductor device 100B may be separate semiconductor chips, or they may be configured to be on the same chip.

[0026] Figure 2 is a cross-sectional view showing an example of a semiconductor device according to Example 1.

[0027] The semiconductor device 100 in this embodiment is an RC-IGBT and has an IGBT region 21 and a diode region 22 on the same chip (on the same semiconductor substrate). Furthermore, the IGBT 204 in this embodiment has two independently driveable gates. Since the first semiconductor device 100A and the second semiconductor device 100B have the same structure as the semiconductor device 100 shown in Figure 2, the semiconductor device 100 will be used as a representative example for explanation.

[0028] The IGBT 204 formed in the IGBT region 21 includes an emitter (emitter layer 7), a collector (collector layer 11), a first trench 3A, a second trench 3B, a first gate (first gate electrode 5A) provided inside the first trench 3A, and a second gate (second gate electrode 5B) provided inside the second trench 3B to which a voltage can be applied independently of the first gate.

[0029] Specifically, the IGBT 204 in the IGBT region 21 has an n-type drift layer 1, a p-type body layer 2 provided on the surface side of the drift layer 1, an n+-type emitter layer 7 provided on the surface side of the body layer 2, a first trench 3A and a second trench 3B penetrating the body layer 2 and reaching the drift layer 1, a gate insulating film 4A provided inside the first trench 3A and the second trench 3B, a first gate electrode 5A provided inside the first trench 3A and facing the body layer 2, emitter layer 7 and drift layer 1 via the gate insulating film 4A, a second gate electrode 5B provided inside the second trench 3B and facing the body layer 2, emitter layer 7 and drift layer 1 via the gate insulating film 4A, and a p-type collector layer 11 provided on the back side of the drift layer 1. Furthermore, it is desirable that the IGBT 204 in the IGBT region 21 has an n-type buffer layer 10 with a higher impurity concentration than the drift layer 1 between the drift layer 1 and the collector layer 11. Although only one first gate electrode 5A is shown in Figure 2, in reality, the first gate electrode 5A and the second gate electrode 5B are arranged alternately on the left side of Figure 2 as well.

[0030] The diode 205 formed in the diode region 22 has an anode (anode layer 12) electrically connected to the emitter, a cathode (drift layer 1, buffer layer 10, cathode layer 13) electrically connected to the collector, a third trench 3C that penetrates the anode and reaches the cathode, an in-trench insulating film 4B provided inside the third trench 3C, and a diode gate (diode gate electrode 6) provided inside the third trench 3C and facing the anode and cathode via the in-trench insulating film 4B.

[0031] Specifically, the diode 205 in the diode region 22 has an n-type drift layer 1 formed in common with the IGBT region 21, a p-type anode layer 12 provided on the surface side of the drift layer 1, a third trench 3C that penetrates the anode layer 12 and reaches the drift layer 1, an in-trench insulating film 4B provided inside the third trench 3C, a diode gate electrode 6 provided inside the third trench 3C and facing the anode layer 12 and the drift layer 1 via the in-trench insulating film 4B, and an n+-type cathode layer 13 provided on the back side of the drift layer 1. Furthermore, it is desirable that the diode 205 in the diode region 22 has an n-type buffer layer 10 formed in common with the IGBT region 21 between the drift layer 1 and the cathode layer 13.

[0032] The semiconductor device 100 also includes an interlayer insulating film 9, a surface electrode 14, and a back surface electrode 15.

[0033] The surface electrode 14 is formed on the surface side of the semiconductor device 100, common to both the IGBT region 21 and the diode region 22. In the IGBT region 21, it functions as the emitter electrode 14A, and in the diode region 22, it functions as the anode electrode 14B. The emitter electrode 14A is electrically connected to the emitter layer 7 and the body layer 2 via a contact hole and a p+ type contact layer 8. The anode electrode 14B is electrically connected to the anode layer 12 via a contact hole and a p+ type contact layer 8. As a result, the emitter of the IGBT 204 and the anode of the diode 205 are electrically connected. Therefore, the surface electrode 14 is both the emitter potential E and the anode potential A.

[0034] The back electrode 15 is formed on the back side of the semiconductor device 100, common to both the IGBT region 21 and the diode region 22. In the IGBT region 21, it functions as a collector electrode 15A, and in the diode region 22, it functions as a cathode electrode 15B. The collector electrode 15A is electrically connected to the collector layer 11. The cathode electrode 15B is electrically connected to the cathode layer 13. As a result, the collector of the IGBT and the cathode of the diode are electrically connected. Therefore, the back electrode 15 is both the collector potential C and the cathode potential K.

[0035] The interlayer insulating film 9 is provided between the various semiconductor layers, the first gate electrode 5A, the second gate electrode 5B, and the diode gate electrode 6, and the surface electrode 14.

[0036] In this embodiment, the emitter layer 7 present in the IGBT region 21 is absent in the diode region 22. Furthermore, the p-type collector layer 11 in the IGBT region 21 is replaced by an n+-type cathode layer 13 in the diode region 22. Since the other structures are almost identical, there is the advantage that most of the manufacturing process for the IGBT 204 and diode 205 can be standardized. Note that the structures of the IGBT 204 and diode 205 described above are merely examples and are not limited to them.

[0037] Figure 3 is a cross-sectional view illustrating an example of the operation of the semiconductor device of Embodiment 1 when the diode conducts immediately before the diode performs a recovery operation.

[0038] Here, the IGBT 204 and diode 205 of the arm are shown in the diagram.

[0039] When the diode 205 of the arm is conducting, the IGBT 204 of the arm is controlled to be off. If the emitter potential E, which is the reference potential of the IGBT 204, is set to 0V, then the first gate electrode 5A and the second gate electrode 5B of the arm are applied with a first gate potential G1 and a second gate potential G2, respectively, of -15V or 0V.

[0040] Furthermore, when the diode is conducting, the anode potential A is higher than the cathode potential K, resulting in a forward bias state. Therefore, holes 31 are injected from the anode layer 12, which is the anode, to the drift layer 1, which is the cathode, and a forward current flows from the anode to the cathode of the diode 205.

[0041] Now, let's consider the case where, after the state shown in Figure 3, the IGBT 204 of the opposing arm turns on and the recovery operation of the diode 205 of the own arm begins. During the recovery of the diode 205, the cathode potential K is higher than the anode potential A, resulting in a reverse bias state. At this time, the holes 31 that were injected into the drift layer 1 and remained are discharged through the anode layer 12, and a reverse current flows from the cathode to the anode. However, if the concentration of holes 31 injected when the diode 205 of the own arm conducts is high, the reverse current during recovery becomes large, leading to a problem of increased recovery loss.

[0042] Therefore, in this embodiment, an on signal is applied to the diode gate of the diode 205 of the self-arm immediately before switching to the recovery operation from the time when the diode 205 of the self-arm conducts. Specifically, as shown in FIG. 3, a positive voltage with respect to the anode potential A, for example, a potential of +15 V with respect to the anode potential A, is applied to the diode gate electrode 6 as the diode gate potential DG. As a result, electrons are collected around the diode gate electrode 6, so that a depletion layer 32 is formed in the anode layer 12 around the third trench 3C, and an n-type accumulation layer 33 is formed in the drift layer 1 around the third trench 3C. Since the width of the anode layer 12 is substantially narrowed by the depletion layer 32, the injection of holes 31 from the anode layer 12 can be reduced. Further, in the n-type accumulation layer 33, electrons are accumulated and the concentration of electrons is high. Therefore, the n-type accumulation layer 33 serves as a barrier, and the injection of holes 31 from the anode layer 12 can be reduced. Furthermore, due to the electrons accumulated by the n-type accumulation layer 33, the concentration of electrons becomes high in the vicinity of the boundary between the anode layer 12 and the drift layer 1. As a result, the annihilation of holes 31 and electrons is likely to occur in the vicinity of this boundary, and the amount of holes 31 remaining in the drift layer 1 at the start of the recovery operation is reduced. As a result of these, the reverse current flowing during recovery can be reduced, and the recovery loss can be minimized.

[0043] FIG. 4 is a cross-sectional view for explaining an example of the operation during normal conduction of the diode in the semiconductor device of Embodiment 1 other than immediately before the diode enters the recovery operation.

[0044] Here also, the IGBT 204 and the diode 205 of the self-arm are illustrated.

[0045] When the recovery operation of the diode 205 of the self-arm ends, the diode 205 of the self-arm turns off. Thereafter, the IGBT 204 of the counter arm turns off, and the diode 205 of the self-arm conducts.

[0046] Even when the diode is off, the IGBT 204 of its own arm is controlled to be off. Also, even when the diode 205 is off, similar to the recovery time, the cathode potential K is in a reverse bias state where it is higher than the anode potential A. Thereafter, the anode potential A becomes a forward bias state where it is higher than the cathode potential K, and the diode 205 conducts.

[0047] In this embodiment, immediately before the diode 205 of its own arm switches from the off state to the conduction state, an off signal is applied to the diode gate of the diode 205 of its own arm. Specifically, a negative voltage with respect to the anode potential A, for example, a potential of -15 V with respect to the anode potential A, is applied to the diode gate electrode 6 as the diode gate potential DG. Then, as shown in FIG. 4, even when the diode conducts, the off signal is kept applied to the diode gate. As a result, holes are collected around the diode gate electrode 6, so a hole accumulation layer 34 is formed in the anode layer 12 around the third trench 3C, and a p-type accumulation layer 35 is formed in the drift layer 1 around the third trench 3C. In the hole accumulation layer 34 and the p-type accumulation layer 35, holes 31 are accumulated and the concentration of the holes 31 is high. Therefore, the injection amount of the holes 31 from the anode to the cathode increases, and as a result, the forward voltage when the diode conducts can be reduced.

[0048] FIG. 5 is a timing chart for explaining an example of the driving method of the power conversion device of Example 1. The vertical axis in FIG. 5 is voltage or current, and the horizontal axis is time.

[0049] Here, the case where the lower arm 203 is its own arm and the upper arm 202 is the opposing arm will be described as an example. Therefore, as shown in FIG. 1, the first gate potential G1 applied to the first gate of the IGBT 204 of the first semiconductor device 100A becomes the first opposing arm gate potential G1', and the second gate potential G2 applied to the second gate of the IGBT 204 of the first semiconductor device 100A becomes the second opposing arm gate potential G2'.

[0050] The drive circuit 206 controls the on / off of the IGBT 204, which is a switching element, and also controls the on / off of the diode gate of the diode 205.

[0051] Period T1 is the period when the diode 205 of the arm is conducting. Period T2 is the period when the diode 205 of the arm is recovering. Period T3 is the period when the diode 205 of the arm is off. Period T4 is the period when the diode 205 of the arm is conducting. A positive current Id flows in the forward direction through the diode 205 of the arm during periods T1 and T4, the current Id decreases during period T2, then a negative reverse current flows in the reverse direction, and the current becomes 0 during period T3.

[0052] Assuming that the emitter potential E of the arm is, for example, 0V and the anode potential A is also 0V, when the diode 205 of the arm is operating, an off signal of, for example, -15V is applied to the first gate electrode 5A and the second gate electrode 5B of the IGBT 204 of the arm, as the first gate potential G1 and the second gate potential G2, respectively, and the IGBT 204 of the arm is controlled to be off.

[0053] In this embodiment, an IGBT 204 having two independently driveable gates is used, and the drive circuit 206 applies an ON signal to the second gate of the first semiconductor device 100A before applying an ON signal to the first gate of the first semiconductor device 100A, which is the pair arm. Specifically, before applying a first pair arm gate potential G1' of, for example, +15V to the first gate of the first semiconductor device 100A, a second pair arm gate potential G2' of, for example, +15V is applied to the second gate of the first semiconductor device 100A. This improves the controllability of the time rate of change (dv / dt) of the output voltage during turn-on of the IGBT 204, allows control of the turn-on speed, and suppresses turn-on vibration and recovery vibration of the diode 205.

[0054] When an ON signal is applied to the second gate of the opposing arm's IGBT 204, the recovery operation of the self-arm's diode 205 begins a short delay later.

[0055] Therefore, in this embodiment, an ON signal is applied to the diode gate of the diode 205 of the second semiconductor device 100B, which is the arm in question, before an ON signal is applied to the second gate of the first semiconductor device 100A, which is the gate that turns ON first in the opposing arm. Specifically, a second diode gate potential DG2 of, for example, +15V is applied to the diode gate of the diode 205 of the second semiconductor device 100B.

[0056] This allows the diode gate to be turned on before the recovery operation of the diode 205 on the arm is initiated, enabling the operation described in Figure 3 to be performed. As a result, the reverse current flowing during recovery can be reduced, and recovery losses can be minimized.

[0057] In this embodiment, as shown in Figure 1, the drive circuit 206 applies the first drive signal directly as the second diode gate potential DG2, delays it by a delay time t2 in the second delay circuit 207B and applies it as the second paired arm gate potential G2', and delays it by a delay time t1, which is longer than the delay time t2, in the first delay circuit 207A and applies it as the first paired arm gate potential G1'. However, the circuit configuration is not limited to that shown in Figure 1, and it may also be implemented using a forward circuit, or the drive signals may be applied with pre-adjusted timings.

[0058] Furthermore, in this embodiment, the drive circuit 206 drives the second gate of the first semiconductor device 100A before driving the first gate of the first semiconductor device 100A, and, as shown in Figure 1, generates a drive signal to drive the diode gate of the diode 205 of the second semiconductor device 100B based on the drive signal for driving the second gate of the first semiconductor device 100A. This makes it possible to synchronize the drive of the diode gate of the diode 205 of its own arm with the drive of the IGBT 204 of the opposing arm.

[0059] Furthermore, in this embodiment, the drive circuit 206 applies an off signal to the second gate of the first semiconductor device 100A before applying an off signal to the first gate of the first semiconductor device 100A, which is the paired arm. Specifically, before applying a first paired arm gate potential G1' of, for example, -15V to the first gate of the first semiconductor device 100A, a second paired arm gate potential G2' of, for example, -15V is applied to the second gate of the first semiconductor device 100A. As a result, the IGBT 204 is turned off with a reduced internal carrier, thereby reducing losses during turn-off.

[0060] When an off signal is applied to the first and second gates of the opposing arm's IGBT 204, the opposing arm's IGBT 204 turns off, and a short delay later, the diode 205 of the own arm begins to conduct.

[0061] Therefore, in this embodiment, an off signal is applied to the diode gate of the diode 205 of the second semiconductor device 100B, which is the arm in question, before an off signal is applied to the second gate of the first semiconductor device 100A, which is the gate that turns off first in the opposing arm. Specifically, a second diode gate potential DG2 of, for example, -15V is applied to the diode gate of the diode 205 of the second semiconductor device 100B.

[0062] This allows the diode gate of the self-arm diode 205 to be turned off before it transitions from the off state to the conductive state, and to remain off even when the diode conducts, thereby enabling the operation described in Figure 4, and thus reducing the forward voltage when the diode conducts.

[0063] The timing for turning off the diode gate does not need to be before the IGBT 204 of the opposing arm turns off. Therefore, the diode gate could be turned off at a time between the application of the off signal to the second gate and the application of the off signal to the first gate. However, as in this embodiment, it is preferable to turn it off before the off signal is applied to the second gate, because this allows the configuration of the drive circuit 206 in Figure 1 to be used as is.

[0064] Furthermore, in order to obtain the effect of reducing the forward voltage when the diode conducts for as long as possible, it is desirable to keep the diode gate off as much as possible when the diode conducts. Therefore, it is desirable that the timing for turning on the diode gate be just before the recovery operation starts. To achieve this, it is desirable to generate a drive signal for driving the diode gate of the diode 205 of the second semiconductor device 100B based on the drive signal for driving the second gate of the first semiconductor device 100A.

[0065] Furthermore, even when the upper arm 202 is the self-arm and the lower arm 203 is the opposing arm, the operation is almost the same, as only the self-arm and the opposing arm are swapped, so a detailed explanation will be omitted.

[0066] To briefly explain the difference, in Figure 5, the second diode gate potential DG2 becomes the first diode gate potential DG1.

[0067] The drive circuit 206 applies an ON signal to the second gate of the second semiconductor device 100B, which is the opposing arm, before applying an ON signal to the first gate of the second semiconductor device 100B, and also applies an ON signal to the diode gate of the diode 205 of the first semiconductor device 100A, which is the own arm, before applying an ON signal to the second gate of the second semiconductor device 100B.

[0068] Furthermore, the drive circuit 206 applies an off signal to the second gate of the second semiconductor device 100B, which is the opposing arm, before applying an off signal to the first gate of the second semiconductor device 100B, and also applies an off signal to the diode gate of the diode 205 of the first semiconductor device 100A, which is the arm, before applying an off signal to the second gate of the second semiconductor device 100B.

[0069] Furthermore, the drive circuit 206 drives the second gate of the second semiconductor device 100B before driving the first gate of the second semiconductor device 100B, which is the opposing arm, and generates a drive signal to drive the diode gate of the diode 205 of the first semiconductor device 100A, which is its own arm, based on the drive signal for driving the second gate of the second semiconductor device 100B.

[0070] As described above, according to this embodiment, in a power conversion device using an RC-IGBT equipped with two independently driveable IGBTs, the recovery loss that occurs during diode recovery can be reduced. Furthermore, the forward voltage when the diode conducts can be reduced.

[0071] Example 2 is a modification of Example 1, and the timing of applying the ON or OFF signal to the diode gate is different from that of Example 1.

[0072] Figure 6 is a circuit diagram showing an example of the power conversion device of Embodiment 2.

[0073] In this embodiment, the drive circuit 206 applies an ON signal to the second gate of the first semiconductor device 100A and simultaneously applies an ON signal to the diode gate of the second semiconductor device 100B. Furthermore, it applies an ON signal to the second gate of the second semiconductor device 100B and simultaneously applies an ON signal to the diode gate of the first semiconductor device 100A.

[0074] Similarly, the drive circuit 206 of this embodiment applies an off signal to the second gate of the first semiconductor device 100A and simultaneously applies an off signal to the diode gate of the second semiconductor device 100B. Furthermore, it applies an off signal to the second gate of the second semiconductor device 100B and simultaneously applies an off signal to the diode gate of the first semiconductor device 100A.

[0075] As a specific circuit configuration for the drive circuit 206 to achieve this, the delay circuit 207 of this embodiment has a fifth delay circuit 207E and a sixth delay circuit 207F. The wiring 208 of this embodiment has a third wiring 208C, a fourth wiring 208D, a fifth wiring 208E, and a sixth wiring 208F.

[0076] The drive circuit 206 of this embodiment includes a fifth delay circuit 207E that delays the input first drive signal and outputs it to the first gate of the first semiconductor device 100A, a third wiring 208C that inputs the first drive signal to the second gate of the first semiconductor device 100A, and a fourth wiring 208D that inputs the first drive signal to the diode gate of the diode 205 of the second semiconductor device 100B. One end of the fourth wiring 208D is connected to node N3 between the amplification circuit 209 and the second gate of the first semiconductor device 100A. With this configuration, the first drive signal can be directly applied to the diode gate of the diode 205 of the second semiconductor device 100B.

[0077] Furthermore, the drive circuit 206 of this embodiment includes a sixth delay circuit 207F that delays the input second drive signal and outputs it to the first gate of the second semiconductor device 100B, a fifth wiring 208E that inputs the second drive signal to the second gate of the second semiconductor device 100B, and a sixth wiring 208F that inputs the second drive signal to the diode gate of the diode 205 of the first semiconductor device 100A. One end of the sixth wiring 208F is connected to node N4 between the amplification circuit 209 and the second gate of the second semiconductor device 100B. With this configuration, the second drive signal can be directly applied to the diode gate of the diode 205 of the first semiconductor device 100A.

[0078] Note that the specific circuit configuration of the drive circuit 206 is merely an example and is not limited to that shown in Figure 6.

[0079] Figure 7 is a timing chart illustrating an example of the driving method for the power converter of Embodiment 2.

[0080] The difference from Example 1 is that the timing of the change in the diode gate potential DG is the same as the timing of the change in the second paired arm gate potential G2'. The delay time due to the fifth delay circuit 207E and the sixth delay circuit 207F is the delay time t3.

[0081] According to this embodiment, the same effects as in Embodiment 1 can be obtained, and the configuration of the drive circuit 206 can be simplified compared to Embodiment 1.

[0082] Although embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical idea of ​​the present invention. Furthermore, some or all of the configurations described in each embodiment may be combined and applied.

[0083] 1: Drift layer, 2: Body layer, 3A: First trench, 3B: Second trench, 3C: Third trench, 4A: Gate insulating film, 4B: In-trench insulating film, 5A: First gate electrode, 5B: Second gate electrode, 6: Diode gate electrode, 7: Emitter layer, 8: Contact layer, 9: Interlayer insulating film, 10: Buffer layer, 11: Collector layer, 12: Anode layer, 13: Cathode layer, 14: Surface electrode, 14A: Emitter Electrodes, 14B: Anode electrode, 15: Backside electrode, 15A: Collector electrode, 15B: Cathode electrode, 21: IGBT region, 22: Diode region, 31: Hole, 32: Depletion layer, 33: n-type storage layer, 34: Hole storage layer, 35: p-type storage layer, 100: Semiconductor device, 100A: First semiconductor device, 100B: Second semiconductor device, 200: Power converter, 201: Power conversion circuit, 202: Upper arm, 203: Lower arm, 204: IGBT, 205: Diode, 206: Drive circuit, 207: Delay circuit, 207A: First delay circuit, 207B: Second delay circuit, 207C: Third delay circuit, 207D: Fourth delay circuit, 207E: Fifth delay circuit, 207F: Sixth delay circuit, 208: Wiring, 208A: First wiring, 208B: Second wiring, 208C: Third wiring, 208D: Fourth wiring, 208E: Fifth wiring, 208F: Sixth Wiring, 209: Amplifier circuit, 210: Load, G1: First gate potential, G2: Second gate potential, G1': First pair arm gate potential, G2': Second pair arm gate potential, DG: Diode gate potential, DG1: First diode gate potential, DG2: Second diode gate potential, E: Emitter potential, A: Anode potential, C: Collector potential, K: Cathode potential, Id: Current, N1, N2, N3, N4: Node

Claims

1. A power conversion device comprising a power conversion circuit in which an upper arm and a lower arm are connected in series, and a drive circuit for driving the power conversion circuit, wherein the upper arm has a first semiconductor device having an IGBT and a diode on the same chip, and the lower arm has a second semiconductor device having an IGBT and a diode on the same chip, and the IGBT in the first and second semiconductor devices each has an emitter, a collector, a first trench, a second trench, a first gate provided inside the first trench, and a second gate provided inside the second trench to which a voltage can be applied independently of the first gate, The diodes in the first semiconductor device and the second semiconductor device each have an anode electrically connected to the emitter, a cathode electrically connected to the collector, a third trench penetrating the anode and reaching the cathode, an in-trench insulating film provided inside the third trench, and a diode gate provided inside the third trench and facing the anode and the cathode via the in-trench insulating film, wherein the diode gate of the first semiconductor device can be voltage-applied independently of the first gate and the second gate of the IGBT of the first semiconductor device, and the diode gate of the second semiconductor device can be voltage-applied independently of the first gate and the second gate of the IGBT of the second semiconductor device. The power conversion device is characterized in that the drive circuit applies an ON signal to the second gate of the first semiconductor device before applying an ON signal to the first gate of the first semiconductor device, and applies an ON signal to the diode gate of the second semiconductor device before or simultaneously with applying an ON signal to the second gate of the first semiconductor device.

2. The power conversion device according to claim 1, characterized in that the drive circuit applies an ON signal to the diode gate of the second semiconductor device before applying an ON signal to the second gate of the first semiconductor device.

3. The power conversion device according to claim 1, characterized in that the drive circuit applies an ON signal to the second gate of the first semiconductor device and simultaneously applies an ON signal to the diode gate of the second semiconductor device.

4. The power conversion device according to claim 1, characterized in that the drive circuit applies an ON signal to the second gate of the second semiconductor device before applying an ON signal to the first gate of the second semiconductor device, and applies an ON signal to the diode gate of the first semiconductor device before or simultaneously with applying an ON signal to the second gate of the second semiconductor device.

5. The power conversion device according to claim 1, characterized in that the ON signal applied to the diode gate is a positive voltage with respect to the anode.

6. The power conversion device according to claim 1, characterized in that the drive circuit applies an off signal to the second gate of the first semiconductor device before applying an off signal to the first gate of the first semiconductor device, and applies an off signal to the diode gate of the second semiconductor device before or simultaneously with applying an off signal to the second gate of the first semiconductor device.

7. The power conversion device according to claim 6, characterized in that the drive circuit applies an off signal to the second gate of the second semiconductor device before applying an off signal to the first gate of the second semiconductor device, and applies an off signal to the diode gate of the first semiconductor device before or simultaneously with applying an off signal to the second gate of the second semiconductor device.

8. The power conversion device according to claim 6, characterized in that the off signal applied to the diode gate is a negative voltage with respect to the anode.

9. The power conversion device according to claim 1, characterized in that the drive circuit drives the second gate of the first semiconductor device before driving the first gate of the first semiconductor device, and generates a drive signal for driving the diode gate of the second semiconductor device based on the drive signal for driving the second gate of the first semiconductor device.

10. The power conversion device according to claim 1, wherein the drive circuit comprises a first delay circuit that delays an input first drive signal and outputs it to the first gate of the first semiconductor device, a second delay circuit that delays the first drive signal by a shorter time than the first delay circuit and outputs it to the second gate of the first semiconductor device, and a first wiring that inputs the first drive signal to the diode gate of the second semiconductor device.

11. The power conversion device according to claim 10, wherein the drive circuit comprises a third delay circuit that delays the input second drive signal and outputs it to the first gate of the second semiconductor device, a fourth delay circuit that delays the second drive signal by a shorter time than the third delay circuit and outputs it to the second gate of the second semiconductor device, and a second wiring that causes the second drive signal to be input to the diode gate of the first semiconductor device.

12. The power conversion device according to claim 1, wherein the drive circuit comprises a fifth delay circuit that delays the input first drive signal and outputs it to the first gate of the first semiconductor device, a third wiring that causes the first drive signal to be input to the second gate of the first semiconductor device, and a fourth wiring that causes the first drive signal to be input to the diode gate of the second semiconductor device.

13. The power conversion device according to claim 12, characterized in that the drive circuit includes a sixth delay circuit that delays the input second drive signal and outputs it to the first gate of the second semiconductor device, a fifth wiring that inputs the second drive signal to the second gate of the second semiconductor device, and a sixth wiring that inputs the second drive signal to the diode gate of the first semiconductor device.

14. The power conversion device according to claim 1, characterized in that the first semiconductor device and the second semiconductor device are located on the same chip.

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