Semiconductor device

Abstract

The purpose of the present invention is to improve convenience of a semiconductor device having a function for detecting fluctuation of a power supply voltage. This semiconductor device has a power supply line, a signal delay circuit, a reference signal generation unit, a delay detection unit, and an adjustment signal generation unit. The power supply line supplies a power supply voltage. The signal delay circuit is configured by cascade-connecting a plurality of delay circuits whose delay time changes according to the power supply voltage. The reference signal generation unit generates a reference signal to be input to a first-stage delay circuit among the plurality of delay circuits of the signal delay circuit. The delay detection unit detects, on the basis of the output signal of each of the plurality of delay circuits when the reference signal is input, the number of stages of the delay circuits in which the delay time with respect to the reference signal becomes a predetermined delay time. The adjustment signal generation unit generates an adjustment signal for adjusting the power supply voltage on the basis of the detected number of stages.

Description

Semiconductor device

[0001] The present disclosure relates to a semiconductor device.

[0002] In a semiconductor device, a semiconductor device that detects a change in power consumption of a built-in circuit and adjusts a power supply voltage inside the semiconductor device is used. For example, a semiconductor device has been proposed in which a power supply circuit is arranged between a global power supply outside the semiconductor device and a local power supply inside the semiconductor device to adjust the voltage of the local power supply (see, for example, Patent Document 1).

[0003] In this semiconductor device, a power supply circuit including a plurality of semiconductor elements connected in parallel is used, and the equivalent resistance of the power supply circuit is changed by switching on and off the semiconductor elements of the power supply circuit according to a change in power consumption of the semiconductor device, thereby adjusting the voltage of the local power supply. Further, this semiconductor device includes a delay monitor circuit having a delay path whose delay amount changes according to a change in power supply voltage, and detects a change in power supply voltage based on the delay amount of the delay monitor circuit.

[0004] Japanese Patent Application Laid-Open No. 2014-057265

[0005] However, in the above prior art, there is a problem that the delay time of the delay monitor circuit cannot be changed, and convenience is reduced in cases such as detecting a wide range of voltage fluctuations.

[0006] Therefore, in the present disclosure, a semiconductor device with improved convenience is proposed in a semiconductor device having a function of detecting fluctuations in power supply voltage.

[0007] The semiconductor device according to the present disclosure includes a power supply line that supplies a power supply voltage, a signal delay circuit configured by cascading a plurality of delay circuits whose delay times change according to the power supply voltage, a reference signal generation unit that generates a reference signal input to the first-stage delay circuit among the plurality of delay circuits of the signal delay circuit, and based on the output signals of the plurality of delay circuits when the reference signal is input, a delay detection unit that detects the number of stages of the delay circuit in which the delay time with respect to the reference signal becomes a predetermined delay time, and an adjustment signal generation unit that generates an adjustment signal for adjusting the power supply voltage based on the detected number of stages.

[0008] This figure shows an example of the configuration of a semiconductor device according to the first embodiment of this disclosure. This figure shows an example of the configuration of a power measurement circuit according to the first embodiment of this disclosure. This figure shows an example of the configuration of a reference signal generation unit according to the first embodiment of this disclosure. This figure shows an example of the configuration of a delay circuit according to the first embodiment of this disclosure. This figure shows an example of the configuration of a delay unit according to the first embodiment of this disclosure. This figure shows an example of the configuration of a signal shaping circuit according to the first embodiment of this disclosure. This figure shows an example of the configuration of a delay detection unit according to the first embodiment of this disclosure. This figure shows an example of delay detection according to the first embodiment of this disclosure. This figure shows an example of moving average detection according to the first embodiment of this disclosure. This figure shows an example of the configuration of a load circuit according to the first embodiment of this disclosure. This figure shows an example of power supply voltage adjustment according to the first embodiment of this disclosure. This figure shows an example of operation of a delay circuit and delay unit according to the first embodiment of this disclosure. This figure shows an example of the configuration of a power measurement circuit according to the second embodiment of this disclosure. This figure shows an example of power supply voltage adjustment according to the second embodiment of this disclosure.

[0009] Embodiments of the present disclosure will be described in detail below with reference to the drawings. The description will be in the following order. In each of the following embodiments, the same parts will be denoted by the same reference numerals, and redundant descriptions will be omitted. 1. First Embodiment 2. Second Embodiment

[0010] (1. First Embodiment) <Configuration of Semiconductor Device> Figure 1 is a diagram showing an example configuration of a semiconductor device according to the first embodiment of the present disclosure. The same figure is a block diagram showing an example configuration of the semiconductor device 1. The semiconductor device 1 is a semiconductor device that has the function of detecting changes in the power consumption of its internal circuit and stabilizing the voltage of the internal power lines based on the detected changes in power consumption. The semiconductor device 1 comprises a processing circuit 30, a power measurement circuit 10, and a load circuit 20. The semiconductor device 1 also has a power line 41 for supplying power from an externally located power supply circuit 2 and a reference potential line 42 for transmitting a reference potential. The power line 41 is labeled "Vdd", and the reference potential line 42 is labeled with a symbol representing ground. In subsequent circuit diagrams, wiring labeled "Vdd" and a symbol representing ground may be used instead of the power line 41 and the reference potential line 42.

[0011] The processing circuit 30 is a circuit in the semiconductor device 1 other than the power measurement circuit 10 and the load circuit 20, and is operated by power supplied from the power line 41. The processing circuit 30 consumes power for its own operation. If the power consumption of the processing circuit 30 is large, the power supply voltage will drop. This may cause the operation of the processing circuit 30 itself to become unstable.

[0012] The power measurement circuit 10 detects changes in the power supply voltage of the power line 41. Based on the detected changes in power supply voltage, the power measurement circuit 10 generates an adjustment signal to adjust the voltage of the power line 41 and outputs it to the load circuit 20.

[0013] The load circuit 20 is a power-consuming circuit. This load circuit 20 consumes power by passing a load current caused by the power supply current from the power line 41, and adjusts the power supply voltage supplied by the power line 41. This load circuit 20 adjusts the power supply voltage based on the adjustment signal from the power measurement circuit 10.

[0014] Figure 2 is a diagram showing an example configuration of a power measurement circuit according to the first embodiment of the present disclosure. The figure is a block diagram showing an example configuration of the power measurement circuit 10. The power measurement circuit 10 includes a reference signal generation unit 110, a signal delay circuit 120, a signal shaping circuit 130, a delay detection unit 140, a moving average detection unit 150, an adjustment signal generation unit 160, a delay circuit selection unit 170, and a delay unit selection unit 180. Power lines 41 are also wired to the power measurement circuit 10. Power lines 41 supply power to the internal circuits of the power measurement circuit 10. An enable signal, a reset signal, and a clock signal are input to the power measurement circuit 10. In the figure, the enable signal, reset signal, and clock signal are referred to as "Enable," "Reset," and "Clock," respectively.

[0015] The reference signal generation unit 110 generates a reference signal. Here, the reference signal is a square wave with a specific period. The generated reference signal is output to the signal delay circuit 120 and the signal shaping circuit 130 via the signal line 103. In Figure 2, the reference signal is denoted as S.

[0016] The signal delay circuit 120 is a circuit that delays a reference signal. This signal delay circuit 120 comprises multiple delay circuits 121 whose delay time changes according to the power supply voltage. The signal delay circuit 120 in Figure 2 shows an example in which L delay circuits 121 (delay circuits 121a-121d) are provided. These delay circuits 121a-121d are connected in cascade. Specifically, the output of delay circuit 121a is connected to the input of delay circuit 121b. Also, the output of delay circuit 121b is connected to the input of delay circuit 121c. The final stage delay circuit 121d is wired similarly. The reference signal is input to the first stage delay circuit 121 (delay circuit 121a) of the cascade-connected delay circuits 121. On the other hand, the output signals of delay circuits 121a-121d are input to the signal shaping circuit 130, respectively. In Figure 2, the signals output from the delay circuits 121a-121d are labeled P1, P2, P3, and PL.

[0017] Furthermore, the signal delay circuit 120 is wired with a signal line 101 that transmits a control signal from the delay circuit selection unit 170 and a signal line 102 that transmits a control signal from the delay unit selection unit 180. Signal line 101 transmits the control signal VSEL[1:L]. This is a control signal that selects the delay circuits 121a-121d. Control signal VSEL[1] is transmitted to delay circuit 121a. Control signal VSEL[2] is transmitted to delay circuit 121b. Control signal VSEL[3] is transmitted to delay circuit 121c. The Lth delay circuit 121d is transmitted with the Lth control signal VSEL[L].

[0018] Furthermore, the control signal HSEL[1:M] is a control signal that selects the delay unit 220, which will be described later in Figure 4. The control signal HSEL[1:M] is transmitted in common to the delay circuits 121a to 121d. Details of the configuration of the signal delay circuit 120 will be described later.

[0019] The signal shaping circuit 130 shapes the signals (P1-PL) from the delay circuits 121a-121d. The signal shaping circuit 130 in Figure 2 further shapes the reference signal S. As will be described later, the reference signal generated by the reference signal generation unit 110 is a signal synchronized with the clock signal. In contrast, the output signal of the signal delay circuit 120 is a signal that is not synchronized with the clock signal due to the delay. The signal shaping circuit 130 shapes this asynchronous signal into a signal synchronized with the clock signal. The signal shaping circuit 130 outputs signals S', P1', P2', P3', and PL' to the delay detection unit 140. These correspond to the reference signal S, signal P1, signal P2, signal P3, and signal PL, respectively. Details of the configuration of the signal shaping circuit 130 will be described later.

[0020] The delay detection unit 140 detects the number of stages in the delay circuits 121a-121d such that the delay time relative to the reference signal is a predetermined delay time. Here, the number of stages represents the number of delay circuits 121 that the output signal from the signal delay circuit 120 has passed through. For example, since signal P1 is a signal that has passed through only delay circuit 121a, it is the first stage signal. The predetermined delay time is, for example, half a period of the reference signal. This corresponds to the period of the clock signal. The delay detection unit 140 detects the number of stages based on the output signals of each of the delay circuits 121a-121d when the reference signal is input. The delay detection unit 140 also encodes the detected number of stages and outputs the encoded detection result to the moving average detection unit 150.

[0021] The moving average detection unit 150 detects the moving average of the number of stages detected by the delay detection unit 140. This moving average detection unit 150 detects the moving average by calculating the moving average of the number of stages. Known methods can be applied to calculate the moving average in the moving average detection unit 150. The moving average detection unit 150 in Figure 2 detects the coded moving average of the number of stages. The moving average of the number of stages is output to the adjustment signal generation unit 160.

[0022] The adjustment signal generation unit 160 generates an adjustment signal to adjust the power supply voltage based on the input number of stages. In Figure 2, the adjustment signal generation unit 160 generates an adjustment signal based on the moving average of the number of stages detected by the moving average detection unit 150. The adjustment signal can be generated by multiplying the moving average value by an arbitrary coefficient. In this case, the adjustment signal can be generated by multiplying the relative change from past data being measured by a coefficient. Alternatively, the adjustment signal can also be generated by multiplying the absolute difference from a set reference value by a coefficient. This adjustment signal is output to the load circuit 20.

[0023] The delay circuit selection unit 170 selects the delay circuit from among the delay circuits 121a-121d to be used for delaying the reference signal. For example, the delay circuit selection unit 170 can select the delay circuits from the first stage to the intermediate stages of the cascaded delay circuits 121a-121d. That is, it can deselect the later stages of the delay circuits 121a-121d that are not used. The delay circuit selection unit 170 outputs a control signal VSEL to the selected delay circuit.

[0024] The delay section selection unit 180 selects the delay section (delay sections 220a-220d) included in the delay circuits 121a-121d, respectively, to be used for delaying the reference signal. The delay section selection unit 180 outputs a control signal HSEL to the selected delay section.

[0025] Figure 3 is a diagram showing an example configuration of a reference signal generation unit according to the first embodiment of the present disclosure. The figure is a circuit diagram showing an example configuration of the reference signal generation unit 110. The reference signal generation unit 110 comprises a D flip-flop 111, an AND gate 112, and an EOR gate 113. As shown in the figure, the EOR gate 113 and the D flip-flop 111 constitute a toggle flip-flop. This circuit generates a reference signal by dividing the clock signal. The AND gate 112 is a gate that permits the generation of the reference signal.

[0026] Figure 4 is a diagram showing an example configuration of a delay circuit according to the first embodiment of the present disclosure. The diagram is a circuit diagram showing an example configuration of the delay circuit 121. Note that the delay circuit 121 in the diagram is assumed to be the case of the delay circuit 121a in Figure 2. The delay circuit 121 comprises an AND gate 210 and a plurality of delay sections 220 (delay sections 220a-220d). The delay circuit 121 in the diagram shows an example in which M delay sections 220 are provided.

[0027] As shown in Figure 4, the delay sections 220a-220d are connected in cascaded order. The first stage of the delay sections 220a, 220a, receives a reference signal S via an AND gate 210. The AND gate 210 is a gate that allows the reference signal S to pass through based on the control signal VSEL of the delay circuit selection unit 170.

[0028] The delay units 220a-220d receive the control signal HSEL from the delay unit selection unit 180. The control signal HSEL[1] is input to delay unit 220a, HSEL[2] is input to delay unit 220b, HSEL[3] is input to delay unit 220c, and HSEL[M] is input to delay unit 220d.

[0029] Figure 5 is a diagram showing an example configuration of a delay unit according to the first embodiment of the present disclosure. The same figure is a circuit diagram showing an example configuration of the delay unit 220. Note that the delay unit 220 in the same figure is assumed to be the case of the delay unit 220a in Figure 4. The delay unit 220 comprises a plurality of inverting gates 221 and 222 and a selector 223. Note that an even number (2N) of inverting gates 221 and 222 are arranged.

[0030] The inverting gates 221 and 222 are logic gates whose delay time changes according to the power supply voltage. As shown in Figure 5, the inverting gates 221 and 222 are connected in cascade. A reference signal is input to the first stage of the inverting gates 221 and 222 via the AND gate 210. The control inputs of the inverting gates 221 and 222 are also input to the control signal HSEL[1] from the delay unit selection unit 180.

[0031] The selector 223 selects and outputs either the reference signal input to the delay unit 220 or the reference signal delayed by the inverting gates 221 and 222, based on the control signal HSEL[1] from the delay unit selection unit 180. In Figure 5, the selector 223 selects the reference signal input to the delay unit 220 when the control signal HSEL[1] is value 0, and selects the reference signal delayed by the inverting gates 221 and 222 when the control signal HSEL[1] is value 1. The selector 223 bypasses the circuits of the inverting gates 221 and 222, thereby suppressing the delay operation of the reference signal. This reduces the power consumption of the inverting gates 221 and 222.

[0032] Figure 6 is a diagram showing an example configuration of a signal shaping circuit according to the first embodiment of the present disclosure. The diagram shows an example configuration of the signal shaping circuit 130. The signal shaping circuit 130 includes signal shaping units 131 to 135 corresponding to the reference signal S and the signal P1-PL, respectively. The signal shaping unit 131 will be described as an example.

[0033] The signal shaping unit 131 includes three D flip-flops (D flip-flops 137 to 139). These D flip-flops 137 to 139 are connected in cascaded order. The clock signal and reset signal are input to the D flip-flops 137 to 139 in common. The cascaded D flip-flops 137 to 139 convert the reference signal S into a signal synchronized with the clock signal. In addition, malfunctions due to the metastable state can be reduced during this process.

[0034] Figure 7 is a diagram showing an example configuration of a delay detection unit according to the first embodiment of the present disclosure. The same figure is a circuit diagram showing an example configuration of the delay detection unit 140. The delay detection unit 140 comprises EOR gates 141 to 144, AND gates 145 to 148, and a decoder 149.

[0035] EOR gates 141 to 144 are gates that detect whether signal S' matches signals P1', P2', P3', and PL', respectively. The output signals of EOR gates 141 to 144 are denoted as P1"-PL". The output of EOR gate 141 is input to decoder 149 via AND gate 145. The output of EOR gate 142 is input to decoder 149 via AND gate 146. The output of EOR gate 143 is input to decoder 149 via AND gate 147. The output of EOR gate 144 is input to decoder 149 via AND gate 148.

[0036] AND gates 145 to 148 are gates that allow the input of the output signals of EOR gates 141 to 144 to the decoder 149 based on the control signal VSEL.

[0037] The decoder 149 encodes the output signals of the EOR gates 141 to 144. The decoder 149 outputs the number of stages of the delay circuit 121, which has been converted into a signal of a predetermined number of bits by encoding.

[0038] Figure 8 is a diagram showing an example of delay detection according to the first embodiment of the present disclosure. The same figure is a timing diagram showing an example of delay detection in the delay detection unit 140, etc. In the same figure, "Clock" represents the clock signal. "S" represents the reference signal S. "P1" represents the signal P1 output from the delay circuit 121a. "P2" represents the signal P2 output from the delay circuit 121b. "P3" represents the signal P3 output from the delay circuit 121c. "S'" represents the signal obtained by shaping the reference signal S. "P1'" represents the signal obtained by shaping the signal P1. "P2'" represents the signal obtained by shaping the signal P2. "P3'" represents the signal obtained by shaping the signal P3. "P1''" represents the output signal of the EOR gate 141 in Figure 7. "P2''" represents the output signal of the EOR gate 142 in Figure 7. "P3" represents the output signal of the EOR gate 143 in Figure 7.

[0039] In Figure 8, T represents the period of the clock signal. The reference signal S is a square wave obtained by dividing the clock signal. Signal P1 is a signal delayed from the reference signal S. This delay amount is D1. Signal P2 is a signal that is further delayed from the reference signal S. This delay amount is D2. Signal P3 is a signal that is further delayed from the reference signal S. This delay amount is D3. As shown in Figure 8, D3 is a delay amount that exceeds half a period of the reference signal S, i.e., the period T of the clock signal.

[0040] Signal S' is the inverted version of the reference signal S. Signals P1'' and P2'' are synchronized with signal S'. Therefore, signals P1'' and P2'' have a value of 0. In contrast, signal P3'' is the inverted version of signal S'. Therefore, signal P3'' has a value of 1.

[0041] By detecting the signal P3'' which has a value of 1, it is possible to detect the number of stages where the delay time with respect to the reference signal S is a predetermined delay time (half a period of the reference signal S). The decoder 149 in Figure 7 generates a code corresponding to the position where the signal with a value of 1 is input.

[0042] Figure 9 is a diagram showing an example of moving average detection according to the first embodiment of this disclosure. The figure shows the movement detection process in the moving average detection unit 150. In the figure, the horizontal axis represents time. The solid line represents the output of the delay detection unit 140. The dashed line represents the detection result of the moving average detection unit 150. By detecting the moving average, the output of the delay detection unit 140 becomes a smoothly changing signal. The bar graph in the figure represents the power consumption of the load circuit 20.

[0043] Figure 10 is a diagram showing an example configuration of a load circuit according to the first embodiment of the present disclosure. The same figure shows an example configuration of a load circuit 20. The load circuit 20 comprises a selection unit 21 and a plurality of electronic load units 22 (electronic load units 22a-22c).

[0044] The selection unit 21 selects the electronic load units 22 based on the adjustment signal. When the adjustment signal is a value that further reduces the power supply voltage, the selection unit 21 selects a larger number of electronic load units 22. When the adjustment signal is a value that does not reduce the power supply voltage, the selection unit 21 reduces the number of electronic load units 22 to be selected.

[0045] The electronic load units 22 allow a power supply current to flow from the power supply line by consuming power. The electronic load units 22 in FIG. 10 illustrate an example configured by a circuit that causes a resistive load to consume power. The electronic load units 22 include a non-inverting gate 23 and a resistor 24. The non-inverting gate 23 allows an output current to flow through the resistor 24 based on the signal from the selection unit 21. The electronic load units 22 selected by the selection unit 21 allow current to flow through the internal resistor 24 and consume power. Thereby, the power supply voltage can be adjusted.

[0046] FIG. 11 is a diagram showing an example of the adjustment of the power supply voltage according to the first embodiment of the present disclosure. This figure represents an example of the adjustment of the power supply voltage by the load circuit 20. The horizontal axis represents time. The vertical axis represents power consumption. The solid line broken line represents the power consumption of the processing circuit 30 in FIG. 1. The dotted line broken line represents the power consumption of the load circuit 20. The dashed-dotted line represents the overall power consumption of the semiconductor device 1.

[0047] As shown in FIG. 11, the power consumption of the load circuit 20 changes so as to cancel out the change in the power consumption of the processing circuit 30. Thereby, the power consumption of the semiconductor device 1 becomes substantially constant, and fluctuations in the power supply voltage can be reduced.

[0048] FIG. 12 is a diagram showing an example of the operations of the delay circuit and the delay units according to the first embodiment of the present disclosure. This figure represents an example of the operations of the delay circuits 121a - 121d and the delay units 220a - 220d. As described above, only the delay circuit selected by the control signal VSEL from the delay circuit selection unit 170 among the delay circuits 121a - 121d operates. Also, only the delay unit selected by the control signal HSEL from the delay unit selection unit 180 among the delay units 220a - 220d operates. Depending on the usage environment, the operation of the subsequent-stage delay unit among the delay units 220a - 220d can be stopped. The delay unit surrounded by the dashed-dotted line 302 in this figure represents the delay unit whose operation has been stopped. Similarly, depending on the usage environment, the operation of the subsequent-stage delay circuit among the delay circuits 121a - 121d can be stopped. The delay circuit surrounded by the dashed-dotted line 301 in this figure represents the delay circuit whose operation has been stopped.

[0049] Thus, the semiconductor device 1 according to the first embodiment of the present disclosure can detect a change in the power supply voltage due to the power consumption of the internal circuit by the signal delay circuit 120, and adjust the power supply voltage by controlling the load circuit 20 based on the detection result. Thereby, the power supply voltage can be stabilized. Also, by selecting a plurality of delay circuits 121 included in the signal delay circuit 120 and a plurality of delay units 220 included in each delay circuit 121, a desired delay amount can be achieved, and convenience can be improved. Further, by stopping the operations of the delay circuits 121 and the delay units 220 that become unused among the plurality of delay circuits 121 and the plurality of delay units 220, the power consumption can be reduced.

[0050] (2. Second Embodiment) The power measurement circuit 10 of the above-described first embodiment always adjusted the power supply voltage. In contrast, the power measurement circuit 10 of the second embodiment of the present disclosure is different from the above-described first embodiment in that it adjusts the power supply voltage during a desired period.

[0051] <Configuration of the Power Measurement Circuit> Figure 13 is a diagram showing an example configuration of a power measurement circuit according to the second embodiment of the present disclosure. This figure, like Figure 2, shows an example configuration of the power measurement circuit 10. The power measurement circuit 10 in this figure differs from the power measurement circuit 10 in Figure 2 in that it further comprises a control unit 190. Note that in this figure, the names of signals and the like have been omitted.

[0052] The control unit 190 controls the adjustment of the power supply voltage of the power measurement circuit 10. This control unit 190 controls the output of the control signal VSEL to the delay circuit selection unit 170 and the output of the control signal HSEL to the delay unit selection unit 180. As a result, the operation of the signal delay circuit 120 and other components can be stopped during periods when adjustment of the power supply voltage is not required, and the operation of the load circuit 20 can be stopped. For example, the adjustment of the power supply voltage can be stopped during sleep periods.

[0053] Figure 14 is a diagram showing an example of power supply voltage adjustment according to a second embodiment of the present disclosure. Similar to Figure 11, this figure shows an example of power supply voltage adjustment by the load circuit 20. In this figure, the period indicated by the arrow represents the adjustment period. The operation of the control unit 190 stops the operation of the load circuit 20 for a period different from the desired adjustment period.

[0054] The configuration of the semiconductor device 1 other than that described above is the same as that of the semiconductor device 1 in the first embodiment of this disclosure, so a description will be omitted.

[0055] Thus, the semiconductor device 1 of the second embodiment of the present disclosure can set a period for adjusting the power supply voltage.

[0056] (Effect) The semiconductor device comprises a power line that supplies a power voltage, a signal delay circuit configured by cascading multiple delay circuits whose delay time changes according to the power voltage, a reference signal generation unit that generates a reference signal to be input to the first stage of the multiple delay circuits of the signal delay circuit, a delay detection unit that detects the number of stages of the delay circuit in which the delay time relative to the reference signal becomes a predetermined delay time based on the output signals of each of the multiple delay circuits when the reference signal is input, and an adjustment signal generation unit that generates an adjustment signal for adjusting the power voltage based on the detected number of stages. This makes it possible to detect the delay based on the number of stages of the cascaded delay circuits and to easily change the delay time.

[0057] Furthermore, the system may include a load circuit that adjusts the power supply voltage by passing a load current corresponding to the generated adjustment signal through the power supply line. This allows for easy adjustment of the load current in the load circuit.

[0058] Furthermore, the load circuit may have a control unit that controls the adjustment of the power supply voltage. This makes it possible to adjust the power supply voltage over a desired period of time.

[0059] Furthermore, the reference signal generation unit may generate a square wave of a specific period as the reference signal, and the delay circuit may detect the number of stages using a predetermined delay time equivalent to half a period of the reference signal. This allows a reference signal synchronized with the clock signal to be used, and a delay time based on the clock signal to be set. Therefore, delay detection can be easily performed.

[0060] Furthermore, the system may include a delay circuit selection unit that selects from among the multiple delay circuits to be used for delaying the reference signal. This allows the operation of unselected delay circuits to be stopped.

[0061] Furthermore, the multiple delay circuits may be configured by cascading multiple delay units, each containing a logic gate whose delay time changes according to the power supply voltage. This allows for the detection of changes in the power supply voltage based on the delay time.

[0062] Furthermore, the system may include a delay section selection unit that selects from among the multiple delay sections of each of the multiple delay circuits to be used for delaying the reference signal. This allows the operation of unselected delay sections to be stopped.

[0063] Furthermore, the delay unit may include a circuit that suppresses delay operation by bypassing the logic gate, and the delay unit selection unit may select the delay unit by outputting a control signal from the circuit that suppresses delay operation. This allows the power consumption of the delay unit to be adjusted based on the control signal.

[0064] Furthermore, the system may include a signal shaping circuit that shapes the output signals of multiple delay circuits, and the delay detection unit may detect the number of stages based on the shaped output signals. This can improve the accuracy of delay detection.

[0065] Furthermore, the system may further include a moving average detection unit that detects the moving average of the detected number of stages, and the adjustment signal generation unit may generate the adjustment signal based on the detected moving average of the number of stages. This allows for smooth adjustment of the power supply voltage.

[0066] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0067] Furthermore, this technology can also take the following configurations: (1) A semiconductor device comprising: a power line that supplies a power voltage; a signal delay circuit configured by cascading a plurality of delay circuits whose delay time changes according to the power voltage; a reference signal generation unit that generates a reference signal to be input to the first stage of the plurality of delay circuits of the signal delay circuit; a delay detection unit that detects the number of stages of the delay circuit in which the delay time with respect to the reference signal becomes a predetermined delay time, based on the output signals of each of the plurality of delay circuits when the reference signal is input; and an adjustment signal generation unit that generates an adjustment signal for adjusting the power voltage based on the detected number of stages. (2) The semiconductor device according to (1), further comprising a load circuit that adjusts the power voltage by flowing a load current corresponding to the generated adjustment signal from the power line. (3) The semiconductor device according to (2), further comprising a control unit that controls the adjustment of the power voltage of the load circuit. (4) The semiconductor device according to any one of (1) to (3), wherein the reference signal generation unit generates a rectangular wave of a specific period as the reference signal, and the delay circuit detects the number of stages with a predetermined delay time corresponding to half a period of the reference signal. (5) The semiconductor device according to any one of (1) to (3), further comprising a delay circuit selection unit that selects from a plurality of delay circuits to be used for delaying the reference signal. (6) The semiconductor device according to any one of (1) to (5), wherein the plurality of delay circuits are configured by cascading a plurality of delay units including a logic gate whose delay time changes according to the power supply voltage. (7) The semiconductor device according to (6), further comprising a delay unit selection unit that selects from a plurality of delay units of each of the plurality of delay circuits to be used for delaying the reference signal. (8) The semiconductor device according to (7), wherein the delay unit includes a circuit that suppresses delay operation by bypassing the logic gate, and the delay unit selection unit selects the delay unit by outputting a control signal for the circuit that suppresses delay operation. (9) The semiconductor device according to any one of (1) to (8), further comprising a signal shaping circuit for shaping the output signals of a plurality of delay circuits, wherein the delay detection unit detects the number of stages based on the shaped output signals.(10) A semiconductor device according to any one of (1) to (9), further comprising a moving average detection unit for detecting the moving average of the detected number of stages, wherein the adjustment signal generation unit generates the adjustment signal based on the moving average of the detected number of stages.

[0068] 1 Semiconductor device 10 Power measurement circuit 20 Load circuit 41 Power line 110 Reference signal generation unit 120 Signal delay circuit 121, 121a, 121b, 121d Delay circuit 130 Signal shaping circuit 140 Delay detection unit 150 Moving average detection unit 160 Adjustment signal generation unit 180 Delay unit selection unit 190 Control unit 220, 220a, 220b, 220c, 220d Delay unit

Claims

1. A semiconductor device comprising: a power line that supplies a power voltage; a signal delay circuit configured by cascading multiple delay circuits whose delay time changes according to the power voltage; a reference signal generation unit that generates a reference signal to be input to the first stage of the multiple delay circuits of the signal delay circuit; a delay detection unit that detects the number of stages of the delay circuit in which the delay time relative to the reference signal becomes a predetermined delay time, based on the output signals of each of the multiple delay circuits when the reference signal is input; and an adjustment signal generation unit that generates an adjustment signal for adjusting the power voltage based on the detected number of stages.

2. The semiconductor device according to claim 1, further comprising a load circuit that adjusts the power supply voltage by passing a load current corresponding to the generated adjustment signal from the power line.

3. The semiconductor device according to claim 2, further comprising a control unit for controlling the adjustment of the power supply voltage of the load circuit.

4. The semiconductor device according to claim 1, wherein the reference signal generation unit generates a rectangular wave of a specific period as the reference signal, and the delay circuit detects the number of stages with a time equivalent to half a period of the reference signal as the predetermined delay time.

5. The semiconductor device according to claim 1, further comprising a delay circuit selection unit that selects from a plurality of delay circuits to be used for delaying the reference signal.

6. The semiconductor device according to claim 1, wherein the plurality of delay circuits are configured by cascading together a plurality of delay units, each including a logic gate whose delay time changes according to the power supply voltage.

7. The semiconductor device according to claim 6, further comprising a delay section selection unit that selects from among a plurality of delay sections of each of the plurality of delay circuits to be used for delaying the reference signal.

8. The semiconductor device according to claim 7, wherein the delay unit includes a circuit that suppresses delay operation by bypassing the logic gate, and the delay unit selection unit selects the delay unit by outputting a control signal of the circuit that suppresses delay operation.

9. The semiconductor device according to claim 1, further comprising a signal shaping circuit for shaping the output signals of a plurality of delay circuits, wherein the delay detection unit detects the number of stages based on the shaped output signals.

10. The semiconductor device according to claim 1, further comprising a moving average detection unit that detects the moving average of the detected number of stages, wherein the adjustment signal generation unit generates the adjustment signal based on the detected moving average of the number of stages.

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