Programmable logic controller

Abstract

The present invention comprises: a control element (2) that is disposed on a signal ground pattern (14) and includes a serial communication unit (3a); a parallel-serial conversion IC (5) that is disposed on an IO ground pattern (15) and transmits and receives serial data to and from the serial communication unit (3a); an insulating element (4) that has a plurality of terminals disposed on the signal ground pattern (14) and connected to the serial communication unit (3a) and a plurality of terminals disposed on the IO ground pattern (15) and connected to the parallel-serial conversion IC (5); an input circuit (7) that is composed of limiting resistors and filters and is connected to the parallel-serial conversion IC (5); and a capacitor (6a) that has a first electrode connected to the signal ground pattern (14) and a second electrode connected to the IO ground pattern (15).

Description

Programmable Logic Controller

[0001] The present disclosure relates to a programmable logic controller.

[0002] The input circuit of a general PLC (Programmable Logic Controller) is composed of an input limiting resistor and a filter, and transfers data by parallel communication via an insulating element between the control element and the input circuit. In the input circuit of a PLC, each communication signal is an independent asynchronous signal without synchronization. The input circuit of a PLC captures these communication signals via a terminal block, which is an external wiring interface. However, since a PLC is a device that requires several tens of input points, it is necessary to provide the same number of input signal lines as the number of input points and a large number of insulating elements accordingly on the circuit board. As a result, there is a problem that the circuit scale of the PLC increases.

[0003] In order to miniaturize the circuit scale between the control element and the input circuit, a circuit configuration using serial communication for communication between the control element and the input circuit is known. Patent Document 1 is an example of an output circuit, and discloses a method of connecting a plurality of slave devices (reception devices) to the interface of the control circuit of the master device. By adopting serial communication, the number of signal lines can be reduced compared to parallel communication, and the circuit scale including the number of insulating elements can be reduced.

[0004] Japanese Patent Application Laid-Open No. 2017-117245

[0005] However, in Patent Document 1, since the capacitance between the primary side circuit and the secondary side circuit of the insulating element that transmits the serial communication signal is small and the impedance between the insulating elements is large, when external noise propagates to the PLC, electromagnetic noise concentrates on the insulating element part. As a result, the serial communication circuit malfunctions, and there arises a problem that the noise resistance is lowered with respect to the conventional input circuit adopting parallel communication.

[0006] Therefore, an object of the present disclosure is to provide a programmable logic controller with high noise resistance.

[0007] The programmable logic controller of this disclosure comprises a printed circuit board having a signal ground pattern and an I / O ground pattern; a control element disposed on the signal ground pattern and having at least one serial communication unit; at least one parallel-to-serial conversion IC disposed on the I / O ground pattern and transmitting and receiving serial data with at least one serial communication unit; at least one insulating element disposed on the signal ground pattern and having a plurality of terminals connected to at least one serial communication unit, and a plurality of terminals disposed on the I / O ground pattern and connected to at least one parallel-to-serial conversion IC; an input circuit composed of a limiting resistor and a filter and connected to at least one parallel-to-serial conversion IC; and at least one capacitor having a first electrode connected to the signal ground pattern and a second electrode connected to the I / O ground pattern.

[0008] The programmable logic controller of this disclosure can be made more susceptible to noise by including at least one capacitor having a first electrode connected to a signal ground pattern and a second electrode connected to an I / O ground pattern.

[0009] This figure shows an example of a control system 100 including a PLC according to Embodiment 1. This is a circuit block diagram of the PLC (input unit 1) according to Embodiment 1. This is a circuit block diagram of the PLC (input unit 1) according to Embodiment 1, including the substrate GND pattern. This is a circuit block diagram of the PLC (input unit 1) according to Modification 1 of Embodiment 1. This is a circuit block diagram of the PLC (input unit 1) according to Modification 2 of Embodiment 1. This is a layout diagram of the SG-IOGND capacitor 6a in the input unit 1 according to Embodiment 2. This figure shows the path of noise current when the SG-IOGND capacitor 6a is placed between the IOGND pattern 15 and the SG pattern 14 on the printed circuit board 10, and close to the FG pattern 16. This figure shows the path of noise current when the SG-IOGND capacitor 6a is placed between the IOGND pattern 15 and the SG pattern 14 on the printed circuit board 10, and directly below the insulating element 4 on the opposite side. This graph shows the relative noise intensity in the SPI signal between the input and output terminals of the insulating element 4 when the capacitance value of the SG-IOGND capacitor 6a is changed. This is a circuit block diagram of the PLC (input unit 1) according to Embodiment 4. This graph shows the relative noise intensity in the SPI signal between the input and output terminals of the insulating element 4 for each number of SG-IOGND capacitors. This is a circuit block diagram of the PLC (input unit 1) according to Embodiment 5. This is a circuit block diagram of the PLC (input unit 1) according to Embodiment 6. This is a circuit block diagram of the PLC (input unit 1) according to Embodiment 7.

[0010] The embodiments will be described below with reference to the attached drawings. Note that the embodiments can be freely combined, modified, or omitted as appropriate.

[0011] Embodiment 1. Figure 1 is a diagram showing an example of a control system 100 including a PLC according to Embodiment 1. The PLC is equipped with an input circuit.

[0012] The control system 100 includes a plurality of control units 102 and a backplane 101 that connects the plurality of control units 102.

[0013] The control system 100 takes in output signals from external output devices such as switches or sensors as input signals and performs calculations and controls external devices according to the PLC sequence. The control system 100 may be a building type composed of a combination of control units 102 equipped with various functions such as power supply, CPU (Central Processing Unit), communication, and I / O, or it may be a block type or package type integrating the aforementioned functions (not shown). In any form, the control system 100 includes the function of an input circuit 7 for controlling the device to which the control system 100 is connected. In the following description, as an example, a PLC targeting the input unit 1 in a block-type control unit 102 will be described.

[0014] Figure 2 is a circuit block diagram of the PLC (input unit 1) according to Embodiment 1. Figure 3 is a circuit block diagram of the PLC (input unit 1) according to Embodiment 1, including the substrate GND pattern.

[0015] In Figures 2 and 3, the control unit 102 is an input unit 1 equipped with an input circuit 7. The input unit 1 may be either an AC input type or a DC input type. The DC input may be either a sink type or a source type. In the following description, the DC input type will be used as an example.

[0016] The input unit 1 comprises at least a control element 2 with a serial communication unit 3a, an isolation element 4, a parallel-to-serial conversion IC 5, an input circuit 7, a printed circuit board 10, an SG (Signal Ground) pattern 14, an IOGND (Input Output Ground) pattern 15, and an SG-IOGND capacitor 6a. The input unit 1 may further comprise, for example, an isolated power supply 8, an FG (Frame Ground) pattern 16, a backplane connector 80 for connecting to a backplane 101, a control power supply circuit 81, an oscillator circuit 82, an FG fitting 83, an FG-SG capacitor 84, an IO power supply circuit 90, and an external wiring interface 91.

[0017] The input circuit 7 is connected to the external wiring interface 91 and the parallel-to-serial conversion IC 5. The input circuit 7 includes multiple limiting resistors and filters.

[0018] The input signal received from the external wiring interface 91 is input to the parallel-to-serial conversion IC 5 via the input circuit 7. Within this IC, the parallel signal is converted to a serial signal and input to the control element 2 via the isolation element 4. The input unit 1 in Figure 2 is an example. For example, there may be one or more serial communication units 3a, isolation elements 4, and parallel-to-serial conversion IC 5. The number of input points in the input unit 1 is not limited to 16, but may be 8, 32, or 64.

[0019] The control element 2 is an integrated circuit (IC) that transmits and receives data to and from the parallel-to-serial conversion IC 5 via an isolation element 4 using SPI (Serial Peripheral Interface) communication. The control element 2 is, for example, an MCU (Microcontroller Unit), an FPGA (Field Programmable Array), or an ASIC (Application Specific Integrated Circuit). In addition to the serial communication unit 3a, the control element 2 may also include a power input supplied from a control power supply circuit 81, a clock input transmitted from an oscillator circuit 82, a CPU, and memory. The control element 2 may contain one or more serial communication units 3a. To increase the amount of data transmitted and received, the control element 2 may be equipped with serial communication ports depending on the data transfer rate and number of wires of the serial signal. The control element 2 may also be equipped with a digital filter to remove external noise.

[0020] The serial communication unit 3a has multiple external connection terminals and is an interface for serial data communication with external devices in accordance with SPI communication. Each part of the serial communication unit 3a operates independently. The serial communication unit 3a includes terminals MOSI (Master Out Slave In) and MISO (Master In Slave Out) for inputting and outputting serial data signals, a terminal CLK for outputting a clock signal, and a terminal CS for outputting a chip select signal. Terminal MOSI outputs a serial data signal in master mode and receives a serial data signal in slave mode. Terminal MISO receives a serial data signal in master mode and outputs a serial data signal in slave mode. In this embodiment, the control element 2 operates as a slave device. Therefore, terminal MOSI of the serial communication unit 3a outputs a serial data signal, and terminal MISO of the serial communication unit 3a receives a serial data signal. It is also possible to use only one of the functions of terminal MOSI and terminal MISO.

[0021] The isolation element 4 is connected between the control element 2 and the parallel-to-serial conversion IC 5. The isolation element 4 is composed of a photocoupler or a digital isolator, etc. The isolation element 4 is provided to transmit and receive signals between devices with different GND potentials and has the function of preventing electromagnetic noise from being conducted to the control element 2. The isolation element 4 shown in Figures 2 and 3 has IN / OUT terminals for 4 channels, so it can output 4 input signals. As a specific example, the isolation element 4 has 4 input terminals IN1 to IN4 and 4 output terminals OUT1 to OUT4. Signals input to input terminal INi (i = 1 to 4) are output from output terminal OUTi. The isolation element 4 is not limited to a 4-terminal product. The number of terminals of the isolation element 4 may be 8 terminals or 16 terminals depending on the number of control elements 2 or parallel-to-serial conversion ICs 5, and it may also be composed of multiple isolation elements 4.

[0022] The parallel-to-serial conversion IC 5 receives the input signal from the input circuit 7 as asynchronous parallel communication, converts the parallel signal into a serial signal (SPI signal), and communicates with the control element 2. To operate and control the parallel-to-serial conversion IC 5, there may be a power supply from an isolated power supply 8, and there may also be a reset circuit and a clock circuit (not shown). As a specific example, if the input unit 1 has 16 inputs as shown in Figures 2 and 3, the signals from the 16-wire parallel bus are transmitted between the external wiring interface 91 and the parallel-to-serial conversion IC 5, excluding the IOGND pattern 15. In other words, 16 single-ended wires are arranged with the IOGND pattern 15 as the reference potential. The parallel-to-serial conversion IC 5 receives the parallel input signal transmitted by the 16 single-ended wires and converts it into a serial signal. There may be one or more parallel-to-serial conversion ICs 5. A single-chip IC integrating the isolated element 4, the parallel-to-serial conversion IC 5, and the isolated power supply 8 may also be provided. Furthermore, the parallel-to-serial conversion IC 5 may be equipped with a reset input terminal (not shown), to which a signal output from a circuit that uses the SG pattern 14 as the reference GND is input via the insulating element 4.

[0023] The SG-IOGND capacitor 6a is, for example, a ceramic capacitor, a film capacitor, an aluminum electrolytic capacitor, a tantalum electrolytic capacitor, or a variable capacitor. Preferably, the SG-IOGND capacitor 6a is one that fails in an open circuit, such as a ceramic capacitor. One or more SG-IOGND capacitors 6a are mounted. The SG-IOGND capacitor 6a may be a surface-mount component or an through-hole component.

[0024] The isolated power supply 8 receives power supplied via the backplane connector 80 or power generated within the input unit 1 as input, and outputs the power input voltage to the isolation element 4 and the parallel serial conversion IC 5 via a transformer built into the isolated power supply 8. The destination of the power input voltage generated by the isolated power supply 8 is not limited to the isolation element 4 and the parallel serial conversion IC 5, but may be other circuits depending on the configuration of the input unit 1. The isolated power supply 8 is modularized and consists of an input filter, an inverter, a control IC that controls the inverter, a transformer that electrically isolates the input and output and performs current and voltage conversion according to the turns ratio, a rectifier circuit, a smoothing circuit, and an isolation element for feeding back the output voltage to the control IC while isolating it. The isolated power supply 8 may also include a capacitor between the primary and secondary circuits as a noise countermeasure. The transformer electrically isolates the input and output and has winding capacitance. This winding capacitance can range from a few pF to several hundred pF. Thus, the isolated power supply 8 has capacitance between the primary and secondary circuits, intentionally or unintentionally.

[0025] The SG-IOGND capacitor 6a is positioned between the SG pattern 14 and the IOGND pattern 15. The SG-IOGND capacitor 6a includes a first electrode EA1 electrically connected to the SG pattern 14 by soldering or the like, and a second electrode EA2 electrically connected to the IOGND pattern 15 by soldering or the like.

[0026] Since the input unit 1 has a voltage withstand voltage requirement between the SG pattern 14 and the IOGND pattern 15, the voltage withstand voltage of the SG-IOGND capacitor 6a is selected to be equal to or greater than the voltage withstand voltage specified in the product specifications. For example, if the input unit 1 has a voltage withstand voltage of DC 500V, a DC 630V or DC 1000V withstand voltage capacitor 6a may be selected. If the input unit 1 has a voltage withstand voltage of AC 500V, the voltage peak-to-peak is ±705V, so an AC 2000V withstand voltage capacitor 6a may be selected.

[0027] An SG-IOGND capacitor 6a having a capacitance value greater than the total capacitance between the input and output of the insulating element 4 may be selected. Specifically, if the insulating element 4 is a four-terminal type and the capacitance value per terminal between the input and output is 0.1 pF, the total parasitic capacitance will be 0.8 pF. In this case, an SG-IOGND capacitor 6a having a capacitance value greater than 0.8 pF is selected. Preferably, a capacitor with a larger constant within the range that satisfies the dielectric strength required by the input unit 1 is preferable, for example, an SG-IOGND capacitor 6a having a capacitance value of 1,000 pF, and more preferably 10,000 pF, can be selected.

[0028] The SG-IOGND capacitor 6a blocks low-frequency noise and bypasses high-frequency noise according to its capacitance value. Specifically, the SG-IOGND capacitor 6a prevents low-frequency noise, including DC, entering from external equipment from propagating from the IOGND pattern 15 to the SG pattern 14 and ultimately to the control element 2, while allowing high-frequency noise to be conducted from the IOGND pattern 15 to the SG pattern 14. By reducing the impedance difference between the SG pattern 14 and the IOGND pattern 15 due to the SG-IOGND capacitor 6a, the noise voltage induced between the SG pattern 14 and the IOGND pattern 15 due to noise containing high-frequency components can be reduced. As a result, the noise voltage induced between the input and output of the isolation element 4 can be suppressed.

[0029] The printed circuit board 10 fixes electronic components such as the control element 2, the insulating element 4, and the parallel-to-serial conversion IC 5. Circuit wiring such as SG pattern 14 and IOGND pattern 15 is formed on the printed circuit board 10 as power supply wiring, signal wiring, and GND wiring for operating these electronic components. In order to realize the function of the circuit block shown in Figure 2, the necessary points are electrically connected according to the circuit. The printed circuit board 10 has at least two conductive layers, and wiring not shown may be formed on the surface or inside the conductive layers. This circuit wiring has a thickness of 1 μm or more and 2000 μm or less. This circuit wiring is formed from a conductive material. Conductive materials include, for example, copper, nickel, gold, aluminum, silver, or tin, or alloys thereof. The materials that make up the printed circuit board 10 include, for example, glass fiber reinforced epoxy resin, phenolic resin, polyphenylene sulfide (PPS), or polyether ether ketone (PEEK). The printed circuit board 10 may be a general-purpose printed circuit board. The printed circuit board 10 may be made of ceramics such as aluminum oxide, aluminum nitride, or silicon carbide.

[0030] The SG pattern 14 is a circuit wiring that serves as the reference GND on the input terminal side of the control element 2 and the insulating element 4 formed on the printed circuit board 10. The SG pattern 14 serves as the reference GND for the entire control circuit, including the control element 2 of the input unit 1. Rather than a line pattern, the SG pattern 14 is preferably a solid GND (GND mat) to increase its area. More preferably, the SG pattern 14 may be composed of a solid GND of multiple conductor layers connected bare. The SG pattern 14 may or may not be connected to the FG (Frame Ground) pattern 16, which will be described later, by an FG-SG capacitor 84, but it is preferable that it be connected to the FG pattern 16 by the FG-SG capacitor 84.

[0031] The circuit wiring of the IOGND pattern 15 is also called the common and is physically separated from the circuit wiring of the SG pattern 14. The output terminal side of the insulating element 4 formed on the printed circuit board 10 is located on the IOGND pattern 15. The IOGND pattern 15 is the circuit wiring that serves as the reference GND for the parallel serial conversion IC 5 and the input circuit 7.

[0032] The FG pattern 16 is a circuit wiring formed on the printed circuit board 10. The potential of the FG pattern 16 is ideally the same as the FG potential of the control system 100. The FG pattern 16 is connected to a conductor with an FG potential outside the printed circuit board 10 using the FG fitting 83 shown in Figure 3, or a cable (not shown). The printed circuit board 10 does not necessarily have to include the FG pattern 16, but it is desirable to have it. The impedance of the FG pattern 16 is the smallest relative to ground compared to the SG pattern 14 and the IOGND pattern 15. The impedance of the IOGND pattern 15 is the largest relative to ground. In other words, the impedance values ​​relative to ground, in ascending order, are FG pattern 16, SG pattern 14, and IOGND pattern 15. In the industrial environment where the control system 100 is located, common-mode noise is dominant among the noise components superimposed on the input unit 1 from the outside. The FG pattern 16 allows common-mode noise to be fed back to ground via the FG pattern 16. The FG pattern 16 and the FG-SG capacitor 84 reduce the impedance of the SG pattern 14 and the IOGND pattern 15.

[0033] The backplane connector 80 mechanically and electrically connects the input unit 1 and the backplane 101 shown in Figure 1. The backplane connector 80 may be a surface-mount component or an through-hole component. The pins of the backplane connector 80 are assigned, for example, power, signal generator (SG), control signals such as a system reset signal, and communication signals for the backplane 101.

[0034] The control power supply circuit 81 converts the power supplied from the backplane 101 into the power supply voltage for the control element 2 and the power supply voltage for the isolation element 4. For example, the control power supply circuit 81 generates DC 3.3V from DC 5V. The control power supply circuit 81 may be a switching power supply or a linear power supply. There is not necessarily only one control power supply circuit 81, but there may be multiple circuits.

[0035] The oscillator circuit 82 generates a reference clock for the control element 2. In Figures 2 and 3, the oscillator circuit 82 is located outside the control element 2, but the oscillator circuit 82 may be an on-chip oscillator or the like built into the control element 2. The serial communication unit 3a of the control element 2 generates the necessary clock using the reference clock generated by the oscillator circuit 82. Since some control elements 2 require multiple clocks, the oscillator circuit 82 does not necessarily have to be just one; there may be multiple. In addition, there may be oscillator circuits for other circuits that are not shown.

[0036] The FG fitting 83 is a conductive structure for connecting the FG pattern 16 on the printed circuit board 10 of the input unit 1 with a conductor of FG potential (not shown) on the backplane 101. The FG fitting 83 does not necessarily need to be rigid; it may be a gasket-like structure with conductive cloth wrapped around a sponge, as long as it can conduct electricity with the FG potential outside the printed circuit board 10. It is desirable for the input unit 1 to be equipped with the FG fitting 83, but it is not required to be equipped with the FG fitting 83. In this case, common-mode noise entering from the external wiring interface 91 will be returned to ground via the backplane connector 80 rather than the FG fitting 83, and if the power supply and signal lines transmitting through the backplane connector 80 are susceptible to noise, this may cause the input unit 1 to malfunction.

[0037] The external wiring interface 91 is an interface with the external wiring for I / O and the external power wiring that connects to external equipment. The external wiring interface 91 is composed of, for example, a screw terminal block, a spring clamp terminal block, or a connector. Depending on the number of input points in the input unit 1, the external wiring interface 91 mediates input signals of, for example, 8, 16, 32, or 64 points. In an example of the operating environment of the control system 100, such as a factory or plant, or in noise immunity tests such as EFT / B (Electrical Fast Transient / Burst) tests and radiated interference tests among EMC (Electromagnetic Compatibility) tests, noise may be superimposed on the external wiring for I / O and the external power wiring, and the noise may propagate into the input unit 1 via the external wiring interface 91, potentially affecting the SPI signals transmitted and received between the parallel serial conversion IC 5 and the control element 2.

[0038] The IOGND pattern 15 and the SG pattern 14 are separated. An insulating element 4 and an SG-IOGND capacitor 6a are connected between these different circuit wirings. The insulating element 4 transmits and receives SPI signals between the control element 2 and the parallel serial conversion IC 5. Of the two electrodes of the SG-IOGND capacitor 6a, the first electrode EA1 is connected to the SG pattern 14, and the second electrode EA2 is connected to the IOGND pattern 15.

[0039] <Effects> In this embodiment, the SG-IOGND capacitor 6a, which has been intentionally added, is used to conduct current applied by external noise, preventing it from concentrating on the insulating element 4 that transmits the serial communication signal, thereby bypassing the noise conducted through the insulating element 4. By lowering the impedance between the insulating elements 4 with the added SG-IOGND capacitor 6a, the voltage induced in the serial communication signal transmitted through the insulating element 4 is reduced. As a result, noise is less likely to be superimposed on the serial communication signal line, and malfunctions of the PLC can be suppressed.

[0040] More specifically, an SG - IOGND capacitor 6a is arranged between the IOGND pattern 15 and the SG pattern 14 separated by the insulating element 4. Due to the capacitance component of the SG - IOGND capacitor 6a, while ensuring the same performance as the case where there is no SG - IOGND capacitor 6a for the impedance at low frequencies between the IOGND pattern 15 and the SG pattern 14, the impedance becomes smaller in the MHz band where the input unit 1 is likely to malfunction.

[0041] That is, between the IOGND pattern 15 and the SG pattern 14, noise in the MHz band that is likely to cause malfunction can be reduced. Specifically, when external noise is superimposed on the input unit 1 via the external wiring interface 91, the noise induced between the four input terminals IN1 to IN4 and the four output terminals OUT1 to OUT4 of the insulating element 4 becomes smaller. As a result, the noise intensity superimposed on the SPI signal transmitted and received in the serial communication unit 3a is reduced. Thereby, the malfunction of the input unit that employs serial communication for signal transmission between the control element 2 and the parallel - serial conversion IC5 can be suppressed.

[0042] Modification Example 1 of Embodiment 1. FIG. 4 is a circuit block diagram of a PLC (input unit 1) according to Modification Example 1 of Embodiment 1.

[0043] In order to ensure the withstand voltage which is a specification of the input unit 1, as shown in FIG. 4, it may be provided with a plurality of SG - IOGND capacitors 6a, 6b connected in series between the SG pattern 14 and the IOGND pattern 15. In this case, the theoretical value of the withstand voltage is proportional to the number of SG - IOGND capacitors. As a specific example, when two DC630V products are connected in series, the withstand voltage can be regarded as DC630V × 2 = DC1260V. Note that the SG - IOGND capacitor 6a may be selected considering derating.

[0044] Modification Example 2 of Embodiment 1. FIG. 5 is a circuit block diagram of a PLC (input unit 1) according to Modification Example 2 of Embodiment 1.

[0045] The difference between the circuit block of FIG. 5 and the circuit block of FIG. 2 is that in the circuit block of FIG. 5, the circuit having the functions of the parallel-serial conversion IC 5 and the isolated power supply 8 is included in the isolation element 4A. The isolation element 4A generates the power supply voltage required in the built-in parallel-serial conversion circuit within the chip. The isolation element 4A directly connects the parallel signal between the input circuit 7 and the isolation element 4, converts the parallel signal into a serial signal inside the isolation element 4, and performs serial communication between the isolation element 4 and the control element 2 while ensuring electrical isolation.

[0046] Embodiment 2. Next, referring to FIGS. 6 to 8, the input unit 1 according to Embodiment 2 will be described. Embodiment 2 has the same configuration, operation, and effect as Embodiment 1 described above unless otherwise specified. Therefore, the same components as those in Embodiment 1 described above are denoted by the same reference numerals, and the description will not be repeated.

[0047] The input unit 1 according to Embodiment 2 basically has the same configuration as the input unit 1 according to Embodiment 1.

[0048] FIG. 6 is an arrangement diagram of the SG - IOGND capacitor 6a in the input unit 1 according to Embodiment 2. The input unit 1 according to Embodiment 2 has the SG - IOGND capacitor 6a disposed between the IOGND pattern 15 and the SG pattern 14 on the printed circuit board 10, at a position closer to the FG pattern 16 than the isolation element 4. That is, the distance between the SG - IOGND capacitor 6a and the FG pattern 16 is shorter than the distance between the isolation element 4 and the FG pattern 16.

[0049] Figure 7 shows the path of noise current when the SG-IOGND capacitor 6a is placed between the IOGND pattern 15 and the SG pattern 14 on the printed circuit board 10, and closer to the FG pattern 16 than the insulating element 4. Figure 8 shows the path of noise current when the SG-IOGND capacitor 6a is placed between the IOGND pattern 15 and the SG pattern 14 on the printed circuit board 10, and directly below the insulating element 4 on the opposite side. In Figure 8, the SG-IOGND capacitor 6a is placed at a position away from the FG pattern 16. In Figures 7 and 8, thick arrows represent the paths of noise current. Relatively thin arrows near the isolated power supply 8 represent noise current propagating through the winding capacitance of the transformer inside the isolated power supply 8.

[0050] <Effects> Referring to Figures 6 to 9, the SG-IOGND capacitor 6a acts as a bypass path for noise current, and the distribution of noise current differs depending on the placement of the SG-IOGND capacitor 6a. If a highly sensitive circuit susceptible to noise is located in a region with strong noise current, it can cause phenomena other than SPI communication, potentially leading to malfunction of the input unit 1. By placing the SG-IOGND capacitor 6a between the IOGND pattern 15 and the SG pattern 14 on the printed circuit board 10, and close to the FG pattern 16, the region with strong noise current can be concentrated at the edge of the printed circuit board 10, reducing the risk of noise current adversely affecting surrounding circuits. In other words, in this embodiment, in addition to the effects of Embodiment 1, the region through which noise current propagates can be minimized. As a result, noise current is less likely to interfere with surrounding circuits, and malfunctions of the input unit can be suppressed.

[0051] Embodiment 3. Next, the input unit 1 according to Embodiment 3 will be described. Embodiment 3 has the same configuration, operation, and effects as Embodiment 1 unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions will not be repeated.

[0052] The input unit 1 according to Embodiment 3 basically has the same configuration as the input unit 1 according to Embodiment 1. The difference between Embodiment 3 and Embodiment 1 is that in Embodiment 3, the capacitance value of the SG-IOGND capacitor 6a is set to 470 pF or more. As described in Embodiment 1, a larger capacitance value for the SG-IOGND capacitor 6a is desirable, but it is necessary to select a capacitor with a voltage rating equal to or greater than that specified in the product specifications of the input unit 1. On the other hand, for the SG-IOGND capacitor 6a itself, the higher the voltage rating of the element, the smaller the capacitance value. Elements with lower voltage ratings have a wider range of capacitance values, and there is a trade-off relationship between voltage rating and capacitance value. Therefore, there is an upper limit to the capacitance value of the SG-IOGND capacitor 6a that can be selected. As the capacitance value of the SG-IOGND capacitor 6a increases, the impedance also decreases at low frequencies, making it easier for low-frequency noise output by the inverter to propagate to the SG pattern side of the input unit 1. Considering that these noises have a large amount of energy and could lead to equipment failure, lowering the low-frequency impedance would likely have adverse effects on signals other than the SPI signal. In other words, considering the product's voltage tolerance and the ability to block low-frequency noise generated in the operating environment in which input unit 1 is used, an upper limit of 10,000 pF for the capacitance value of SG-IOGND capacitor 6a is appropriate.

[0053] Figure 9 is a graph showing the relative noise intensity in the SPI signal between the input and output terminals of the isolation element 4 when the capacitance value of the SG-IOGND capacitor 6a is changed. It can be seen that the larger the capacitance value of the SG-IOGND capacitor 6a, the smaller the noise voltage induced in the MHz band. Therefore, by setting the constant of the SG-IOGND capacitor 6a to 470 pF or more and 10,000 pF or less, malfunctions related to SPI communication can be prevented, and low-frequency noise can also be blocked, so that malfunctions of the input unit 1 can be comprehensively suppressed in response to noise generated in the operating environment. In addition, since capacitance is provided between the primary and secondary circuits of the isolation power supply 8, the parallel combined capacitance of the capacitance of the SG-IOGND capacitor 6a and the capacitance of the isolation power supply 8 may be 470 pF or more and 10,000 pF or less.

[0054] Embodiment 4. Next, the input unit 1 according to Embodiment 4 will be described with reference to Figures 10 and 11. Embodiment 4 has the same configuration, operation, and effects as Embodiment 1 unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions will not be repeated.

[0055] Figure 10 is a circuit block diagram of the PLC (input unit 1) according to Embodiment 4. The input unit 1 according to Embodiment 4 basically has the same configuration as the input unit 1 according to Embodiment 1. The difference between Embodiment 4 and Embodiment 1 is that Embodiment 4 includes a plurality of SG-IOGND capacitors 6a, 6b connected in parallel between the SG pattern 14 and the IOGND pattern 15.

[0056] The SG-IOGND capacitor 6a is positioned on the same plane as the mounting surface of the control element 2, to the right of the insulating element 4 (i.e., on the side where the external wiring interface is located), and closer to the FG fitting 83 compared to the other SG-IOGND capacitors 6b. The SG-IOGND capacitor 6b is positioned on the same plane as the mounting surface of the control element 2, to the left of the insulating element 4 (i.e., on the side where the backplane connector 80 is located), and further from the FG fitting 83 compared to the other SG-IOGND capacitors 6a. Figure 10 is drawn in a way that distinguishes between the SG-IOGND capacitors 6a and SG-IOGND capacitors 6b when the IOGND pattern 15 and the SG pattern 14 are not arranged in parallel.

[0057] The SG-IOGND capacitors 6a and 6b do not necessarily need to have the same capacitance value; their capacitance values ​​may be changed depending on the frequency components of the external noise. By implementing multiple SG-IOGND capacitors 6a and 6b, the capacitance value between the SG pattern 14 and the IOGND pattern 15 can be increased without reducing the voltage rating compared to implementing only one. As a result, the impedance between the SG pattern 14 and the IOGND pattern 15 can be lowered.

[0058] Figure 11 is a graph showing the relative noise intensity in the SPI signal between the input and output terminals of the insulating element 4 for each number of SG-IOGND capacitors. By increasing the number of SG-IOGND capacitors, the noise intensity is reduced by about 10 dB, except around 20 MHz. In Figure 10, the capacitances of SG-IOGND capacitors 6a and 6b are the same. By using SG-IOGND capacitors 6a and 6b with different capacitances, it is possible to reduce the noise intensity induced in the SPI signal between the input and output terminals of the insulating element over a wide frequency range.

[0059] Embodiment 5. Figure 12 is a circuit block diagram of the PLC (input unit 1) according to Embodiment 5.

[0060] The input unit 1 according to Embodiment 5 basically has the same configuration as the input unit 1 according to Embodiment 1. The difference between Embodiment 5 and Embodiment 1 is that Embodiment 5 includes a plurality of SG-IOGND capacitors 6a, 6b, and 6c connected in parallel between the SG pattern 14 and the IOGND pattern 15.

[0061] SG-IOGND capacitor 6a is positioned on the same plane as the mounting surface of the control element 2, to the right of the insulating element 4, and closer to the FG fitting 83 compared to the other SG-IOGND capacitors 6b and 6c. SG-IOGND capacitor 6b is positioned on the same plane as the mounting surface of the control element 2, to the left of the insulating element 4, and further from the FG fitting 83 compared to the other SG-IOGND capacitors 6a and 6c. SG-IOGND capacitor 6c is positioned on the surface layer of the substrate opposite to the mounting surface of the control element 2, and further from the FG fitting 83.

[0062] The SG-IOGND capacitors 6a, 6b, and 6c do not necessarily need to have the same capacitance value; their capacitance values ​​may be changed depending on the frequency components of the external noise. By implementing multiple SG-IOGND capacitors 6a, 6b, and 6c, the capacitance value between the SG pattern 14 and the IOGND pattern 15 can be increased without reducing the voltage rating compared to implementing only one. As a result, the impedance between the SG pattern 14 and the IOGND pattern 15 can be lowered.

[0063] Embodiment 6. Figure 13 is a circuit block diagram of the PLC (input unit 1) according to Embodiment 6.

[0064] The differences between the PLC of Embodiment 6 and the PLC of Embodiment 1 will now be explained. The control element 2 of the PLC of Embodiment 6 includes a clock generation unit 55, serial communication units 3a and 3b, and a plurality of parallel-to-serial conversion ICs 5a and 5b. In Figure 13, there are two serial communication units 3a and 3b and two parallel-to-serial conversion ICs 5a and 5b, but there may be two or more depending on the specifications of the input unit 1.

[0065] The clock generation unit 55 generates a clock and supplies it to the serial communication units 3a and 3b. This allows the transmission and reception of data by the serial communication units 3a and 3b to be synchronized.

[0066] The terminal CS of the serial communication unit 3a is connected to the input terminal IN1 of the isolation element 4. The output terminal OUT1 of the isolation element 4 is connected to the terminal CS of the parallel serial conversion ICs 5a and 5b. As a result, the chip select signal output from the terminal CS of the serial communication unit 3a is input to the terminal CS of the parallel serial conversion ICs 5a and 5b via the isolation element 4. In other words, the chip select signal is shared by the parallel serial conversion ICs 5a and 5b.

[0067] The terminal CLK of the serial communication unit 3a is connected to the input terminal IN2 of the isolation element 4. The output terminal OUT2 of the isolation element 4 is connected to the terminal CLK of the parallel serial conversion ICs 5a and 5b. As a result, the clock signal output from the terminal CLK of the serial communication unit 3a is input to the terminal CLK of the parallel serial conversion ICs 5a and 5b. In other words, the clock signal is shared by the parallel serial conversion ICs 5a and 5b.

[0068] The terminal MISO of the serial communication unit 3a is connected to the input terminal IN3 of the isolation element 4. The output terminal OUT3 of the isolation element 4 is connected to the terminal MOSI of the parallel serial conversion IC 5a. As a result, the serial data signal output from terminal MOSI of the parallel serial conversion IC 5a is input to the terminal MISO of the serial communication unit 3a of the control element 2 via OUT3 and IN3 of the isolation element 4.

[0069] The terminal MISO of the serial communication unit 3b is connected to the input terminal IN4 of the isolation element 4. The output terminal OUT4 of the isolation element 4 is connected to the terminal MOSI of the parallel serial conversion IC 5b. As a result, the serial data signal output from the terminal MOSI of the parallel serial conversion IC 5b is input to the terminal MISO of the serial communication unit 3b of the control element 2 via the OUT4 and IN4 of the isolation element 4.

[0070] According to this embodiment, the terminals CS and CLK of one serial communication unit 3a, 3b are connected to the terminals CS and CLK of all parallel serial conversion ICs 5a to 5b via the insulating element 4. Therefore, the number of signal lines required to send and receive data between the serial communication unit and the parallel serial conversion IC is 2 × (N + 1) lines when all SPI communication CS, CLK, MISO, and MOSI are connected, and the number of parallel serial conversion ICs is N (N ≥ 2). As shown in Figure 13, when MOSI related to data output is not used in the serial communication unit 3b, the number of signal lines required to send and receive data between the serial communication unit and the parallel serial conversion IC is (2 + N) lines, and the number of parallel serial conversion ICs is N (N ≥ 2). In the example shown in Figure 13, only four signal lines are needed, and only one insulating element 4 is required. According to this embodiment, the number of insulating elements can be reduced. As a result, the cost and mounting area required for insulating elements can be reduced.

[0071] <Effects> According to this embodiment, the same effects as in the first embodiment can be obtained. Furthermore, according to this embodiment, even if the number of input points in the input unit 1 increases, and consequently the number of parallel serial conversion ICs 5 increases, the number of signal lines for communicating the clock signal and select signal does not increase, and the increase in the number of signal lines between the control element and the multiple parallel serial conversion ICs 5 can be suppressed.

[0072] Embodiment 7. Figure 14 is a circuit block diagram of the PLC (input unit 1) according to Embodiment 7.

[0073] The differences between the PLC of Embodiment 7 and the PLC of Embodiment 6 will now be explained. The control element 2 of the PLC of Embodiment 7 includes a synchronization unit 65 in addition to the components of the control element 2 of Embodiment 5.

[0074] Each of the serial communication units 3a to 3b operates according to the operating clock generated by the clock generation unit 55. However, before the serial communication units 3a to 3b can perform communication processing, software processing is required. The time required for this software processing is not exactly the same for the serial communication units 3a to 3b, but may differ slightly. The time required for software processing is longer than the time required for hardware processing that operates according to the operating clock. Therefore, the completion times of the software processing in the serial communication units 3a to 3b may differ from each other. If the time difference in the completion times of the software processing in the serial communication units 3a to 3b becomes longer than the period of the operating clock, the timing at which the serial communication units 3a to 3b perform communication processing may be shifted from each other by several clock cycles or more. This phenomenon becomes more pronounced as the operating clock speed increases (i.e., as the communication clock speed increases).

[0075] Therefore, in this embodiment, the synchronization unit 65 puts the serial communication unit that has completed its software processing earlier than the other serial communication units and is ready to execute communication processing into standby mode. Then, the synchronization unit 65 starts all communication processing of serial communication units 3a to 3b in accordance with the serial communication unit that had the latest software processing completion time. This suppresses malfunctions caused by the different times required for software processing in serial communication units 3a to 3b.

[0076] Furthermore, the synchronization unit 65 may execute an interrupt process to interrupt all communication processes of serial communication units 3a to 3b if an interrupt occurs in the control element 2 during communication and the communication process of one serial communication unit is interrupted. After the interrupt process is completed, the synchronization unit 65 should synchronize the start timing of all communication processes of serial communication units 3a to 3b. This suppresses malfunctions caused by discrepancies in the start timing of communication processes of serial communication units 3a to 3b.

[0077] According to this embodiment, the same effects as in the first embodiment can be obtained. Furthermore, according to this embodiment, the cost and mounting area required for the insulating element 4 can be reduced, and malfunctions caused by a timing difference in the start of communication processing of the serial communication units 3a to 3b can be suppressed.

[0078] The embodiments described above can be combined as appropriate. The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present invention is indicated by the claims rather than the foregoing description, and all modifications within the meaning and scope of equivalents of the claims are intended.

[0079] 1 Input unit, 2 Control elements, 3a, 3b Serial communication section, 4 Isolation elements, 5, 5a, 5b Parallel-to-serial conversion IC, 6a, 6b, 6c SG-IOGND capacitors, 7 Input circuit, 8 Isolation power supply, 10 Printed circuit board, 14 SG pattern, 15 IOGND pattern, 16 FG pattern, 41a, 41b, 42a, 42b Circuit section, 55 Clock generation section, 65 Synchronization section, 80 Backplane connector, 81 Control power supply circuit, 82 Oscillator circuit, 83 FG fitting, 84 FG-SG capacitor, 90 I / O power supply circuit, 91 External wiring interface, 100 Control system, 101 Backplane, 102 Control unit, CLK, CS, MISO, MOSI, IN1-IN4, OUT1-OUT4 terminals.

Claims

1. A programmable logic controller comprising: a printed circuit board having a signal ground pattern and an I / O ground pattern; a control element disposed on the signal ground pattern and having at least one serial communication unit; at least one parallel-to-serial conversion IC disposed on the I / O ground pattern for transmitting and receiving serial data to and from the at least one serial communication unit; at least one insulating element disposed on the signal ground pattern and having a plurality of terminals connected to the at least one serial communication unit, and a plurality of terminals disposed on the I / O ground pattern and connected to the at least one parallel-to-serial conversion IC; an input circuit composed of a limiting resistor and a filter and connected to the at least one parallel-to-serial conversion IC; and at least one capacitor having a first electrode connected to the signal ground pattern and a second electrode connected to the I / O ground pattern.

2. The programmable logic controller according to claim 1, wherein the at least one capacitor is positioned between the signal ground pattern and the I / O ground pattern.

3. The programmable logic controller according to claim 2, wherein the at least one capacitor is positioned closer to the frame ground pattern formed on the printed circuit board than the insulating element.

4. The programmable logic controller according to any one of claims 1 to 3, wherein the capacitance of at least one capacitor is 470 pF or more and 10,000 pF or less.

5. The programmable logic controller according to any one of claims 1 to 3, wherein the parallel combined capacitance of at least one capacitor capacitance and the capacitance of the isolated power supply is 470 pF or more and 10,000 pF or less.

6. The programmable logic controller according to claim 1, wherein the at least one capacitor includes a plurality of capacitors connected in series between the signal ground pattern and the I / O ground pattern.

7. The programmable logic controller according to claim 1, wherein the at least one capacitor includes a plurality of capacitors connected in parallel between the signal ground pattern and the I / O ground pattern.

8. The programmable logic controller according to claim 7, wherein the capacitance values ​​of the plurality of capacitors are different from each other.

9. The programmable logic controller comprises first to nth parallel serial conversion ICs, where N is an integer of 2 or more, the control element has first to nth serial communication units, each of the first to nth serial communication units includes a first terminal for receiving serial data signals, the first serial communication unit further includes a second terminal for outputting a clock signal and a third terminal for outputting a select signal, each of the first to nth parallel serial conversion ICs includes a fourth terminal for outputting the serial data signals, a fifth terminal for which the clock signal is input and a sixth terminal for which the select signal is input, the first terminal of each of the first to nth serial communication units is connected to the fourth terminal of each of the first to nth parallel serial conversion ICs via the insulating element, the second terminal of the first serial communication unit is connected to the fifth terminal of each of the first to nth parallel serial conversion ICs via the insulating element, The programmable logic controller according to any one of claims 1 to 8, wherein the third terminal of the first serial communication unit is connected to the sixth terminal of the first to Nth parallel serial conversion ICs via the insulating element.

10. The programmable logic controller according to claim 9, wherein the control element further includes a synchronization unit for synchronizing the communication processing of the first to Nth serial communication units.

11. A programmable logic controller comprising: a printed circuit board having a signal ground pattern and an I / O ground pattern; a control element disposed on the signal ground pattern and comprising at least one serial communication unit; at least one insulating element disposed on the signal ground pattern and having a plurality of terminals connected to the at least one serial communication unit, at least one parallel-to-serial conversion circuit for sending and receiving serial data to and from the serial communication unit; a plurality of terminals disposed on the I / O ground pattern and connected to the at least one parallel-to-serial conversion circuit; an input circuit comprising a limiting resistor and a filter and connected to the at least one parallel-to-serial conversion circuit; and at least one capacitor having a first electrode connected to the signal ground pattern and a second electrode connected to the I / O ground pattern.

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