Method for manufacturing display panel and electronic device including display panel

Abstract

An embodiment of the present invention provides a method for manufacturing a display panel including a pixel area and a connection area surrounding the pixel area, the method including the steps of: forming a lower layer including a substrate; forming a pixel circuit layer including an inorganic insulating layer and a pixel circuit on the lower layer to overlap the pixel area; removing a portion of the inorganic insulating layer overlapping the connection area; forming a light-emitting diode on the pixel circuit layer; forming a connection line overlapping the connection area by using a sacrificial layer; and removing the sacrificial layer.

Description

Method for manufacturing a display panel and an electronic device including a display panel

[0001] The present invention relates to a method for manufacturing a display panel and an electronic device including a display panel.

[0002] In general, as display panels that visually display electrical signals advance, various display panels with excellent characteristics such as thinness, lightness, and low power consumption, as well as electronic devices containing them, are being introduced. For example, research and development is actively underway on display panels of various structures, such as flexible display panels that can be folded or rolled into a roll shape, and stretchable display panels, as well as electronic devices containing them.

[0003] Embodiments of the present invention aim to provide a method for manufacturing a display panel that improves stretchability and realizes an image of excellent quality even when stretched, and an electronic device including the display panel. However, these objectives are exemplary and do not limit the scope of the present invention.

[0004] One embodiment of the present invention provides a method for manufacturing a display panel comprising a pixel region and a connection region surrounding the pixel region, comprising: a step of forming a lower layer including a substrate; a step of forming a pixel circuit layer including an inorganic insulating layer and a pixel circuit so as to overlap with the pixel region on the lower layer; a step of removing a portion of the inorganic insulating layer that overlaps with the connection region; a step of forming a light-emitting diode on the pixel circuit layer; a step of forming a connection wiring that overlaps with the connection region using a sacrificial layer; and a step of removing the sacrificial layer.

[0005] In one embodiment, the sacrificial layer may include a hydrophobic material.

[0006] In one embodiment, the step of removing the sacrificial layer may include removing the sacrificial layer through a cleaning process using water.

[0007] In one embodiment, the step of forming the pixel circuit layer includes the step of forming a signal line electrically connected to the pixel circuit; and the signal line disposed in the pixel area extends to the connection area and can come into direct contact with the connection wiring.

[0008] In one embodiment, the signal line may be a gate line extending along a first direction or a data line extending along a second direction intersecting the first direction.

[0009] In one embodiment, the step of forming a connecting wire overlapping with the connecting area using the sacrificial layer may include: forming the sacrificial layer in which a first opening overlapping with the connecting area is defined; and forming a connecting wire in the area overlapping with the first opening.

[0010] In one embodiment, between the step of forming the light-emitting diode and the step of forming the connecting wire, the method may further include the step of inverting the display panel so that the upper and lower surfaces of the display panel are inverted; and the step of removing the lower layer.

[0011] In one embodiment, the sacrificial layer may be formed on the bottom surface of the pixel circuit layer.

[0012] In one embodiment, between the step of forming the light-emitting diode and the step of inverting the display panel, the method further includes the step of forming an upper elastomer layer to cover the light-emitting diode; and the connecting wiring may be disposed on the bottom surface of the upper elastomer layer.

[0013] In one embodiment, after the step of removing the sacrificial layer, the method may further include the step of forming a lower elastomer layer disposed on the bottom surface of the pixel circuit layer and covering the connection wiring.

[0014] In one embodiment, the steps of forming a connection wiring that overlaps with the connection region using the sacrificial layer and removing the sacrificial layer may be performed between the step of forming the pixel circuit layer and the step of forming the light-emitting diode.

[0015] In one embodiment, the sacrificial layer may be formed on the upper surface of the pixel circuit layer.

[0016] In one embodiment, the step of forming the lower layer includes the step of forming a base layer on the substrate; and the connecting wiring may be disposed within a second opening defined in the base layer and overlapping with the first opening.

[0017] In one embodiment, the second opening may expose the upper surface of the substrate.

[0018] In one embodiment, the method may further include the step of detaching the substrate; and the step of forming a lower elastomer layer on the bottom surface of the base layer and the bottom surface of the connecting wire.

[0019] In one embodiment, the step of forming the lower layer further includes the step of forming a lower elastomer layer interposed between the substrate and the base layer; and the second opening may expose the upper surface of the lower elastomer layer.

[0020] In one embodiment, the method may further include the step of forming an upper elastomer layer to cover the light-emitting diode and the stretched wiring.

[0021] In one embodiment, the steps of forming a connection wiring that overlaps with the connection area using the sacrificial layer and removing the sacrificial layer may be performed between the step of forming the lower layer and the step of forming the pixel circuit layer.

[0022] In one embodiment, the step of forming the lower layer includes the step of forming a lower elastomer layer on the substrate; and the sacrificial layer and the connecting wiring may be formed on the lower elastomer layer.

[0023] In one embodiment, the method may further include the step of forming an upper elastomer layer to cover the light-emitting diode and the stretched wiring.

[0024] In one embodiment, the step of forming a connecting wire that overlaps with the connecting region using the sacrificial layer may include: forming a sacrificial layer on the lower layer; forming a sub-elastomer layer patterned to overlap with the connecting region on the sacrificial layer; and forming the connecting wire on the upper surface of the sub-elastomer layer.

[0025] In one embodiment, the method may further include the step of forming an upper elastomer layer to cover the light-emitting diode and the connecting wiring.

[0026] In one embodiment, after the step of removing the sacrificial layer, the method may further include the step of forming a lower elastomer layer on the bottom surface of the pixel circuit layer and the bottom surface of the sub-elastomer layer.

[0027] Another embodiment of the present invention provides an electronic device comprising a pixel area and a connection area surrounding the pixel area, the device comprising: a display panel; and a lower cover having an opening that forms an exterior and exposes a portion of the display panel on a front surface; wherein the display panel comprises: a lower elastomer layer; a pixel circuit layer disposed on the lower elastomer layer and including an inorganic insulating layer and a pixel circuit so as to overlap with the pixel area; a light-emitting diode disposed on the pixel circuit layer; and a connection wire disposed on the lower elastomer layer and overlapping with the connection area; wherein the pixel circuit layer includes a signal line electrically connected to the pixel circuit, and the signal line disposed in the pixel area extends to the connection area and comes into direct contact with the connection wire.

[0028] In one embodiment, the side and bottom surface of the connecting wire may be surrounded by the lower elastomer layer.

[0029] In one embodiment, the apparatus further comprises a base layer interposed between the lower elastomer layer and the pixel circuit layer, wherein the base layer is disposed on the pixel area and the connecting wire can cover the end of the base layer.

[0030] The above signal line can cover the end of the above connection wiring.

[0031] It further includes a sub-elastomer layer interposed between the lower elastomer layer and the connecting wire; wherein the sub-elastomer layer and the connecting wire may be arranged to overlap each other in a planar manner.

[0032] The planar area of ​​the above sub-elastomer layer and the planar area of ​​the above connecting wire may be the same.

[0033] It may further include an upper elastomer layer covering the light-emitting diode and the connecting wiring.

[0034] According to some embodiments of the present invention, a method for manufacturing a display panel that improves elasticity and realizes an image of excellent quality, and a method for manufacturing an electronic device including the display panel, may be provided. The aforementioned effects are exemplary, and the effects of the present invention are not limited to those described above.

[0035] FIG. 1a is a schematic perspective view of an electronic device according to one embodiment of the present invention.

[0036] FIG. 1b is a block diagram schematically illustrating an electronic device according to one embodiment of the present invention.

[0037] FIG. 2 is a schematic perspective view of a display panel according to one embodiment of the present invention.

[0038] FIGS. 3A and FIGS. 3B are perspective views showing the display panel of FIG. 2 extended in the first direction, respectively.

[0039] FIG. 3c is a perspective view showing the display panel of FIG. 2 extended in a second direction.

[0040] FIG. 3d is a perspective view showing the display panel of FIG. 2 extended in the first direction and the second direction.

[0041] FIG. 3e is a perspective view showing the display panel of FIG. 2 extended in a third direction.

[0042] FIG. 4 is a schematic plan view of a display panel according to one embodiment of the present invention.

[0043] FIG. 5 is a plan view schematically showing the arrangement of pixels of a display panel according to one embodiment of the present invention.

[0044] FIG. 6 is a cross-sectional view schematically showing a part of a display panel according to one embodiment of the present invention.

[0045] FIGS. 7a to 7c are each equivalent circuit diagrams of pixels of a display panel according to an embodiment of the present invention.

[0046] FIGS. 8a to 8d are cross-sectional views schematically showing a light-emitting diode of a display panel according to one embodiment of the present invention.

[0047] FIG. 9 is a schematic plan view showing a part of a display panel according to one embodiment of the present invention.

[0048] FIG. 10 is a cross-sectional view schematically showing a part of a display panel according to one embodiment of the present invention.

[0049] FIGS. 11a to 11j are cross-sectional views sequentially illustrating the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0050] FIG. 12 is a cross-sectional view schematically showing a part of a display panel according to another embodiment of the present invention.

[0051] FIGS. 13a to 13j are cross-sectional views sequentially illustrating the steps of a method for manufacturing a display panel according to another embodiment of the present invention.

[0052] FIGS. 14a to 14i are cross-sectional views sequentially illustrating the steps of a method for manufacturing a display panel according to another embodiment of the present invention.

[0053] FIG. 15 is a cross-sectional view schematically showing a part of a display panel according to another embodiment of the present invention.

[0054] FIGS. 16a to 16h are cross-sectional views sequentially illustrating the steps of a method for manufacturing a display panel according to another embodiment of the present invention.

[0055] FIG. 17 is a cross-sectional view schematically showing a part of a display panel according to another embodiment of the present invention.

[0056] FIGS. 18a to 18h are cross-sectional views sequentially illustrating the steps of a method for manufacturing a display panel according to another embodiment of the present invention.

[0057] FIGS. 19a to 19g are schematic perspective views illustrating embodiments of an electronic device including a display panel according to one embodiment of the present invention.

[0058] One or more embodiments are described in more detail below with reference to the accompanying drawings. In the drawings, the same reference numerals refer to the same components, and redundant descriptions thereof may be omitted. Accordingly, embodiments of the present invention may take various forms and should not be interpreted as being limited to the contents described in this specification. Therefore, embodiments are described in more detail below with reference to the drawings to explain various aspects of the present invention. The term "and / or" as used in this specification refers to any combination including one or more of the listed items. Furthermore, throughout this specification, when expressions such as "at least one," "one," or "among the selected ones" are used before a list of items, they modify the entire list and not only individual items. For example, expressions such as "at least one of a, b, and c," "at least one of a, b, or c," and "at least one of a, b, and / or c" may mean only a, only b, or only c; they may mean a and b simultaneously, a and c simultaneously, b and c simultaneously, or all of a, b, and c, and may include variations thereof.

[0059] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0060] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0061] In the following embodiments, terms such as "first," "second," etc., are used not in a limiting sense but for the purpose of distinguishing one component from another. Accordingly, the first component may be referred to as the second component without departing from the technical spirit of the present invention. Likewise, the second component may also be referred to as the first component.

[0062] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0063] In the following embodiments, terms such as "comprising" or "having" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added. Furthermore, terms such as "comprising," "include," "have," or "having," or similar expressions, have the meaning of including or supporting "consisting of" and "consisting essentially of." These terms indicate the presence of the specified components, means, steps, actions, elements, and / or parts, and include cases where other components, means, steps, actions, elements, parts, and / or sets thereof are not present or are substantially absent.

[0064] The terms "use," "using," and "used" as used in this specification may be considered synonyms for the terms "utilize," "utilizing," and "utilized," respectively.

[0065] In this specification, when a layer, region, or component is described as being "formed on" another layer, region, or component, it means that it may be formed directly or indirectly thereon. That is, for example, an interlayer, interregion, or intercomponent may exist between them. On the other hand, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element, it means that no intercomponent exists between them. In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are arbitrarily depicted for convenience of explanation, so the present invention is not necessarily limited to what is depicted.

[0066] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0067] In the following embodiments, when a membrane, region, component, etc. is described as being connected, it includes not only cases where the membrane, region, or component is directly connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect connection. For example, when a membrane, region, component, etc. is described as being electrically connected in this specification, it includes not only cases where the membrane, region, or component, etc. are directly electrically connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect electrical connection.

[0068] Spatial relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” “bottom,” and “top” may be expressions of convenience used to describe the relationship between one element or feature and other element(s) or feature(s) as illustrated in the drawings. These spatial relative terms should be understood to include not only the directions illustrated in the drawings but also all the various directions in which the device is used or operated. For example, if the device illustrated in the drawings is inverted, an element described as being located “below” or “beneath” another element or feature may then be located “above” or “over.” Thus, the term “below” may include both the up and down directions. Additionally, the device may be rotated 90 degrees or oriented in other directions, and accordingly, the spatial relative terms used in this specification should be interpreted in accordance with such various directions.

[0069] As used herein, terms such as “substantially,” “about,” and similar terms are not expressions indicating a degree but expressions indicating an approximation, intended to account for the inherent deviation of a measured or calculated value that is recognizable by a person skilled in the art. As used herein, “about” or “approximately” includes the specified value and means within an acceptable range of deviation that a person skilled in the art can determine by considering the relevant measurement and the error associated with the measurement value (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the specified value, or within ±30%, ±20%, ±10%, or ±5% of the specified value.

[0070] All numerical ranges described herein are intended to include all sub-ranges of the same numerical precision that are included within the specified range. For example, the range “1.0 to 10.0” includes all sub-ranges between (and including) a minimum value of 1.0 and a maximum value of 10.0, that is, all ranges where the minimum value is 1.0 or greater and the maximum value is 10.0 or less, such as, for example, a range like “2.4 to 7.6”. Furthermore, all maximum numerical limitations described herein are intended to include all smaller numerical limitations that are included therein, and all minimum numerical limitations are intended to include all larger numerical limitations that are included therein. Accordingly, the applicant reserves the right to modify this specification (including the claims) to explicitly describe all sub-ranges that are included within the ranges explicitly described herein.

[0071] The electronic devices and / or other related devices or components according to the embodiments of the present invention described herein may be implemented using suitable hardware, firmware (e.g., Application-Specific Integrated Circuit (ASIC)), software, or a combination of software, firmware, and hardware. For example, various components of the device may be formed on a single integrated circuit (IC) chip or on multiple individual IC chips. Additionally, various components of the device may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or on a single substrate. Furthermore, various components of the device may be implemented as processes or threads executed on one or more processors, and may interact with other system components to execute computer program instructions within one or more computing devices and perform the various functions described herein. Computer program instructions may be stored in memory within a computing device using standard memory devices, such as Random Access Memory (RAM), for example. Additionally, computer program instructions may be stored on non-transitory computer-readable media, such as CD-ROMs and flash drives. Furthermore, a person skilled in the art will understand that the functions of various computing devices may be combined or integrated into a single computing device, or conversely, that the functions of a specific computing device may be distributed across one or more other computing devices. Such implementations do not depart from the scope of the embodiments of the present invention.

[0072] A person skilled in the art will understand, considering the overall description in this specification, that the respective suitable features according to the various embodiments of the invention may be combined or interconnected, either partially or wholly, and may be technically linked to operate in various suitable ways. Furthermore, unless otherwise explicitly or implicitly stated, each embodiment may be implemented in a suitable manner, either independently or in a combined form.

[0073] FIG. 1a is a schematic perspective view of an electronic device (1) according to one embodiment of the present invention, and FIG. 1b is a schematic block diagram of an electronic device (1) according to one embodiment of the present invention.

[0074] Referring to FIGS. 1a and 1b, an electronic device (1) having a display panel (10) according to one embodiment of the present invention is a device for displaying video or still images, and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs). An electronic device (1) according to one embodiment can be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). An electronic device (1) according to one embodiment can be used as a center information display (CID) placed on the center fascia or dashboard of a vehicle, a room mirror display replacing the side mirror of a vehicle, and a display placed on the back of the front seat for entertainment for the rear seat of a vehicle.

[0075] FIG. 1a illustrates an electronic device (1) according to one embodiment being used as a smartphone. The electronic device (1) may include a display panel (10) and a lower cover (90) disposed below the display panel (10). The electronic device (1) may include a cover window covering the upper surface of the display panel (10).

[0076] The lower cover (90) forms the exterior of the electronic device (10) and may have an opening that exposes a portion of the display panel (10) on the front surface. The lower cover (90) may be assembled with the display panel (10) in a shape in which the side corresponding to the display panel (10) is open (e.g., having an opening). The lower cover (90) forms the exterior of the lower surface of the electronic device (1), and a display circuit board, components, a main circuit board, a battery, a driver, etc. may be placed between the display panel (10) and the lower cover (90). The lower cover (90) may include plastic, metal, or both plastic and metal.

[0077] The electronic device (1) may include a main processor (510), a wireless communication unit (520), an input unit (530), a sensor unit (540), an output unit (550), an interface unit (560), a memory (570), and / or a power supply unit (580).

[0078] The main processor (510) can control all functions of the electronic device (1). For example, the main processor (510) can output digital video data to a data driver through a display circuit board so that the display panel (10) displays an image. The main processor (510) can receive detection data from a touch sensor driver. The main processor (510) can determine whether the user touches based on the detection data and execute an action corresponding to the user's direct touch or proximity touch. The main processor (510) may be an application processor, a central processing unit, or a system chip made of an integrated circuit.

[0079] The camera device (531) processes image frames, such as still images or video, obtained by an image sensor in camera mode and outputs them to the main processor (510). The camera device (531) may include at least one of a camera sensor (e.g., CCD, CMOS, etc.), a photo sensor (or image sensor), and a laser sensor. The camera device (531) may be connected to an image sensor and process an image input to the image sensor.

[0080] The wireless communication unit (520) may include at least one of a broadcast reception module (521), a mobile communication module (522), a wireless internet module (523), a short-range communication module (524), and a location information module (525).

[0081] The broadcast receiving module (521) receives broadcast signals and / or broadcast-related information from an external broadcast management server through a broadcast channel. The broadcast channel may include a satellite channel and a terrestrial channel.

[0082] A mobile communication module (522) transmits and receives wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network built according to technical standards or communication methods for mobile communication (e.g., GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), CDMA2000 (Code Division Multi Access 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc.). The wireless signals may include various forms of data such as voice call signals, video call call signals, or text / multimedia message transmission and reception.

[0083] The wireless internet module (523) refers to a module for wireless internet access. The wireless internet module (523) may be configured to transmit and receive wireless signals in a communication network according to wireless internet technologies. Examples of wireless internet technologies include WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, DLNA (Digital Living Network Alliance), etc.

[0084] The short-range communication module (524) is for short-range communication and can support short-range communication by using at least one of Bluetooth, RFID (Radio Frequency Identification), Infrared Data Association (IrDA), UWB (Ultra Wideband), ZigBee, NFC (Near Field Communication), Wi-Fi (Wireless-Fidelity), Wi-Fi Direct, and Wireless USB (Wireless Universal Serial Bus) technologies. The short-range communication module (524) can support wireless communication between the electronic device (1) and a wireless communication system, between the electronic device (1) and another electronic device, or between the electronic device (1) and a network where another electronic device (or external server) is located, through a short-range wireless communication network. The short-range wireless communication network may be a short-range wireless personal area network. Other electronic devices may be wearable devices capable of exchanging data with (or interoperable with) the electronic device (1).

[0085] The location information module (525) is a module for obtaining the location (or current location) of the electronic device (1) and may include a GPS (Global Positioning System) module or a WiFi (Wireless Fidelity) module.

[0086] The input unit (530) may include a video input unit such as a camera device (531) for inputting a video signal, an audio input unit such as a microphone (532) for inputting an audio signal, and an input device (533) for receiving information from a user.

[0087] The camera device (531) processes image frames, such as still images or video, obtained by an image sensor in video call mode or shooting mode. The processed image frames may be displayed on a display panel (10) or stored in memory (570).

[0088] The microphone (532) processes an external acoustic signal into electrical voice data. The processed voice data can be utilized in various ways depending on the function (or application) being performed on the electronic device (1).

[0089] The main processor (510) can control the operation of the electronic device (1) to correspond to information input through the input device (533). The input device (533) may include mechanical input means or touch input means, such as a button, dome switch, jog wheel, jog switch, etc., located on the rear or side of the electronic device (1). The touch input means may be formed by a touchscreen layer of the display panel (10).

[0090] The sensor unit (540) may include one or more sensors that sense at least one of information within the electronic device (1), surrounding environment information surrounding the electronic device (1), and user information, and generate a corresponding sensing signal. Based on these sensing signals, the main processor (510) may control the operation or function of the electronic device (1), or perform data processing, functions, or operations related to an application installed on the electronic device (1). The sensor unit (540) may include at least one of a proximity sensor, an illumination sensor, an acceleration sensor, a magnetic sensor, a gravity sensor (G-sensor), a gyroscope sensor, a motion sensor, an RGB sensor, an infrared sensor (IR sensor: infrared sensor), a fingerprint sensor, an ultrasonic sensor, an optical sensor, a battery gauge, an environmental sensor (e.g., a barometer, a hygrometer, a thermometer, a radiation detection sensor, a heat detection sensor, a gas detection sensor, etc.), and a chemical sensor (e.g., an electronic nose, a healthcare sensor, a biometric sensor, etc.).

[0091] The output unit (550) is for generating output related to sight, hearing, or touch, and may include at least one of a display panel (10), an acoustic output unit (551), a haptic module (552), and a light output unit (553).

[0092] The display panel (10) displays (outputs) information processed by the electronic device (1). For example, the display panel (10) can display information on the execution screen of an application running on the electronic device (1), or UI (User Interface) and GUI (Graphic User Interface) information based on the execution screen information. The display panel (10) may include a display layer that displays an image and a touchscreen layer that detects touch input from a user. As a result, the display panel (10) can function as one of the input devices (533) that provide an input interface between the electronic device (1) and the user, and at the same time, as one of the output units (550) that provide an output interface between the electronic device (1) and the user.

[0093] The sound output unit (551) can output sound data received from the wireless communication unit (520) or stored in the memory (570) in signal reception, call mode or recording mode, voice recognition mode, broadcast reception mode, etc. The sound output unit (551) may also output sound signals related to functions performed by the electronic device (1) (e.g., call signal reception sound, message reception sound, etc.). The sound output unit (551) may include a receiver and a speaker. At least one of the receiver and the speaker may be a sound generating device attached to the lower part of the display panel (10) to vibrate the display panel (10) and output sound. The sound generating device may be a piezoelectric element or a piezoelectric actuator that contracts and expands according to an electrical signal, or an exciter that generates magnetic force using a voice coil to vibrate the display panel (10).

[0094] The haptic module (552) generates various tactile effects that the user can feel. The haptic module (552) can provide vibration to the user as a tactile effect (tactile aspect). The haptic module (552) can not only transmit tactile effects through direct contact, but can also be implemented so that the user can feel tactile effects through the sense of touch of fingers or arms.

[0095] The light output unit (553) outputs a signal to indicate the occurrence of an event using light from a light source. Examples of events occurring in the electronic device (1) may include receiving a message, receiving a call signal, a missed call, an alarm, a schedule notification, receiving an email, receiving information through an application, etc. The signal output by the light output unit (553) is implemented as the electronic device (1) emits single-color or multiple-color light from the front or back. The signal output may be terminated when the electronic device (1) detects the user's confirmation of the event.

[0096] The interface section (560) serves as a passage for various types of external devices connected to the electronic device (1). The interface section (560) may include at least one of a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device equipped with an identification module, an audio I / O (Input / Output) port, a video I / O (Input / Output) port, and an earphone port. The electronic device (1) can perform appropriate control related to the connected external device in response to the external device being connected to the interface section (560).

[0097] The memory (570) stores data that supports various functions of the electronic device (1). The memory (570) can store a number of application programs running on the electronic device (1), data for the operation of the electronic device (1), and commands. At least some of the number of applications can be downloaded from an external server via wireless communication. The memory (570) can store applications for the operation of the main processor (510) and can temporarily store input / output data, such as phonebooks, messages, still images, videos, etc. Additionally, the memory (570) can store haptic data for various patterns of vibration provided to the haptic module (552) and acoustic data regarding various sounds provided to the sound output unit (551). The memory (570) may include at least one type of storage medium among flash memory type, hard disk type, SSD type (Solid State Disk type), SSD type (Silicon Disk Drive type), multimedia card micro type, card type memory (e.g., SD or XD memory, etc.), RAM (random access memory; RAM), SRAM (static random access memory), ROM (read-only memory; ROM), EEPROM (electrically erasable programmable read-only memory), PROM (programmable read-only memory), magnetic memory, magnetic disk, and optical disk.

[0098] The power supply unit (580), under the control of the main processor (510), receives external power and internal power and supplies power to each component included in the electronic device (1). The power supply unit (580) may include a battery. Additionally, the power supply unit (580) is provided with a connection port, and the connection port may be configured as an example of an interface unit (560) to which an external charger that supplies power for charging the battery is electrically connected. Alternatively, the power supply unit (580) may be configured to charge the battery wirelessly without using the connection port.

[0099] FIG. 2 is a schematic perspective view of a display panel (10) according to an embodiment of the present invention. FIG. 3a and FIG. 3b are perspective views showing the display panel (10) of FIG. 2 extended in a first direction. FIG. 3c is a perspective view showing the display panel (10) of FIG. 1 extended in a second direction. FIG. 3d is a perspective view showing the display panel (10) of FIG. 1 extended in the first direction and the second direction. FIG. 3e is a perspective view showing the display panel (10) of FIG. 1 extended in a third direction.

[0100] Referring to FIG. 2, the display panel (10) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a plurality of pixels. The display panel (10) may provide a predetermined image using light emitted from a plurality of pixels. The non-display area (NDA) may be placed outside the display area (DA). The non-display area (NDA) may completely surround the display area (DA).

[0101] The display panel (10) can be extended or retracted in various directions. The display panel (10) can be extended in a first direction (e.g., x direction and / or -x direction) by an external force applied by an external object or a user. In one embodiment, as shown in FIGS. 3a and 3b, the display area (DA) and / or non-display area (NDA) of the display panel (10) can be extended in a first direction (e.g., x direction and / or -x direction). For example, as shown in FIG. 3a, it can be extended along the x direction and -x direction, or as shown in FIG. 3b, it can be extended along the x direction while one side of the display panel (10) remains fixed.

[0102] The display panel (10) may be extended in a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a user. In one embodiment, as shown in FIG. 23c, the display area (DA) and / or non-display area (NDA) of the display panel (10) may be extended in the y direction and the -y direction. In another embodiment, one side of the display panel (10) may be fixed while being extended in the y direction or the -y direction.

[0103] The display panel (10) can be extended in multiple directions, such as a first direction (e.g., x direction and / or -x direction) and a second direction (e.g., y direction and / or -y direction) by an external force applied by an external object or a part of a person's body. As shown in FIG. 3d, the display area (DA) and / or non-display area (NDA) of the display panel (10) can be extended in the ±x direction and ±y direction.

[0104] The display panel (10) can be extended in a third direction (e.g., the z direction or the -z direction) by an external force applied by an external object or a part of a person's body. In one embodiment, FIG. 3e illustrates a part of the display panel (10), such as a part of the display area (DA), protruding in the z direction. In another embodiment, a part of the display panel (10), such as a part of the display area (DA), may protrude along the z direction (or be sunken along the -z direction).

[0105] FIGS. 3a through 3e illustrate a display panel (10) extended in a first direction, a second direction, and / or a third direction, but the present invention is not limited thereto. In other embodiments, the display panel (10) may be deformed into various irregular shapes, such as having two or more axes, being bent or twisted.

[0106] FIG. 4 is a schematic plan view of a display panel (10) according to one embodiment of the present invention.

[0107] Referring to FIG. 4, the display panel (10) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). Pixels (P) are arranged in the display area (DA) of the substrate (100). Each pixel (P) can display an image using light emitted from a light-emitting element, such as a light-emitting diode. Each light-emitting diode can emit light, for example, red, green, or blue.

[0108] Each light-emitting diode may be electrically connected to a pixel circuit, and each pixel circuit may include transistors and a storage capacitor. Each pixel circuit may be electrically connected to peripheral circuits and peripheral wiring located in a non-display area (NDA). Peripheral circuits located in the non-display area (NDA) may include a gate driving circuit (GDC) and a terminal section (PAD). Peripheral wiring may include a driving voltage supply line (W11), a common voltage supply line (W13), and a fan-out line (FW).

[0109] The gate driving circuit (GDC) may include drivers for providing an electrical signal to the gate electrode of each of the transistors electrically connected to the light-emitting elements. Specifically, the gate driving circuit (GDC) may apply a scan signal to each of the pixel circuits corresponding to the pixels (P) through the gate line (GL).

[0110] The gate driving circuit (GDC) may include a first gate driving circuit (GDC1) and a second gate driving circuit (GDC2) positioned on both sides with the display area (DA) in between. The second gate driving circuit (GDC2) may be located on the opposite side of the first gate driving circuit (GDC1) with respect to the display area (DA) and may be approximately parallel to the first gate driving circuit (GDC1). Some of the pixel circuits may be electrically connected to the first gate driving circuit (GDC1), and the rest may be electrically connected to the second gate driving circuit (GDC2). In some embodiments, the second gate driving circuit (GDC2) may be omitted.

[0111] A terminal portion (PAD) may be disposed on one side of the substrate (100). The terminal portion (PAD) is exposed without being covered by an insulating layer and is connected to a display circuit board (30). A display driving portion (32) may be disposed on the display circuit board (30). The display driving portion (32) may generate a control signal to be transmitted to a first gate driving circuit (GDC1) and a second gate driving circuit (GDC2). The display driving portion (32) generates a data signal, and the generated data signal may be transmitted to the pixel circuits of pixels (P) through a fan-out wiring (FW) and a data line (DL) connected to the fan-out wiring (FW).

[0112] The display driving unit (32) can supply a first power supply voltage (VDD, FIG. 7a) to the driving voltage supply wire (W11) and a second power supply voltage (VSS, FIG. 7a) to the common voltage supply wire (W13). The first power supply voltage (VDD, FIG. 7a) is applied to the pixel circuit of the pixel (P) through the driving voltage line (PL) connected to the driving voltage supply wire (W11), and the second power supply voltage (VSS, FIG. 7a) is connected to the common voltage supply wire (W13) and can be applied to the opposing electrode of the light-emitting element. The driving voltage supply wire (W11) may be provided extending along the x-direction from the lower side of the display area (DA). The common voltage supply wire (W13) may have a loop shape with one side open, so as to partially surround the display area (DA).

[0113] FIG. 5 is a plan view schematically showing the arrangement of pixels of a display panel according to one embodiment of the present invention.

[0114] Referring to FIG. 5, a plurality of pixels (PXr, PXg, PXb) may be arranged in a display area (DA) of a display panel (10). The display area (DA) may include a pixel area (11) and a connecting area (12) outside the pixel area (11). A red pixel (PXr), a green pixel (PXg), and a blue pixel (PXb) may be arranged in the pixel area (11). The red pixel (PXr), the green pixel (PXg), and the blue pixel (PXb) may constitute a single pixel unit (PU). Pixel units (PUs) may be repeatedly arranged in the display area (DA).

[0115] Signal lines electrically connected to adjacent pixels may be disposed in the connection area (12). Each of the signal lines may include a first part disposed in the pixel area (11) and electrically connected to a pixel circuit, and a second part disposed in the connection area (12) and connected to adjacent pixel circuits. At this time, the first part and the second part may include different materials. Hereinafter, the second part of each of the signal lines may be referred to as a connection wire in the specification.

[0116] The connection area (12) can be stretched relatively more than the pixel area (11) when the display panel (10) is stretched. In one embodiment, the connection wires placed in the connection area (12) may include a material having excellent elasticity and electrical properties simultaneously. For example, the connection wires placed in the connection area (12) may include liquid metal, etc. The pixel areas (11) may be arranged at predetermined intervals along a first direction (e.g., x-direction) and a second direction (e.g., y-direction).

[0117] FIG. 6 is a cross-sectional view schematically showing a part of a display panel according to one embodiment of the present invention.

[0118] Referring to FIG. 6, the display area (DA) may include a pixel area (11) and a connection area (12), and the connection area (12) may be an area connecting pixel areas (11) that are arranged adjacent to each other. The pixel area (11) may include a light-emitting diode (LED) and a circuit for driving the light-emitting diode (LED), such as a pixel circuit (PC). The connection area (12) may include a connection wire (WL) included in a signal line that supplies a signal to each of the pixel circuits (PC).

[0119] A pixel area (11) and a connection area (12) can be formed on the lower elastomer layer (400). In other words, the lower elastomer layer (400) can have a pixel area (11) and a connection area (12) defined respectively. A light-emitting diode (LED) and a pixel circuit (PC) can be placed on the pixel area (11) of the lower elastomer layer (400), and a connection wire (WL) can be placed on the connection area (12) of the lower elastomer layer (400).

[0120] The lower elastomer layer (400) can absorb stress that may occur during the stretching of the display panel (10). The lower elastomer layer (400) may include an elastic polymer. For example, the lower elastomer layer (400) is thermoplastic polyurethane, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, fluoroelastomers, ethylene-vinyl acetate, PDMS (polydimethylsiloxane), It may include at least one of and ecoflex.

[0121] A display layer (200) may be disposed on the pixel area (11) of the lower elastomer layer (400). The display layer (200) may include an inorganic insulating layer (IIL), a pixel circuit (PC), an organic insulating layer (OIL), and a light-emitting diode (LED). A pixel circuit (PC) may be disposed on the lower elastomer layer (400), and an inorganic insulating layer (IIL) may be disposed between the electrodes included in the pixel circuit (PC). An organic insulating layer (OIL) may be disposed on the inorganic insulating layer (IIL) to cover the pixel circuit (PC). A light-emitting diode (LED) may be disposed on the organic insulating layer (OIL) and may be electrically connected to the corresponding pixel circuit (PC). The inorganic insulating layer (IIL) may include an inorganic insulating material such as silicon nitride and / or silicon oxide, and the organic insulating layer (OIL) may include an organic insulating material such as polyimide.

[0122] In one embodiment, a pixel unit (PU) may be disposed on a pixel area (11). As previously described, the pixel unit (PU) may include a red pixel (PXr, FIG. 5), a green pixel (PXg, FIG. 5), and a blue pixel (PXb, FIG. 5). The red pixel (PXr, FIG. 5a) may include a first light-emitting diode (LED1), the green pixel (PXg, FIG. 5a) may include a second light-emitting diode (LED2), and the blue pixel (PXb) may include a third light-emitting diode (LED3). For example, the first light-emitting diode (LED1) may emit red light, the second light-emitting diode (LED2) may emit green light, and the third light-emitting diode (LED3) may emit blue light. In some embodiments, the light-emitting diode (LED) may emit white light.

[0123] A connecting wire (WL) may be disposed on the connecting region (12) of the lower elastomer layer (400). In one embodiment, as shown in FIG. 6, the connecting wire (WL) may be disposed on the lower elastomer layer (400). In another embodiment, the connecting wire (WL) may be disposed within the lower elastomer layer (400). The connecting wire (WL) may comprise a material having both excellent elasticity and electrical properties. In one embodiment, the connecting wires disposed in the connecting region (12) may comprise liquid metal. In another embodiment, the connecting wires may comprise metal nanostructures and elastic polymers. In yet another embodiment, the connecting wires may comprise a conductive composite material containing an elastomer.

[0124] An organic insulating layer (OIL) may be disposed on the connection area (12) of the lower elastomer layer (400). In one embodiment, the organic insulating layer (OIL) disposed in the connection area (12) may be a portion of the organic insulating layer (OIL) disposed in the pixel area (11) that extends to the connection area (12). When the display panel (10) is stretched, the connection area (12) may undergo relatively more deformation compared to the pixel area (11). Accordingly, unlike the pixel area (11), a layer containing an inorganic insulating material that is prone to cracking may not exist in the connection area (12).

[0125] In one embodiment, an upper elastomer layer (300) may be disposed on a light-emitting diode (LED). The upper elastomer layer (300) may be disposed in both the pixel area (11) and the connection area (12). That is, the upper elastomer layer (300) may be disposed to cover the entire display area (DA). The upper elastomer layer (300) may cover the light-emitting diode (LED) and the connection wiring (WL). The upper elastomer layer (300) may absorb stress that may occur when the display panel (10) is stretched. Specifically, the upper elastomer layer (300) may serve to prevent stress that may occur when the display panel (10) is stretched from being transmitted to the light-emitting diode (LED) and the pixel circuit (PC).

[0126] The upper elastomer layer (300) may include an elastic polymer. The upper elastomer layer (300) is made of thermoplastic polyurethane, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, and fluoroelastomers, ethylene-vinyl acetate, and PDMS (polydimethylsiloxane). It may include at least one. In one embodiment, the upper elastomer layer (300) may include the same material as the lower elastomer layer (400). However, it is not limited thereto, and the upper elastomer layer (300) may include a different material from the lower elastomer layer (400).

[0127] FIGS. 7a to 7c are each equivalent circuit diagrams of pixels of a display panel according to an embodiment of the present invention.

[0128] Referring to FIG. 7a, a light-emitting diode (LED) corresponding to a pixel is electrically connected to a pixel circuit (PC), and the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The pixel circuit (PC) may be electrically connected to signal lines and voltage lines. The signal lines may include a gate line (GL, FIG. 4), such as a scan signal line (GWL), and a data line (DL), and the voltage lines may include a first voltage line (VDDL). In this case, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 4), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 4).

[0129] The second transistor (T2) can be electrically connected to the scan signal line (GWL) and the data line (DL). The scan signal line (GWL) can provide a scan signal (GW) to the gate electrode of the second transistor (T2). The second transistor (T2) can transmit a data signal (Dm) input from the data line (DL) to the first transistor (T1) according to the scan signal (GW) input from the scan signal line (GWL).

[0130] The storage capacitor (Cst) is electrically connected to the second transistor (T2) and the first voltage line (VDDL), and can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the first power supply voltage (VDD) supplied by the first voltage line (VDDL).

[0131] The first transistor (T1) is a driving transistor and can control the driving current flowing through the light-emitting diode (LED). The first transistor (T1) can be connected to the first voltage line (VDDL) and the storage capacitor (Cst). The first transistor (T1) can control the driving current flowing from the first voltage line (VDDL) to the light-emitting diode (LED) in correspondence with the voltage value stored in the storage capacitor (Cst). The light-emitting diode (LED) can emit light having a predetermined brightness by the driving current. The first electrode of the light-emitting diode (LED) is electrically connected to the first transistor (T1), and the second electrode can be electrically connected to the second voltage line (VSSL) that supplies the second power supply voltage (VSS).

[0132] FIG. 7a illustrates a pixel circuit (PC) comprising two transistors and one storage capacitor, but in other embodiments, the pixel circuit (PC) may comprise three or more transistors.

[0133] Referring to FIG. 7b, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a storage capacitor (Cst).

[0134] The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines (GL, FIG. 4), such as scan signal lines (GWL), bypass control lines (GBL), initialization control lines (GIL), and light emission control lines (EML), and data lines (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2) and a first voltage line (VDDL). In this case, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 4), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 4).

[0135] The first voltage line (VDDL) can transmit a first power supply voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) that initializes the first electrode of the light-emitting diode (LED) to the pixel circuit (PC).

[0136] The first transistor (T1) can be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The first transistor (T1) acts as a driving transistor and receives a data signal (Dm) according to the switching operation of the second transistor (T2) and supplies a driving current to the light-emitting diode (LED).

[0137] The second transistor (T2) is a data write transistor and is electrically connected to the scan signal line (GWL) and the data line (DL). The second transistor (T2) is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5). The second transistor (T2) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0138] The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The third transistor (T3) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and can diode-connect the first transistor (T1).

[0139] The fourth transistor (T4) is the first initialization transistor and is electrically connected to the initialization control line (GIL) and the first initialization voltage line (VIL1). The fourth transistor (T4) is turned on according to the initialization control signal (GI) received through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1), thereby initializing the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel circuit placed in the previous row of the corresponding pixel circuit (PC).

[0140] The fifth transistor (T5) may be an operation control transistor, and the sixth transistor (T6) may be a light emission control transistor. The fifth transistor (T5) and the sixth transistor (T6) are electrically connected to the light emission control line (EML) and are simultaneously turned on according to the light emission control signal (EM) received through the light emission control line (EML) to form a current path so that a driving current can flow from the first voltage line (VDDL) toward the light-emitting diode (LED).

[0141] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the bypass control line (GBL), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL), and can initialize the first electrode of the light-emitting diode (LED) by transmitting the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting diode (LED).

[0142] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the first voltage line (VDDL). The storage capacitor (Cst) can maintain the voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages of the first voltage line (VDDL) and the gate electrode of the first transistor (T1).

[0143] Referring to FIG. 7c, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a storage capacitor (Cst), and an auxiliary capacitor (Ca).

[0144] The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines (GL, FIG. 4), such as scan signal lines (GWL), bypass control lines (GBL), initialization control lines (GIL), and light emission control lines (EML), and data lines (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), holding voltage lines (VSL), and first voltage lines (VDDL). In this case, the first voltage line (VDDL) may be connected to a driving voltage supply line (W11, FIG. 4), and the second voltage line (VSSL) may be connected to a common voltage supply line (W13, FIG. 4).

[0145] The first voltage line (VDDL) can transmit a first power supply voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) that initializes the first electrode of the light-emitting diode (LED) to the pixel circuit (PC). The holding voltage line (VSL) can provide a holding voltage (VSUS) to the second electrode (CE2) of the second node (N2), for example, the storage capacitor (Cst), during the initialization period and the data writing period.

[0146] The first transistor (T1) can be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8), and can be electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The first transistor (T1) acts as a driving transistor and can receive a data signal (Dm) according to the switching operation of the second transistor (T2) and supply a driving current to the light-emitting diode (LED).

[0147] The second transistor (T2) is electrically connected to the scan signal line (GWL) and the data line (DL), and is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8). The second transistor (T2) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0148] The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The third transistor (T3) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and connects the first transistor (T1) to the diode, thereby compensating for the threshold voltage of the first transistor (T1).

[0149] The fourth transistor (T4) is electrically connected to the initialization control line (GIL) and the first initialization voltage line (VIL1), and is turned on according to the initialization control signal (GI) received through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel circuit placed in the previous row of the corresponding pixel circuit (PC).

[0150] The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are electrically connected to the light emission control line (EML) and are simultaneously turned on according to the light emission control signal (EM) received through the light emission control line (EML) to form a current path so that driving current can flow from the first voltage line (VDDL) toward the light-emitting diode (LED).

[0151] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the bypass control line (GBL), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL) and transmits the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting diode (LED) to initialize the first electrode of the light-emitting diode (LED).

[0152] The ninth transistor (T9) can be electrically connected to the bypass control line (GBL), the second electrode (CE2) of the storage capacitor (Cst), and the holding voltage line (VSL). The ninth transistor (T9) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL), and can transmit a holding voltage (VSUS) to the second node (N2), such as the second electrode (CE2) of the storage capacitor (Cst), during the initialization period and the data writing period.

[0153] The eighth transistor (T8) and the ninth transistor (T9) can each be electrically connected to the second node (N2), for example, the second electrode (CE2) of the storage capacitor (Cst). In some embodiments, the eighth transistor (T8) may be turned off and the ninth transistor (T9) may be turned on during the initialization period and the data writing period, and the eighth transistor (T8) may be turned on and the ninth transistor (T9) may be turned off during the light emission period. Since the second node (N2) receives the holding voltage (VSUS) during the initialization period and the data writing period, the uniformity of the brightness of the display device (e.g., LRU, Long Range Uniformity) due to the voltage drop of the first voltage line (VDDL) can be improved.

[0154] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the eighth transistor (T8) and the ninth transistor (T9).

[0155] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the holding voltage line (VSL), and the first electrode of the light-emitting diode (LED). By storing and maintaining a voltage corresponding to the voltage difference between the first electrode of the light-emitting diode (LED) and the holding voltage line (VSL) while the seventh transistor (T7) and the ninth transistor (T9) are turned on, the auxiliary capacitor (Ca) can prevent the problem of the black brightness rising when the sixth transistor (T6) is turned off.

[0156] FIGS. 8a to 8d are cross-sectional views schematically showing a light-emitting diode of a display panel according to one embodiment of the present invention.

[0157] Referring to FIG. 8a, the light-emitting diode (LED) may include an inorganic light-emitting diode containing an inorganic material. The light-emitting diode (LED) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), a first electrode (235) electrically connected to the first semiconductor layer (231), and a second electrode (238) electrically connected to the second semiconductor layer (232). The first electrode (235) and the second electrode (238) of the light-emitting diode (LED) may each be electrically connected to a first electrode pad (241) and a second electrode pad (243) disposed on the same layer. The second electrode pad (243) may be a part of the second voltage line (VSSL, FIG. 7a) or a conductive layer electrically connected to the second voltage line (VSSL, FIG. 7a).

[0158] In some embodiments, the first semiconductor layer (231) may include a p-type semiconductor layer. The p-type semiconductor layer may be selected from semiconductor materials having the compositional formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with p-type dopants such as Mg, Zn, Ca, Sr, Ba, etc.

[0159] The second semiconductor layer (232) may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be selected from semiconductor materials having the composition formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with n-type dopants such as Si, Ge, and Sn.

[0160] The intermediate layer (233) is a region where electrons and holes recombine, and as electrons and holes recombine, they transition to a lower energy level and can generate light having a corresponding wavelength. The intermediate layer (233) can be formed by including a semiconductor material having, for example, the composition formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multi-quantum well (MQW) structure. Additionally, it may include a quantum wire structure or a quantum dot structure.

[0161] FIG. 8a illustrates that the first semiconductor layer (231) includes a p-type semiconductor layer and the second semiconductor layer (232) includes an n-type semiconductor layer, but the present invention is not limited thereto. In another embodiment, the first semiconductor layer (231) may include an n-type semiconductor layer and the second semiconductor layer (232) may include a p-type semiconductor layer.

[0162] FIG. 8a illustrates that the first electrode pad (241) and the second electrode pad (243) are disposed on the same layer, but the present invention is not limited thereto. Referring to FIG. 8b, the first electrode pad (241) and the second electrode pad (243) may be disposed on different layers. For example, a bank layer (230) having an opening that overlaps with at least a portion of the first electrode pad (241) may be disposed on the first electrode pad (241), and the second electrode pad (243) may be disposed on the upper surface of the bank layer (230). The structure of the light-emitting diode (LED) illustrated in FIG. 7b is the same as previously described with reference to FIG. 7a.

[0163] In another embodiment, as shown in FIG. 8c, the second electrode pad (243) may be positioned on both sides centered on the first electrode pad (241) in a cross-sectional view. The bank layer (230) includes an opening that overlaps at least a portion of the first electrode pad (241), and the second electrode pad (243) may be positioned around the opening of the bank layer (230). In some embodiments, the second electrode pad (243) may have a closed-loop shape that completely surrounds the opening of the bank layer (230) and / or the first electrode pad (241) in a planar view. The structure of the light-emitting diode (LED) shown in FIG. 7c is the same as previously described with reference to FIG. 7a.

[0164] FIGS. 8a to 8c illustrate the first electrode (235) and the second electrode (238) of a light-emitting diode (LED) facing in the same direction (e.g., downward direction, -z direction), but the present invention is not limited thereto. As shown in FIG. 8d, the first electrode (235) and the second electrode (238) of the light-emitting diode (LED) may face in opposite directions.

[0165] The bank layer (230) includes an opening that exposes at least a portion of the first electrode pad (241), and the thickness of the bank layer (230) may be substantially the same as the thickness of the light-emitting diode (LED). The opening of the bank layer (230) may be filled with a filling material (FM), and the second electrode pad (243) may be disposed on the upper surface of the bank layer (230) so as to be electrically connected (e.g., in contact) with the second electrode (238) of the light-emitting diode (LED). The filling material may be an insulating organic material.

[0166] FIG. 9 is a schematic plan view showing a part of a display panel according to one embodiment of the present invention.

[0167] Referring to FIG. 9, the display area (DA, FIG. 4) may include a plurality of pixel areas (11) and a connecting area (12) surrounding each of the plurality of pixel areas (11). The plurality of pixel areas (11) may be repeatedly arranged along a first direction (e.g., x-direction) and a second direction (e.g., y-direction). The distance between adjacent pixel areas (11) in the first direction (e.g., x-direction) may have a constant (or substantially constant) interval, and the distance between adjacent pixel areas (11) in the second direction (e.g., y-direction) may also have a constant (or substantially constant) interval.

[0168] As previously explained with reference to FIG. 5, at least one pixel may be disposed in the pixel area (11). The pixel may be one of a red pixel (PXr, FIG. 5), a green pixel (PXg, FIG. 5), and a blue pixel (PXb, FIG. 5). For example, the pixel area (11) may be provided with a pixel unit (PU) comprising a set of pixels. The pixel unit (PU) may include a red pixel (PXr, FIG. 5), a green pixel (PXg, FIG. 5), and a blue pixel (PXb, FIG. 5).

[0169] Each pixel may include a light-emitting diode (LED, FIG. 6) and a pixel circuit (PC) that drives the light-emitting diode. For example, a red pixel (PXr, FIG. 5) may include a first light-emitting diode (LED1, FIG. 6) and a first pixel circuit (PC1) electrically connected to the first light-emitting diode (LED1, FIG. 6). A green pixel (PXg, FIG. 5) may include a second light-emitting diode (LED2, FIG. 6) and a second pixel circuit (PC2) electrically connected to the second light-emitting diode (LED2, FIG. 6). A blue pixel (PXb, FIG. 5) may include a third light-emitting diode (LED3, FIG. 6) and a third pixel circuit (PC3) electrically connected to the third light-emitting diode (LED3, FIG. 6). In other words, first to third light-emitting diodes (LED1, LED2, LED3, FIG. 6) and first to third pixel circuits (PC1, PC2, PC3) may be arranged in the pixel area (11).

[0170] The pixel area (11) may have a larger modulus (e.g., modulus of elasticity) than the surrounding connection area (12). Accordingly, when the display panel is stretched, the pixel area (11) may undergo less deformation than the connection area (12). (e.g., relatively less deformation may occur.) The pixel area (11) may be referred to as an island area or a low-deformation area. Additionally, the pixel area (11) may be referred to as a light-emitting area as the area where light-emitting elements are arranged.

[0171] The connection area (12) is arranged to surround the pixel area (11) and may have a smaller modulus (e.g., elastic modulus) than the pixel area (11). The connection area (12) may be an area where the main deformation occurs as the display panel expands and contracts. Since the connection area (12) is arranged between a plurality of pixel areas (11), it may be referred to as a connecting part or a bridge part that connects the pixel areas (11). Additionally, the connection area (12) may be referred to as a peripheral deformation part or a high deformation part. The connection area (12) may be referred to as a non-luminous area, as it is an area within the display area where a light-emitting element is not arranged. A connecting wire (WL) that electrically connects adjacent pixel circuits may be arranged in the connection area (12).

[0172] Signal lines connected to each of the first to third pixel circuits (PC1, PC2, PC3) may be arranged in the display area (DA, FIG. 4). The signal lines may include first to third data lines (DL1, DL2, DL3) arranged extending in a second direction (e.g., y-direction), and a gate line (GL) arranged extending in a first direction (e.g., x-direction).

[0173] Specifically, the data line (DL) may include a first part (DLa) placed in the pixel area (11), a bridge line (BL), a second part (DLb), and a first connecting wire (WL1) placed in the connecting area (12). The first part (DLa) of the data line (DL) may be electrically connected to the pixel circuit through a second contact hole (CNT2).

[0174] A bridge line (BL) is placed in an area where a data line (DL) and a gate line (GL) intersect, and may be a pattern that connects a first part (DLa) and a second part (DLb) of the data line (DL). The bridge line (BL) may be placed on a different layer from the first part (DLa) and the second part (DLb). One end of the bridge line (BL) may be connected to the first part (DLa) through the third-1 contact hole (CNT3a), and the other end of the bridge line (BL) may be connected to the second part (DLb) through the third-2 contact hole (CNT3b).

[0175] The first connecting wire (WL1) can connect the second part (DLb) placed in the nth row and the first part (DLa) placed in the n+1th row. In one embodiment, as shown in FIG. 9, the first connecting wire (WL1) can be in direct contact with each of the first part (DLa) and the second part (DLb). However, it is not limited thereto, and if an insulating layer is interposed between the first part (DLa) and the first connecting wire (WL1), the first part (DLa) and the first connecting wire (WL1) may be electrically connected through a contact hole.

[0176] The gate line (GL) may include a first portion (GLa) disposed in the pixel area (11) and a second connecting wire (WL2) disposed in the connecting area (12). The first portion (GLa) of the gate line (GL) may be electrically connected to the pixel circuit through a first contact hole (CNT1).

[0177] The second connecting wire (WL2) can connect the first part (GLa) placed in the m-th column and the first part (GLa) placed in the m+1-th column. In one embodiment, as shown in FIG. 9, the second connecting wire (WL2) can come into direct contact with the first part (GLa). However, it is not limited thereto, and if an insulating layer is interposed between the first part (GLa) and the second connecting wire (WL2), the first part (GLa) and the second connecting wire (WL2) can be electrically connected through a contact hole.

[0178] The connecting wire (WL) placed in the connecting area (12) may have a smaller modulus (e.g., elastic modulus) than parts of the signal lines (DLa, BL, DLb, GLa) placed in the pixel area (11). For example, the connecting wire (WL) may include liquid metal, or may include metal nanostructures and elastic polymers. Alternatively, the connecting wire (WL) may include a conductive composite material including an elastomer. The first part (GLa) of the gate line (GL), the first part (DLa) and second part (DLb) of the data line (DL), and the bridge line (BL) may each include a metal thin film formed as a triple layer of titanium (Ti) / aluminum (Al) / titanium (Ti) structure. As described above, since the connecting wire (WL) contains a material having a smaller modulus than the wires arranged in the pixel area (11), when the display panel (10, FIG. 1) is stretched, high deformation may occur in the connecting wire (WL) and the connecting area (12).

[0179] FIG. 10 is a cross-sectional view schematically showing a part of a display panel according to one embodiment of the present invention.

[0180] Referring to FIG. 10, the display panel (10) may include a lower elastomer layer (400). The lower elastomer layer (400) can absorb stress generated during the stretching of the display panel (10) as previously described. The lower elastomer layer (400) may include the same material as described with reference to FIG. 6.

[0181] A display panel (10) may have a pixel area (11) and a connection area (12) between the pixel areas (11). In each of the pixel areas (11) of the lower elastomer layer (400), a pixel circuit layer (PCL) including a pixel circuit (PC) and a light-emitting diode (LED) disposed on the pixel circuit layer (PCL) may be disposed.

[0182] A buffer layer (111) is disposed on the lower elastomer layer (400), and a pixel circuit (PC) can be disposed on the buffer layer (111). The buffer layer (111) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0183] A thin-film transistor (TFT) may include a semiconductor layer (Act), a gate electrode (GE), a source electrode (SE), and a first drain electrode (DE). FIG. 10 illustrates a top-gate type in which the gate electrode (GE) is placed on the semiconductor layer (Act) with the gate insulating layer (113) in between, but according to another embodiment, the thin-film transistor (TFT) may be a bottom-gate type.

[0184] The semiconductor layer (Act) may include polysilicon. Alternatively, the semiconductor layer (Act) may include amorphous silicon, oxide semiconductor, organic semiconductor, etc. The gate electrode (GE) may include a metal thin film composed of a low-resistance metal material. The gate electrode (GE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. For example, the gate electrode (GE) may be provided as a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0185] The gate insulating layer (113) between the semiconductor layer (Act) and the gate electrode (GE) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide. The gate insulating layer (113) may be a single layer or a multilayer containing the aforementioned materials.

[0186] The source electrode (SE) and the drain electrode (DE) may be located on the same layer, for example, the second interlayer insulating layer (117), and may contain the same material. Each of the source electrode (SE) and the drain electrode (DE) may contain a metal thin film composed of a low-resistance metal material. The source electrode (SE) and the drain electrode (DE) may contain a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer containing the above materials. For example, each of the source electrode (SE) and the drain electrode (DE) may be provided with a metal thin film formed as a triple layer of titanium (Ti) / aluminum (Al) / titanium (Ti) structure, similar to the gate electrode (GE). The second interlayer insulating layer (117) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or a multilayer containing the aforementioned material.

[0187] A storage capacitor (Cst) may include a first electrode (CE1) and a second electrode (CE2) that overlap with a first interlayer insulating layer (115) in between. The storage capacitor (Cst) may overlap with a thin-film transistor (TFT). In this regard, FIG. 12 illustrates that the gate electrode (GE) of the thin-film transistor (TFT) is the first electrode (CE1) of the storage capacitor (Cst). In another embodiment, the storage capacitor (Cst) may not overlap with the thin-film transistor (TFT). The storage capacitor (Cst) may be covered by a second interlayer insulating layer (117).

[0188] The first interlayer insulating layer (115) may be disposed between the gate insulating layer (113) and the second interlayer insulating layer (117). The first interlayer insulating layer (115) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or a multilayer containing the aforementioned material.

[0189] The second electrode (CE2) of the storage capacitor (Cst) may include a conductive material and may be formed as a multilayer or single layer. The second electrode (CE2) may include a metal thin film composed of a low-resistance metal material. The second electrode (CE2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. For example, the second electrode (CE2) may be provided as a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0190] The first organic insulating layer (121) may be disposed on the second interlayer insulating layer (117), and the second organic insulating layer (123) may be disposed on the first organic insulating layer (121). Additionally, in the outer region of the pixel region (11) adjacent to the connection region (12), a sub-organic insulating layer (119) may be interposed between the second interlayer insulating layer (117) and the first organic insulating layer (121). The sub-organic insulating layer (119), the first organic insulating layer (121), and the second organic insulating layer (123) may each include an organic insulating material such as polyimide.

[0191] An inorganic insulating layer (IIL, FIG. 6) comprising a buffer layer (111), a gate insulating layer (113), a first interlayer insulating layer (115), and a second interlayer insulating layer (117) may be disposed only in the pixel area (11) and not in the connection area (12). In other words, some areas of the inorganic insulating layer (IIL, FIG. 6) that overlap with the connection area (12) may be removed. At this time, a sub-organic insulating layer (119) may fill in the step difference (e.g., a stepped or uneven structure) that may occur between the pixel area (11) and the connection area (12). The second organic insulating layer (123) may extend from the pixel area (11) and may also be partially disposed in the connection area (12).

[0192] The gate line (GL) and the data line (DL) may be disposed on the second interlayer insulating layer (117), and the first organic insulating layer (121) may be disposed on the gate line (GL) and the data line (DL). In one embodiment, a portion of the data line (DL) disposed in the pixel area (11) may extend to the connection area (12) and come into direct contact with the connection wire (WL). A portion of the data line (DL) extending to the connection area (12) may be disposed on the sub-organic insulating layer (119). In one embodiment, the end of the portion of the data line (DL) extended to the connection area (12) may come into direct contact with the connection wire (WL).

[0193] A connecting electrode (CM) and a second voltage line (VSSL) may be disposed on the first organic insulating layer (121). The connecting electrode (CM) can electrically connect a thin-film transistor (TFT) and a light-emitting element (LED). The second voltage line (VSSL) can be connected to a common voltage supply line (W13, FIG. 4) to transmit a second power supply voltage (VSS, FIG. 7a) to the second electrode (238). Each of the connecting electrode (CM) and the second voltage line (VSSL) may include a metal thin film composed of a low-resistance metal material. Each of the connecting electrode (CM) and the second voltage line (VSSL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer containing the above materials. For example, the connecting electrode (CM) and the second voltage line (VSSL) may each be provided with a metal thin film formed of a triple layer of titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0194] The first electrode pad (241) and the second electrode pad (243) may be disposed on the second organic insulating layer (123). The first electrode pad (241) may be electrically connected to a thin-film transistor (TFT) through a connecting electrode (CM) between the first organic insulating layer (121) and the second organic insulating layer (123). The light-emitting element (LED) on the first electrode pad (241) and the second electrode pad (243) may be the same as the inorganic light-emitting diode described earlier with reference to FIG. 8b. Each light-emitting element (LED), which is an inorganic light-emitting diode, may include a first semiconductor layer (231, FIG. 8b), a second semiconductor layer (232, FIG. 8b), an intermediate layer (233, FIG. 8b) between the first semiconductor layer (231, FIG. 8b) and the second semiconductor layer (232, FIG. 8b), a first electrode (235, FIG. 8b) electrically connected to the first semiconductor layer (231, FIG. 8b), and a second electrode (238, FIG. 8b) electrically connected to the second semiconductor layer (232, FIG. 8b). The light-emitting element (LED) may be covered by a protective layer (240). The protective layer (240) may include an organic insulating material such as polyimide.

[0195] A connecting wire (WL) may be placed in the connecting area (12) of the display panel (10). In one embodiment, the connecting wire (WL) may be placed on the bottom surface of the display layer (200, FIG. 6), as shown in FIG. 10. In other words, the side and bottom surface of the connecting wire (WL) may be surrounded by a lower elastomer layer (400). As the connecting wire (WL) has a structure embedded in the lower elastomer layer (400), the lower elastomer layer (400) can absorb the stress that may be concentrated on the connecting wire (WL) when the display panel (10) is stretched.

[0196] Additionally, since the connection area (12) of the display panel (10) may undergo significant deformation, an inorganic insulating layer may not be disposed on the connection area (12) of the lower elastomer layer (400), and organic insulating layers may be disposed thereon. For example, a sub-organic insulating layer (119), a first organic insulating layer (121), and a second organic insulating layer (123) disposed in the pixel area (11) may be extended and disposed on the connection area (12).

[0197] An upper elastomer layer (300) may be disposed on the light-emitting element (LED) and the connecting wire (WL). The upper elastomer layer (300) covers the light-emitting element (LED) and the connecting wire (WL) to absorb stress that may be transmitted to the light-emitting element (LED) and the connecting wire (WL). In one embodiment, the upper elastomer layer (300) may contain the same material as the lower elastomer layer (400). However, it is not limited thereto, and in another embodiment, the upper elastomer layer (300) may contain a different material from the lower elastomer layer (400).

[0198] FIGS. 11a to 11j are cross-sectional views sequentially illustrating the steps of a method for manufacturing a display panel according to an embodiment of the present invention. In describing the method for manufacturing a display panel according to an embodiment, the description of the display panel described with reference to FIGS. 9 and 10 may be applied to the display panel. Identical reference numerals among the components of FIGS. 11a to 11j may be replaced with those previously described with reference to FIGS. 9 and 10.

[0199] First, referring to FIG. 11a, a lower layer (LL) may be formed to form a display panel (10, FIG. 10). The lower layer (LL) may be a layer temporarily placed to form a stretchable display panel (10, FIG. 10). That is, the lower layer (LL) is placed to support the display layer (200, FIG. 6) while forming the display layer (200, FIG. 6), but may be removed after the display layer (200, FIG. 6) is formed.

[0200] In one embodiment, the lower layer (LL) may include a substrate (100) and a base layer (110) disposed on the substrate (100). The substrate (100) may be a rigid substrate. For example, the substrate (100) may be a transparent glass substrate with SiO2 as the main component, or a substrate comprising a polymer resin material such as reinforced plastic. The base layer (110) may include a polymer resin. For example, the base layer (100) may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate, etc. In one embodiment, the thickness of the base layer (110) may be greater than the thickness of the substrate (100).

[0201] On the lower layer (LL), an inorganic insulating layer (IIL) and a part of a thin-film transistor (TFT, FIG. 10) may be formed. For example, on the lower layer (LL), a buffer layer (111), an active layer (Act), a gate insulating layer (113), a gate electrode (GE), a first interlayer insulating layer (115), a second electrode (CE2), and a second interlayer insulating layer (117) may be sequentially stacked.

[0202] However, the inorganic insulating layer (IIL) may be placed only in the pixel area (11) and not in the connection area (12). For example, a portion of the inorganic insulating layer (IIL) that overlaps with the connection area (12) may be removed through an etching process.

[0203] Next, referring to FIG. 11b, a sub-organic insulating layer (119) can be formed on the second interlayer insulating layer (117). The sub-organic insulating layer (119) can cover the side of the inorganic insulating layer (IIL) from which a portion has been removed. The sub-organic insulating layer (119) can prevent the wiring from being disconnected due to the step difference between the inorganic insulating layer (IIL) and the lower layer (LL). Source electrodes (SE, FIG. 10) and drain electrodes (DE, FIG. 10) of a pixel circuit (PC) can be formed on the second interlayer insulating layer (117), and gate lines (DL) and data lines (DL) can be formed on the second interlayer insulating layer (117) and the sub-organic insulating layer (119).

[0204] A first organic insulating layer (121) may be formed on the pixel circuit (PC), and a connection electrode (CM) and a second voltage line (VSSL) may be formed on the first organic insulating layer (121). A second organic insulating layer (123) may be formed on the connection electrode (CM), and a first electrode pad (241) and a second electrode pad (243) may be formed on the second organic insulating layer (123). In one embodiment, the first organic insulating layer (121) may be formed only on the pixel area (11), and the second organic insulating layer (123) may be formed partially on the connection area (12) extending from the pixel area (11). However, as shown in FIG. 11b, the second organic insulating layers (123) that are arranged adjacently may be spaced apart from each other within the connection area (12).

[0205] Next, referring to FIG. 11c, a light-emitting diode (LED) can be formed on a pixel circuit layer (PCL). The light-emitting diode (LED) can be placed on a pixel area (11). The light-emitting diode (LED) can be an inorganic light-emitting diode, as previously described with reference to FIG. 8a. The light-emitting diode (LED) can be covered by a protective layer (240).

[0206] Next, referring to FIG. 11d, the upper elastomer layer (300) may be formed to cover a light-emitting diode (LED). The upper elastomer layer (300) may include the same material as described with reference to FIG. 6. The upper elastomer layer (300) may absorb stress that may be transmitted to the light-emitting diode (LED) and pixel circuit (PC) when the display panel (10, FIG. 10) is stretched. Additionally, the upper elastomer layer (300) may function to flatten (or substantially flatten) the display panel (10, FIG. 10). The upper elastomer layer (300) may be formed through a thermal curing process after the material constituting the upper elastomer layer (300) is deposited. The thermal curing process may heat the display panel (10, FIG. 10) at 150°C or higher for 30 minutes to 2 hours. However, it is not limited to this, and the upper elastomer layer (300) may be cured through a UV curing process.

[0207] A carrier film (500) may be formed on the upper elastomer layer (300). In some embodiments, the carrier film (500) may be attached to the upper surface of the upper elastomer layer (300) through an adhesive layer interposed between the upper elastomer layer (300) and the carrier film (500). The carrier film (500) may be a protective film capable of preventing or reducing scratches or dents that occur on the display panel (10, FIG. 10) during the manufacturing process. For example, the carrier film (500) may include an insulating film. However, this is exemplary, and the method of attaching the carrier film (500) may be varied.

[0208] Next, referring to FIG. 11e, after detaching the substrate (100) from the lower layer (LL, FIG. 11d), the display panel (10, FIG. 10) can be inverted. Specifically, the substrate (100) can be removed from the base layer (110). By irradiating a laser onto the other side of the substrate (100) opposite to the side of the substrate (100) in contact with the base layer (110), the bonding force between the substrate (100) and the base layer (110) can be weakened. Accordingly, the substrate (100) can be peeled off from the base layer (110). However, this is an example, and the method of removing the substrate (100) can be varied.

[0209] After the substrate (100) is removed, the display panel (10, FIG. 10) can be inverted so that the upper and lower surfaces are reversed. For example, the display panel (10, FIG. 10) can be inverted so that the carrier film (500) is placed on the lower side and the base layer (110) is placed on the upper side.

[0210] Next, referring to FIG. 11f, the base layer (110) can be removed while the display panel (10, FIG. 10) is inverted. The base layer (110) can be completely removed through a dry etching process. As the base layer (110) is removed, the bottom surface of the pixel circuit layer (PCL) can be exposed. Here, the bottom surface of the pixel circuit layer (PCL) can be seen as the top surface of the pixel circuit layer (PCL) because the display panel (10, FIG. 10) is inverted.

[0211] Next, referring to FIG. 11g, a sacrificial layer (600) can be formed on the bottom surface of a pixel circuit layer (PCL) while the display panel (10, FIG. 10) is in an inverted state. The sacrificial layer (600) can be patterned to have an opening (600OP) that overlaps with the connection area (12). In one embodiment, the sacrificial layer (600) can be formed through a dispensing process or an inkjet printing process. However, this is exemplary, and the method of forming the sacrificial layer (600) can be varied.

[0212] A connecting wire (WL, FIG. 10) may be disposed within the opening (600OP) of the sacrificial layer (600). That is, the sacrificial layer (600) may be a layer temporarily used to pattern the connecting wire (WL, FIG. 10). In one embodiment, when the connecting wire (WL, FIG. 10) is formed from liquid metal, the sacrificial layer (600) may include a liquid metal adhesion inhibitor. However, this is exemplary, and the sacrificial layer (600) may not be limited to any material having hydrophobicity.

[0213] Next, referring to FIG. 11h, a connecting wire (WL) may be formed within an opening (600OP) of the sacrificial layer (600). The area of ​​the connecting wire (WL) in the planar form may be equal to the area of ​​each of the organic insulating layer and the upper elastomer layer (300) whose upper surfaces are exposed by the opening (600OP). For example, the length of the connecting wire (WL) may be equal to the combined length of the upper surfaces of the organic insulating layer and the upper elastomer layer (300) exposed through the opening (600OP). In one embodiment, the connecting wire (WL) may include liquid metal, and the material for forming the connecting wire (WL) may be applied using a roller or a stamp, etc. However, when using a roller or stamp, it is difficult to achieve fine patterning (e.g., precise and complex patterning), so the material for forming the connecting wire (WL) may be applied up to the area around the opening (600OP). In this case, if the sacrificial layer (600) includes a liquid metal adhesion inhibitor as described above, the material for forming the connecting wire (WL) may not be placed on the sacrificial layer (600) but only within the opening (600OP). That is, the connecting wire (WL) can be patterned through the opening of the sacrificial layer (600) containing the hydrophobic material.

[0214] Next, referring to FIG. 11i, the sacrificial layer (600, FIG. 11h) can be removed. The sacrificial layer (600, FIG. 11h), which contains a hydrophobic material such as a liquid metal adhesion inhibitor, can be removed through a cleaning process using water. Accordingly, only the connecting wire (WL) formed within the opening (600OP, FIG. 11h) of the sacrificial layer (600, FIG. 11h) may remain on the bottom surface of the display panel (10, FIG. 10).

[0215] That is, according to the method for manufacturing a display panel according to one embodiment of the present invention, fine patterning of the connecting wire (WL) is possible, and since the sacrificial layer (600, FIG. 11h) is completely removed so that no material that could reduce the elasticity of the display panel (10, FIG. 10) remains, the elongation of the display panel (10, FIG. 10) can be improved. Meanwhile, if the sacrificial layer (600, FIG. 11h) containing a hydrophobic material remains, the bonding force with the upper layer may be weakened. Accordingly, the display panel (10, FIG. 10) according to one embodiment of the present invention can also secure structural stability of the display panel (10, FIG. 10) by removing the sacrificial layer (600, FIG. 11h).

[0216] Next, referring to FIG. 11j, a lower elastomer layer (400) can be formed on the bottom surface of the pixel circuit layer (PCL). The lower elastomer layer (400) can be positioned to cover the connecting wire (WL). The lower elastomer layer (400) may include the same material as described with reference to FIG. 6. The lower elastomer layer (400) can function to encapsulate the bottom of the display panel (10, FIG. 10) and can absorb stress that may occur when the display panel (10, FIG. 10) is stretched.

[0217] After forming the lower elastomer layer (400), the display panel of FIG. 11j can be inverted again to form the structure of the display panel (10, FIG. 10) as in FIG. 10. Afterwards, the carrier film (500, FIG. 11i) attached to the upper surface of the display panel (10, FIG. 10) can be removed. The carrier film (500, FIG. 11i) can be removed using a release tape. However, this is an example, and the method of removing the carrier film (500, FIG. 11j) can be varied.

[0218] FIG. 12 is a schematic cross-sectional view of a portion of a display panel according to another embodiment of the present invention. Referring to FIG. 12, other features are the same as those described in FIG. 9 and FIG. 10, except for features regarding the base layer (110) and the connecting wiring (WL). Among the components of FIG. 12, identical reference numerals are replaced with those previously described with reference to FIG. 9 and FIG. 10, and the following description focuses on the differences.

[0219] Referring to FIG. 12, the display panel (10) may include a lower elastomer layer (400). The display panel (10) may have pixel regions (11) and connection regions (12) between the pixel regions (11). In each of the pixel regions (11) of the lower elastomer layer (400), a pixel circuit layer (PCL) including a pixel circuit (PC) and a light-emitting diode (LED) disposed on the pixel circuit layer (PCL) may be disposed.

[0220] In one embodiment, a base layer (110) may be interposed between the lower elastomer layer (400) and the pixel circuit layer (PC). That is, the base layer (110) may be disposed between the lower elastomer layer (400) and the buffer layer (111). The base layer (110) may include a polymer resin. For example, the base layer (100) may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0221] In one embodiment, the base layer (110) may include an opening that overlaps with the connection area (12), and a connection wire (WL) may be disposed within the opening of the base layer (110). In other words, the connection wire (WL) may be disposed on the upper surface of the lower elastomer layer (400) exposed by the opening of the base layer (110). The connection wire (WL) may not only fill the opening of the base layer (110) but also be disposed on the upper surface of the end of the base layer (110). That is, the connection wire (WL) may cover a portion of the side and upper surface of the base layer (110).

[0222] FIGS. 13a to 13j are cross-sectional views sequentially illustrating the steps of a method for manufacturing a display panel according to another embodiment of the present invention. In describing the method for manufacturing a display panel of another embodiment, the description of the display panel described with reference to FIG. 12 may be applied. Identical reference numerals among the components of FIGS. 13a to 13j may be replaced with those previously described with reference to FIGS. 9 to 12, and the following description focuses on the differences.

[0223] First, referring to FIG. 13a, a lower layer (LL) may be formed to form a display panel (10, FIG. 12). In one embodiment, the lower layer (LL) may include a substrate (100) and a base layer (110) disposed on the substrate (100).

[0224] On the lower layer (LL), an inorganic insulating layer (IIL) and a portion of a thin-film transistor (TFT, FIG. 10) may be formed. However, the inorganic insulating layer (IIL) may be placed only in the pixel area (11) and not in the connection area (12). For example, a portion of the inorganic insulating layer (IIL) that overlaps with the connection area (12) may be removed through an etching process.

[0225] Next, referring to FIG. 13b, a sub-organic insulating layer (119) can be formed on the second interlayer insulating layer (117). The sub-organic insulating layer (119) can cover the side of the inorganic insulating layer (IIL) from which a portion has been removed. Source electrodes (SE, FIG. 10) and drain electrodes (DE, FIG. 10) of a pixel circuit (PC) can be formed on the second interlayer insulating layer (117), and gate lines (DL) and data lines (DL) can be formed on the second interlayer insulating layer (117) and the sub-organic insulating layer (119).

[0226] A first organic insulating layer (121) may be formed on the pixel circuit (PC), and a connection electrode (CM) and a second voltage line (VSSL) may be formed on the first organic insulating layer (121). A second organic insulating layer (123) may be formed on the connection electrode (CM), and a first electrode pad (241) and a second electrode pad (243) may be formed on the second organic insulating layer (123).

[0227] Next, referring to FIG. 13c, an opening (110OP) can be formed in the base layer (110). That is, a portion of the base layer (110) that overlaps with the connection area (12) can be removed. A portion of the base layer (110) can be removed through a dry etching process. By forming an opening (110OP) in the base layer (110), a portion of the upper surface of the substrate (100) can be exposed.

[0228] Next, referring to FIG. 13d, a sacrificial layer (600) can be formed on the pixel circuit layer (600). The sacrificial layer (600) can be patterned to have an opening (600OP) that overlaps with the connection area (12). The opening (600OP) of the sacrificial layer (600) may partially overlap with the opening (110OP) of the base layer (110). In one embodiment, the sacrificial layer (600) can be formed through a dispensing process or an inkjet printing process. However, this is exemplary, and the method of forming the sacrificial layer (600) can be varied.

[0229] A connecting wire (WL, FIG. 12) may be disposed within the opening (600OP) of the sacrificial layer (600). That is, the sacrificial layer (600) may be a layer temporarily used to pattern the connecting wire (WL, FIG. 12). In one embodiment, when the connecting wire (WL, FIG. 12) is formed from liquid metal, the sacrificial layer (600) may include a liquid metal adhesion inhibitor. However, this is exemplary, and the sacrificial layer (600) may not be limited to any material that has hydrophobicity.

[0230] Next, referring to FIG. 13e, a connecting wire (WL) can be formed within the opening (600OP, FIG. 13d) of the sacrificial layer (600). Since the opening (600OP, FIG. 13d) of the sacrificial layer (600) partially overlaps with the opening (110OP, FIG. 13d) of the base layer (110), the connecting wire (WL) can fill the opening (110OP, FIG. 13d) of the base layer (110). Specifically, the connecting wire (WL) can fill the opening (110OP, FIG. 13d) of the base layer (110) and cover the upper surface of the base layer (110) exposed by the opening (600OP, FIG. 13d) of the sacrificial layer (600).

[0231] In one embodiment, the connecting wire (WL) may include liquid metal, and the material for forming the connecting wire (WL) may be applied using a roller or stamp, etc. However, since fine patterning is difficult when using a roller or stamp, the material for forming the connecting wire (WL) may be applied up to the area around the opening (600OP, FIG. 13d). In this case, if the sacrificial layer (600) includes a liquid metal adhesion inhibitor as described above, the material for forming the connecting wire (WL) may not be placed on the sacrificial layer (600) but only within the opening (600OP, FIG. 13d). That is, the connecting wire (WL) may be patterned through the opening of the sacrificial layer (600) containing a hydrophobic material.

[0232] Next, referring to FIG. 13f, the sacrificial layer (600, FIG. 13e) can be removed. The sacrificial layer (600, FIG. 13e), which contains a hydrophobic material such as a liquid metal adhesion inhibitor, can be removed through a cleaning process using water. Accordingly, only the connecting wire (WL) formed within the opening of the sacrificial layer (600, FIG. 13e) may remain on the connecting area (12).

[0233] That is, according to the method for manufacturing a display panel according to another embodiment of the present invention, fine patterning of the connecting wire (WL) (e.g., precise and complex patterning) is possible, and since the sacrificial layer (600, FIG. 13e) is completely removed so that no material remains that could reduce the elasticity of the display panel (10, FIG. 12), the stretchability of the display panel (10, FIG. 12) can be improved. Meanwhile, if the sacrificial layer (600, FIG. 13e) containing a hydrophobic material remains, the bonding force with the upper layer may be weakened. Accordingly, the display panel (10, FIG. 12) according to another embodiment of the present invention can also secure structural stability of the display panel (10, FIG. 12) by removing the sacrificial layer (600, FIG. 13e).

[0234] Next, referring to FIG. 13g, a light-emitting diode (LED) can be formed on a pixel circuit layer (PCL). The light-emitting diode (LED) can be placed on a pixel area (11). The light-emitting diode (LED) can be an inorganic light-emitting diode, as previously described with reference to FIG. 8a. The light-emitting diode (LED) can be covered by a protective layer (240).

[0235] Next, referring to FIG. 13h, the upper elastomer layer (300) can be formed to cover the light-emitting diode (LED) and the connecting wire (WL). The upper elastomer layer (300) may include the same material as described with reference to FIG. 6. The upper elastomer layer (300) can be formed through a heat curing process after the material constituting the upper elastomer layer (300) is deposited.

[0236] A carrier film (500) may be formed on the upper elastomer layer (300). Although not shown in FIG. 13h, the carrier film (500) may be attached to the upper surface of the upper elastomer layer (300) through an adhesive layer interposed between the upper elastomer layer (300) and the carrier film (500). However, this is an example, and the curing method of the upper elastomer layer (300) and the attachment method of the carrier film (500) may be varied.

[0237] Next, referring to FIG. 13i, after detaching the substrate (100, 13h) from the lower layer (LL, FIG. 13a), the display panel (10, FIG. 12) can be inverted. Specifically, the substrate (100, FIG. 13h) can be removed from the base layer (110). By irradiating a laser onto the other side of the substrate (100, FIG. 13h) opposite to the side of the substrate (100, FIG. 13h) in contact with the base layer (110), the bonding force between the substrate (100, FIG. 13h) and the base layer (110) can be weakened. After detaching the substrate (100, FIG. 13h), the display panel (10, FIG. 12) can be inverted so that the upper and lower surfaces are inverted. For example, the display panel (10, FIG. 12) can be inverted so that the carrier film (500) is placed at the bottom and the base layer (110) is placed at the top.

[0238] Next, referring to FIG. 13j, a lower elastomer layer (400) can be formed on the bottom surface of the base layer (110) and the bottom surface of the connecting wire (WL) while the display panel (10, FIG. 12) is inverted. The lower elastomer layer (400) can encapsulate the bottom of the display panel (10, FIG. 12).

[0239] After forming the lower elastomer layer (400), the display panel of FIG. 13j can be inverted again to form the structure of the display panel (10, FIG. 12) as in FIG. 12. Afterwards, the carrier film (500, FIG. 13i) attached to the upper surface of the display panel (10, FIG. 12) can be removed. The carrier film (500, FIG. 13i) can be removed using a release tape. However, this is an example, and the method of removing the carrier film (500, FIG. 13i) can be varied.

[0240] FIGS. 14a to 14i are cross-sectional views sequentially illustrating the steps of a method for manufacturing a display panel according to another embodiment of the present invention. In describing the method for manufacturing a display panel of another embodiment, the description of the display panel described with reference to FIG. 12 may be applied to the display panel. Identical reference numerals among the components of FIGS. 14a to 14i may be replaced with those previously described with reference to FIGS. 9 to 12, and the following description focuses on the differences.

[0241] First, referring to FIG. 14a, a lower layer (LL) may be formed to form a display panel (10, FIG. 12). The lower layer (LL) may be a layer temporarily placed to form a stretchable display panel (10, FIG. 12). The lower layer (LL) may include a substrate (100), a lower elastomer layer (400) placed on the substrate (100), and a base layer (110) placed on the lower elastomer layer (400).

[0242] On the lower layer (LL), an inorganic insulating layer (IIL) and a portion of a thin-film transistor (TFT, FIG. 10) may be formed. However, the inorganic insulating layer (IIL) may be placed only in the pixel area (11) and not in the connection area (12). For example, a portion of the inorganic insulating layer (IIL) that overlaps with the connection area (12) may be removed through an etching process.

[0243] Next, referring to FIG. 14b, a sub-organic insulating layer (119) can be formed on the second interlayer insulating layer (117). The sub-organic insulating layer (119) can cover the side of the inorganic insulating layer (IIL) from which a portion has been removed. Source electrodes (SE, FIG. 10) and drain electrodes (DE, FIG. 10) of a pixel circuit (PC) can be formed on the second interlayer insulating layer (117), and gate lines (DL) and data lines (DL) can be formed on the second interlayer insulating layer (117) and the sub-organic insulating layer (119).

[0244] A first organic insulating layer (121) may be formed on the pixel circuit (PC), and a connection electrode (CM) and a second voltage line (VSSL) may be formed on the first organic insulating layer (121). A second organic insulating layer (123) may be formed on the connection electrode (CM), and a first electrode pad (241) and a second electrode pad (243) may be formed on the second organic insulating layer (123).

[0245] Next, referring to FIG. 14c, an opening (110OP) can be formed in the base layer (110). That is, a portion of the base layer (110) that overlaps with the connection area (12) can be removed. A portion of the base layer (110) can be removed through a dry etching process. By forming an opening (110OP) in the base layer (110), a portion of the upper surface of the lower elastomer layer (400) can be exposed.

[0246] Next, referring to FIG. 14d, a sacrificial layer (600) can be formed on the pixel circuit layer (600). The sacrificial layer (600) can be patterned to have an opening (600OP) that overlaps with the connection area (12). The opening (600OP) of the sacrificial layer (600) may partially overlap with the opening (110OP) of the base layer (110). In one embodiment, the sacrificial layer (600) can be formed through a dispensing process or an inkjet printing process. However, this is exemplary, and the method of forming the sacrificial layer (600) can be varied.

[0247] A connecting wire (WL, FIG. 12) may be disposed within the opening (600OP) of the sacrificial layer (600). That is, the sacrificial layer (600) may be a layer temporarily used to pattern the connecting wire (WL, FIG. 12). In one embodiment, when the connecting wire (WL, FIG. 12) is formed from liquid metal, the sacrificial layer (600) may include a liquid metal adhesion inhibitor. However, this is exemplary, and the sacrificial layer (600) may not be limited to any material that has hydrophobicity.

[0248] Next, referring to FIG. 14e, a connecting wire (WL) can be formed within the opening (600OP, FIG. 14d) of the sacrificial layer (600). Since the opening (600OP, FIG. 14d) of the sacrificial layer (600) partially overlaps with the opening (110OP, FIG. 14d) of the base layer (110), the connecting wire (WL) can fill the opening (110OP, FIG. 14d) of the base layer (110). Specifically, the connecting wire (WL) can fill the opening (110OP, FIG. 14d) of the base layer (110) and cover the upper surface of the base layer (110) exposed by the opening (600OP, FIG. 14d) of the sacrificial layer (600).

[0249] In one embodiment, the connecting wire (WL) may include liquid metal, and the material for forming the connecting wire (WL) may be applied using a roller or stamp, etc. However, since fine patterning is difficult when using a roller or stamp, the material for forming the connecting wire (WL) may be applied up to the area around the opening (600OP, FIG. 14d). In this case, if the sacrificial layer (600) includes a liquid metal adhesion inhibitor as described above, the material for forming the connecting wire (WL) may not be placed on the sacrificial layer (600) but only within the opening (600OP, FIG. 14d). That is, the connecting wire (WL) may be patterned through the opening of the sacrificial layer (600) containing a hydrophobic material.

[0250] Next, referring to FIG. 14f, the sacrificial layer (600, FIG. 14e) can be removed. The sacrificial layer (600, FIG. 14e), which contains a hydrophobic material such as a liquid metal adhesion inhibitor, can be removed through a cleaning process using water. Accordingly, only the connecting wire (WL) formed within the opening of the sacrificial layer (600, FIG. 14e) may remain on the connecting area (12).

[0251] That is, according to the method for manufacturing a display panel according to another embodiment of the present invention, fine patterning of the connecting wire (WL) is possible, and since the sacrificial layer (600, FIG. 14e) is completely (or substantially) removed so that no material remains that could reduce the elasticity of the display panel (10, FIG. 12), the stretchability of the display panel (10, FIG. 12) can be improved. Meanwhile, if the sacrificial layer (600, FIG. 14e) containing a hydrophobic material remains, the bonding force with the upper layer may be weakened. Accordingly, the display panel (10, FIG. 12) according to another embodiment of the present invention can also secure structural stability of the display panel (10, FIG. 12) by removing the sacrificial layer (600, FIG. 14e).

[0252] Next, referring to FIG. 14g, a light-emitting diode (LED) can be formed on a pixel circuit layer (PCL). The light-emitting diode (LED) can be placed on a pixel area (11). The light-emitting diode (LED) can be an inorganic light-emitting diode, as previously described with reference to FIG. 8a. The light-emitting diode (LED) can be covered by a protective layer (240).

[0253] Next, referring to FIG. 14h, the upper elastomer layer (300) can be formed to cover the light-emitting diode (LED) and the connecting wire (WL). The upper elastomer layer (300) may include the same material as described with reference to FIG. 6. The upper elastomer layer (300) can be formed through a heat curing process after the material constituting the upper elastomer layer (300) is deposited.

[0254] A carrier film (500) may be formed on the upper elastomer layer (300). Although not shown in FIG. 14h, the carrier film (500) may be attached to the upper surface of the upper elastomer layer (300) through an adhesive layer interposed between the upper elastomer layer (300) and the carrier film (500). However, this is an example, and the curing method of the upper elastomer layer (300) and the attachment method of the carrier film (500) may be varied.

[0255] Next, referring to FIG. 14i, the substrate (100) can be detached. Specifically, the substrate (100, FIG. 14h) can be removed from the lower elastomer layer (400). By irradiating a laser onto the other side of the substrate (100, FIG. 14h) opposite to the side of the substrate (100, FIG. 14h) in contact with the lower elastomer layer (400), the bonding force between the substrate (100, FIG. 14h) and the lower elastomer layer (400) can be weakened.

[0256] After removing the substrate (100, FIG. 14h), the carrier film (500, FIG. 14h) attached to the upper surface of the display panel (10) can also be removed. The carrier film (500, FIG. 14h) can be removed using a release tape. However, this is an example, and the method of removing the substrate (100, FIG. 14h) and the method of removing the carrier film (500, FIG. 14h) can be varied.

[0257] FIG. 15 is a schematic cross-sectional view showing a portion of a display panel according to another embodiment of the present invention. Referring to FIG. 15, other features are the same as those described in FIG. 9 and FIG. 10, except for the features regarding the connecting wiring (WL). Among the components of FIG. 15, identical reference numerals are replaced with those previously described with reference to FIG. 9 and FIG. 10, and the following description focuses on the differences.

[0258] Referring to FIG. 15, the display panel (10) may include a lower elastomer layer (400). The display panel (10) may have a pixel area (11) and a connection area (12) between the pixel areas (11). On the pixel area (11) of the lower elastomer layer (400), a pixel circuit layer (PCL) including a pixel circuit (PC) and a light-emitting diode (LED) disposed on the pixel circuit layer (PCL) may be disposed.

[0259] In one embodiment, a connecting wire (WL) may be disposed on the connecting area (12) of the lower elastomer layer (400). The connecting wire (WL) may be disposed on the upper surface of the lower elastomer layer (400) as shown in FIG. 15. In other words, only the lower surface of the connecting wire (WL) is in contact with the lower elastomer layer (400), and the side of the connecting wire (WL) may be covered by a data line (DL) or a sub-organic insulating layer (119).

[0260] FIGS. 16a to 16h are cross-sectional views sequentially illustrating the steps of a method for manufacturing a display panel according to another embodiment of the present invention. In describing the method for manufacturing a display panel of another embodiment, the description of the display panel described with reference to FIG. 15 may be applied. Identical reference numerals among the components of FIGS. 16a to 16h may be replaced with those previously described with reference to FIGS. 9, 10, and 15, and the following description focuses on the differences.

[0261] First, referring to FIG. 16a, a lower layer (LL) may be formed to form a display panel (10, FIG. 15). In one embodiment, the lower layer (LL) may include a substrate (100) and a lower elastomer layer (400) disposed on the substrate (100).

[0262] A sacrificial layer (600) may be formed on the lower layer (LL). The sacrificial layer (600) may be patterned to have an opening (600OP) that overlaps with the connection area (12). In one embodiment, the sacrificial layer (600) may be formed through a dispensing process or an inkjet printing process. However, this is exemplary, and the method of forming the sacrificial layer (600) may be varied.

[0263] A connecting wire (WL, FIG. 15) may be disposed within the opening (600OP) of the sacrificial layer (600). That is, the sacrificial layer (600) may be a layer temporarily used to pattern the connecting wire (WL, FIG. 15). In one embodiment, when the connecting wire (WL, FIG. 15) is formed from liquid metal, the sacrificial layer (600) may include a liquid metal adhesion inhibitor. However, this is exemplary, and the sacrificial layer (600) may not be limited to any material that has hydrophobicity.

[0264] Next, referring to FIG. 16b, a connecting wire (WL) may be formed within an opening (600OP) of the sacrificial layer (600). The area of ​​the connecting wire (WL) in the planar form may be equal to the area of ​​the lower elastomer layer (400) whose upper surface is exposed by the opening (600OP). For example, the length of the upper surface of the lower elastomer layer (400) exposed through the opening (600OP) may be equal to the length of the connecting wire (WL). In one embodiment, the connecting wire (WL) may include liquid metal, and the material for forming the connecting wire (WL) may be applied using a roller or stamp, etc. However, since fine patterning is difficult when using a roller or stamp, the material for forming the connecting wire (WL) may be applied up to the area around the opening (600OP). In this case, if the sacrificial layer (600) includes a liquid metal adhesion inhibitor as described above, the material for forming the connecting wire (WL) may not be placed on the sacrificial layer (600) but only within the opening (600OP). That is, the connecting wire (WL) may be patterned through the opening of the sacrificial layer (600) containing the hydrophobic material.

[0265] Next, referring to FIG. 16c, the sacrificial layer (600, FIG. 16b) can be removed. The sacrificial layer (600, FIG. 16b), which contains a hydrophobic material such as a liquid metal adhesion inhibitor, can be removed through a cleaning process using water. Accordingly, only the connecting wire (WL) formed within the opening (600OP, FIG. 16b) of the sacrificial layer (600, FIG. 16b) may remain on the upper surface of the lower elastomer layer (400).

[0266] That is, according to the method for manufacturing a display panel according to another embodiment of the present invention, fine patterning of the connecting wire (WL) is possible, and since the sacrificial layer (600, FIG. 16b) is completely removed so that no material that could reduce the elasticity of the display panel (10, FIG. 15) remains, the elongation of the display panel (10, FIG. 15) can be improved. Meanwhile, if the sacrificial layer (600, FIG. 16b) containing a hydrophobic material remains, the bonding force with the upper layer may be weakened. Accordingly, the display panel (10, FIG. 15) according to another embodiment of the present invention can also secure structural stability of the display panel (10, FIG. 15) by removing the sacrificial layer (600, FIG. 16b).

[0267] Next, referring to FIG. 16d, an inorganic insulating layer (IIL) and a part of a thin-film transistor (TFT, FIG. 10) may be formed on the lower layer (LL). However, the inorganic insulating layer (IIL) may be placed only in the pixel area (11) and not in the connection area (12). For example, a part of the inorganic insulating layer (IIL) that overlaps with the connection area (12) may be removed through an etching process.

[0268] Next, referring to FIG. 16e, a sub-organic insulating layer (119) can be formed on the second interlayer insulating layer (117). The sub-organic insulating layer (119) can cover the side of the inorganic insulating layer (IIL) from which a portion has been removed. Source electrodes (SE, FIG. 10) and drain electrodes (DE, FIG. 10) of a pixel circuit (PC) can be formed on the second interlayer insulating layer (117), and gate lines (DL) and data lines (DL) can be formed on the second interlayer insulating layer (117) and the sub-organic insulating layer (119).

[0269] A first organic insulating layer (121) may be formed on the pixel circuit (PC), and a connection electrode (CM) and a second voltage line (VSSL) may be formed on the first organic insulating layer (121). A second organic insulating layer (123) may be formed on the connection electrode (CM), and a first electrode pad (241) and a second electrode pad (243) may be formed on the second organic insulating layer (123).

[0270] Next, referring to FIG. 16f, a light-emitting diode (LED) can be formed on a pixel circuit layer (PCL). The light-emitting diode (LED) can be placed on a pixel area (11). The light-emitting diode (LED) can be an inorganic light-emitting diode, as previously described with reference to FIG. 8a. The light-emitting diode (LED) can be covered by a protective layer (240).

[0271] Next, referring to FIG. 16g, the upper elastomer layer (300) can be formed to cover a light-emitting diode (LED) and a connecting wire (WL). The upper elastomer layer (300) may include the same material as described with reference to FIG. 6. The upper elastomer layer (300) can be formed through a heat curing process after the material constituting the upper elastomer layer (300) is deposited.

[0272] A carrier film (500) may be formed on the upper elastomer layer (300). Although not shown in FIG. 16g, the carrier film (500) may be attached to the upper surface of the upper elastomer layer (300) through an adhesive layer interposed between the upper elastomer layer (300) and the carrier film (500). However, this is an example, and the curing method of the upper elastomer layer (300) and the attachment method of the carrier film (500) may be varied.

[0273] Next, referring to FIG. 16h, the substrate (100) can be detached. Specifically, the substrate (100, FIG. 16g) can be removed from the lower elastomer layer (400). By irradiating a laser onto the other side of the substrate (100, FIG. 16g) opposite to the side of the substrate (100, FIG. 16g) in contact with the lower elastomer layer (400), the bonding force between the substrate (100, FIG. 16g) and the lower elastomer layer (400) can be weakened.

[0274] After removing the substrate (100, FIG. 16g), the carrier film (500, FIG. 16g) attached to the upper surface of the display panel (10, FIG. 15) can also be removed. The carrier film (500, FIG. 16g) can be removed using a release tape. However, this is an example, and the method of removing the substrate (100, FIG. 16g) and the method of removing the carrier film (500, FIG. 16g) can be varied.

[0275] FIG. 17 is a schematic cross-sectional view showing a portion of a display panel according to another embodiment of the present invention. Referring to FIG. 17, other features are the same as those described in FIG. 9 and FIG. 10, except for the features regarding the connecting wiring (WL). Among the components of FIG. 17, identical reference numerals are replaced with those previously described with reference to FIG. 9 and FIG. 10, and the following description focuses on the differences.

[0276] Referring to FIG. 17, the display panel (10) may include a lower elastomer layer (400). The display panel (10) may have pixel regions (11) and connection regions (12) between the pixel regions (11). In each of the pixel regions (11) of the lower elastomer layer (400), a pixel circuit layer (PCL) including a pixel circuit (PC) and a light-emitting diode (LED) disposed on the pixel circuit layer (PCL) may be disposed.

[0277] In one embodiment, a sub-elastomer layer (400b) may be disposed on the connection area (12) of the lower elastomer layer (400). Unlike the lower elastomer layer (400) being disposed over the entire display area (DA, FIG. 4), the sub-elastomer layer (400b) may be disposed to overlap only with a portion of the connection area (12).

[0278] In one embodiment, the sub-elastomer layer (400b) may contain the same material as the lower elastomer layer (400). For example, the sub-elastomer layer (400b) is thermoplastic polyurethane, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, fluoroelastomers, ethylene-vinyl acetate, It may include at least one of PDMS (polydimethylsiloxane) and Ecoflex. However, it is not limited thereto, and the sub-elastomer layer (400b) may include a material different from the lower elastomer layer (400).

[0279] In one embodiment, a connecting wire (WL) may be disposed on a sub-elastomer layer (400b). The sub-elastomer layer (400b) and the connecting wire (WL) may be disposed so as to overlap each other in a planar manner. The area of ​​the connecting wire (WL) in the planar manner may be equal to the area of ​​the sub-elastomer layer (400b) or smaller than the area of ​​the sub-elastomer layer (400b). In other words, the lower surface of the connecting wire (WL) may be in contact only with the sub-elastomer layer (400b).

[0280] FIGS. 18a to 18h are cross-sectional views sequentially illustrating the steps of a method for manufacturing a display panel according to another embodiment of the present invention. In describing the method for manufacturing a display panel of another embodiment, the description of the display panel described with reference to FIG. 17 may be applied to the display panel. Identical reference numerals among the components of FIGS. 18a to 18h may be replaced with those previously described with reference to FIGS. 9, 10, and 17, and the following description focuses on the differences.

[0281] First, referring to FIG. 18a, a lower layer (LL) may be formed to form a display panel (10, FIG. 17). In one embodiment, the lower layer (LL) may include a substrate (100). A sacrificial layer (600) may be formed on the substrate (100), which is the lower layer (LL). In one embodiment, the sacrificial layer (600) may be formed through a dispensing process or an inkjet printing process. However, this is exemplary, and the method of forming the sacrificial layer (600) may be varied. In one embodiment, when the connecting wire (WL, FIG. 17) is formed with liquid metal, the sacrificial layer (600) may include a liquid metal adhesion inhibitor. However, this is exemplary, and the sacrificial layer (600) may not be limited to any material having hydrophobicity.

[0282] A sub-elastomer layer (400b) may be formed on the sacrificial layer (600). The sub-elastomer layer (400b) may be battered to overlap only some of the connection areas (12). That is, the sub-elastomer layer (400b) may be a material that is pre-deposited in the area where the connection wiring (WL, FIG. 17) is required. In one embodiment, the thickness of the sub-elastomer layer (400b) may be smaller than the thickness of the lower elastomer layer (400, FIG. 17).

[0283] Next, referring to FIG. 18b, a connecting wire (WL) may be formed on the upper surface of the sub-elastomer layer (400b). The area of ​​the connecting wire (WL) on the plane may be equal to the area of ​​the upper surface of the sub-elastomer layer (400b) or smaller than the area of ​​the upper surface of the sub-elastomer layer (400b).

[0284] In one embodiment, the connecting wire (WL) may include liquid metal, and the material for forming the connecting wire (WL) may be applied using a roller or stamp, etc. However, since fine patterning is difficult when using a roller or stamp, the material for forming the connecting wire (WL) may be applied up to the peripheral area of ​​the sub-elastomer layer (400b). In this case, if the sacrificial layer (600) includes a liquid metal adhesion inhibitor as described above, the material for forming the connecting wire (WL) may not be placed on the sacrificial layer (600) but only on the upper surface of the sub-elastomer layer (400b). That is, the connecting wire (WL) can be patterned through the sacrificial layer (600) and the sub-elastomer layer (400b).

[0285] Next, referring to FIG. 18c, an inorganic insulating layer (IIL) and a part of a thin-film transistor (TFT, FIG. 10) may be formed on the sacrificial layer (600). However, the inorganic insulating layer (IIL) may be placed only in the pixel area (11) and not in the connection area (12). For example, a part of the inorganic insulating layer (IIL) that overlaps with the connection area (12) may be removed through an etching process.

[0286] Next, referring to FIG. 18d, a sub-organic insulating layer (119) can be formed on the second interlayer insulating layer (117). The sub-organic insulating layer (119) can cover the side of the inorganic insulating layer (IIL) from which a portion has been removed. Source electrodes (SE, FIG. 10) and drain electrodes (DE, FIG. 10) of a pixel circuit (PC) can be formed on the second interlayer insulating layer (117), and gate lines (DL) and data lines (DL) can be formed on the second interlayer insulating layer (117) and the sub-organic insulating layer (119).

[0287] A first organic insulating layer (121) may be formed on the pixel circuit (PC), and a connection electrode (CM) and a second voltage line (VSSL) may be formed on the first organic insulating layer (121). A second organic insulating layer (123) may be formed on the connection electrode (CM), and a first electrode pad (241) and a second electrode pad (243) may be formed on the second organic insulating layer (123).

[0288] Next, referring to FIG. 18e, a light-emitting diode (LED) can be formed on a pixel circuit layer (PCL). The light-emitting diode (LED) can be placed on a pixel area (11). The light-emitting diode (LED) can be an inorganic light-emitting diode, as previously described with reference to FIG. 8a. The light-emitting diode (LED) can be covered by a protective layer (240).

[0289] Next, referring to FIG. 18f, the upper elastomer layer (300) can be formed to cover a light-emitting diode (LED) and a connecting wire (WL). The upper elastomer layer (300) may include the same material as described with reference to FIG. 6. The upper elastomer layer (300) can be formed through a heat curing process after the material constituting the upper elastomer layer (300) is deposited.

[0290] A carrier film (500) may be formed on the upper elastomer layer (300). Although not shown in FIG. 18f, the carrier film (500) may be attached to the upper surface of the upper elastomer layer (300) through an adhesive layer interposed between the upper elastomer layer (300) and the carrier film (500). However, this is merely an example, and the curing method of the upper elastomer layer (300) and the attachment method of the carrier film (500) may be varied.

[0291] Next, referring to FIG. 18g, the lower layer (LL, FIG. 18f) can be removed from the structure of FIG. 18f. Specifically, the substrate (100, FIG. 18f) can be detached from the structure of FIG. 18f. By irradiating a laser onto the other side of the substrate (100, FIG. 18f) opposite to the side of the substrate (100, FIG. 18f) that is in contact with the sacrificial layer (600), the bonding force between the substrate (100, FIG. 18f) and the sacrificial layer (600) can be weakened.

[0292] After the substrate (100, FIG. 18f) is detached, the sacrificial layer (600) can be removed. The sacrificial layer (600, FIG. 18f), which contains a hydrophobic material such as a liquid metal adhesion inhibitor, can be removed through a cleaning process using water. As the entire sacrificial layer (600, FIG. 18f) is removed, the bottom surface of the pixel circuit layer (PCL), the bottom surface of the sub-organic insulating layer (119), and the bottom surface of the sub-elastomer layer (400b) may be exposed.

[0293] That is, according to the method for manufacturing a display panel according to another embodiment of the present invention, fine patterning of the connecting wire (WL) is possible, and since the sacrificial layer (600, FIG. 18f) is completely (or substantially) removed so that no material remains that could reduce the elasticity of the display panel (10, FIG. 17), the stretchability of the display panel (10, FIG. 17) can be improved. Meanwhile, if the sacrificial layer (600, FIG. 18f) containing a hydrophobic material remains, the bonding force with the upper layer may be weakened. Accordingly, the display panel (10, FIG. 17) according to another embodiment of the present invention can also secure structural stability of the display panel (10, FIG. 17) by removing the sacrificial layer (600, FIG. 18f).

[0294] Next, referring to FIG. 18h, a lower elastomer layer (300) can be formed on the bottom surface of the pixel circuit layer (PCL), the bottom surface of the sub-organic insulating layer (119), and the bottom surface of the sub-elastomer layer (400b). The lower elastomer layer (400) can encapsulate the bottom of the display panel (10, FIG. 17).

[0295] After forming the lower elastomer layer (400), the carrier film (500, FIG. 18g) attached to the upper surface of the display panel (10, FIG. 17) can be removed. The carrier film (500, FIG. 18g) can be removed using a release tape. However, this is an example, and the method of removing the carrier film (500, FIG. 18g) can be varied.

[0296] FIGS. 19a to 19g are schematic perspective views illustrating embodiments of an electronic device including a display panel according to one embodiment of the present invention.

[0297] Referring to FIG. 19a, a display panel according to one embodiment of the present invention can be utilized in a wearable electronic device (3100) that can be worn on a part of a user's body. The wearable electronic device (3100) may include a body part (3110) and a display part (3120) provided in the body part (3110). A display panel according to embodiments of the present invention can be used as the display part (3120) of the wearable electronic device (3100). As illustrated in FIG. 13a, the wearable electronic device (3100) may be modified. In one embodiment, it can be used as a smart watch or a smartphone depending on the user's choice.

[0298] FIG. 19b illustrates a medical electronic device (3200). In one embodiment, the medical electronic device (3200) may include a body part (3210) and a light-emitting part (3220). A display panel according to embodiments of the present invention may be used as the light-emitting part (3220) of the medical electronic device (3200). The light-emitting part (3220) may emit light of a specific wavelength band (e.g., infrared, visible light, etc.) to the patient's body. In one embodiment, the body part (3210) may have a stretchable fiber material and may have a structure that can be worn on the body of the user of the light-emitting part.

[0299] FIG. 19c illustrates an educational electronic device (3300). In one embodiment, the educational electronic device may include a display unit (3320) provided within a frame (3310). The display unit (3320) may utilize a display panel according to embodiments of the present invention. The display unit (3320) may provide images such as a sea with waves, a snow-covered mountain, or a volcano with flowing lava, wherein the display unit (3320) may extend in the height direction (e.g., z-direction) to reflect the height of the waves, mountain, or volcano. In some embodiments, a portion of the display unit (3320) may sequentially vary in height along the direction of the lava flow to show the movement of the lava in three dimensions. The educational electronic device (3300) may include a plurality of pins (or stroke units, 3330) arranged on the back of the display unit (3320) so that the display unit (3320) extends in the height direction. The pins (3330) can be implemented to move along a third direction (e.g., z direction or -z direction) so that the image displayed on the display unit (3320) has a three-dimensional height. FIG. 19c describes an educational electronic device (3300), but its use is not limited as long as it provides certain image information.

[0300] The electronic device illustrated in FIGS. 19a to 19c is described as having a variable shape, but the present invention is not limited thereto. As in the embodiments described below, the display panel according to the embodiments of the present invention can be used in an electronic device in which a portion capable of displaying an image (e.g., a screen) is fixed.

[0301] FIG. 19d illustrates a robot (3400) as another electronic device in one embodiment of the present invention. The robot (3400) can move or perceive objects using a camera unit (3440) and can display a predetermined image to a user through a display unit (3420, 3430). In some embodiments, since the display panels according to one embodiment of the present invention can be extended in various directions as described above, they can be assembled to a body frame having a hemispherical shape, and thus the robot (3400) may include a hemispherical display unit (3420, 3430).

[0302] FIG. 19e illustrates a vehicle display device (3500) as another electronic device in one embodiment of the present invention. The vehicle display device (3500) may include a cluster (3510), a Center Information Display (CID) (3520), and / or a passenger display. Since the display panel according to the embodiment of the present invention can be extended in various directions, it can be used for the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display without being constrained by the shape of the vehicle's internal frame.

[0303] FIG. 19e illustrates the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display being separated, but the invention is not limited thereto. In another embodiment, two or more selected from the cluster (3510), the Center Information Display (CID) (3520), and the co-driver display may be connected as a single unit.

[0304] In some embodiments, the vehicle display device (3500) may include a button (3540) capable of displaying a predetermined image. Referring to the enlarged view of FIG. 19e, the hemispherical button (3540) may include an object (3542) that provides a sense of use of the button while moving in the z-direction or -z-direction, and a display device placed on the object (3542). In some embodiments, if the object (3542) has a three-dimensionally rounded surface (e.g., a convex surface), the display device may also have a three-dimensionally rounded surface (e.g., a convex surface).

[0305] FIG. 19f illustrates that an electronic device according to one embodiment of the present invention is an electronic device for advertising or display (3600). In some embodiments, the electronic device for advertising or display (3600) may be installed on a fixed structure (3610), such as a wall or a column. If the structure (3610) includes an uneven surface as shown in FIG. 19f, the electronic device for advertising or display (3600) may also be placed along the uneven surface of the structure (3610). In some embodiments, the electronic device for advertising or display (3600) may be installed on the structure (3610) using a heat-shrink film or the like.

[0306] FIG. 19g illustrates that an electronic device according to one embodiment of the present invention is a controller (3700). The controller (3700) may include an image-type button. For example, the controller (3700) may include first to third button areas (3720, 3730, 3740) in which a portion of the display portion (3710) protrudes in the z-direction or protrudes in the -z-direction (or is recessed in the z-direction). In some embodiments, the first and third button areas (3720, 3740) may protrude in the z-direction, and the second button area (3730) may protrude in the -z-direction (or be recessed in the z-direction).

[0307] Although the present invention has been described with reference to an embodiment illustrated in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A method for manufacturing a display panel comprising a pixel region and a connecting region surrounding the pixel region, A step of forming a lower layer including a substrate; A step of forming a pixel circuit layer including an inorganic insulating layer and a pixel circuit so as to overlap with the pixel region on the lower layer; A step of removing a portion of the above-mentioned inorganic insulating layer that overlaps with the above-mentioned connection region; A step of forming a light-emitting diode on the pixel circuit layer; A step of forming a connection wiring that overlaps with the connection area using a sacrificial layer; and A method for manufacturing a display panel comprising the step of removing the sacrificial layer.

2. In Paragraph 1, A method for manufacturing a display panel in which the sacrificial layer comprises a hydrophobic material.

3. In Paragraph 1, A method for manufacturing a display panel, wherein the step of removing the sacrificial layer includes removing the sacrificial layer through a cleaning process using water.

4. In Paragraph 1, The step of forming the pixel circuit layer above is, The method includes the step of forming a signal line electrically connected to the pixel circuit. A method for manufacturing a display panel in which the signal line disposed in the pixel area extends to the connection area and comes into direct contact with the connection wiring.

5. In Paragraph 4, The above signal line is, A method for manufacturing a display panel, wherein the gate line extending along a first direction or the data line extending along a second direction intersecting the first direction.

6. In Paragraph 1, The step of forming a connecting wire that overlaps with the connecting area using the above sacrificial layer; is, A step of forming the sacrificial layer having a first opening defined that overlaps with the above connection area; and A method for manufacturing a display panel, comprising the step of forming a connecting wire in an area overlapping with the first opening.

7. In Paragraph 6, Between the step of forming the light-emitting diode and the step of forming the connecting wire, A step of inverting the display panel so that the upper and lower surfaces of the display panel are inverted; and The step of removing the lower layer; further comprising, A method for manufacturing a display panel, wherein the above sacrificial layer is formed on the bottom surface of the above pixel circuit layer.

8. In Paragraph 7, Between the step of forming the light-emitting diode and the step of inverting the display panel, The method further includes the step of forming an upper elastomer layer to cover the light-emitting diode; and A method for manufacturing a display panel, wherein the above connecting wires are disposed on the bottom surface of the upper elastomer layer.

9. In Paragraph 7, After the step of removing the above-mentioned sacrificial layer, A method for manufacturing a display panel, further comprising the step of forming a lower elastomer layer disposed on the bottom surface of the pixel circuit layer and covering the connection wiring.

10. In Paragraph 6, The steps of forming a connection wiring that overlaps with the connection area using the sacrificial layer and removing the sacrificial layer are: This is performed between the step of forming the pixel circuit layer and the step of forming the light-emitting diode, and A method for manufacturing a display panel, wherein the above sacrificial layer is formed on the upper surface of the above pixel circuit layer.

11. In Paragraph 10, The step of forming the lower layer includes the step of forming a base layer on the substrate; A method for manufacturing a display panel, wherein the above connecting wiring is defined in the base layer and disposed within a second opening that overlaps with the first opening.

12. In Paragraph 11, A method for manufacturing a display panel, wherein the second opening exposes the upper surface of the substrate.

13. In Paragraph 11, A step of detaching the above substrate; and A display panel further comprising the step of forming a lower elastomer layer on the bottom surface of the base layer and the bottom surface of the connecting wire.

14. In Paragraph 11, The step of forming the lower layer further includes the step of forming a lower elastomer layer interposed between the substrate and the base layer. A method for manufacturing a display panel, wherein the second opening exposes the upper surface of the lower elastomer layer.

15. In Paragraph 10, A method for manufacturing a display panel, further comprising the step of forming an upper elastomer layer to cover the light-emitting diode and the stretched wiring.

16. In Paragraph 6, The steps of forming a connection wiring that overlaps with the connection area using the sacrificial layer and removing the sacrificial layer are: A method for manufacturing a display panel, performed between the step of forming the lower layer and the step of forming the pixel circuit layer.

17. In Paragraph 16, The step of forming the lower layer comprises the step of forming a lower elastomer layer on the substrate; A method for manufacturing a display panel, wherein the sacrificial layer and the connecting wiring are formed on the lower elastomer layer.

18. In Paragraph 1, The step of forming a connecting wire that overlaps with the connecting area using the above sacrificial layer; is, A step of forming a sacrificial layer on the lower layer; A step of forming a sub-elastomer layer patterned to overlap with the connection region on the sacrificial layer; and A method for manufacturing a display panel, comprising the step of forming the connecting wire on the upper surface of the sub-elastomer layer.

19. In Paragraph 18, A method for manufacturing a display panel, further comprising the step of forming a lower elastomer layer on the bottom surface of the pixel circuit layer and the bottom surface of the sub-elastomer layer after the step of removing the sacrificial layer.

20. A display panel including a pixel area and a connection area surrounding the pixel area; and It includes a lower cover that forms an exterior and has an opening that exposes a portion of the display panel on the front surface; and The above display panel is, Lower elastomer layer; A pixel circuit layer disposed on the lower elastomer layer and comprising an inorganic insulating layer and a pixel circuit so as to overlap with the pixel region; A light-emitting diode disposed on the pixel circuit layer above; and A connecting wire disposed on the lower elastomer layer and overlapping with the connecting area; comprising The pixel circuit layer includes a signal line electrically connected to the pixel circuit, and An electronic device in which a signal line placed in the pixel area extends to the connection area and comes into direct contact with the connection wiring.

Images