Scalable qubit arrays with merged barrier gate

Abstract

Barrier-gate configurations for quantum-dot structures are disclosed, as well as methods to operate quantum-dot structures provided with such barrier-gate configurations and methods to fabricate quantum-dot structures provided with such barrier-gate configurations. The quantum-dot structure (300) comprises a quantum-dot array, e.g., a two-dimensional quantum-dot array or a three-dimensional quantum-dot array. Each quantum dot (304) in the quantum-dot array is provided with a plunger gate (106). The quantum-dot structure further comprises a plurality of barrier gates (108, 308), each barrier gate of the plurality of barrier gates separating two neighbouring quantum-dots in the quantum-dot array. The barrier gates are arranged in lines and at least two of the lines are galvanically connected. Since the barrier gate lines are interconnected, the number of barrier gate lines to be connected may be independent from the number of qubits.

Description

[0001] W040460 / SV-TD

[0002] Scalable qubit arrays with merged barrier gate

[0003] Technical field

[0004] This disclosure relates to quantum-dot structures, and in particular, though not exclusively, to barrier gate configurations for quantum-dot structures, to a method for operating such quantum-dot structures, and to a method of fabricating such quantum-dot structures.

[0005] Quantum computing is fundamentally different than classical computing. The quantum computer’s structure gives access to quantum-mechanical properties such as superposition and entanglement which are not available to classical computers. For certain problems, quantum computers offer drastic computational speed-up, ranging from quadratic acceleration of searching unstructured data, to exponential improvements for factoring large numbers used in encryption applications. Quantum computing is based on qubits. Qubits can be formed, for example, by a single particle spin in a so-called quantum dot, wherein the particle is typically either an electron or a hole. In each quantum dot, a qubit (or more generally, qudit) may be created. Quantum dots not containing a qubit may be referred to as empty.

[0006] Systems with larger amounts of (interconnected) qubits can execute more complicated algorithms, or can execute algorithms more efficiently than systems with fewer qubits. Practically speaking, these qubits are arranged on a two-dimensional array. However, current designs for qubit arrays are typically poorly scalable in more than one dimension. It is therefore desirable to create scalable two-dimensional arrays for individually addressable qubits.

[0007] It is generally desirable to have closely spaced quantum dots, as the interaction strength between two qubits generally depends on the distance between those qubits. However, it is very challenging to physically fit all control electronics for the qubits close together in a scalable layout.

[0008] In general, both the number of plunger gates and the number of barrier gates scales polynomially with the number of quantum dots. Consequently, also the electrodes for applying a voltage to the gates and the control electronics for controlling the gates scales as a polynomial of the number of quantum dots. Assuming a square array of N quantum dots, wherein all plunger gates and barrier gates are individually controllable, the total number of controllable gates scales as 3N.

[0009] US 11721725 B2 describes a quantum dot device with barrier gate lines in a first direction in a first layer and quantum dot lines in a second direction, perpendicular to the first direction, in a second layer. Consequently, the number of both barrier gates and plunger gates scales only as o(V v). However, control over the quantum dots is limited, and implementing two-qubit gates would require a high level over control in both the time domain and the voltage domain, for both the barrier gate lines and the quantum dot lines. Moreover, due to the limited amount of control lines, it is not possible to implement two-qubit gates between any arbitrary combination of neighbouring qubits simultaneously. Instead two-qubit operations generally need to be performed sequentially.

[0010] There is therefore a need in the art for a device and method for a scalable quantum dot layout, while maintaining a sufficient degree of controllability over the qubits, possibly even individual qubit control.

[0011] Summary

[0012] It is an aim of embodiments in this disclosure to provide a device and method that avoids, or at least reduces the drawbacks of the prior art.

[0013] In a first aspect, this disclosure relates to a quantum-dot structure comprising a two- dimensional quantum-dot array or a three-dimensional quantum-dot array. Each quantum dot in the quantum-dot array is provided with an individually controllable plunger gate. The plunger gate may be configured to control a qudit in the quantum dot. The quantum-dot structure further comprises a plurality of barrier gates, each barrier gate of the plurality of barrier gates separating two neighbouring quantum-dots in the quantum-dot array. The barrier gates are arranged in galvanically connected lines and at least two of the galvanically connected lines are galvanically connected with each other.

[0014] A three-dimensional quantum-dot array may comprise two or more layers of two- dimensional quantum-dot arrays.

[0015] As used herein, a barrier gate is a gate to which a controllable voltage can be applied, which controllable voltage controls an interaction between qudits (typically qubits) in neighbouring quantum dots on opposing sides of the barrier gate, or between a qubit and an empty quantum dot on opposing sides of the barrier gate. A line of barrier gates refers to a plurality of electrically connected barrier gates in a straight or crooked line. Barrier gates that are galvanically connected have substantially the same voltage and can be controlled by a single control signal. Hence, they interact in substantially the same way with neighbouring qudits. Such galvanically connected barrier gates may be referred to as a barrier having a shared barrier gate voltage, or for short, a shared barrier or a merged barrier gate.

[0016] By electrically connecting the barrier gates, substantially fewer feed lines are needed. In an architecture with individually controllable barrier gates in a rectangular lay-out, about two barrier gates are needed for each quantum dot. As chips are substantially two- dimensional structures, the feedlines for these barriers are limited by the space on the ‘sides’ of the quantum-dot array, and the manufacturing size. A more three-dimensional solution using vias, is more expensive, more error-prone, and typically requires larger structures.

[0017] The embodiments described herein use only a constant number of barrier gates, independent of the number of quantum dots. By drastically reducing the number of individually controllable barrier gates, less physical space is needed, and lower demands are placed on the control electronics. The control electronics are typically limited in the number of channels that can be controlled simultaneously. This, in turn, leaves more space (both physical space and control space) for individually controllable plunger gates.

[0018] It is furthermore noted that by increasing the scalability, quantum-dot structures with larger numbers of quantum dots can be fabricated, which in turn allows to leave a substantial fraction of quantum dots empty, using so-called sparse qubit arrays. Sparse qubit arrays are described in more detail by J.M. Boter et al., ‘A sparse spin qubit array with integrated control electronics’, 2019 IEEE International Electron Devices Meeting, IEDM 2019 (2019).

[0019] In an embodiment, an amount of independently controllable barrier gates is independent of an amount of quantum dots in the quantum-dot structure. Thus, the amount of independently controllable barrier gates can be a constant number. For example, the amount of independently controllable barrier gates can be one, two, three, or four. A single independently controllable barrier gate (or barrier grid) can be fabricated in a single layer. Two, three, or four independently controllable barrier gates can be fabricated in two layers. In such an embodiment, the amount of space needed for the electrodes (feed lines) to control the amount of independently controllable barrier gates is also independent of the amount of quantum dots in the quantum-dot structure, and hence maximally scalable.

[0020] In an embodiment, the barrier gates are arranged in an electrically connected grid such that a voltage difference between the at least two lines is negligibly small. The grid can be a two-dimensional grid or a three-dimensional grid, e.g., the three-dimensional grid comprising two or more layers, each layer forming a two-dimensional grid. The grid may comprise all or substantially all barrier gates in the quantum-dot structure, or in a region of the quantum-dot structure.

[0021] As will be explained below in more detail, a global barrier gate can be beneficial for certain types of error correction, where the same computation must be performed by a large number of qubits, typically in a simultaneous manner. In an embodiment the barrier gates are arranged in two mutually orthogonal pluralities of lines. For ease of reference, these may be referred to as horizontal and vertical lines. In such an embodiment, all barrier gate lines in one direction may be electrically connected, or a substantial portion may be electrically connected, e.g., in an alternating fashion.

[0022] In an embodiment, the quantum-dot array comprises at least 16 quantum dots, at least 24 quantum dots, at least 32 quantum dots, at least 36 quantum dots, or even at least 64 quantum dots. For example, the quantum-dot array may be a rectangular array with a width of six, eight, ten, twelve, or more than twelve quantum dots, and a height limited only by other constraints, e.g., at least six, eight, ten, twelve, sixteen, 24, 32, 42, or 64 quantum dots.

[0023] In an embodiment, two neighbouring quantum dots in the quantum dot array have a pitch that is at most 500 nm, at most 200 nm, at most 150 nm, or at most 100 nm. For example, the pitch may be about 90 nm or 80 nm, or even smaller.

[0024] Typically, each plunger gate is individually controllable, or individually addressable. By changing the voltage of one or more plunger gates relative to that of the barrier gate, e.g., two neighbouring plunger gates, individual barrier gate control may be mimicked. This allows a high level of control over qubit interactions. Individually controllable plunger gates allow the control voltage in each quantum dot to be precisely controlled. This lowers manufacturing constraints on the individual quantum dots and plunger gates, as differences can be compensated for. In devices with shared plunger gate control, a high degree of manufacturing uniformity is required, because the control signals for each quantum dot on a shared line are necessarily the same.

[0025] In an embodiment, the two-dimensional quantum dot array is formed in a stack of one or more semiconductor layers arranged on a substrate. The quantum dot structure may further comprise a plurality of electrodes. The plurality of electrodes may be arranged to create and / or adjust an electric field, preferably a time-varying electric field, in the quantum dot structure. For example, the plurality of electrodes may be arranged to create and control qubits, e.g., Electric Dipole Spin Resonance (EDSR) controllable qubits, in the two- dimensional quantum dot array. However, other means of manipulating charge carriers, and in particular the spin of the charge carriers (e.g., to control qubits) are not excluded. Different embodiments may use different kinds of quantum dots, e.g., nitrogen-induced defects in e.g. semiconductor materials, nitrogen-vacancy centres in diamond, quantum dots based on a 2D electron gas or 2D hole gas, et cetera.

[0026] In a further aspect, embodiments in this disclosure relate to a quantum chip, preferably a quantum processing unit, comprising one or more quantum-dot arrays as described above. In an aspect, this disclosure relates to a method for operating a quantum-dot structure as described herein. The method comprises providing a plurality of qudits, preferably qubits, in a plurality of quantum dots in the quantum-dot array, each of the plurality of quantum dots comprising at most one qudit, and controlling a barrier gate voltage and / or one or more plunger gate voltages to cause at least two of the plurality of qudits to interact with each other.

[0027] In an embodiment, the qudits are provided in at most 50% of the quantum dots, e.g., in at most 25% of the quantum dots. The qudits may form a sparse qudit array. The qubits may be distributed approximately equally over the quantum-dot array. The qudits may be distributed such that at least most qudits do not have a neighbouring qudit at least part of the time or even at least most of the time. In other words, each qudit may be surrounded by empty quantum dots most of the time.

[0028] In an embodiment, the method further comprises: selecting a first qudit in a first quantum dot provided with a first plunger gate having a first voltage and a second qudit in a second quantum dot provided with a second plunger gate having a first voltage, the first and second quantum dots being separated by a third quantum dot provided with a third plunger gate having a third voltage, the third quantum dot neighbouring both the first and second quantum dots, the third quantum dot being empty; and controlling a first voltage of the first plunger gate to shuttle the first qudit to the third quantum dot.

[0029] This way, qudits in a sparse qudit array can be controlled to selectively interact with each other. Depending on the implementation, bringing two qudits in neighbouring quantum dots may be sufficient for the qubits to interact with each other. In other embodiments, a further control sequence may be required to control the interaction.

[0030] Hence, in an embodiment, the method further comprises controlling the second voltage of the second plunger gate and the third voltage of the third plunger gate, and / or the barrier gate voltage, to cause the first and second qudit to interact with each other.

[0031] In these embodiments, the interaction between the neighbouring qudits may be controlled by the voltage of the plunger gates relative to the voltage of the barrier gate separating the neighbouring qudits. Controlling the plunger gate voltages of the (in this case) first and third plunger gates may allow for selective interaction of the first and second qudits, without affecting pairs of qudits separated by a shared barrier. Controlling the (shared) barrier gate, on the other hand, allows all pairs of qudits separated by the shared barrier gate to interact simultaneously and in substantially the same way. This can be advantageous in, e.g., certain error correction schemes. In an embodiment, the method further comprises, after interaction of the first and second qubits during a predetermined duration, controlling the third voltage of the third plunger gate and the first voltage of the first plunger gate to shuttle the first qudit to the first quantum dot; or after interaction of the first and second qubits during a predetermined duration, controlling the third voltage of the third plunger gate and a further voltage of a further plunger gate belonging to a further quantum dot, the further quantum dot neighbouring the third quantum dot, the further quantum dot being empty, to shuttle the first qudit to the further quantum dot; or after interaction of the first and second qubits during a predetermined duration, controlling the third voltage of the third plunger gate and a further voltage of a further plunger gate belonging to a further quantum dot, the further quantum dot neighbouring the second quantum dot, the further quantum dot being empty, to shuttle the second qudit to the further quantum dot.

[0032] These alternatives all cause the first and second qudits to be no longer neighbouring. In the case of an ‘always on’ interaction, this ends the interaction between the first and second qudits. Moreover, by spatially separating the qudits, interference between the qudtis is much reduced, increasing their fidelity.

[0033] In a further aspect, embodiments of this disclosure relate to a method of fabricating a quantum-dot structure. The method comprises providing a quantum-well stack, providing a plurality of barrier gates defining a quantum-dot array, each barrier gate of the plurality of barrier gates separating two neighbouring quantum-dots in the quantum-dot array, and providing an individually controllable plunger gate for each quantum dot in the quantum-dot array. The plunger gate may be configured to control a qudit in the quantum dot. The barrier gates are arranged in galvanically connected lines and at least two of the galvanically connected lines are galvanically connected with each other. This way, a quantum-dot structure as described above may be fabricated. The steps may be performed in the described order, or in a different order. One or more such quantum-dot structures may be provided on a single quantum chip.

[0034] In an embodiment, providing the plurality of barrier gates comprises providing the plurality of barrier gates in a single layer, the plurality of barrier gates being arranged in a grid that is galvanically connected. Thus, this single layer may also comprise the galvanic connections between the barrier gates.

[0035] In an embodiment, providing the plurality of barrier gates comprises providing the plurality of barrier gates in exactly two layers, wherein the lines in a first direction are provided in a first layer of the two layers, and the lines in a second direction, different from the first direction, are provided in a second layer of the two layers. For example, the first and second directions may be orthogonal to each other. Each of these two layers may also comprise the galvanic connections between the barrier gates in that layer.

[0036] In an embodiment, providing the plurality of barrier gates comprises providing the plurality of barrier gates in exactly two layers, wherein the lines in a first layer of the two layers define a first galvanically connected grid of barrier lines and the lines in a second layer of the two layers define a second galvanically connected grid of barrier lines, the second galvanically connected grid of barrier lines being galvanically separated from the first galvanically connected grid of barrier lines, and the second galvanically connected grid of barrier lines being shifted relative to the first galvanically connected grid of barrier lines. For example, the first and second grid may have a spacing that is twice the spacing between the quantum dots. Each of these two layers may also comprise the galvanic connections between the barrier gates in that layer.

[0037] As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system”. Functions described in this disclosure may be implemented as an algorithm executed by a microprocessor of a computer. Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied, e.g., stored, thereon.

[0038] The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. Brief of the

[0039] The embodiments will be further illustrated with reference to the attached schematic drawings, in which:

[0040] Fig. 1 depicts a schematic of a cross-section of a typical large-area two-dimensional quantum dot structure;

[0041] Fig. 2A-2G schematically show examples of galvanically connected lines of barrier gates according to various embodiments;

[0042] Fig. 3A-C schematically show examples of sparse qubit arrays;

[0043] Fig. 4A and 4B schematically show methods for controlling exchange interaction between neighbouring qubits in a quantum structure with a merged barrier gate according to various embodiments;

[0044] Fig. 5A-E schematically depict a top view and various cross-sections of a chip according to an embodiment;

[0045] Fig. 6A-C are microscopy images of a merged barrier grid and of a chip according to an embodiment;

[0046] Fig. 7A and 7B are flowcharts of a method for operating a quantum-dot structure according to various embodiments; and .

[0047] Fig. 8 is a flowchart of a method of fabricating a quantum-dot structure according to an embodiment.

[0048] In the figures, identical reference number indicate identical or at least similar elements.

[0049] Detailed description

[0050] The embodiments in this disclosure aim to provide a scalable two-dimensional or three-dimensional array of quantum structures, e.g. quantum dots, formed in one or more semiconductor layers, wherein barrier gates separating these quantum structures are arranged in galvanically connected (straight or crooked) lines — typically deposited in a single layer of a semi-conductor device — , several of which lines are galvanically connected, or merged, and hence share control electronics. Thus, the number of individually controllable barrier gates is generally constant, independent of the number of quantum dots or qubits; in very large implementations, separate regions may be used, with, e.g., tens to hundreds of quantum dots sharing a constant number (e.g., one to four) of merged barrier gates.

[0051] The merged barrier gate lines may be parallel or in mutually different directions, e.g., perpendicular to each other. This reduces the spatial demands of the array, without undue limitation of performance parameters. The quantum structures may be individually addressable using individually controllable plunger gates, so that each quantum structure can be reliably operated as a qubit. The examples hereunder are described with reference to gate-induced and lateral gate-defined quantum dot structures in semiconductors; however, embodiments not limited to such quantum dot structures are also envisaged. In general, the described shared-barrier configurations can be applied to any type of quantum structure that is sensitive to local electric fields and / or local electric field gradients.

[0052] The barrier gates are galvanically connected within the quantum structure (i.e. , on chip).

[0053] Fig. 1 depicts a schematic of a cross-section of a typical large-area two-dimensional quantum dot structure. The quantum dot structure comprises an array of quantum dot regions HO1-3 which can be configured, for example, as qubits. Quantum dots are tiny regions of conducting material in an environment of insulating material. Different types of quantum dots may be envisaged, e.g., quantum dots formed in a stack of semiconductor layers 104 in which a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) is formed, i.e., a thin (~10 nm) sheet of electrons or holes that can only move along an interface between two semiconductor layers. Such a stack of semiconductor layers may also be referred to as a quantum-well stack. The quantum dots can be defined in this 2D electron or hole gas using electric charges applied by gates. Because of the small size of these quantum dots (lateral size typically 10-200 nm, depending on the materials used), it takes a finite (non-zero) charging energy to add an extra charge carrier (e.g., electron or hole) to the quantum dot, due to Coulomb repulsion. A sufficiently large charging energy allows to control the number of electrons (or holes) confined in a quantum dot accurately down to the single-electron regime. For ease of reference, the following generally assumes a electrons in a 2DEG, but is equally applicable to holes in a 2DHG.

[0054] Furthermore, the small size of the quantum dots also causes the orbital levels of electrons in the quantum dots to be quantized, leading to behaviour that is similar to electron shells in atoms. The quantum states of a quantum dot, e.g. the spin state of a single charge carrier such as an electron or a hole in the quantum dot, may be used to configure and operate a quantum dot as a qubit. Quantum dots with more than two quantum states may be operated as qudits (having d quantum states, d being an integer number larger than 1), e.g., qutrits (having 3 quantum states). Although the examples presented herein primarily refer to qubits, other quantum dot usages are similarly envisaged.

[0055] Typically, in order to create lateral gate-defined quantum dots, first a two-dimensional electron gas (2DEG) is formed by confinement at an interface in a heterostructure. Band gap differences between materials in the heterostructure result in strong confinement in the vertical direction, which yields quantization of the electron motion perpendicular to the interface. The 2DEG may be supplied with electrons from a doping layer in the heterostructure (depletion-mode quantum dots) or induced by accumulation gates (accumulation-mode quantum dots). An example of such a system is gallium arsenide / aluminium gallium arsenide (GaAs / AIGaAs). Suitable silicon-compatible systems for forming quantum structures include silicon-germanium (SiGe) heterostructures and silicon metal-oxide-semiconductor (SiMOS) structures. Examples of such structures are describe in the article by Lawrie et al, Quantum Dot Arrays in Silicon and Germanium, Appl. Phys. Lett. 116, 080501 (2020), which is hereby incorporated by reference.

[0056] For example, in an embodiment, the semiconductor layer stack may include a Silicon substrate, an intrinsic Silicon layer, an isotopically purified Silicon (28Si) epitaxial layer and a SiO2 layer. In another embodiment, the semiconductor layer stack may include a Si / SiGe heterostructure formed on a Silicon substrate, wherein the Si / SiGe heterostructure may include a graded Sii.xGexlayer and an isotopically purified Silicon (28Si) epitaxial layer between two SiGe layers. In another embodiment, the semiconductor layer stack may include a Ge / SiGe heterostructure formed on a Silicon substrate, wherein the Ge / SiGe heterostructure includes a Germanium layer formed on the Silicon substrate followed by a reversed graded Sii.xGexand a Ge epitaxial layer between two SiGe layers. Other suitable systems for forming quantum structures include nanowires, hut wires, self-assembled quantum dots, etc.

[0057] After forming the 2DEG, fine gate electrodes on top of the heterostructure allow to locally tune the potential landscape in the 2DEG by setting the gate voltages, thereby forming quantum dots that are isolated from other dots and the reservoirs by tunnel barriers. The regions in which quantum dots may be formed by application of a voltage, may be referred to as quantum dot regions. The same gate electrodes can be used to control the number of electrons in the quantum dots. A quantum dot array comprises a plurality of such quantum dots. Each quantum dot may be created in a quantum dot region. The quantum dot regions may be arranged, for example, in a regular array of k rows and I columns (with k and I being integer numbers larger than one). The structure may be described using a Cartesian coordinate system, wherein conventionally, the in-plane coordinates are defined as the x and y coordinates.

[0058] In the example depicted in Fig. 1A, the quantum dot structure further comprises plunger gate electrodes 105I-3, wherein each electrode may control one or more quantum dots, e.g., a row (or column) of quantum dots (in a direction orthogonal to the depicted quantum dots), in the quantum dot array. In other embodiments, each plunger gate may be controlled by a dedicated electrode; more complicated arrangements are also contemplated. It is noted that the figure only shows a small part of the quantum dot array, which may comprise a large number of quantum dot regions HO1-3. The figure includes one or more semiconductor layers 104 arranged on a substrate 102. The electrode structures for forming and controlling a plurality of quantum dot regions in the one or more semiconductor layers may be formed over the one or more semiconductor layers. The substrate and the one or more semiconductor layers may form a layered semiconductor stack that is suitable for the formation of quantum dot arrays.

[0059] The electrode structures may be electrically isolated from the semiconductor layers by one or more insulating layers 103 between the semiconductor layers and the electrode structures. The electrode structures may include a plurality of plunger gates IO61-3, in this example connected to a plurality of gate electrodes 105i-3. In other embodiments, some of the plunger gates may have shared gate electrodes. The gate electrodes galvanically connect the plunger gates to a controller 116, which is connected to a voltage source 107. By applying a suitable voltage to the gate electrodes, quantum dot regions HO1-3, e.g., quantum wells, may be formed under the respective plunger gates in the one or more semiconductor layers in which charge carriers (e.g., electrons and / or holes) are laterally confined. The voltages of the plunger gates may be tuned such that a quantum well is formed under one or more of the plunger gates. The plunger gate voltages may be tuned such that exactly zero or exactly one charge carrier 112I-3 (e.g., an electron or a hole) is confined in each quantum well, depending on the desired occupancy of the quantum dot. This voltage will typically determine the working voltage of the quantum dots, which may be manipulated to execute single- or multi-qubit gates.

[0060] Each charge carrier 1121-3 may be trapped in a potential well which is separated from neighbouring potential wells by barrier potentials located between the quantum dot regions. The height of the potential barriers 114I,2 may be controlled by barrier gates IO81-4 which, in the depicted example, are connected to a common barrier electrode 111 to control barrier electrodes between the quantum dots, thus forming a line of barrier gates. As described in more detail below with reference to Fig. 2A-G, at least two such lines of barrier gates may be galvanically connected. This reduces the ‘real estate’ required to control the barrier gates. In other embodiments, different groups of barrier gates, or even all barrier gates may be galvanically connected to each other. The barrier electrode connects the barrier gates to a barrier voltage source \4 109 (either directly or through a controller), which can be configured to control the barrier height 114I,2. For example, lowering the voltage may lower the barrier, so that charge carriers configured as qubits may interact with each other. As will be discussed in more detail below, the barrier gate voltage(s) may be determined in interdependence with the plunger gate voltages.

[0061] The electron is a spin-1 particle, and therefore, a single electron in a quantum dot can form a quantum mechanical two-level system (or an approximation thereof), defined by the electron spin-up and spin-down states. The spin of an electron is an intrinsic angular momentum giving rise to a magnetic dipole moment. The magnitude of this dipole moment is given by the Bohr magneton B. AS a result, an external magnetic field Bext splits the spin-up and spin-down states in energy due to the Zeeman effect. Similar considerations apply to holes, which can be considered spin-3 / 2 particle, and which also have angular momentum states that can define a spin-up and spin-down system that is split in energy by the external magnetic field due to the Zeeman effect. Hence, when reference is made herein to an electron, a hole may be read as well, and vice versa.

[0062] The spin states of an electron or hole in a magnetic field may serve as the computational basis states of a qubit in what is referred to as a single-spin qubit. The singlespin qubit is the simplest form of a spin qubit, but several other implementations of spin qubits exist, which employ spin states of more than one electron or hole in more than one quantum dot to define a qubit. In contrast with the single-spin qubit, all other types of spin qubits constitute an effective pseudo-spin two-level system. Examples of other spin qubit implementations are a singlet-triplet qubit (two spins in two dots), a hybrid qubit (three spins in two dots), an (always-on) exchange-only qubit (three spins in three dots), as well as a quadrupolar exchange-only qubit (four spins in three dots). All these spin-qubit implementations attempt to mitigate certain decoherence mechanisms or to reduce the experimental requirements at the expense of complexity. In general, using spin states as basis states for a qubit has the advantage of long coherence times, compared to for example a charge qubit, because spin does not interact directly with electric noise. However, spinorbit coupling does provide an indirect coupling, which still causes decoherence, albeit less than for charge qubits. With a reduced effect of electrical noise sources, the hyperfine interaction is also a relevant decoherence mechanism for spin qubits.

[0063] Fig. 2A-2G are examples of galvanically connected lines of barrier gates according to various embodiments. All examples show a two-dimensional array of 6x6 quantum dot regions 210, except for Fig. 2D which shows a ‘skewed’ configuration with alternating rows of 4 and 5 quantum dot regions 200. Other embodiments may use different sizes, or different configurations, e.g., triangular or hexagonal configurations. In some embodiments, the quantum-dot array may be substantially longer in one direction than in the other direction. For example, the quantum-dot structure may be constrained to a limited number of quantum dots in a first direction, e.g., 6, 8, 10, 12, or 16 quantum dots, while being substantially freely scalable in a second direction. In these figures, identically shaded areas represent areas that are galvanically connected and have substantially identical voltages, whereas different shading represents areas that are not galvanically connected and may be controlled separately.

[0064] In particular, Fig. 2A shows a 2D grid 202 wherein all barrier gates are galvanically connected. In this context, a grid refers to a structure comprising lines of barrier gates in different directions, typically orthogonal directions (in this case: horizontal and vertical). This configuration has the lowest spatial footprint, as all structure can be applied in a single plane, greatly simplifying production and the three-dimensional chip layout. Moreover, generally, only a single electrode (not shown) is needed for applying a voltage to the grid. In some embodiments, multiple electrodes may be used, e.g., for symmetry reasons.

[0065] Fig. 2B shows a plurality of non-overlapping 2D grids 204I,2, where each grid covers a part of the quantum-dot structure.

[0066] Fig. 2C shows a configuration where the barrier gate lines are connected in an alternating manner, resulting in four sets 206-212 of galvanically connected barrier gate lines. These may be referred to as ‘vertical odd’ 2O61-4, ‘vertical even’ 2O81-3, ‘horizontal odd’ 2IO1-4, and ‘horizontal even’ 212I-3. Such a configuration allows for a relatively large degree of control, as each quantum dot is surrounded by four separately controlled barrier gates.

[0067] Fig. 2D shows a skewed configuration, wherein the barrier gate lines 214 in a first direction are galvanically connected to each other and galvanically separated from the barrier gate lines 216 in a second direction, in this case orthogonal to the first direction. Similarly, the barrier gate lines 216 in the second direction are also galvanically connected to each other.

[0068] The barrier gate lines (in, e.g., Figs. 2C and 2D) that are galvanically connected may be connected, e.g., through vias (allowing, e.g., connections to a plane parallel to the shown plane) or through structure outside the quantum dot array, e.g., analogous to the connections shown in Figs. 2E and 2F. It is noted that although in these examples the electrodes are shown on the side, it may be advantageous to position them somewhere else, e.g., in or near the centre, or on top in a different layer.

[0069] Fig. 2E shows a configuration wherein first barrier gate lines 218 in a first direction are galvanically connected to each other through an electrode 222. The first barrier gate lines in the first direction are galvanically separated from second barrier gate lines 220 in a second direction, in this case orthogonal to the first direction. Similarly, the second barrier gate lines 220 in the second direction are also galvanically connected to each other through an electrode 224. The electrodes 222,224 may be galvanically connected to a controller configured to apply a first voltage to the first barrier gate lines and, possibly independently, a second voltage to the second barrier gate lines.

[0070] Fig. 2F shows a configuration which is very similar to the one shown in Fig. 2E, in that all horizontal lines are galvanically connected and galvanically separated from the vertical lines, which are also galvanically connected. In this example, however, the horizontal and vertical lines are connected in a meandering pattern.

[0071] Fig. 2G shows a configuration in which the odd horizontal lines are galvanically connected to each other and to the even vertical lines, whilst being galvanically separated from the even horizontal lines and the odd vertical lines, which are also galvanically connected to each other. Thus, essentially two grids are formed, each with a grid period twice the period of the quantum dots in the quantum-dot array, and offset by half a grid period. Each such grid may be deposited in a single layer.

[0072] It is noted that although in the examples depicted in Fig. 2A-G all lines formed by the merged barrier gates are straight, other embodiments may have ‘crooked’ lines, e.g., going essentially diagonally by alternating horizontal and vertical segments. Crooked lines may also appear, for example, in triangular or hexagonal arrays. Many other variations and combinations will be readily apparent to the skilled person.

[0073] One advantage of a quantum-dot structure with merged barrier gates as described herein is that the fabrication is relatively simple: because the barrier gates are merged, they can be deposited in a single layer for embodiments such as those shown in Fig. 2A and 2B; or two layers (not counting any isolating layers that may be used to separate the barrier gate layers) for the embodiments shown in Fig. 2C-G. Moreover, each galvanically connected part of the barrier gate structure can be deposited in a single layer, removing or at least strongly diminishing the need for vias and simplifying fabrication, in particular in comparison with individually controllable barrier gates.

[0074] Furthermore, merging barrier gate lines reduces the number of separately controllable barrier gates, in the examples of Fig. 2A-G to one to four separately controllable barrier gates (possibly per region of the quantum-dot structure). This simplifies the control of the barrier gate voltage, and requires fewer voltage control lines connecting the barrier gates to a controller. This simplifies both the fabrication and the control electronics of the resulting quantum-dot structure.

[0075] Another advantage of a (scalable) system with one or more merged barriers, is that such a system may reduce the overhead of quantum error correction. Many quantum-error correction algorithms require execution of identical two-qubit operation on large numbers of (pairs of) qubits simultaneously. As described in more detail below with reference to Fig. 4, a merged barrier gate allows to execute such a parallel operation with a single control voltage.

[0076] Finally, the scalability resulting from the merged barrier gates allows for quantum-dot arrays containing larger numbers of quantum dots, which in turn enable sparse qubit array with sufficient numbers of qubits. A sparse qubit array increases the connectivity of the qubits, as qubits can be moved around to interact with large numbers of (different) qubits. This is advantageous for, e.g., quantum error correction. For example, for surface codes, sparse qubit arrays as depicted in Fig. 3A-C open up the opportunity to apply transversal gates, which have recently been demonstrated experimentally in a cold atom array. Furthermore, this high connectivity enables higher encoding rate low-density parity check (LDPC) codes. In particular, this connectivity can be achieved through integrated shuttling lanes 306 which allow, in principle, any pair of qubits to be brought together to interact. In addition, the native integration of empty quantum dots in a sparse qubit array allows for the execution of shuttling-based gates. This in turn leads to a lower magnetic field strength and hence higher coherence times and a higher two-qubit gate fidelity. Shuttling is described in more detail in Van Riggelen-Doelman et al., ‘Coherent spin qubit shuttling through germanium quantum dots’, Nature Communications 15 (2024) article 5716, which is hereby incorporated by reference in its entirety. Shuttling-based gates are described in more detail in Wang et al., ‘Operating semiconductor quantum processors with hopping spins’, Science, Vol. 385:6707 (2024), pages 447-452, which is hereby incorporated by reference in its entirety.

[0077] In the embodiments described herein, these high fidelities are combined with reduced crosstalk and reduced residual exchange associated with a spatially separated sparse qubit array. Fig. 3A-C provide examples of sparse qubit arrays. In particular, Fig. 3A-C depict a 6x6 quantum dot array with a merged barrier grid 300 similar to the one depicted in Fig. 2A. Other embodiments may use different barrier gate configurations In the sparse array distributions depicted in Fig. 3A and 3B, a unit cell 308 hosting a single qubit 302 is formed by four distinct quantum dots 304. In the sparse array distribution depicted in Fig. 3C, each unit cell 308 comprises two qubits 302 and two empty quantum dots 304.

[0078] While operating the qubits 302, they are positioned in neighbouring quantum dots 304 to minimise exchange interaction. During shuttling-based single-qubit gates, the qubits are never neighbouring, and when a qubit is shuttled, integrated shuttling lanes 306,3161,2 can be formed by moving other qubits to the side. Only during two-qubit gates, neighbouring dots are occupied, as the qubits are intentionally shuttled to neighbouring quantum dots to execute entangling operations. During the execution of shuttle-based single qubit gates, as well as during shuttling through the qubit array, no qubit is ever directly neighbouring another qubit. This reduces unwanted cross-talk and residual coupling. The resulting physical qubit operations are expected to surpass the fidelity threshold of surface codes and recent LDPC codes.

[0079] Evidently, other known control methods may also be used, e.g., electric dipole spin resonance (EDSR). EDSR may be implemented, for example, by subjecting a particle to an effective oscillating magnetic field by moving the particle back and forth in a spatially varying magnetic field (i.e., a magnetic field with a non-zero magnetic field gradient), thereby driving spin transitions if the frequency of the oscillating motion matches the energy difference between the spin-up and spin-down states. In that case the coupling is indirect, via the charge of the electron.

[0080] Another control option is based on electron-spin resonance (ESR), which may be implemented by applying an oscillating magnetic field to the particle, e.g., by passing an alternating current with a suitable frequency through an on-chip microwave strip-line close to the particle spin.

[0081] Despite the advantages of using a sparse array for error correction, an qubit array as displayed in Fig. 3A is challenged by additional electronic overhead using standard quantum structure layouts without merged barriers. Naively increasing the number of qubits following a typical gate layout with individually controllable barriers, would lead to NG= 3 NqNDmetallic gates in a sparse array. Here, Nqis the total amount of qubits and NDis the number of quantum dots in a unit cell hosting a single qubit. Using an occupation as in Fig. 3A or 3B leads to ND= 4, resulting in 12 gates for each qubit assuming individual barrier control, which are spaced closely to each other. This is deemed infeasible due to fabrication and electronics limitations. Although it is possible to use a shared control approach such a shared control of the plunger gates will necessitate unwanted temporal overhead to perform operations.

[0082] In particular, when the neighbouring quantum dots are empty, individual control over the barrier gates is not required. Using a single barrier gate grid, forming the barrier between all quantum dots, not only reduces the total number of individual gates of the system by a factor of three to NG= NqND(ignoring charge sensors), but the remaining gates are plunger gates with a larger fabrication footprint. The resulting structure is considerably more scalable from a fabrication point of view compared to designs with separately defined (non-merged) barrier gates.

[0083] It is noted that the lower number of gates NGin implementations with shared barrier gates, does not hamper the ability to execute arbitrary single and two-qubit gates. In implementations with individually controllable plunger gates, this individual plunger gate control gives enough tunability to perform all desired operations. Various control methods may be used to execute gates on the qubits, such as EDSR or shuttling-based gates. As an example, in the following shuttling-based single-qubit gates are considered. While the tunnelcoupling indeed influences the adiabaticity of the shuttling operation, and hence the ability to initiate shuttling-based rotation, typically the ramp time provides sufficient control to perform the shuttling-based operation over a range of barrier gate voltages. Therefore, even with no fine-tuning of the tunnel coupling through the barrier gates, shuttling operations can still be achieved. Moreover, in a sparse qubit array the individual plunger gates can be used to modify the effective barrier between neighbouring quantum dots, as shown in Fig. 4A. After all, for the tunnel-coupling the height of the barrier is relative to the depth of the potential wells. As a result, qualitatively the same level of control over the quantum dots can be obtained as in an architecture with individually controlled barrier gates. This is a unique feature of the sparse array. In a densely populated array, on the other hand, lowering the potential well in which the hole resides could induce unwanted interdot transitions from the neighbouring quantum dots.

[0084] For non-sparse (dense) configurations, a merged barrier-gate configuration such as shown in Fig. 2C may be used, where interaction with the four neighbours of a quantum dot can be individually controlled. Additionally or alternatively, EDSR may be used to execute single-qubit gates. Other implementations can be readily envisaged.

[0085] Fig. 4A schematically shows a method for increasing exchange interaction between neighbouring qubits in a quantum structure with a shared barrier according to an embodiment. In panel (a), pulsing on the barrier 404 between two qubits 402I,2 will manipulate their mutual exchange interaction. In the depicted example, an alternating shared barrier is used, e.g., as depicted in Fig. 2C, so that adjusting the voltage on the barrier 404 does not affect the voltage on the barrier 406I,2. When considering just the depicted pair of qubits 402I,2, this behaviour is similar to that in a known quantum-dot structure with individually controllable barrier gates. However, it is noted that in this case, all qubit pairs in the quantum-dot structure that are separated by a barrier gate galvanically connected to barrier 404, would undergo the same interaction. Depending on the protocol being executed, this may be an advantage. In an embodiment with at least two independently controlled barrier gates alternating shared barriers, e.g., as depicted in Fig. 2C-F, pairs of qubits not intended to undergo the same interaction, may be moved such that they are separated by a barrier that is not galvanically connected to the barrier being operated.

[0086] In embodiments where barrier gates 404 and 406I,2 are galvanically connected, barriers 406I,2 would exhibit similar behaviour. In some cases, this may affect the shape of the signal applied to the shared barriers.

[0087] In panel (b), it is assumed that it is not desirable to adjust the (shared) barrier gate 404, for example because that would result in unwanted interaction between other pairs of qubits (not shown) which are separated by a galvanically connected barrier. Instead, individual control of the plunger gates 408I,2 is used to tune the effective barrier potential. Since the voltage on the plunger gates 410I,2 of the neighbouring (empty) quantum dots 412I,2 prevents transitions into these empty dots, this strategy is particular suitable for a sparse quantum-dot array. In a dense quantum-dot array, adjusting the plunger gates could lead to unwanted interactions with other neighbouring qubits.

[0088] In panel (c), barriers 404 and 406I,2 are galvanically connected, e.g., as depicted in Fig. 2A-B,D-F. As mentioned above, it is then still possible to pulse on this single shared barrier. This changes the exchange interaction in all neighbouring quantum dots. As the location of the qubits can be controlled through shuttling, this can be used to determine which qubits undergo the exchange interaction. The voltage on plunger gates 410I,2 on empty quantum dots can provide additional confinement. Furthermore, the plunger gates may compensate for local variation during these global two-qubit gates.

[0089] To perform two-qubit gates, the exchange interaction between the two qubits can be increased by spatially shuttling qubits closer together. The exact gate execution can happen in several ways. Fig. 4B (a) illustrates an example in which the exchange interaction is always on, so that a two-qubit gate is executed whenever two qubits 422I,2 are shuttled to be next to each other. In that case, the qubits can be brought together (allowing them to interact) for a desired (generally variable) amount of time. In this example, qubit 422i is shuttled to the empty quantum dot 432 by raising the voltage of plunger gate 426 (to cause the qubit to leave) and lowering the voltage of plunger gate 428 (to ensure the qubit ends up in the correct position). After the interaction, the qubit is shuttled back by increasing the voltage 428 and lowering the voltage 426. The voltage of plunger gate 430 and the voltage of the merged barrier gate 424 remain unaltered in this example. It is noted that the voltages here have an arbitrary scale and are shown schematically to illustrate the qualitative behaviour over time; no conclusions should be drawn about the relative magnitudes of these voltages.

[0090] Fig. 4B (b) illustrates an example in which the exchange interaction is tuned by the relative voltage in the region between the quantum dots, as in common implementations of two-qubit gates. In conventional implementation, this is typically achieved by adjusting the barrier gate voltage of the barrier gate separating the qubits 422I,2. casein the embodiments described herein, in particular those using a sparse qubit layout, the plunger gates 428,430 can be used to tune the tunnel coupling as described above with reference to Fig. 4A. In that case, the ability to perform smooth pulse shaping on each plunger gate would be advantageous.

[0091] Fig. 4B (c) illustrates an example similar to (b), but here, full advantage is taken of the merged barrier gate 424. After bringing the qubits together, a ‘global’ voltage 424 is applied on the shared barrier gate to increase the exchange coupling and execute the desired gate between all qubit pairs simultaneously. The tunnel-coupling generally will be different for different quantum dot pairs at a given global barrier gate voltage, which naively would result in a different unitary being executed for each pair. However, the barrier offset can be fine-tuned as before with the plunger gates 428,430. This fine-tuning may constrain the hardware less than performing smooth, large amplitude, pulses on each individual plunger gate. Such a scheme requires generating and calibrating the smooth envelope only for a small amount of barrier gates (down to only one gate for a barrier grid as shown in Fig. 2A), independent of the number of quantum dots or qubits (per operating block, for very large implementations). Meanwhile, the fine-tuning of the effective barrier height can be done on a local level, using the plunger gates, without the need to worry about the envelope. One benefit is that the electronics of the plunger gates can be optimized for short ramp times and smaller voltage ranges while having very high timing precision for high-fidelity shuttling gates. At the same time, the electronics controlling the barrier grid can be optimized over a larger voltage range, with smoother pulses, but with a smaller sampling rate. Thus, in such an implementation, the sharp pulses of the plunger gates may have a high timing precision, but a low voltage precision, while the pulses applied to the merged barrier gates could have a high voltage precision and a low timing precision. Combining high voltage precision with high timing precision for the same gate (e.g., a plunger gate or merged barrier gate) is difficult to realise and costly.

[0092] Shuttling may also be used for efficient readout and initialisation. For example, to initialise a qubit in a central location in the quantum dot array, two charges can be shuttled (no spin-coherence necessary) from reservoirs to the central location. The reservoirs may be located at the charge sensors outside the array, but can also be integrated inside the array in some designs. After any orbital excitations have decayed into a singlet ground state, the (0,2)— (1 ,1) charge transition can be crossed and both quantum dots will have a well-defined spin state. Both holes can be used as qubits, by separating them again to form the sparse array. For readout a well-defined ancilla qubit can be initialised close to a data qubit, similar to the method described for initialisation. Spin-to-charge conversion can be performed using Pauli Spin Blockade near the site of the data qubit. The charge state can then be shuttled towards a charge sensor (no spin-coherence necessary) to perform readout.

[0093] Fig. 5A-E schematically depict a top view and various cross-sections of a chip according to an embodiment. In particular, Fig. 5A schematically depicts a top view of a quantum dot structure 500 with some of the material removed to improve visibility of the underlying structures. Fig. 5B-E show cross-section through the same quantum dot structure 500 along, respectively, the lines marked B-B’ through E-E’ in Fig. 5A.

[0094] The figure includes a 5x5 quantum dot array with 25 plunger gates 5O61-25 which may be controlled to generate qubits in quantum dots regions 5IO1-25 (partially shown in Fig. 5C and 5E). The plunger gates are controlled with plunger gate electrodes 505I-25. The quantum-dot regions are separated by barrier gates 5O81-4. The barrier gates are controlled using barrier gate electrodes 5111-4. Barrier gates and barrier gate electrodes with the shame shading are galvanically connect, and barrier gates with different shading are galvanically separated. In other embodiments, there can be more or fewer merged barrier gates, for instance a single barrier grid.

[0095] The quantum-dot structure furthermore includes one or more semiconductor layers 504 (also referred to as a quantum-well stack) arranged on a substrate 502. The plunger gates 5061-25 and barrier gates 5O81-4 for forming and controlling a plurality of quantum dot regions 5IO1-25 in the one or more semiconductor layers may be formed over the one or more semiconductor layers. The substrate and the one or more semiconductor layers may form a layered semiconductor stack that is suitable for the formation of a quantum-dot array. The electrode structures may be electrically isolated from the semiconductor layers by one or more insulating layers 503 between the semiconductor layers and the electrode structures. Further insulating layers may separate the depicted structures, but are not shown for clarity.

[0096] In the current example, there is only sufficient space for three plunger gate electrodes, e.g., electrodes 505n, 16,21 parallel to each other in a single layer, per column of quantum dots. The electrodes for plunger gates 506I,6 will need to be fabricated either in a separate layer, e.g., on top of the layer comprising plunger gates electrodes 505n, 16,21 (separated by an insulating layer), or to the opposite side (towards the top side of the figure).

[0097] Fig. 6A-C are microscopy images of a merged barrier grid and of a chip comprising a merged barrier grid according to an embodiment. In particular, Fig. 6A is a scanning electron microscopy (SEM) image of a semiconductor substrate comprising a barrier grid according to an embodiment. The barrier grid is fabricated in a single layer in an academic cleanroom on top of a silicon-germanium I germanium (SiGe / Ge) heterostructure using evaporation of 3 nm titanium and 17 nm palladium metal. However, as also noted above, other materials (e.g., aluminium, platinum, poly-silicon, et cetera) and other thicknesses are also possible (indeed, the layers forming the plungers gates shown in Fig. 6C have thicknesses of 3 / 17 nm, 3 / 27 nm and 3 / 37 nm of Ti / Pd). The structure of the barrier grid is defined using a combination of electron-beam lithography and lift-off; however, other fabrication techniques, such as optical lithography and chemical-mechanical polishing, can also be used. The round openings are configured to receive a plunger gate and correspond to the quantum dot regions. Thus, the barrier grid is intended for use in a two-dimensional array of 6x6 quantum dot regions, e.g., similar to the one shown schematically in Fig. 2A.

[0098] Fig. 6B is an atomic force microscopy (AFM) image of a quantum chip at an intermediate fabrication step. The grey level corresponds to the z-direction, i.e. , perpendicular to the imaged plane. The structure is fabricated in multiple layers of titanium / palladium with an aluminium oxide insulator in between. The merged barrier grid, similar in fabrication and design to 6A, is fabricated in a single layer, after which several layers of plunger gates are fabricated, column-wise. In this image, the two central columns in the barrier grid 608 have not yet been provided with plunger gates 6O61-36, nor with the electrodes for controlling the plunger gates, so that the barrier grid remains at least partially clearly visible. In this example, the barrier grid is connected to two barrier electrodes 6111,2 on the top and bottom, but other embodiments may have only a single barrier gate electrode. The plunger gates are controllable though plunger gates electrodes 605I-36 which are connected to the left and right sides. The structures in the corners (connected to the electrodes in between the barrier electrodes and the first plunger gate electrodes) can be used for read-out and monitoring. Other embodiments may have no such structures, other structures, or more structures.

[0099] Fig. 6C is an AFM microscopy image of the same quantum chip as Fig. 6B after a further fabrication step. In this image, the quantum chip comprises all 6x6 plunger gates and corresponding electrodes. It can be seen that there is hardly any space between the plunger gate electrodes for further structures, such as, e.g., barrier gate electrodes, illustrating the advantage of reducing the required number of barrier gate electrodes to a constant. It is noted that the shown structure is, in principle, almost lim itlessly scalable in the ‘vertical’ direction (relative to the page), since all plunger gate electrodes are provided on the sides. A ‘wider’ structure could be implemented by using smaller plunger gate electrodes, or by providing an additional layer with plunger gate electrodes.

[0100] In the depicted example, the plunger electrodes of the previous layer can provide a smooth platform for further electrodes to be fabricated on top, further improving ease of fabrication (especially for more complex or wider structures). This smooth platform would be lost if dedicated barrier structures, fabricated in multiple layers were present. For example, with the dimensions shown, each additional layer with plunger gate electrodes would allow for six additional plunger gates in the horizontal direction.

[0101] It is noted that due to the relatively large size of the plunger gates compared to typical barrier gates, vias can be implemented more easily for plunger gates than for barrier gates. This is because for a via to work properly, any dielectric, such as aluminium oxide or silicon oxide, needs to be fully etched away down to the gate that needs to be contacted, while leaving the remaining oxide intact. This can be done, for example, by lithographically defining the area that needs to be etched away, for example through electron-beam or optical lithography, and etching the defined area using, e.g., argon milling or focussed ion beam milling. Subsequently, a metal needs to be deposited within this etched space to contact this desired gate creating the via. The planar dimensions of the via is therefore typically smaller than the gate that needs to be contacted, while the vertical dimension can be larger, dictated by the amount of deposition layers between the gate and the electrode contacting it. As a result, smaller gates, like barrier gates, necessitate even smaller vias to contact them. Smaller vias make each step in the via-fabrication process more difficult, from lithography, to etching, to contacting. Removing the need to contact smaller (barrier) gates through vias is therefor advantageous.

[0102] Fig. 7A is a flowchart of a method for operating a quantum-dot structure according to an embodiment. A first step 702 comprises providing a plurality of qudits in a plurality of quantum dots in a quantum-dot array, for example a quantum-dot array as described herein. Each of the plurality of quantum dots may comprise at most one qudit. If a sparse qudit array is used, qudits are provided in only a (small) fraction of the quantum dots, e.g., at most in 50% of the quantum dots or at most 25% of the quantum dots. The qudits may be distributed approximately homogeneously over the quantum-dot array. For example, a unit cell comprising a single qudit and one or more empty quantum dots may be repeated to cover the quantum-dot array. After initialisation, the qudits may be surrounded by empty quantum dots. Depending on the implementation, only direct (laterally) neighbouring quantum dots may be empty, or also diagonally neighbouring quantum dots. The qudits may be arranged such that completely empty rows and / or columns are formed. Providing a qudit in a quantum dot can comprise obtaining a qudit from a reservoir and moving the qudit to the quantum dot, or generating the qudit directly in the quantum dot. The qudit can be a qubit, e.g., a spinbased qubit based on, e.g., a spin of an electron or a hole. Other suitable qubits or other qudits are well-known in the art.

[0103] A step 704 comprises controlling a barrier gate voltage and / or one or more plunger gate voltages to cause at least two of the plurality of qudits to interact with each other, for example, as described above with reference to Fig. 4A and 4B.

[0104] Fig. 7B is a flowchart of a method according to an embodiment. First step 702 comprises again providing a plurality of qudits in a plurality of quantum dots in a quantum-dot array. A step 706 comprises selecting a first qudit in a first quantum dot and a second qudit in a second quantum dot, the first and second quantum dots being separated by an empty third quantum dot. The first, second, and third quantum dots may be provided with, respectively, first, second, and third plunger gates, to which, respectively, a first, second, and third voltage may be applied. Typically, the quantum dots surrounding the first and second qudits are empty. The barrier gate separating the first and third quantum dots may be shared with a first set of further quantum dots, which may comprise a first set of further qudits. Similarly, the barrier gate separating the second and third quantum dots may be shared with a second set of further quantum dots, which may comprise a second set of further qudits. The first barrier gate separating the first quantum dot form the third quantum dot may be galvanically connected to the second barrier gate separating the second quantum dot from the third quantum dot.

[0105] A step 708 comprises controlling a first voltage of a first plunger gate of the first quantum dot and a third voltage of a third plunger gate of the third quantum dot, to shuttle the first qudit to the third quantum dot. In some embodiments, further plunger gate voltages of neighbouring quantum dots may be controlled to facilitate or improve the shuttling. In some embodiments, the second voltage of the second plunger gate may be adjusted to compensate for local changes in the electric field caused by a change of the third voltage.

[0106] As a result of the shuttling, the first and second qudits are now in neighbouring quantum dots, potentially allowing them to interact. Depending on the implementation, providing the first and second qudits in neighbouring quantum dots may be sufficient for the first and second qudits to interact with each other.

[0107] An optional step 710 comprises controlling the second voltage of the second plunger gate and the third voltage of the third plunger gate, and / or the barrier gate voltage, to cause the first and second qudit to interact with each other. As was noted above, in some embodiments, the first and third qudits may interact with each other even without (further) adjustment of the second or third voltages, or of the barrier gate voltage of the barrier gate separating the second and third quantum dots (and hence the first and second qudits). Several examples of such interaction have been described above with reference to Fig. 4A and 4B.

[0108] An optional step 712 comprises controlling the third voltage of the third plunger gate and the first voltage of the first plunger gate to shuttle the first qudit to the first quantum dot. This step may be performed after the first and second qudits have interacted with each other for a predetermined time. Increasing the distance between the first and second qudits may end or at least severely limit any wanted and / or unwanted interactions between the first and second qudits.

[0109] Instead of moving the first qudit back to the first quantum dot, either the first or second qudit may be moved away to a different quantum dot, possibly to interact with a further qudit. Hence, in an embodiment, the third voltage of the third plunger gate and a further voltage of a further plunger gate belonging to a further quantum dot may be controlled to shuttle the first qudit to the further quantum dot; or the third voltage of the third plunger gate and the further voltage of the further plunger gate may be controlled to shuttle the second qudit to the further quantum dot. To this end, the further quantum dot may be a neighbour of, respectively the third or second quantum dots. Typically, the further quantum dot should be empty before the first or second qudit is shuttled into it.

[0110] Fig. 8 is a flowchart of a method of fabricating a quantum-dot structure according to an embodiment.

[0111] A first step 802 comprises providing a quantum-well stack. The quantum-well stack may be provided on a substrate, e.g., a semiconductor substrate. The quantum-well stack may comprise one or more semiconductor layers. The quantum-well stack may be configured such that qubits may be formed in the quantum-well stack by providing a voltage. The fabrication of such quantum-well stacks is well-known in the art. Thus, an array of quantum dots for housing qubits may be created.

[0112] A step 804 comprises providing a plurality of barrier gates. The plurality of barrier gates can define a quantum-dot array, each barrier gate of the plurality of barrier gates separating two neighbouring quantum-dots in the quantum-dot array. The barrier gates are arranged in lines and at least two of the lines are galvanically connected. Various fabrication techniques have been described above with reference to Fig. 6A-C; other suitable fabrication techniques are known in the art.

[0113] In an embodiment, providing the plurality of barrier gates comprises providing the plurality of barrier gates in a single layer. In such an embodiment, the plurality of barrier gates may be arranged in one or more galvanically connected grids. Thus, a structure as, e.g., shown in Fig. 2A or 2B may be provided.

[0114] In an embodiment, providing the plurality of barrier gates comprises providing the plurality of barrier gates in exactly two layers. In such an embodiment, the lines in a first direction are provided in a first layer of the two layers, and the lines in a second direction, different from the first direction, are provided in a second layer of the two layers. For example, the first and second directions may be orthogonal to each other. Thus, a structure as, e.g., shown in Fig. 2C-2F may be provided. Alternatively, the lines in a first layer of the two layers may define a first galvanically connected grid of barrier lines and the lines in a second layer of the two layers define a second galvanically connected grid of barrier lines. The second galvanically connected grid of barrier lines may being galvanically separated from the first galvanically connected grid of barrier lines. The second galvanically connected grid of barrier lines may be shifted relative to the first galvanically connected grid of barrier lines. For example, the first and second grid may have a spacing that is twice the spacing between the quantum dots. Thus, a structure as, e.g., shown in Fig. 2G may be provided.

[0115] A step 806 comprises providing a plunger gate for each quantum dot in the quantumdot array. Each of the plunger gates may be individually controllable. The plunger gates may be provided in one or more layers, e.g., as described above with reference to Fig. 6B and 6C.

[0116] This way, quantum-dot structures as described herein may be fabricated. The steps may be performed in the described order, or in a different order. One or more such quantumdot structures may be provided on a single quantum chip.

[0117] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0118] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles and the practical application, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.

Claims

CLAIMS1. A quantum-dot structure for use with a sparse qudit array comprising: a two-dimensional quantum-dot array or a three-dimensional quantum-dot array, each quantum dot in the quantum-dot array being provided with an individually controllable plunger gate for controlling a qudit in the quantum dot, and a plurality of barrier gates, each barrier gate of the plurality of barrier gates separating two neighbouring quantum-dots in the quantum-dot array, wherein the barrier gates are arranged in galvanically connected lines and wherein at least two of the galvanically connected lines are galvanically connected with each other.

2. The quantum-dot structure according to claim 1 , wherein an amount of independently controllable barrier gates is independent of an amount of quantum dots in the quantum-dot structure, preferably the amount of independently controllable barrier gates being one, two, three, or four.

3. The quantum-dot structure according to claim 1 or 2, wherein the barrier gates are arranged in a grid that is galvanically connected.

4. The quantum-dot structure according to any one of the preceding claims , wherein the quantum-dot array comprises at least 16 quantum dots, preferably at least 24 quantum dots, more preferably at least 32 quantum dots, even more preferably at least 64 quantum dots.

5. The quantum-dot structure according to any one of the preceding claims, wherein between two neighbouring quantum dots in the quantum dot array have a pitch that is at most 500 nm, at most 200 nm, preferably at most 150 nm, more preferably at most 100 nm.

6. A quantum chip, preferably a quantum processing unit, comprising one or more quantum-dot arrays according to any one of claims 1-5.

7. A method for operating a quantum-dot structure according to any one of claims 1- 5, the method comprising: providing a plurality of qudits, preferably qubits, in a plurality of quantum dots in the quantum-dot array, each of the plurality of quantum dots comprising at most one qudit; and controlling a barrier gate voltage and / or one or more plunger gate voltages to cause at least two of the plurality of qudits to interact with each other.

8. The method according to claim 7, wherein the qudits are provided in at most 50% of the quantum dots, preferably in at most 25% of the quantum dots.

9. The method according to claim 7 or 8, further comprising: selecting a first qudit in a first quantum dot provided with a first plunger gate having a first voltage and a second qudit in a second quantum dot provided with a second plunger gate having a second voltage, the first and second quantum dots being separated by a third quantum dot provided with a third plunger gate having a third voltage, the third quantum dot neighbouring both the first and second quantum dots, the third quantum dot being empty; and wherein controlling the barrier gate voltage and / or the one or more plunger gate voltages comprises controlling the first voltage of the first plunger gate and the third voltage of the third plunger gate, to shuttle the first qudit to the third quantum dot.

10. The method according to claim 9, wherein controlling the barrier gate voltage and / or the one or more plunger gate voltages comprises controlling the second voltage of the second plunger gate and the third voltage of the third plunger gate, and / or the barrier gate voltage, to cause the first and second qudit to interact with each other.

11. The method according to claim 9 or 10, further comprising: after interaction of the first and second qubits during a predetermined duration, controlling the third voltage of the third plunger gate and the first voltage of the first plunger gate to shuttle the first qudit to the first quantum dot; or after interaction of the first and second qubits during a predetermined duration, controlling the third voltage of the third plunger gate and a further voltage of a further plunger gate belonging to a further quantum dot, the further quantum dot neighbouring the third quantum dot, the further quantum dot being empty, to shuttle the first qudit to the further quantum dot; or after interaction of the first and second qubits during a predetermined duration, controlling the third voltage of the third plunger gate and a further voltage of a further plunger gate belonging to a further quantum dot, the further quantum dot neighbouring the second quantum dot, the further quantum dot being empty, to shuttle the second qudit to the further quantum dot.

12. A method for fabricating a quantum-dot structure, the method comprising: providing a quantum-well stack;providing a plurality of barrier gates defining a quantum-dot array, each barrier gate of the plurality of barrier gates separating two neighbouring quantum-dots in the quantum-dot array; and providing an individually plunger gate for each quantum dot in the quantum-dot array; wherein the barrier gates are arranged in galvanically connected lines and wherein at least two of the galvanically connected lines are galvanically connected with each other.

13. The method according to claim 12, wherein providing the plurality of barrier gates comprises: providing the plurality of barrier gates in a single layer, the plurality of barrier gates being arranged in a grid that is galvanically connected; or providing the plurality of barrier gates in exactly two layers, wherein the lines in a first direction are provided in a first layer of the two layers, and the lines in a second direction, different from the first direction, are provided in a second layer of the two layers; or providing the plurality of barrier gates in exactly two layers, wherein the lines in a first layer of the two layers define a first galvanically connected grid of barrier lines and the lines in a second layer of the two layers define a second galvanically connected grid of barrier lines, the second galvanically connected grid of barrier lines being galvanically separated from the first galvanically connected grid of barrier lines, and the second galvanically connected grid of barrier lines being shifted relative to the first galvanically connected grid of barrier lines.

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