Diagnosable library scan cells with controllable inverter

Abstract

A library scan cell comprises: one or more state elements configured to serve as a single bit or multiple bits of the library scan cell; and a controllable inverting device placed in a shift path of the library scan cell and between an input of one of the one or more state elements and a serial input of the library scan cell or an output of another one of the one or more state elements. The controllable inverting device is configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal. The one of the one or more state elements is configured to operate in a plurality of test-related modes which comprises a diagnosis capture mode.

Description

[0001] DIAGNOSABLE LIBRARY SCAN CELLS WITH CONTROLLABLE INVERTER

[0002] FIELD OF THE DISCLOSED TECHNOLOGY

[0003]

[0001] The present disclosed technology relates to the field of circuit test and diagnosis. Various implementations of the disclosed technology may be particularly useful for scan chain diagnosis.

[0004] BACKGROUND OF THE DISCLOSED TECHNOLOGY

[0005]

[0002] Modem integrated circuits are complex. At leading technology nodes, feature sizes have shrunk to a few nrn wide. Non-planar or “three-dimensional” transistors (FinFET and GAA (gate-all-around)) are being used to achieve higher performance with lower power consumption. The non-planar transistors and transistor connections have more complicated structures with more layers and thus require more process steps. More process steps and smaller feature sizes can result in more root causes of defects. For these integrate circuits to be commercially viable, the manufacture yield needs to reach and maintain above a certain threshold. Therefore, accurately identifying yield-limiting root causes becomes highly critical. In the past, bitmapping static random-access memories (SRAMs) has been employed as a “yield learning vehicle”. For leading technology nodes, however, being capable of manufacturing these regular structures does not guarantee that a product with irregular structures can be successfully manufactured.

[0006]

[0003] Software-based diagnosis of scan test failures has proven to be of enormous value for yield learning. Scan testing is commonly used in a manufacturing process to ensure that integrated circuits are fabricated correctly. Diagnosis uses failure data from scan testing along with circuit design information to determine the most likely defect locations and mechanisms for failing circuits (dies). The diagnosis results can guide physical failure analysis (PF A) to focus on a much smaller area in a failing circuit, leading to higher success rates of PFA with reduced turnaround time and costs. Based on the yield loss mechanism obtained by PFA, circuit design or manufacture process can be adjusted to improve manufacture yields.

[0007]

[0004] The PFA process is destructive to integrated circuits. It is thus important for diagnosis to provide a target area for PFA that is as precise as possible. The resolution or diagnosis coverage of a diagnostic tool is related to the number of suspected defect locations identified. The larger the number of suspect locations reported, the larger the area for PFA to work on. The demand for diagnosis resolution / coverage has increased, especially for chain diagnosis, where, due to the complexity of scan cell structures, PFA needs a diagnosis tool to report a single scan cell for PFA to work on. Recent data shows that diagnosis based directly on manufacture test patterns does not consistently achieve the required diagnostic quality. Even using test patterns specifically generated for diagnosis cannot pinpoint specific faulty scan cells in many cases.

[0008] BRIEF SUMMARY OF THE DISCLOSED TECHNOLOGY

[0009]

[0005] Various aspects of the present disclosed technology relate to techniques for designs and applications of diagnosable library scan cells for improving diagnosis coverage. In one aspect, there is a library scan cell, comprising: one or more state elements configured to serve as a single bit or multiple bits of the library scan cell; and a controllable inverting device placed in a shift path of the library scan cell and between an input of one of the one or more state elements and a serial input of the library scan cell or an output of another one of the one or more state elements, a control input of the controllable inverting device being coupled to an inversion-control input of the library scan cell, wherein the controllable inverting device is configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal received at the inversion-control input, and wherein the one of the one or more state elements is configured to operate in a plurality of test-related modes, the plurality of test-related modes comprising a diagnosis capture mode in which the one of the one or more state elements is configured to capture the inverted version of a bit received at the data input of the controllable inverting device.

[0010]

[0006] The diagnosis capture mode may be activated based on the inversion-control signal and a local scan enable signal received at a scan enable input of the library scan cell when a circuit is being tested, the local scan enable signal being derived based on a diagnosis mode signal and a regular scan enable signal, the diagnosis mode signal being provided by a storage device in the circuit. The storage device may be another scan cell or a shadow register of another scan cell in the circuit. The local scan-enable signal may be derived by a logical OR operation of the diagnosis mode signal and the regular scan enable signal. The inversion-control signal may be derived by inverting the regular scan enable signal or by a logical AND operation of the diagnosis mode signal and a signal derived by inverting the regular scan enable signal. The local scan enable signal may be a global scan enable signal used by other scan cells in the circuit.

[0011]

[0007] The library scan cell may be used to implement a scan cell in a circuit design which is identified by design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof.

[0012]

[0008] The library scan cell may further comprise: another controllable inverting device being placed in the shift path of the library scan cell, an output of the another controllable inverting device being coupled to a serial input of a state element in the one or more state elements that is different from one of the one or more state elements, a control input of the another controllable inverting device being also coupled to the inversion-control input of the library scan cell.

[0013]

[0009] The library scan cell may further comprise: one controllable inverting device for each of state elements in the one or more state elements that are different from one of the one or more state elements, the one controllable inverting device being placed in the shift path of the library scan cell, a control input of the one controllable inverting device being also coupled to the inversion-control input of the library scan cell.

[0014]

[0010] In another aspect, there is a method for scan chain diagnosis, comprising: shifting a test pattern into scan chains to load a bit of “v” into a scan cell (K + 1) in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of a scan cell K, the scan cell K being implemented using a diagnosable library scan cell, the diagnosable library scan cell comprising a state element and a controllable inverting device placed in a shift path of the library scan cell and between a serial input of the library scan cell and an input of the state element, the controllable inverting device being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal received at an inversion-control input of the diagnosable library scan cell; performing a capture operation for one clock cycle, the scan cell - being configured to operate in a diagnosis captured mode - capturing a bit of “1 - v” outputted by the controllable inverting device, wherein the diagnosis captured mode is activated based at least in part on the inversioncontrol signal; and shifting out the bit of “1 - v” captured by the scan cell K to determine whether the scan cell K has a stuck-at-v fault at output side. The diagnosis captured mode may be activated based further on a scan enable signal received at a scan enable input of the diagnosable library scan cell, the inversion-control signal and the scan enable signal being derived based on a regular scan enable signal and a diagnosis mode signal, the diagnosis signal being supplied by a storage device in a circuit being tested.

[0015]

[0011] In still another aspect, there is a method for scan chain diagnosis, comprising: shifting a test pattern into scan chains to load a bit of “v” into each of scan cells (K + 1) and K in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of the scan cell K, the scan cell " being implemented using a diagnosable library scan cell, the diagnosable library scan cell comprising a state element and a controllable inverting device placed in a shift path of the library scan cell and between a serial input of the library scan cell and an input of the state element, the controllable inverting device being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal received at an inversion-control input of the diagnosable library scan cell; performing a capture operation for each of two clock cycles, wherein for each of the two clock cycles, the scan cell K and a scan cell (K - 1) are configured to operate in a diagnosis captured mode - the scan cell K capturing the inverted version of a bit received by the controllable inverting device while the scan cell (K - 1) capturing a bit outputted by the scan cell K, wherein the diagnosis captured mode is activated based at least in part on the inversioncontrol signal; and shifting out a bit captured by the scan cell (K - 1) at a second clock cycle in the two clock cycles to determine whether the scan cell K has a slow-to-fall / rise fault at output side. The diagnosis captured mode may be activated based further on a scan enable signal received at a scan enable input of the diagnosable library scan cell, the inversion-control signal and the scan enable signal being derived based on a regular scan enable signal and a diagnosis mode signal, the diagnosis signal being supplied by a storage device in a circuit being tested.

[0016]

[0012] In still another aspect, there is a method for scan chain diagnosis, comprising: shifting a test pattern into scan chains to load a bit of “v” into each of scan cells (K+ 1) and K in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of the scan cell K, the scan cell K being implemented using a diagnosable library scan cell, the diagnosable library scan cell comprising a state element and a controllable inverting device placed in a shift path of the library scan cell and between a serial input of the library scan cell and an input of the state element, the controllable inverting device being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal received at an inversion-control input of the diagnosable library scan cell; performing a capture operation for one clock cycle, wherein the scan cell K and a scan cell (K - 1) are configured to operate in a diagnosis captured mode - the scan cell K capturing the inverted version of a bit received by the controllable inverting device while the scan cell K- 1) capturing a bit outputted by the scan cell K, wherein the diagnosis captured mode is activated based at least in part on the inversion-control signal; and shifting out a bit captured by the scan cell K - 1 ) at the one clock cycle to determine whether the scan cell K has a fast-to-fall / rise fault at output side. The diagnosis captured mode may be activated based further on a scan enable signal received at a scan enable input of the diagnosable library scan cell, the inversion-control signal and the scan enable signal being derived based on a regular scan enable signal and a diagnosis mode signal, the diagnosis signal being supplied by a storage device in a circuit being tested.

[0017]

[0013] Certain inventive aspects are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

[0018]

[0014] Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed technology may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0019] BRIEF DESCRIPTION OF THE DRAWINGS

[0020]

[0015] Figure 1 illustrates an example of a conventional library scan cell.

[0021]

[0016] Figure 2 illustrates an example of a conventional four-bit library scan cell.

[0017] Figure 3 illustrates an example scan chain.

[0022]

[0018] Figure 4 illustrates an example of a diagnosable library scan cell that may be implemented according to various embodiments of the disclosed technology.

[0023]

[0019] Figure 5 illustrates an example of a diagnosable four-bit library scan cell that may be implemented according to various embodiments of the disclosed technology.

[0024]

[0020] Figure 6 illustrates another example of a diagnosable four-bit library scan cell that may be implemented according to various embodiments of the disclosed technology.

[0025]

[0021] Figure 7 illustrates an example of a controllable inverting device that may be implemented according to various embodiments of the disclosed technology.

[0026]

[0022] Figure 8 illustrates an example of a control signal generation device that may be implemented according to various embodiments of the disclosed technology.

[0027]

[0023] Figure 9 illustrates an example of a diagnosable library scan cell that may be implemented according to various embodiments of the disclosed technology.

[0028]

[0024] Figure 10 illustrates another example of a control signal generation device that may be implemented according to various embodiments of the disclosed technology.

[0029]

[0025] Figure 11 illustrates an example of two neighboring scan cells forming a part or a whole of a shift register.

[0030]

[0026] Figure 12 illustrates another example of two neighboring scan cells forming a part or a whole of a shift register.

[0031]

[0027] Figure 13 illustrates an example of a diagnosable library scan cell with no scan enable input that may be implemented according to various embodiments of the disclosed technology.

[0032] -1-

[0028] Figure 14 illustrates an example of using diagnosable library scan cells in a scan chain that may be implemented according to various embodiments of the disclosed technology.

[0033]

[0029] Figure 15 illustrates another example of using diagnosable library scan cells in a scan chain that may be implemented according to various embodiments of the disclosed technology.

[0034]

[0030] Figure 16 illustrates an example of a scan cell that can be used to implement a storage device for storing the diagnosis mode signal according to various embodiments of the disclosed technology.

[0035]

[0031] Figure 17 illustrates a table that shows a chain pattern and chain pattern responses of a faulty scan chain for eight permanent fault models.

[0036]

[0032] Figure 18A illustrates a flowchart showing a process of using diagnosable library scan cell to determine whether a scan cell or its upstream scan cells has a stuck-at-v fault that may be implemented according to various examples of the disclosed technology.

[0037]

[0033] Figure 18B illustrates a diagram showing a process of using diagnosable library scan cell to determine whether a scan cell or its upstream scan cells has a stuck-at-v fault that may be implemented according to various examples of the disclosed technology.

[0038]

[0034] Figure 19A illustrates a flowchart showing a process of using diagnosable library scan cell to determine whether a scan cell or its upstream scan cells has a slow-to-fall / rise fault that may be implemented according to various examples of the disclosed technology.

[0039]

[0035] Figure 19B illustrates a diagram showing a process of using diagnosable library scan cell to determine whether a scan cell or its upstream scan cells has a slow-to-fall / rise fault that may be implemented according to various examples of the disclosed technology.

[0036] Figure 20A illustrates a flowchart showing a process of using diagnosable library scan cell to determine whether a scan cell or its upstream scan cells has a fast-to-fall / rise fault that may be implemented according to various examples of the disclosed technology.

[0040]

[0037] Figure 20B illustrates a diagram showing a process of using diagnosable library scan cell to determine whether a scan cell or its upstream scan cells has a fast-to-fall / rise fault that may be implemented according to various examples of the disclosed technology.

[0041]

[0038] Figure 21 illustrates an example of a computing device that may be used to implement various embodiments of the disclosed technology.

[0042] DETAILED DESCRIPTION OF THE DISCLOSED TECHNOLOGY

[0043] General Considerations

[0044]

[0039] Various aspects of the present disclosed technology relate to techniques for designs and applications of diagnosable library scan cells for improving diagnosis coverage. In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the disclosed technology may be practiced without the use of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the present disclosed technology.

[0045]

[0040] Some of the techniques described herein can be implemented in software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of both. Some of the disclosed techniques, for example, can be implemented as part of an electronic design automation (EDA) tool. Such methods can be executed on a single computer or on networked computers.

[0046]

[0041] Although the operations of the disclosed methods are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. The detailed description sometimes uses terms like “perform”, “load,” “invert,” and “capture” to describe the disclosed methods / systems. Such terms are high-level descriptions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.

[0047]

[0042] As used in this disclosure, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly dictates otherwise. Additionally, the term “includes” means “comprises.” Moreover, unless the context dictates otherwise, the term “coupled” means electrically or electromagnetically connected or linked and includes both direct connections or direct links and indirect connections or indirect links through one or more intermediate elements not affecting the intended operation of the circuit.

[0048]

[0043] Also, as used herein, the term “design” is intended to encompass data describing an entire integrated circuit device. This term also is intended to encompass a smaller group of data describing one or more components of an entire device, however, such as a portion of an integrated circuit device. Still further, the term “design” also is intended to encompass data describing more than one microdevice, such as data to be used to form multiple microdevices on a single wafer.

[0049] Design For Test, Test Pattern Generation, Testing And Diagnosis

[0050]

[0044] The reduction in feature size increases the probability that a manufacture defect in an integrated circuit will result in a faulty chip. A very small defect can result in a faulty transistor or interconnecting wire. Even a single faulty transistor or wire can cause the entire chip to function improperly. Manufacture defects are unavoidable nonetheless, no matter whether the manufacturing process is at the prototype stage or the high-volume manufacturing stage. It is thus necessary to test chips during the manufacturing process. Diagnosing faulty chips is also needed to ramp up and to maintain the manufacturing yield.

[0051]

[0045] Testing typically includes applying a set of test stimuli (test patterns) to the circuit-under- test and then analyzing responses generated by the circuit-under-test. Functional testing attempts to validate that the circuit-under-test operates according to its functional specification while structural testing tries to ascertain that the circuit-under-test has been assembled correctly from some low-level building blocks as specified in a structural netlist and that these low-level building blocks and their wiring connections have been manufactured without defect. For structural testing, it is assumed that if functional verification has shown the correctness of the netlist and structural testing has confirmed the correct assembly of the structural circuit elements, then the circuit should function correctly. Structural testing has been widely adopted at least in part because it enables the test (test pattern) generation to focus on testing a limited number of relatively simple circuit elements rather than having to deal with an exponentially exploding multiplicity of functional states and state transitions.

[0052]

[0046] To make it easier to develop and apply test patterns, certain testability features are added to circuit designs, which is referred to as design for test or design for testability (DFT). Scan testing is the most common DFT method. In a basic scan testing scheme, all or most of internal sequential state elements (latches, flip-flops, et al.) in a circuit design are made controllable and observable via a serial interface. These functional state elements are usually replaced with dual-purpose state elements called scan cells. Scan cells are connected together to form scan chains - serial shift registers for shifting in test patterns and shifting out test responses. A scan cell can operate as originally intended for functional purposes (functional / mission mode) and as a unit in a scan chain for scan testing (scan mode). A widely used type of scan cell includes an edge-trigged flip-flop with two-way multiplexer for the data input. The two-way multiplexer is typically controlled by a single control signal called scan enable, which selects the input signal for a scan cell from either a scan signal input port or a system signal input port. The scan signal input port is typically connected to an output of another scan cell while the system signal input port is connected to the functional logic. Scan cells can serve as both a control point and an observation point. Control points can be used to set certain logic values at some locations of the circuit-under-test, exciting (activating) a fault and propagating the incorrect value to an observation point. Scan testing allows the test equipment to access gates deeply embedded through the primary inputs / outputs and / or some physical test points and can remove the need for complicated state transition sequences when trying to control or observe what is happening at some internal circuit element.

[0053]

[0047] In a typical scan test, a series of known values (test stimuli or test pattern) are shifted-in (or loaded into) scan cells through their sequential inputs. The shifting-in occurs by placing the integrated circuit in a special mode, known as shift mode, and then applying a series of clock pulses, called “shift pulses” or “shift clock pulses.” Each shift clock pulse pushes a bit of test stimuli into a scan cell in each of the scan chains. This continues until all scan cells in the scan chains are filled with test pattern bits. Then, one or more clock pulses, called “capture pulses” or “capture clock pulses,” are applied to the circuit as they would be in normal operation. This is referred to as capture mode. After the test pattern bits are injected into the circuit, the results of the test (test responses) are “captured” and stored in the scan cells. The circuit then returns to shift mode, and with each additional clock pulse, a bit of the test responses is pushed or shifted out as each bit of new test pattern is pushed or shifted in. The shifted-out test responses are then compared with expected results to determine and locate any errors. Shift mode and capture mode together may be referred to as test mode.

[0054]

[0048] Test patterns for scan testing are typically generated through an automatic test pattern generation (ATPG) process. ATPG usually focuses on a set of faults derived from a gate- level fault model. A defect is a flaw or physical imperfection caused in a device during the manufacturing process. A fault model (or briefly a fault) is a description of how a defect alters design behavior. For a given target fault, ATPG comprises two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault site opposite that produced by the fault (e.g., for a stuck-at-0 fault, the fault activation process will try to establish a logic '1' at that site). Fault propagation propagates the fault effect (e.g., stuck at 0) forward by sensitizing a path from a fault site to a scan cell or a primary output. A fault at a site is said to be detected by a test pattern if a test response value captured by a scan cell or a primary output is different than the expected value. The objective of ATPG is to find a test pattern that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by one or more particular faults. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors (test pattern counts), which should be directly proportional to test application time. Here, the fault coverage is defined as a ratio of the number of detected faults vs. the total number of faults.

[0055]

[0049] A popular fault model used in practice is the single stuck-at fault model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. The stuck-at fault model is a logical fault model because no delay information is associated with the fault definition. Delay faults cause errors in the functioning of a circuit based on its timing. They are caused by the finite rise and fall time periods of the signals in the gates, as well as the propagation delay of interconnects between the gates. Transition faults are used for their simplicity in modeling spot defects that affect delays at inputs or outputs of gates. Under scan-based tests, the transition faults are associated with an extra delay that is large enough to cause the delay of any path through the fault site to exceed the clock period. Cell internal fault models can be derived using transistor-level circuit simulations (analog simulations). This approach can pinpoint the defect location within a cell for various cell internal defects.

[0056]

[0050] During the circuit design and manufacturing process, a manufacturing test screens out chips (dies) containing defects. The test itself, however, does not identify the reason for the unacceptable low or fluctuating yield that may be observed. Physical failure analysis (PF A) can inspect the faulty chip to locate the defect location(s) and to discover the root cause. The process usually includes etching away certain layers and then imaging the silicon surface by scanning electronic microscopy or focused ion beam systems. This PFA process is laborious and time consuming. To facilitate the PFA process, diagnosis (also referred to as scan diagnosis) is often employed to narrow down possible locations of the defect(s) based on analyzing the fail log (fail file, failure file). The fail log typically contains information about when (e.g., tester cycle), where (e.g., at what tester channel), and how (e.g., at what logic value) the test failed and which test patterns generate expected test responses. The layout information of the circuit design may also be employed to further reduce the number of defect suspects.

[0057]

[0051] Diagnosis includes logic diagnosis (sometimes referred to as scan diagnosis) and chain diagnosis. Logic diagnosis may employ a fault dictionary or directly examine the syndrome (i.e., the effect) of the failing chip to determine likely defect locations (defect suspects). The latter approach may include structural pruning (back tracing), fault injection and evaluation (fault simulation for both failing and passing test patterns).

[0058]

[0052] Chain diagnosis determines scan cells that are likely to be defective. Scan elements and related clocking circuitry can take up about 30% of silicon area of an IC chip. It has been reported that scan chain failures account for almost 50% of chip failure in some cases. Chain diagnosis is thus important to guide physical failure analysis and yield learning process. In a chain diagnosis process, two types of test patterns may be used. The first type is called chain patterns. A chain pattern is a pattern used in a process comprising shift-in and shift-out without pulsing capture clocks. The other type is often referred to as scan patterns. A scan pattern is a pattern used in a process comprising shift-in, one or multiple capture clock cycles, and shift-out, and the scan patterns include patterns generated by ATPG for testing system logic, special chain diagnostic patterns generated only for scan chain diagnosis purpose and some special functional patterns. Chain patterns can be used to test the integrity of scan chains and / or determine fault models associated with faulty scan chains while scan patterns can be used to inject certain values to some scan cells for locating defective scan cells.

[0059]

[0053] The quality of diagnosis can be measured by diagnostic resolution (the number of the real defects vs. the number of the defect suspects). Diagnostic resolution is linked not only to the algorithm used for diagnosis but also to the test patterns used for the manufacturing test (manufacturing test patterns). The quality of diagnosis can also be measured by diagnosis coverage. Diagnosis coverage may be determined in several ways. A simple way is to divide the number of equivalent fault groups by the number of faults. Faults in an equivalent fault group cannot be separated or distinguished under a certain condition by a diagnosis technique. To enhance the quality of diagnosis, a diagnostic test pattern generation process may be employed. This process generates test patterns that can increase the number of equivalent fault groups or reduce the average number of faults in the equivalent fault groups.

[0060]

[0054] Test application in chip manufacturing test is normally performed by automatic test equipment (ATE) (a type of testers). Scan-based tests consume significant amounts of storage and test time on ATE. The data volume increases with the number of logic gates on the chip and the same holds for the number of scan cells. Yet, practical considerations and ATE specifications often limit both the number of pins available for scan in / out and the maximum scan frequency. It is highly desirable to reduce the amount of test data that need to be loaded onto ATE and ultimately to the circuit under test. Fortunately, test patterns are compressible mainly because only 1% to 5% of test pattern bits are typically specified bits (care bits) while the rest are unspecified bits (don't-care bits). Unspecified bits can take on any values with no impact on the fault coverage. Test compression may also take advantage of the fact that test cubes tend to be highly correlated. A test cube is a deterministic test pattern in which the don't-care bits are not filled by ATPG. The correlation exists because faults are structurally related in the circuit.

[0061]

[0055] Various test compression techniques have been developed. In general, additional on-chip hardware before and after scan chains is inserted. The hardware (decompressor) added before scan chains is configured to decompress test stimulus coming from ATE, while the hardware (compactor) added after scan chains is configured to compact test responses captured by the scan chains. The decompressor expands the data from n tester channels to fill greater than n scan chains. The increase in the number of scan chains shortens each scan chain and thus reduces the number of clock cycles needed to shift in each test pattern. Thus, test compression can not only reduce the amount of data stored on the tester but also reduce the test time for a given test data bandwidth.

[0062] Diagnosable Library Scan Cells

[0063]

[0056] In circuit design, library cells (often called standard cells) are pre-designed, pre-verified and reusable circuit elements that serve as building blocks for creating larger circuits or systems. These cells encapsulate specific functionalities, such as logic gates, flip-flops, and analog components, and are typically stored in a library for easy access and integration into larger circuits. Designers verify and test library cells extensively, ensuring their correctness and reliability in the final circuit. Designers also optimize them for speed, power and area. Thus, using library cells can simplify the design process and help maintain design consistency and uniformity across different projects.

[0064]

[0057] Fig. 1 illustrates an example of a conventional library scan cell 100. The conventional library scan cell 100 comprises a state element 110 and a two-way multiplexer 120. The state element 110 can be implemented using an edge-trigged flip-flop. The two-way multiplexer 120 selects a signal from either a serial input port 130 or a parallel input port 140 of the library scan cell 100 as the data input signal for the state element 110. The selection is based on a scan enable signal supplied from a scan enable port 150 of the library scan cell 100. The serial input port 130 can be coupled to an output of another scan cell in the same scan chain and the parallel input port 140 can be coupled to functional circuitry 170.

[0065]

[0058] When the scan enable signal 150 is asserted, the serial input port 130 is coupled to the data input for the state element 110. As a result, the library scan cell 100 operates in a shift mode (normal shift mode). When the scan enable signal 150 is deasserted, the parallel input port 140 is coupled to the data input for the state element 110. As a result, the library scan cell 100 operates in a capture mode (normal capture mode). The library scan cell 100 fans out into two outputs: a serial output 160 and a parallel output 180. The serial output 160 can be coupled to the serial input port of the next scan cell in the same scan chain. The parallel output 180 can be coupled to the functional circuitry 170.

[0066]

[0059] Recently, the multi-bit flip-flop (MBFF) technique was introduced to improve efficiency, reduce area, and minimize power consumption during both normal operation and testing. A multi-bit scan cell (multi-bit flip-flop) combines two or more flip-flops into a single scan cell. It has one serial input (scan input), one serial output (scan output), and some shared control inputs required for the flip-flops such as the scan-enable input and the clock input. The control input sharing can lead to significant area and power savings. Fig.

[0067] 2 illustrates an example of a conventional four-bit library scan cell 200. Four built-in flipflops 210, 212, 214 and 216 in the conventional four-bit library scan cell 200 share a common clock input 240 and a common scan enable input 250. Each of the built-in flipflops 210, 212, 214, and 216 has a data input (also referred to as parallel input, 221, 222, 223, and 224) and a data output (also referred to as parallel output, 225, 226, 227, and 228). The conventional four-bit library scan cell 200 has a scan input port 260 and a scan output port 270. A scan enable signal received at the scan enable input 250 controls, via four multiplexers 271, 272, 273, and 274, whether the built-in flip-flops 210, 212, 214, and 216 operate in a shift mode or not. The shift direction is from left to right: from the scan input port 260 to the built-in flip-flops 221, 222, 223 and 224 in sequence, and finally to the scan output port 270.

[0068]

[0060] In a scan chain, a scan cell is often labeled with an index, indicating its position. In this disclosure, scan cells in a scan chain are numbered incrementally from the scan output to the scan input, with the first scan cell assigned an index of 0, the second assigned an index of 1, and so on. This convention is widely used in the industry. The scan cells between the scan input of the scan chain and the serial input of a particular scan cell are called “upstream scan cells” of the particular scan cell, while the scan cells between the scan output of the scan chain and the serial output of the particular scan cell are called “downstream scan cells” of the particular scan cell.

[0069]

[0061] In a circuit design, scan cells are stitched together to form scan chains. Fig. 3 illustrates an example scan chain 300. The scan chain 300 has no shadow register and thus data bits stored in scan cells 310, 320, 330 are being applied to the functional circuitry 340 continuously even in the shift mode. During a test, scan chains can shift in test stimuli bits of a test pattern in the shift mode, capture test response bits for the test pattern from the functional circuitry in the capture mode, and shift out the test response bits again in the shift mode.

[0070]

[0062] It should be noted that in some cases, one or more scan cells in a scan chain either do not have parallel inputs or their inputs are not coupled to the functional circuitry. Such a scan cell may serve as a shift register. It should also be noted that a scan cell may not have a built-in multiplexer, but its input can be coupled to an output of a multiplexer placed outside of the scan cell. A combination of the scan cell and the multiplexer can function as a typical scan cell.

[0063] Fig. 4 illustrates an example of a diagnosable library scan cell 400 that may be implemented according to various embodiments of the disclosed technology. Like the conventional library scan cell 100 in Fig. 1, the diagnosable library scan cell 400 comprises a state element 410 and a two-way multiplexer 430. The state element 410 can be implemented using an edge-trigged flip-flop. Unlike the conventional library scan cell 100, the diagnosable library scan cell 400 further comprises a controllable inverting device 420. The controllable inverting device 420 is placed in the shift path of the diagnosable library scan cell 400 and between an input 440 of the state element 410 and a serial input 450 of the diagnosable library scan cell 400. Specifically, a data input 460 of the controllable inverting device 420 is coupled to the serial input 450 and an output 470 of the controllable inverting device 420 is coupled to one of the two inputs of the two-way multiplexer 430. A control input 480 of the controllable inverting device 420 is coupled to an inversion-control input 490 of the diagnosable library scan cell 400. The controllable inverting device 420 is configured to output an inverted version or an original version of a bit received at the data input 460 of the controllable inverting device 420 based on an inversion-control signal received at the inversion-control input 490. The state element 410 and accordingly the diagnosable library scan cell 400 can be configured to operate in one of a plurality of test-related modes which comprise a diagnosis capture mode. In the diagnosis capture mode, the state element 410 is configured to capture the inverted version of a bit received at the data input 460 of the controllable inverting device 420 which is also the bit received at the serial input 450 of the diagnosable library scan cell 400.

[0071]

[0064] Fig. 5 illustrates an example of a diagnosable four-bit library scan cell 500 that may be implemented according to various embodiments of the disclosed technology. Like the conventional four-bit library scan cell 200 in Fig. 2, the diagnosable four-bit library scan cell 500 has flip-flops 510, 512, 514 and 516 and four multiplexers 571, 572, 573, and 574. Unlike the conventional four-bit library scan cell 200, the diagnosable four-bit library scan cell 500 further comprises a controllable inverting device 520. The controllable inverting device 520 is placed in the shift path of the diagnosable four-bit library scan cell 500 and between an output 530 of the state element 510 and an input 540 of the flip-flop 512. Specifically, a data input 550 of the controllable inverting device 520 is coupled to the output 530 of the flip-flop 510, and an output 560 of the controllable inverting device 520 is coupled to one of the two inputs of the two-way multiplexer 572. A control input 570 of the controllable inverting device 520 is coupled to an inversioncontrol input 590 of the diagnosable four-bit library scan cell 500. The controllable inverting device 520 is configured to output an inverted version or an original version of a bit received at the data input 550 of the controllable inverting device 520 based on an inversion-control signal received at the inversion-control input 590. The flip-flop 512 and accordingly Bit 1 of the diagnosable four-bit library scan cell 500 can be configured to operate in one of a plurality of test-related modes which comprise a diagnosis capture mode. In the diagnosis capture mode, the flip-flop 512 is configured to capture the inverted version of a bit received at the data input 550 of the controllable inverting device 520 which is the bit outputted from the flip-flop 510 (Bit 0).

[0072]

[0065] Fig. 6 illustrates another example of a diagnosable four-bit library scan cell 600 that may be implemented according to various embodiments of the disclosed technology. The diagnosable four-bit library scan cell 600 is similar to the diagnosable four-bit library scan cell 500 in Fig. 5, except for the number of controllable inverting devices inserted. Rather than just the single controllable inverting device 520 inserted for the flip-flop 512, four controllable inverting devices 620, 622, 624 and 626 are inserted, each for one of four flip-flops 610, 612, 614 and 616. Control inputs of the four controllable inverting devices 620, 622, 624 and 626 are all coupled to a same inversion-control input 690 of the diagnosable four-bit library scan cell 600. The four flip-flops 610, 612, 614 and 616 and accordingly the diagnosable four-bit library scan cell 600 can be configured to operate in one of a plurality of test-related modes which comprise the diagnosis capture mode similar to the one described for the flip-flop 512 in Fig. 5. It should be noted that a diagnosable four-bit library scan cell may comprise two or three controllable inverting devices in addition to those shown in Figs. 5 and 6.

[0073]

[0066] Fig. 7 illustrates an example of a controllable inverting device 700 that may be implemented according to various embodiments of the disclosed technology. The controllable inverting device 700 is an XOR gate. The two inputs 710 and 720 of the XOR gate serve as the data input and the control input of the controllable inverting device 700, respectively. When an inversion-control signal 730 is asserted, the bit at the output 715 of the controllable inverting device 700 is the inverted version (“1 - v”) of the bit (“v”) received at the input 710. When the inversion-control signal 730 is deasserted, the bit at the output 715 of the controllable inverting device 700 is the original version (“v”) of the bit (“v”) at the input 710.

[0074]

[0067] The diagnosis capture mode in which diagnosable library scan cells such as the diagnosable library scan cell 300 in Fig. 3 and the diagnosable four-bit library scan cells 400 and 500 in Figs. 4 and 5 operate according to various embodiments of the disclosed technology can be activated based on the inversion-control signal received at their inversion-control inputs and the local scan enable signal received at their scan enable inputs when a circuit is being tested. The local scan enable signal can be derived based on a diagnosis mode signal and a regular scan enable signal using a control signal generation device. The same control signal generation device can also be used to generate the inversion-control signal. Fig. 8 illustrates an example of a control signal generation device 800 that may be implemented according to various embodiments of the disclosed technology. The control signal generation device 800 comprises an inverter 810 and an OR gate 820. The inverter 810 is configured to generate an inversion-control signal 850 by inverting a regular scan enable signal 830. The OR gate 820 is configured to generate a local scan enable signal 860 by performing a logical OR operation of the regular scan enable signal 830 and a diagnosis mode signal 840. When the regular scan enable signal 830 is asserted and the diagnosis mode signal 840 is deasserted, the local scan enable signal 860 is asserted and the inversion-control signal 850 is deasserted, activating the normal shift mode for the scan cell. When both the regular scan enable signal 830 and the diagnosis mode signal 840 are deasserted, the local scan enable signal 860 is deasserted, activating the normal capture mode for the scan cell. When both the regular scan enable signal 830 and the diagnosis mode signal 840 are asserted, the local scan enable signal 860 is asserted and the inversion-control signal 850 is deasserted, activating the diagnosis shift mode for the scan cell. It should be noted that the diagnosis shift mode is essentially the same as the normal shift mode. When the regular scan enable signal 830 is deasserted and the diagnosis mode signal 840 is asserted, both the local scan enable signal 860 and the inversion-control signal 850 are asserted, activating the diagnosis capture mode for the scan cell. In the diagnosis capture mode, the scan cell is to capture the inverted version (“1 - v”) of a bit (“v”) received at the data input of the controllable inverting device. A table 870 in Fig. 8 summarizes the above-described four test-related modes in which a scan cell can operate based on the regular scan enable signal 830 and the diagnosis mode signal 840.

[0075]

[0068] In Fig. 8, the inverter 810 is configured to invert the regular scan enable signal 830 to generate the inversion-control signal 850. The inverter 810 may be placed into a library scan cell. Fig. 9 illustrates an example of a diagnosable library scan cell 900 that may be implemented according to various embodiments of the disclosed technology. Like the diagnosable library scan cell 400 in Fig. 4, the diagnosable library scan cell 900 comprises a state element 910, a two-way multiplexer 930, and a controllable inverting device 920. However, the diagnosable library scan cell 900 further comprises an inverter 995 placed between an inversion-control input 990 and the controllable inverting device 920. As such, a regular scan enable signal can be directly coupled to the inversion-control input 990. The diagnosable library scan cell 900 can be configured to operate in four test- related modes including a diagnosis capture mode. The diagnosis capture mode is activated when the regular scan enable signal is desserted and a diagnosis mode signal is asserted assuming a local scan enable signal is derived from a logical OR operation of the regular scan enable signal and the diagnosis mode signal. This is similar to the table 870 in Fig. 8. The only difference is that the regular scan enable signal is used as the inversion-control signal.

[0076]

[0069] Fig. 10 illustrates another example of a control signal generation device 1000 that may be implemented according to various embodiments of the disclosed technology. The control signal generation device 1000 comprises an inverter 1010, an OR gate 1020 and an AND gate 1080. Similar to the OR gate 820 in Fig. 8, the OR gate 1020 is configured to generate a local scan enable signal 1060 by performing a logical OR operation of a regular scan enable signal 1030 and a diagnosis mode signal 1040. Also similar to the inverter 810 in Fig. 8, the inverter 1010 is configured to invert a regular scan enable signal 1030. Unlike the control signal generation device 800 in Fig. 8, however, the output of the inverter 1010 is not the output of the control signal generation device 1000. Rather, the AND gate 1080 is configured to combine the output of the inverter 1010 with the diagnosis mode signal 1040 to generate the inversion-control signal 1050. When the regular scan enable signal 1030 is asserted and the diagnosis mode signal 1040 is deasserted, the local scan enable signal 1060 is asserted and the inversion-control signal 1050 is deasserted, activating the normal shift mode for the scan cell. When both the regular scan enable signal 1030 and the diagnosis mode signal 1040 are deasserted, the local scan enable signal 1060 is deasserted, activating the normal capture mode for the scan cell. When both the regular scan enable signal 1030 and the diagnosis mode signal 1040 are asserted, the local scan enable signal 1060 is asserted and the inversion-control signal 1050 is deasserted, activating the diagnosis shift mode for the scan cell. It should be noted that the diagnosis shift mode is essentially the same as the normal shift mode. When the regular scan enable signal 1030 is deasserted and the diagnosis mode signal 1040 is asserted, both the local scan enable signal 1060 and the inversion-control signal 1050 are asserted, activating the diagnosis capture mode for the scan cell. In the diagnosis capture mode, the diagnosable library scan cell is to capture the inverted version (“1 - v”) of a bit (“v”) received at the data input of the controllable inverting device. A table 1070 in Fig. 10 summarizes the above-described four test-related modes in which a diagnosable library scan cell can operate based on the regular scan enable signal 1030 and the diagnosis mode signal 1040.

[0077]

[0070] A comparison of the table 1070 in Fig. 10 with the table 870 in Fig. 8 shows one difference between them. In the normal capture mode: the inversion-control signal is deasserted in the table 1070 but asserted in the table 870. The assertion of the inversioncontrol signal in the normal capture mode may not matter in many cases since the inversion happens on the shift path of the scan cell and should not affect the capture operation. In some situations, however, the inserted controllable inverting devices may impact the circuit behavior in capture cycles. As noted previously, a scan cell may serve as a part or a whole of a shift register. When the controllable inverting device is placed inside the scan cell to improve diagnosis coverage, such a scan cell can capture the inverted version rather than the original version of the bit that it is supposed to capture in the normal capture mode.

[0078]

[0071] In some embodiments of the disclosed technology, the diagnosis capture mode can be activated directly by a regular scan enable signal and an inversion-control signal. The regular scan enable signal is coupled to the scan enable inputs of the scan cells implemented with diagnosable library scan cells like those implemented with conventional library scan cells. The inversion-control signal is coupled to the inversioncontrol inputs of the scan cells implemented with diagnosable library scan cells. When the regular scan enable signal is deasserted and the inversion-control signal is asserted, the scan cells implemented with diagnosable library scan cells operate in the diagnosis capture mode. The inversion-control signal may be generated in the circuit using a counter, a state machine and a register. The state machine and the register may be associated with the IJTAG network (IEEE P1687 Internal JTAG).

[0079]

[0072] A diagnosable library scan cell can have a silicon footprint larger than a corresponding conventional library scan cell due to the built-in controllable inverting device. To reduce silicon area overhead, a diagnosis coverage analysis process may be employed to identify scan cells in a circuit design that need to be implemented using the diagnosable library scan cell according to various embodiments. The rest of the scan cells in the circuit design can still be implemented using convention library scan cells which have smaller silicon footprints. The diagnosis coverage analysis process may comprise design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof. The diagnosis coverage can be calculated based on how many equivalent fault groups have a single fault. A simple way to compute the diagnosis coverage is to divide the number of equivalent fault groups by the number of faults. Faults in an equivalent fault group are faults that cannot be separated or distinguished under a certain condition or using one or more specific diagnosis techniques. In chain diagnosis, two equivalent faults are often associated with two scan cells, particularly two neighboring ones.

[0080]

[0073] When the production test patterns are insufficient to achieve 100% diagnosis coverage, additional test patterns may be generated for diagnosis to ensure as many faults as possible to have unique failing bits. This type of ATPG may be referred to as diagnosis ATPG or diagnosis (test) pattern generation. Two diagnosis test pattern generation algorithms may be employed to create two kinds of test patterns for separating faults at two neighboring scan cells, namely scan cell K and scan cell K + 1). One is referred to as observe-unload test patterns and the other is referred to as observe-load test patterns. To distinguish whether the scan cell K or the scan cell (K + 1) has the stuck-at-v fault, for example, the observe-unload test generation algorithm tries to create a test pattern to determine specifically whether the scan cell K has the stuck-at-v fault. In this algorithm, each of scan cells (K + 1), K, (K - 1),..., 0 is constrained to a bit value v and an ATPG process is performed to ensure that the scan cell K can capture a bit value (1 - v). If the unloaded test response bit for the scan cell K is (1 - v), then the scan cell K does not have the stuck-at-v fault. Otherwise, the scan cell K has the stuck-at-v fault. The captured value (1 - v) is referred to as clean bit data. For a scan pattern, scan loading operations are performed before the capture operations. To ensure the capture data is clean, each of the scan cells from cell ( + l) to its downstream scan cell in the same scan chain is loaded with a value v to ensure no loading failures due to the stuck-at-v fault in either of the scan cells ( T+ 1) and K. The diagnosis ATPG process decides how to supply the clean bit data. Without loading errors due to the constraints, the capture value (1 - v) at the scan cell K can be guaranteed to be clean. The unloaded value at scan cell K is referred to as an output care bit because its value indicates whether or not the scan cell K has the stuck- at-v fault.

[0081]

[0074] On the other hand, to distinguish whether the scan cell K or the scan cell (K + 1) has the stuck-at-v fault, the observe-load test generation algorithm tries to create a test pattern to determine specifically whether the scan cell (K + 1) has the stuck-at-v fault. In this algorithm, the scan cell (K + 1) is loaded with a value (1 - v) and each of scan cells K, (K - 1),..., 0 is constrained to a value v; and a diagnosis ATPG process is performed to propagate the fault effect at the scan cell K + 1) output, which should excite the fault at the scan cell (K + 1) due to the last load cycle having a value (1 - v) at the scan cell (K + 1) but not the fault at the scan cell K due to its load value v, to a clean observation value. The clean observation value should be captured by either a scan cell in other good scan chains or any scan cell downstream of the scan cell K, referring to as a chain observation point. This algorithm constrains the scan cell K and its downstream scan cells to value v. These constraints ensure that all these loading values are unaffected by the fault in either of the scan cells (K + 1) and K. If the fault is at the scan cell (K + 1), this test pattern can observe a failing bit at the clean observation point. If the fault is at the scan cell K, this pattern cannot have a failing bit at the clean observation point. This clean observation point is the output care bit that needs to be observed.

[0082]

[0075] For design with test response compaction, it is necessary to ensure that unknown values from other chains do not mask the output care bit. Both observe-unload and observe-load patterns have one output care bit each.

[0083]

[0076] There are several reasons why diagnosis ATPG cannot always generate the abovedescribed two types of test patterns. One reason is that diagnosis ATPG cannot find a test pattern that can distinguish the two scan cells under the abovementioned constraints. Scan cells can be used to control circuit behavior, such as scan wrapper cells in core boundaries for hierarchical tests, low-power clock management scan cells, and on-chip clock generator control scan cells. When these scan cells are faulty, it significantly impacts circuit behavior, complicating chain diagnosis. As described in the requirements to generate observe-unload and observe-load test patterns for a target cell, scan cells downstream of the target cell need to be constrained to ensure clean data. These constraints may shut off hierarchical test capability or capture clock operations. Without proper capture operations, neither of the two types of test patterns can be created.

[0084]

[0077] Another reason why diagnosis ATPG cannot always generate the above-described two types of test patterns is that the test generation program can reach a user-defined CPU (central processing unit) time limit or backtracking limit. Due to constraints on loading values, scan cells do not have complete controllability, such that more capture clock cycles may be needed to get specific values at certain scan cells. Using more capture clock cycles increases ATPG complexity exponentially. In other words, some test patterns are expected to fail to be created due to sequential depth limits. In modem designs, it is impractical to expect ATPG to use more than four capture clock cycles in its test generation search space. For designs with test compression, since there are many constraints on loading value, many input care bits may exceed the test compression capacity.

[0085]

[0078] Still another reason why diagnosis ATPG cannot always generate the above-described two types of test patterns is that two neighboring scan cells are in a shift register. For example, some scan cells are often added to test chips without functional usage. Fig. 11 illustrates an example of two neighboring scan cells 1110 and 1120 forming a part or a whole of a shift register. All failing bits created from the shift register are independent of fault location. As such, the two neighboring scan cells 1110 and 1120 are not distinguishable using any test patterns. Fig. 12 illustrates another example of two neighboring scan cells 1230 and 1240 forming a part or a whole of a shift register. They are also not distinguishable using any test patterns even through each of the two neighboring scan cells 1230 and 1240 has a parallel input and a scan enable input.

[0086]

[0079] To overcome the limitations of diagnosis test pattern generation like those described above and to further increase the diagnosis coverage, diagnosable library scan cells like the library scan cells 400 (Fig. 4), 500 (Fig. 5), 600 (Fig. 6), 900 (Fig. 9) or those without scan enable inputs may be employed to help create clean bit data sources. Fig. 13 illustrates an example of a diagnosable library scan cell 1300 with no scan enable input that may be implemented according to various embodiments of the disclosed technology. Here, the controllable inverting device in a library scan cell can be referred to as a diagnosis point. By adding a diagnosis point between a pair of scan cells (K+ 1) and K, an observe -unload test pattern can be created successfully for the scan cell K so that the scan cells (K + 1 ) and K can be distinguished. For the stuck-at-0 fault, for example, value 0 are loaded to both the scan cells (K + 1) and K. As such, the scan cell (K + 1) loading value 0 will provide the clean bit value 1 at the scan cell K after the capture cycle in the diagnosis capture mode due to the inversion at the shift path of the scan cell K. Diagnosis points (library scan cells) can also be employed to solve diagnosis coverage problems associated with other types of chain faults which will be discussed in detail below, Inserting diagnosis points is equivalent to replacing conventional library scan cells with library scan cells inserted with controllable inverting devices.

[0087]

[0080] As noted previously, one approach to determine locations of diagnosis points is based on diagnosis test pattern generation (test pattern generation for diagnosis). According to various embodiments of the disclosed technology, diagnosis simulation is first performed for production test patterns to identify equivalent fault groups. Then, observe-unload or observe-load test patterns are generated to break up neighboring equivalent fault groups. Upon the test patterns being generated, diagnosis simulation is incrementally performed with these new test patterns to break up equivalent fault groups further. Next, diagnosis test patterns may be generated for non-neighboring equivalent faults left and diagnosis simulation is performed incrementally with these new test patterns to break up equivalent fault groups still further. Based on the remaining equivalent fault groups that have more than one fault, locations of diagnosis points or scan cells to be implemented using diagnosable library scan cells can be determined. Some equivalent faults may not exist in two neighboring scan cells, but a controllable inverting device may still be placed on the shift path between the two scan cells associated with two equivalent faults and in front of the downstream one of the two scan cells, which is equivalent to using a diagnosable library scan cell to implement the downstream scan cell.

[0088]

[0081] Alternatively or additionally, locations of diagnosis points may be determined using a design rule checking (DRC) tool. For example, the design rule checking tool may be configured to search for scan cells that are in or serve as shift registers like the scan cells 1210 - 1240 in Figs. 12A-12B.

[0089]

[0082] Another method for determining locations of diagnosis points is based on diagnosability analysis. Diagnosability analysis of two neighboring scan cells (K + 1 ) and K with respect to stuck-at-v faults may comprise: determining (1 - v)-controllability of a data input of the scan cell K, and determining observability of a data output of the scan cell (K + 1). The (1 - v)-controllability is defined as the difficulty of setting a particular logic signal to a logic value of (1 - v), and the observability is defined as the difficulty of observing the state of a logic signal. SCOAP (Sandia controllability / observability analysis program) testability measures may be employed for determining the (1 - v)-controllability and the observability. The above three approaches for determining scan cells to be implemented using diagnosable library scan cells may be used individually or in any combination.

[0090]

[0083] Fig. 14 illustrates an example of using diagnosable library scan cells in a scan chain 1400 that may be implemented according to various embodiments of the disclosed technology. Stuck-at faults associated with scan cells 1410, 1411 and 1412 are in an equivalent fault group, and stuck-at faults associated with scan cells 1413 and 1415 are in another equivalent fault group. Diagnosable library scan cells are used to implement the scan cells 1410 and 1411 to make the stuck-at faults associated with the scan cells 1410, 1411 and 1412 unique. A diagnosable library scan cell is used to implement the scan cell 1413 to make the stuck-at faults associated with the scan cells 1413 and 1415 unique. The inversion-control inputs of the three diagnosable scan cells 1410, 1411 and 1413 are coupled to an inversion-control signal 1470. The scan enable inputs of the three corresponding diagnosable scan cells 1410, 1411 and 1413 are coupled to a local scan enable signal 1450, and scan enable inputs of the rest of scan cells are coupled to a regular scan enable signal 1460. The local scan enable signal 1450 and the inversion-control signal 1470 can be generated locally based on the regular scan enable signal 1460 and a diagnosis mode signal 1480. As will be discussed below, the diagnosis mode signal 1480 can be a static signal provided by a scan cell such as the first one counted from the scan input of the scan chain 1400. This kind of setup can reduce area overhead and makes the diagnosis-related mode control flexible. In circuit designs with low power management, scan cells may not have a capture clock, which is needed to have proper observe-unload patterns even with diagnosis points added. Typically, these clocks must be active when the regular scan enable signal 1460 is asserted to ensure proper normal shift operation. To fix this problem, the modified scan enable signal 1450 can be used to activate the shift clock.

[0091]

[0084] Fig. 15 illustrates another example of using diagnosable library scan cells in a scan chain 1500 that may be implemented according to various embodiments of the disclosed technology. Stuck-at faults associated with scan cells 1510, 1511 and 1512 are in an equivalent fault group, and stuck-at faults associated with scan cells 1513 and 1515 are in another equivalent fault group. Diagnosable library scan cells are used to implement the scan cells 1510 and 1511 to make the stuck-at faults associated with the scan cells 1510, 1511 and 1512 unique. A diagnosable library scan cell is used to implement the scan cell 1513 to make the stuck-at faults associated with the scan cells 1513 and 1515 unique. The use of diagnosable library scan cells in Fig. 15 is similar to the one shown in Fig. 14. Also similar is the controlling of the scan cells 1510, 1511 and 1513 by an inversion-control signal 1570. A difference between Fig. 15 and Fig. 14 is that scan enable inputs of the scan cells in the scan chain 1500 are all coupled to a “local” scan enable signal 1550 whereas only the diagnosable scan cells 1410, 1411, and 1413 in the scan chain 1400 are controlled by the local scan enable signal 1460. Here, the “local” scan enable signal 1550 may become a global scan enable signal if it is used for all of the scan chains in the circuit design (maybe referred to as a modified scan enable signal). This arrangement is beneficial to scan cells that do not have clear separation between shift path and capture path and it is challenging to locate scan enable inputs for diagnosable scan cells. Moreover, the clocks of all scan cells are activated during the diagnosable capture mode due to the assertion of the “local” scan enable signal 1550, the problem of missing capture clocks will not occur. The downside is that even regular scan cells stay in shift and don’t capture from their functional inputs, which does not provide benefit to logic fault detection. However, considering that the special diagnosis test patterns are generated for breaking remaining equivalent faults, this should not have a big impact.

[0085] In Figs. 8, 10, 14 and 15, two control signals, the regular scan enable signal and the diagnosis mode signal, are needed for activating various modes of the scan chains. The circuit typically has an input pin for or can locally generate the regular scan enable signal. The regular scan enable signal may be referred to as a dynamic signal as it changes during the period of applying a test pattern: causing scan chains to change from the shift mode to the capture mode and then change back to the shift mode. If the diagnosis mode signal needs to be changed as well, an additional input pin or an additional locally generated active signal is required. If the diagnosis mode signal can be made as a static signal, i.e., no need to change during the period of applying a test pattern, it can be provided by a storage device and thus no extra pin is required. The control signal generation device 800 in Fig. 8 and the control signal generation device 1000 in Fig. 10 are examples in which the diagnosis mode signal is a static signal as shown by the tables 870 and 1070. The storage device may be a scan cell or a shadow register of a scan cell in the scan chains or a test data register in an IJTAG network (IEEE P1687 Internal JTAG). A scan cell can be used for this purpose because the diagnosis mode signal typically has no effect during the loading of the scan chain. In either the table 870 in Fig. 8 or the table 1070 in Fig. 10, no matter what the value of the diagnosis mode signal is, the other three signals are the same for either the normal shift mode or the diagnosis shift mode.

[0092]

[0086] Fig. 16 illustrates an example of a scan cell 1600 that can be used to implement a storage device for storing the diagnosis mode signal according to various embodiments of the disclosed technology. The scan cell 1600 comprises a state element 1610 and a two-way multiplexer 1620. To make the scan cell 1600 stable during the functional mode and the normal capture mode, the parallel output 1660 of the scan cell 1600 is connected to the parallel input 1640. To avoid the stored diagnosis mode signal 1680 being changed during the diagnosis capture mode if a circuit configuration like the one shown in Fig. 8 is used, the scan enable input 1690 of the scan cell 1600 is coupled to the output of an XOR gate 1630 rather directly to a local scan enable signal 1650. The two inputs of the XOR gate 1630 are the local scan enable signal 1650 and an inversion-control signal 1670. Another way to avoid the problem is to let the scan cell 1600 be controlled by a regular scan enable signal. Another way to avoid the stored diagnosis mode signal 1680 being changed during either the functional mode or the normal capture mode or the diagnosis capture mode is to use a shadow register for the scan cell 1600. The shadow register can be loaded with a bit “0” in both the functional mode and the normal test mode, can change to a bit “1” after being loading loaded with the first diagnosis test pattern, and then can change back to a bit “0” after the capture operation for the last diagnosis test pattern.

[0093] Chain Diagnosis Using Diagnosable Library Scan Cells

[0094]

[0087] As noted previously, the analysis of chain pattern responses not only can identify faulty scan chains but also may determine the fault model associated with each of the faulty scan chains. The fault models for scan chains can include stuck-at faults (stuck-at- O / stuck-at-1), slow faults (slow-to-rise / slow-to-fall / slow) and fast faults (fast-to-rise / fast- to-fall / fast). Slow faults are normally caused by setup-time violations while fast faults are normally caused by hold-time violations. The fault models often include a fault model reserved for those that can be assigned to none of the above fault models. With a specific fault model, a scan chain defect can also be modeled as a permanent fault (the fault happens for all shift cycles) or an intermittent fault (the fault only happens for a subset of shift cycles). Note that the defect itself is still permanent, but the fault model used to represent the defect is intermittent. An intermittent fault may be used to describe some characteristics for an un-modeled defect. For example, an intermittent stuck-at-0 fault refers to a defect that can cause some shift operations to fail as if a stuck-at-0 fault intermittently appears while which shift cycles may fail is not known. Fig. 17 illustrates a table 1700 that shows a chain pattern and chain pattern responses of a faulty scan chain for the above eight permanent fault models. The faulty scan chain has 12 scan cells and the chain pattern is 001100110011 where the leftmost bit is loaded into scan cell No. 11 and the rightmost bit is loaded into scan cell No. 0. By comparing unloaded chain pattern responses with those listed in the table 1700, one can identify the fault model associated with the faulty scan chain. Fig. 17 is just an example. Other types of fault models may also be included in the table.

[0095]

[0088] Fig. 18A illustrates a flowchart 1800 showing a process of using a diagnosable library scan cell to determine whether a scan cell or its upstream scan cells has a stuck-at-v fault that may be implemented according to various examples of the disclosed technology. Fig.

[0096] 18B illustrates a diagram 1805 corresponding to the process shown by the flowchart 1800. Here, the number “v” can be “0” or “1”.

[0097]

[0089] In operation 1810, a test pattern is shifted into scan chains to load a bit of “v” into a scan cell (K + 1) in one of the scan chains. The scan cell (K + 1) is an upstream neighboring scan cell of a scan cell K. The scan cell K is implemented using a diagnosable library scan cell such as the diagnosable library scan cell 400 in Fig. 4.

[0098]

[0090] In operation 1820, a capture operation is performed for one clock cycle. Here, the scan cell K is configured to operate in a diagnosis captured mode - capturing a bit of “1 - v” outputted by its controllable inverting device which is controlled by an inversion-control signal 1855. The diagnosis captured mode is activated based a regular scan-enable signal and a diagnosis mode signal that is supplied by a storage device, both of which are not shown in Fig. 18B. At least a scan enable input of the scan cell K is coupled to a local scan enable signal 1865. The scan enable input of the scan cell (K + 1 ) can be coupled to the local scan enable signal 1865 as shown in Fig. 15 or to the regular scan-enable signal as shown in Fig 14. The modified scan enable signal 1865 and the inversion-control signal 1855 are derived based on the regular scan enable signal and the diagnosis mode signal like the examples shown in Fig. 8 or Fig. 10.

[0091] In operation 1830, the bit of “1 - v” captured by the scan cell K is shifted out to determine whether the scan cell K has a stuck-at-v fault at output side. If the shifted-out bit is “ 1 - v”, no stuck-at-v fault is at output side of the scan cell K and the stuck-at-v fault should be at output side of an upstream scan cell for the scan cell K. Otherwise, the stuck-at-v fault is at the output side of the scan cell K. It should be noted that the process shown by the flowchart 1800 can be used to determine whether the scan cell K has a stuck-at-v fault at input side. This is equivalent to determining whether the scan cell (K + 1) has a stuck-at- v fault at output side. In such a case, the controllable inverting device 1845 is inserted in front of the scan cell (K + 1) instead of the scan cell K.

[0099]

[0092] Fig. 19A illustrates a flowchart 1900 showing a process of using a diagnosable library scan cell to determine whether a scan cell or its upstream scan cells has a slow-to-fall / rise fault that may be implemented according to various examples of the disclosed technology. Fig. 19B illustrates a diagram 1905 corresponding to the process shown by the flowchart 1900. To save space, the diagram 1905 does not include the unloading operation in the diagnosis shift mode. A bit captured by a downstream scan cell for the scan cell at issue will not be changed after being unloaded because all downstream scan cells should be fault-free (assuming only one scan cell is faulty in one scan chain). Here, the number “v” can be “0” or “1”. If the number “v” is “0”, the fault to be located is a slow-to-rise fault. Otherwise, the fault to be located is a slow-to-fall fault.

[0100]

[0093] In operation 1910, a test pattern is shifted into scan chains to load a bit of “v” into each of scan cells K + 1) and K in one of the scan chains. The scan cell (K + 1) is an upstream neighboring scan cell of the scan cell K. The scan cell K is implemented using a library diagnosable scan cell such as the diagnosable library scan cell 400 in Fig. 4.

[0101]

[0094] In operation 1920, a capture operation is performed for each of two clock cycles. The scan cell K and a scan cell (K- 1) are configured to operate in a diagnosis captured mode for each of two clock cycles - the scan cell K capturing the inverted version of a bit received by its controllable inverting device which is controlled by an inversion-control signal 1955 while the scan cell (K- ) capturing a bit outputted by the scan cell K. The diagnosis captured mode is activated based a regular scan-enable signal and a diagnosis mode signal that is supplied by a storage device, both of which are not shown in Fig.

[0102] 19B. At least scan enable inputs of the scan cells K and (K - 1) are coupled to a local scan enable signal 1965. The scan enable input of the scan cell (K+ 1) can be coupled to the local scan enable signal 1965 as shown in Fig. 15 or to the regular scan-enable signal as shown in Fig 14. The local scan enable signal 1965 and the inversion-control signal 1955 are derived based on the regular scan enable signal and the diagnosis mode signal like the examples shown in Fig. 8 or Fig. 10.

[0103]

[0095] In operation 1930, a bit captured by the scan cell (K - 1) at a second clock cycle in the two clock cycles is shifted out to determine whether the scan cell K has a slow-to-fall / rise fault at output side. If the shifted-out bit is “1 - v”, no slow-to-fall / rise fault is at output side of the scan cell K and the slow-to-fall / rise fault should be at output side of a upstream scan cell for the scan cell K. If the shifted-out bit is “v”, the scan cell K has a slow-to- fall / rise fault (v = 1, slow-to-fall fault; v = 0, slow-to-rise fault) at output side. It should be noted that the process shown by the flowchart 1900 can be used to determine whether the scan cell K has a slow-to-fall / rise fault at input side, which is equivalent to determining whether the scan cell K + 1) has a slow-to-fall / rise fault at output side. In such a case, the scan cell (K + 1), rather than the scan cell K, is implemented using a diagnosable library scan cell.

[0104]

[0096] Fig. 20 A illustrates a flowchart 2000 showing a process of using a diagnosable library scan cell to determine whether a scan cell or its upstream scan cells has a fast-to-fall / rise fault that may be implemented according to various examples of the disclosed technology. Fig. 20B illustrates a diagram 2005 corresponding to the process shown by the flowchart 2000. To save space, the diagram 2005 does not include the unloading operation in the diagnosis shift mode. A bit captured by a downstream scan cell for the scan cell at issue will not be changed after being unloaded because all downstream scan cells should be fault-free (assuming only one scan cell is faulty in one scan chain). Here, the number “v” can be “0” or “1”. If the number “v” is “0”, the fault to be located is a fast-to-rise fault. Otherwise, the fault to be located is a fast-to-fall fault.

[0105]

[0097] In operation 2010, a test pattern is shifted into scan chains to load a bit of “v” into each of scan cells (K + 1) and K in one of the scan chains. The scan cell (K + 1) is an upstream neighboring scan cell of the scan cell K. The scan cell K is implemented using a diagnosable library scan cell such as the diagnosable library scan cell 400 in Fig. 4.

[0106]

[0098] In operation 2020, a capture operation is performed for one clock cycle. The scan cell K and a scan cell (K- 1) are configured to operate in a diagnosis captured mode - the scan cell K capturing the inverted version of a bit received by its controllable inverting device which is controlled by an inversion-control signal 2055 while the scan cell (K - 1) capturing a bit outputted by the scan cell K. The diagnosis captured mode is activated based a regular scan-enable signal and a diagnosis mode signal that is supplied by a storage device, both of which are not shown in Fig. 20B. At least scan enable inputs of the scan cells K and (K - 1) are coupled to a local scan enable signal 2065. The scan enable input of the scan cell K + 1) can be coupled to the local scan enable signal 2065 as shown in Fig. 15 or to the regular scan-enable signal as shown in Fig 14. The local scan enable signal 2065 and the inversion-control signal 2055 are derived based on the regular scan enable signal and the diagnosis mode signal like the examples shown in Fig.

[0107] 8 or Fig. 10.

[0108]

[0099] In operation 2030, a bit captured by the scan cell (K - 1) at the one second clock cycle in the two clock cycles is shifted out to determine whether the scan cell K has a fast-to- fall / rise fault at output side. If the shifted-out bit is “v”, no fast-to-fall / rise fault is at output side of the scan cell K and the fast-to-fall / rise fault should be at output side of a upstream scan cell for the scan cell K. If the shifted-out bit is “1 - v”, the scan cell K has a fast-to-fall / rise fault (v = 1, fast-to-fall fault; v = 0, fast-to-rise fault) at output side. It should be noted that the process shown by the flowchart 2000 can be used to determine whether the scan cell K has a fast-to-fall / rise fault at input side, which is equivalent to determining whether the scan cell (K + 1) has a fast-to-fall / rise fault at output side. In such a case, the controllable inverting device 2045 is inserted in front of the scan cell (K + 1), rather than the scan cell K.

[0109] Illustrative Operating Environment

[0110]

[0100] Various examples of the disclosed technology may be implemented through the execution of software instructions by a computing device, such as a programmable computer. Accordingly, Fig. 21 shows an illustrative example of a computing device 2101. As seen in this figure, the computing device 2101 includes a computing unit 2103 with a processing unit 2105 and a system memory 2107. The processing unit 2105 may be any type of programmable electronic device for executing software instructions, but it will conventionally be a microprocessor. The system memory 2107 may include both a read-only memory (ROM) 2109 and a random access memory (RAM) 2111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 2109 and the random access memory (RAM) 2111 may store software instructions for execution by the processing unit 2105.

[0111]

[0101] The processing unit 2105 and the system memory 2107 are connected, either directly or indirectly, through a bus 2113 or alternate communication structure, to one or more peripheral devices. For example, the processing unit 2105 or the system memory 2107 may be directly or indirectly connected to one or more additional memory storage devices, such as a “hard” magnetic disk drive 2115, a removable magnetic disk drive 2117, an optical disk drive 2119, or a flash memory card 2121. The processing unit 2105 and the system memory 2107 also may be directly or indirectly connected to one or more input devices 2123 and one or more output devices 2125. The input devices 2123 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 2125 may include, for example, a monitor display, a printer and speakers. With various examples of the computer 2101, one or more of the peripheral devices 2115-2125 may be internally housed with the computing unit 2103. Alternately, one or more of the peripheral devices 2115-2125 may be external to the housing for the computing unit 2103 and connected to the bus 2113 through, for example, a Universal Serial Bus (USB) connection.

[0112]

[0102] With some implementations, the computing unit 2103 may be directly or indirectly connected to one or more network interfaces 2127 for communicating with other devices making up a network. The network interface 2127 translates data and control signals from the computing unit 2103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the interface 2127 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0113]

[0103] It should be appreciated that the computer 2101 is illustrated as an example only, and it is not intended to be limiting. Various embodiments of the disclosed technology may be implemented using one or more computing devices that include the components of the computer 2101 illustrated in Fig. 21, which include only a subset of the components illustrated in Fig.21, or which include an alternate combination of components, including components that are not shown in Fig. 21. For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both. Conclusion

[0114]

[0104] Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments to which the principles of the disclosed technologies can be applied, it should be recognized that the illustrated embodiments are only preferred examples of the technologies and should not be taken as limiting the scope of the disclosed technology. Rather, the scope of the disclosed technology is defined by the following claims and their equivalents. We therefore claim as our disclosed technology all that comes within the scope and spirit of these claims.

Claims

1. What is claimed is:

1. A library scan cell, comprising:3.one or more state elements configured to serve as a single bit or multiple bits of the library scan cell; and4.a controllable inverting device placed in a shift path of the library scan cell and between an input of one of the one or more state elements and a serial input of the library scan cell or an output of another one of the one or more state elements, a control input of the controllable inverting device being coupled to an inversion-control input of the library scan cell, wherein the controllable inverting device is configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal received at the inversion-control input, and5.wherein the one of the one or more state elements is configured to operate in a plurality of test-related modes, the plurality of test-related modes comprising a diagnosis capture mode in which the one of the one or more state elements is configured to capture the inverted version of a bit received at the data input of the controllable inverting device.

2. The library scan cell recited in claim 1, wherein the diagnosis capture mode is activated based on the inversion-control signal and a local scan enable signal received at a scan enable input of the library scan cell when a circuit is being tested, the local scan enable signal being derived based on a diagnosis mode signal and a regular scan enable signal, the diagnosis mode signal being provided by a storage device in the circuit.

3. The library scan cell recited in claim 2, wherein the storage device is another scan cell or a shadow register of another scan cell in the circuit.

4. The library scan cell recited in claim 2, wherein the local scan-enable signal is derived by a logical OR operation of the diagnosis mode signal and the regular scan enable signal.

5. The library scan cell recited in claim 2, wherein the inversion-control signal is derived by inverting the regular scan enable signal.

6. The library scan cell recited in claim 2, wherein the inversion-control signal is derived by a logical AND operation of the diagnosis mode signal and a signal derived by inverting the regular scan enable signal.

7. The library scan cell recited in claim 2, wherein the local scan enable signal is a global scan enable signal used by other scan cells in the circuit.

8. The library scan cell recited in claim 1, wherein the library scan cell is used to implement a scan cell in a circuit design which is identified by design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof.

9. The library scan cell recited in claim 1, further comprising:12.another controllable inverting device being placed in the shift path of the library scan cell, an output of the another controllable inverting device being coupled to a serial input of a state element in the one or more state elements that is different from one of the one or more state elements, a control input of the another controllable inverting device being also coupled to the inversion-control input of the library scan cell.

10. The library scan cell recited in claim 1, further comprising:14.one controllable inverting device for each of state elements in the one or more state elements that are different from one of the one or more state elements, the one controllable inverting device being placed in the shift path of the library scan cell, a control input of the one controllable inverting device being also coupled to the inversion-control input of the library scan cell.

11. A method for scan chain diagnosis, comprising:16.shifting a test pattern into scan chains to load a bit of “v” into a scan cell (K+ 1) in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of a scan cell K, the scan cell K being implemented using a diagnosable library scan cell, the diagnosable library scan cell comprising a state element and a controllable inverting device placed in a shift path of the library scan cell and between a serial input of the library scan cell and an input of the state element, the controllable inverting device being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal received at an inversion-control input of the diagnosable library scan cell;17.performing a capture operation for one clock cycle, the scan cell K being configured to operate in a diagnosis captured mode - capturing a bit of “1 - v” outputted by the controllable inverting device, wherein the diagnosis captured mode is activated based at least in part on the inversion-control signal; and18.shifting out the bit of “1 - v” captured by the scan cell K to determine whether the scan cell K has a stuck-at-v fault at output side.

12. The method recited in claim 11, wherein the diagnosis captured mode is activated based further on a scan enable signal received at a scan enable input of the diagnosable library scan cell, the inversion-control signal and the scan enable signal being derived based on a regular scan enable signal and a diagnosis mode signal, the diagnosis signal being supplied by a storage device in a circuit being tested.

13. A method for scan chain diagnosis, comprising:21.shifting a test pattern into scan chains to load a bit of “v” into each of scan cells (K+ 1) and K in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of the scan cell K, the scan cell K being implemented using a diagnosable library scan cell, the diagnosable library scan cell comprising a state element and a controllable inverting device placed in a shift path of the library scan cell and between a serial input of the library scan cell and an input of the state element, the controllable inverting device being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal received at an inversion-control input of the diagnosable library scan cell;22.performing a capture operation for each of two clock cycles, wherein for each of the two clock cycles, the scan cell K and a scan cell (K - 1) are configured to operate in a diagnosis captured mode - the scan cell K capturing the inverted version of a bit received by the controllable inverting device while the scan cell (K - 1) capturing a bit outputted by the scan cell K, wherein the diagnosis captured mode is activated based at least in part on the inversion-control signal; and23.shifting out a bit captured by the scan cell (K - 1) at a second clock cycle in the two clock cycles to determine whether the scan cell K has a slow-to-fall / rise fault at output side.

14. The method recited in claim 13, wherein the diagnosis captured mode is activated based further on a scan enable signal received at a scan enable input of the diagnosable library scan cell, the inversion-control signal and the scan enable signal being derived based on a regular scan enable signal and a diagnosis mode signal, the diagnosis signal being supplied by a storage device in a circuit being tested.

15. A method for scan chain diagnosis, comprising:shifting a test pattern into scan chains to load a bit of “v” into each of scan cells (K+ 1) and K in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of the scan cell K, the scan cell K being implemented using a diagnosable library scan cell, the diagnosable library scan cell comprising a state element and a controllable inverting device placed in a shift path of the library scan cell and between a serial input of the library scan cell and an input of the state element, the controllable inverting device being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal received at an inversion-control input of the diagnosable library scan cell;26.performing a capture operation for one clock cycle, wherein the scan cell K and a scan cell (K- 1) are configured to operate in a diagnosis captured mode - the scan cell K capturing the inverted version of a bit received by the controllable inverting device while the scan cell (K-1) capturing a bit outputted by the scan cell K, wherein the diagnosis captured mode is activated based at least in part on the inversion-control signal; and27.shifting out a bit captured by the scan cell (K- 1) at the one clock cycle to determine whether the scan cell K has a fast-to-fall / rise fault at output side.

16. The method recited in claim 15, wherein the diagnosis captured mode is activated based further on a scan enable signal received at a scan enable input of the diagnosable library scan cell, the inversion-control signal and the scan enable signal being derived based on a regularscan enable signal and a diagnosis mode signal, the diagnosis signal being supplied by a storage device in a circuit being tested.

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