Low-profile submodule for multi-level system-in-package integration

Abstract

The present disclosure relates to a multi-level system-in-package (SIP) module featuring at least one low-profile submodule, and a process for manufacturing the same. In the disclosed multi-level SIP module, the submodule and top components are attached to a top side of the module substrate. The submodule includes submodule components, submodule bumps, and a submodule substrate having a laminate body and metal layers. One of the metal layers protrudes vertically from a boundary surface of the laminate body, while another one of the metal layers is embedded in the laminate body and shares a flat plane with the laminate body. The submodule components and the submodule bumps are mounted on opposite sides of the submodule substrate via corresponding ones of the metal layers, respectively. Additionally, the submodule bumps extend towards the top side of the module substrate to provide a stand-off space vertically between the submodule substrate and the module substrate.

Description

LOW-PROFILE SUBMODULE FOR MULTI-LEVEL SYSTEM-IN-PACKAGE INTEGRATIONRelated Applications

[0001] This application claims the benefit of provisional patent application serial number 63 / 714,181 , filed October 31 , 2024, and provisional patent application serial number 63 / 762,405, filed February 24, 2025, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] The present disclosure relates to a multi-level system-in-package (SIP) module with one or more low-profile submodules, and a process of manufacturing the multi-level SIP including the one or more low-profile submodules.Background

[0003] Electronic components have become ubiquitous in modern society. With the popularity of portable consumer electronic products, such as smart phones, tablet computers, and so forth, the demand for microelectronic devices that achieve higher electronic density within a smaller footprint is continually increasing. One approach for advancement is to utilize the full volume of a package to enable greater integration, such as three-dimensional (3D) package integration.

[0004] However, a system-in-package (SIP) module with the 3D package integration, while significantly reducing the footprint and improving electrical performance by shortening signal paths, will lead to a relatively large overall thickness of the final product. In particular, when the SIP module incorporates double-sided packaging in addition to the 3D package integration, the overall thickness of the final product will increase further, which is undesirable for portable devices.

[0005] Accordingly, to accommodate low-profile and small footprint requirements for portable products, and to achieve electronic density andincreased functionality, it is therefore an object of the present disclosure to provide an improved design of a SIP module and a process for making the same. Additionally, due to the increased electronic density and functionality within a small size, the SIP module may also be desired to achieve internal electrical and magnetic isolation.

[0006] The present disclosure relates to a multi-level system-in-package (SIP) module with one or more low-profile submodules, designed to achieve increased functionality within a small footprint and a desired thickness, and a process for manufacturing the multi-level SIP including the one or more low-profile submodules. According to one embodiment, the disclosed multi-level SIP module includes a module substrate, a submodule attached to a top side of the module substrate, and at least one top component attached to the top side of the module substrate. Herein, the submodule includes at least one submodule component, a number of submodule bumps, and a submodule substrate that has at least a laminate body, a top metal layer, and a bottom metal layer. One of the top metal layer and the bottom metal layer protrudes vertically from a corresponding boundary surface of the laminate body, while another one of the top metal layer and the bottom metal layer is embedded in the laminate body and exposed through the laminate body, and shares a flat plane with the laminate body. The at least one submodule component is mounted to a top side of the submodule substrate via the top metal layer, while the submodule bumps are connected to the bottom metal layer on a bottom side of the submodule substrate and extend towards the top side of the module substrate, which provides a stand-off space that is vertically between the submodule substrate and the module substrate.

[0007] In one embodiment of the multi-level SIP module, the top metal layer protrudes vertically from a top surface of the laminate body, while the bottom metal layer is embedded in the laminate body and exposed through the laminate body. The bottom side of the submodule substrate is a flat surface composed ofa bottom surface of the laminate body and a bottom surface of the bottom metal layer.

[0008] In one embodiment of the multi-level SIP module, the bottom metal layer is formed by an embedded trace substrate (ETS) technology and at least includes bottom metal pads to accommodate the submodule bumps, and patterned metal features.

[0009] In one embodiment of the multi-level SIP module, the submodule further includes a patterned mask layer, which is formed on the bottom side of the submodule substrate and has a thickness between 5 pm and 20 pm. The patterned mask layer partially covers each of the bottom metal pads to define locations to mount the submodule bumps, respectively.

[0010] In one embodiment of the multi-level SIP module, the patterned mask layer further covers certain portions of the bottom side of the submodule substrate other than the bottom metal pads.

[0011] In one embodiment of the multi-level SIP module, the top metal layer is embedded in the laminate body and exposed through the laminate body, while the bottom metal layer protrudes vertically from a bottom surface of the laminate body. The top side of the submodule substrate is a flat surface composed of a top surface of the laminate body and a top surface of the top metal layer.

[0012] In one embodiment of the multi-level SIP module, the top metal layer is formed by an ETS technology and at least includes top metal pads to accommodate the at least one submodule component. The bottom metal layer at least includes bottom metal pads, each of which is configured to accommodate a corresponding one of the submodule bumps and protrudes vertically from the bottom surface of the laminate body.

[0013] In one embodiment of the multi-level SIP module, the submodule further includes a patterned mask layer, which is formed on the bottom side of the submodule substrate and has a thickness between 5 pm and 20 pm. The patterned mask layer only partially covers each of the bottom metal pads to define locations to mount the submodule bumps, respectively.

[0014] According to one embodiment, the multi-level SIP module further includes a top mold compound. Herein, the submodule further includes a submodule mold compound that is formed on the top side of the submodule substrate to surround the at least one submodule component. The top mold compound is formed on the top side of the module substrate to fully encapsulate the at least one top component and to surround the submodule.

[0015] In one embodiment of the multi-level SIP module, the top mold compound and the submodule mold compound are formed from different materials.

[0016] In one embodiment of the multi-level SIP module, the at least one top component includes a first top component, which is positioned in the stand-off space vertically between the bottom side of the submodule substrate and the top side of the module substrate and surrounded by submodule bumps. A gap between the bottom surface of the laminate body of the submodule substrate and a top surface of the first top component has a vertical distance between 10 pm and 50 pm and is filled with the top mold compound.

[0017] In one embodiment of the multi-level SIP module, the at least one top component further includes a second top component, which is positioned horizontally outside the submodule.

[0018] In one embodiment of the multi-level SIP module, the at least one top component is positioned horizontally outside the submodule. No electronic component is surrounded by the submodule bumps and positioned vertically between the bottom side of the submodule substrate and the top side of the module substrate. Each of the submodule bumps has a same height of at least 25 pm.

[0019] In one embodiment of the multi-level SIP module, the at least one submodule component is a flip-chip die. The submodule mold compound surrounds and underfills the at least one submodule component without covering a backside of the at least one submodule component. The submodule further includes a stiffening layer, which is formed over the submodule mold compound to encapsulate the backside of the at least one submodule component. Herein, atop surface of the submodule is a top surface of the stiffening layer, and a side surface of the submodule is a combination of a side surface of the submodule substrate, a side surface of the submodule mold compound, and a side surface of the stiffening layer. The top mold compound at least surrounds and underfills the submodule without covering the top surface of the submodule. The submodule does not vertically extend beyond a top surface of the top mold compound.

[0020] According to one embodiment, the multi-level SIP module further includes a module shielding structure. The top surface of the top mold compound and the top surface of the submodule are coplanar. The module shielding structure directly and continuously covers a combination of the top surface of the top mold compound and the top surface of the submodule, and a combination of a side surface of the top mold compound and a side surface of the module substrate.

[0021] According to one embodiment, the multi-level SIP module further includes a submodule side shielding structure. The submodule side shielding structure directly and completely covers the side surface of the submodule, and the top mold compound surrounds the submodule side shielding structure. A cross-sectional surface of the submodule side shielding structure is exposed through the top mold compound at a periphery of the submodule, and is coplanar with the top surface of the top mold compound and the top surface of the submodule. The module shielding structure is in contact with the submodule side shielding structure.

[0022] According to one embodiment, the multi-level SIP module further includes at least one bottom component and a number of bump structures. The at least one bottom component and the bump structures are attached to a bottom side of the module substrate, which is opposite from the top side of the module substrate.

[0023] According to one embodiment, the multi-level SIP module further includes the bottom mold compound that surrounds each of the bump structures without covering an end surface of each of the bump structures. The bottomsurface of the bottom mold compound and the end surface of each of the bump structures are coplanar. The bottom mold compound at least surrounds the at least one bottom component, and the at least one bottom component does not vertically extend beyond the bottom mold compound.

[0024] In one embodiment of the multi-level SIP module, the submodule has a thickness between 200 pm and 350 pm.

[0025] According to one embodiment, a communication device includes a control system, a baseband processor, receive circuitry, and transmit circuitry. Herein, at least one or any combination of the control system, the baseband processer, the transmit circuitry, and the receive circuitry is implemented in a multi-level SIP module, which includes a module substrate, a submodule, and at least one top component. The submodule and the at least one top component are attached to a top side of the module substrate. The submodule includes at least one submodule component, a number of submodule bumps, and a submodule substrate that has at least a laminate body, a top metal layer, and a bottom metal layer. One of the top metal layer and the bottom metal layer protrudes vertically from a corresponding boundary surface of the laminate body, while another one of the top metal layer and the bottom metal layer is embedded in the laminate body and exposed through the laminate body, and shares a flat plane with the laminate body. The at least one submodule component is mounted to a top side of the submodule substrate via the top metal layer, while the submodule bumps are connected to the bottom metal layer on a bottom side of the submodule substrate and extend towards the top side of the module substrate, which provides a stand-off space that is vertically between the submodule substrate and the module substrate.

[0026] According to one embodiment, a method of manufacturing a multi-level SIP module starts with forming a submodule, which includes at least one submodule component, a number of submodule bumps, and a submodule substrate that has at least a laminate body, a top metal layer, and a bottom metal layer. Herein, one of the top metal layer and the bottom metal layer protrudes vertically from a corresponding boundary surface of the laminate body, whileanother one of the top metal layer and the bottom metal layer is embedded in the laminate body and exposed through the laminate body, and shares a flat plane with the laminate body. The at least one submodule component is mounted to a top side of the submodule substrate via the top metal layer, while the submodule bumps are mounted to a bottom side of the submodule substrate via the bottom metal layer. Next, at least one top component is attached to a top side of a module substrate. The submodule is then attached to the top side of the module substrate, where each of the submodule bumps extends from the bottom side of the submodule substrate towards the top side of the module substrate, which provides a stand-off space that is vertically between the submodule substrate and the module substrate.

[0027] In another aspect, any of the foregoing aspects individually or together, and / or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.

[0028] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0029] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0030] Figures 1 A-1 B illustrate an exemplary multi-level system-in-package (SIP) module with an exemplary low-profile submodule according to some embodiments of the present disclosure.

[0031] Figures 2-3 illustrate alternative implementations of the submodule according to some embodiments of the present disclosure.

[0032] Figure 4 provides a flow diagram that illustrates an exemplary process for manufacturing the submodule according to some embodiments of the present disclosure.

[0033] Figures 5A-11 illustrate steps associated with the manufacturing process of the submodule provided in Figure 4.

[0034] Figure 12 provides a flow diagram that illustrates an exemplary process for manufacturing the multi-level SIP module according to some embodiments of the present disclosure.

[0035] Figures 13-20 illustrate steps associated with the manufacturing process of the multi-level SIP module provided in Figure 12.

[0036] Figure 21 is a block diagram of a communication device, which may include the multi-level SIP according to some embodiments of the present disclosure.

[0037] It will be understood that for clarity of illustration, Figures 1 A-21 may not be drawn to scale.Detailed Description

[0038] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0039] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departingfrom the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0041] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude thepresence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0044] Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently redescribed.

[0045] The present disclosure relates to a multi-level system-in-package (SIP) module with one or more low-profile submodules, designed to achieve increased functionality within a small footprint and a desired thickness, and a process for manufacturing the multi-level SIP including the one or more low-profile submodules. In particular, the disclosed multi-level SIP module utilizes three- dimensional (3D) packaging technology to enhance the integration density andutilizes the low-profile submodules to ensure a desired thickness and / or improve electrical performance.

[0046] Figures 1 A-1 B illustrate an exemplary multi-level SIP module 10 according to some embodiments of the present disclosure. Figure 1 A is a cross- sectional diagram illustrating the multi-level SIP module 10, while Figure 1 B is an enlarged cross-sectional diagram illustrating a portion of the multi-level SIP module 10 including an exemplary submodule 12. For the purpose of this illustration, besides the submodule 12, the multi-level SIP module 10 also includes a module substrate 14, four top components 16 (e.g., two first top components 16-1 , one second top component 16-2, and one third top component 16-3), one bottom component 18, four bump structures 20, a top mold compound 22, and a bottom mold compound 24. Herein, the top components 16 are formed on a top side of the module substrate 14, and the submodule 12 is formed on the top side of the module substrate 14 and caps the two first top components 16-1 to provide a stack-up structure. The bottom component 18 is formed on a bottom side of the module substrate 14, and the bump structures 20 are formed on the bottom side of the module substrate 14 and surround the bottom component 18. In different applications, the multi-level SIP module 10 may include fewer or more top components 16 of various types (e.g., surface mounted devices, flip-chip dies, wire-bonding dies, passive electronic components, etc.) and more submodules 12, and each submodule 12 may cap more top components 16 or not cap any top components 16 on the top side of the module substrate 14.Additionally, the multi-level SIP module 10 may include more bottom components 18 of various types (e.g., surface mounted devices, flip-chip dies, wire-bonding dies, passive electronic components, etc.) and fewer or more bump structures 20, formed in different layouts on the bottom side of the module substrate 14. Furthermore, the multi-level SIP module 10 may be a single-side module instead of a double-side module, so that the bottom component 18 and the bump structures 20 may be omitted.

[0047] In detail, the module substrate 14 includes a laminate body 14B, which may be composed of prepreg (PPG) layers (not shown for clarity and simplicity),and multiple metal layers 26 alternating vertically with the PPG layers (not shown for clarity and simplicity). The multiple metal layers 26 have a top metal layer 26TL on a top surface of the laminate body 14B, a bottom metal layer 26BL on a bottom surface of the laminate body 14B, and multiple internal metal layers embedded in the laminate body 14B (not shown for clarity and simplicity). For the purpose of this illustration, the top metal layer 26TL includes top metal pads 26TP (for clarity and simplicity, only certain top metal pads are labeled with a reference number) to accommodate the top components 16 as well as the submodule 12. Each top metal pad 26TP may have a same or different size with an appropriate shape, such as a circle, square, etc. The top metal layer 26TL may also include other top metal features (not shown for clarity and simplicity), such as top routing lines to connect between the top metal pads 26TP and / or to provide passive components (e.g., a ground plane, inductors, capacitors, resistors, etc.). Similarly, the bottom metal layer 26BL includes bottom metal pads 26BP (for clarity and simplicity, only certain bottom metal pads are labeled with a reference number) to accommodate the bottom component 18 and the bump structures 20. Each bottom metal pad 26BP may have a same or different size with an appropriate shape, such as a circle, square, etc. The bottom metal layer 26BL may also include other bottom metal features (not shown for clarity and simplicity), such as bottom routing lines to connect between the bottom metal pads 26BP and / or to provide passive components (e.g., a ground plane, inductors, capacitors, resistors, etc.). The multiple metal layers 26 are electrically connected through vias and are designed to establish electrical connections (with vias) among the submodule 12, the top components 16, the bottom component 18, and the bump structures 20. Additionally, these metal layers 26 may also be configured to provide passive components (e.g., a ground plane, inductors, capacitors, resistors, etc.). The module substrate 14 may have a thickness between 70 pm and 400 pm.

[0048] For a non-limiting example, the two first top components 16-1 are low- profile flip-chip dies with solder balls 30, the second top component 16-2 is a surface mounted device (SMD), and the third top component 16-3 is a flip-chipdie with solder balls 32 (for clarity and simplicity, only one solder ball of the first top component 16-1 and one solder ball of the third top component 16-3 are labeled with reference numbers). Each top component 16 is attached to the top side of the module substrate 14 on one or more corresponding top metal pads 26TP. In different applications, there might be fewer or more top components 16 attached to the top side of the module substrate 14 via corresponding top metal pads 26TP, respectively. The top components 16 may be other electrical components, such as wire-bonding dies, flip-chip dies with die copper pillars, Silicon (Si) devices, power amplifiers (PAs), and / or passive components. The top components 16 might be mounted to the top metal pads 26TP with or without an adhesive material (e.g., the second top component, SMD, 16-2 is mounted to the corresponding top metal pad 26TP with a top adhesive material 34, while the first and third top components, flip-chip dies with solder balls, 16-1 and 16-3 are attached to the corresponding top metal pads 26TP directly).

[0049] Referring to the submodule 12, it is desired to be low-profile (e.g., a thickness H1 between 220pm - 300pm, or between 200pm - 350pm) and may still provide clearance / stand-off height so as to be vertically stacked with certain top components 16 (e.g., the first top components 16-1 ). The submodule 12 includes a submodule substrate 36, one or more submodule components 38, submodule bumps 40, and a submodule mold compound 42, as illustrated in Figure 1 B.

[0050] Herein, the submodule substrate 36 includes a laminate body 36B composed of PPG layers (not shown) and metal layers 44 alternating vertically with the PPG layers, in order to achieve a low-profile for the submodule 12, the submodule substrate 36 may only include 2~5 metal layers 44 and has a thickness T1 between 70 pm -100 pm (metal to metal thickness). For the purpose of this illustration, the submodule substrate 36 includes a top metal layer 44TL, an internal metal layer 44IL, and a bottom metal layer 44BL. The top metal layer 44TL is formed on a top surface of the laminate body 36B (i.e., protruding from the top surface of the laminate body 36B) and includes top metal pads 44TP to accommodate the submodule components 38 (only one top metal pad islabeled with a reference number for clarity and simplicity). The top metal layer 44TL may also include other top metal features (not shown for clarity and simplicity), such as top routing lines to connect between the top metal pads 44TP and / or to provide passive components (inductors / capacitors / resistors). The internal metal layer 44IL is embedded in the laminate body 36B and electrically connected to both the top metal layer 44TL and the bottom metal layer 44BL through vias (not shown for clarity and simplicity). The internal metal layer 44IL may include various metal features (e.g., pads, traces, etc..), which are designed to provide internal electrical connections and / or passive components (inductors / capacitors / resistors).

[0051] Additionally, the bottom metal layer 44BL is also embedded within the laminate body 36B but not fully covered by the laminate body 36B. In other words, the bottom metal layer 44BL is exposed through the laminate body 36B without protruding from a bottom surface of the laminate body 36B. The laminate body 36B and the bottom metal layer 44BL share a planarized bottom plane. The bottom metal layer 44BL includes bottom metal pads 44BP (only one bottom metal pad is labeled with a reference number for clarity and simplicity) to accommodate the submodule bumps 40, respectively, and bottom routing lines to connect between the bottom metal pads 44BP (not shown), and / or metal traces 44BT to provide passive components (inductors / capacitors / resistors). In this embodiment, the metal layers 44, especially the bottom metal layer 44BL might be formed by an embedded trace substrate (ETS) technology, which allows for very fine feature sizes (e.g. a width of a metal feature can be as small as 5 pm and a pitch between two adjacent metal features can be as small as 8 pm) to form patterned metal features (e.g., inductors / transformers). In some applications, the submodule substrate 36 may include more than one internal metal layer, provided that the total thickness of the submodule substrate 36 does not exceed 100 pm. In some applications, the internal metal layer 44IL may be omitted from the submodule substrate 36, if the submodule components 38 and / or the submodule bumps 40 are desired to have a relatively large height.Each of the metal layers 44 may incorporate a variety of metal features, which may vary in shape, size, and / or layouts.

[0052] Furthermore, for the purpose of this illustration, the submodule components 38 are four flip-chip dies with solder balls 46 (for clarity and simplicity, only two solder balls are labeled with a reference number). As such, each submodule component 38 is attached to a top side of the submodule substrate 36 by connecting each solder ball 46 to a corresponding top metal pad 44TP. The submodule mold compound 42 surrounds each submodule component 38 and underfills any submodule component 38 if it is a flip-chip die (e.g., fills gaps among the solder balls 46 of the submodule component 38). In different applications, the submodule 12 may include fewer or more submodule components 38 attached to the top side of the submodule substrate 36 via corresponding top metal pads 44TP. Each submodule component 38 may have a thickness between 30 pm and 100 pm, and may be any suitable electrical component, such as a bulk acoustic wave (BAW) resonator / filter, a surface acoustic wave (SAW) resonator / filter, a flip-chip die with solder balls, an SMD, a wire-bonding die, a flip-chip die with die copper pillars, a Si device, a PA, and / or a passive component. The mounting of each submodule component 38 to its corresponding top metal pad(s) 44TP may be done with or without an adhesive material, depending on the type of submodule component 38.

[0053] In one embodiment, when the submodule components 38 are flip-chip dies, a backside of one submodule component 38 (herein and hereafter, a backside of one flip-chip die refers to a surface away from an active region of the flip-chip die and opposite the die solder balls / die copper pillars) is not covered by the submodule mold compound 42 (i.e., the backside of the submodule component 38 is exposed through the submodule mold compound 42). A stiffening layer 48 is provided over the submodule components 38 and in contact with the backside of each submodule component 38. The stiffening layer 48 may be a non-conductive protective film (e.g., ADWILL LC Tape) with a thickness between 10 pm and 50 pm or between 10 pm and 25 pm. The stiffening layer 48 is configured to prevent the submodule components 38 from being electricallycoupled to a shielding structure that covers the submodule 12 (more details are described below). In one embodiment, each submodule component 38 may be fully encapsulated by the submodule mold compound 42, in which case the stiffening layer 48 is omitted (not shown). A portion of the submodule mold compound 42 that is positioned vertically above the submodule component 38 may range from 30 pm to 100 pm. The submodule mold compound 42 may be an organic epoxy resin system or the like.

[0054] Each submodule bump 40 is in contact with a corresponding bottom metal pad 44BP and extends from the planarized bottom surface of the submodule substrate 36 towards a corresponding top metal pad 26TP of the module substrate 14. The submodule bumps 40 are conductive and may be solder balls or copper pillars (not shown). Herein, each submodule component 38 is electrically connected to one or more submodule bumps 40 through the metal layers 44 and the vias of the submodule substrate 36, and is further electrically connected to one or more of the top components 16, the bottom component 18, and the bump structures 20 through the metal layers 26 and the vias of the module substrate 14.

[0055] Each submodule bump 40 may have a same height between 25 pm and 150 pm, so as to provide a stand-off space that is vertically between the submodule substrate 36 and the module substrate 14 and surrounded by the submodule bumps 40. Each submodule bump 40 may have a horizontal diameter between 90 pm and 200 pm. For the purpose of this illustration, two top components 16 (e.g., the two flip-chip dies 16-1 ) are attached to the module substrate 14, underneath the submodule substrate 36 without contacting the submodule substrate 36, and surrounded by the submodule bumps 40. In order to provide enough clearance for the submodule substrate 36 relative to the top components 16 underneath the submodule substrate 36 and maintain the thinness and reliability of the final multi-level SIP module 10, a gap between the bottom surface of the submodule substrate 36 (i.e., the bottom surface of the laminate body 36B) and a top surface of each top component 16 may have a vertical distance D1 between 10 pm and 50 pm, or in some cases between 20pm and 30 pm. When the vertical distance D1 is too small, there will be technical challenges in filling a mold compound therebetween, which may lead to reliability issues. In different applications, there might be fewer or more top components 16 with various types covered by the submodule 12. Herein, the height of each submodule bump 40 may be determined based on the height of the top components 16 underneath the submodule substrate 36. For a non-limiting example, the height of each top component 16 underneath the submodule substrate 36 may range between 50 pm and 120 pm, while the height of the submodule bumps 40 may correspondingly range between 80 pm and 150 pm.

[0056] In some embodiments, there might be no top component 16 positioned underneath the submodule substrate 36 (e.g., a ground plane, formed from the top metal layer 26TL, is underneath the submodule substrate 36). With the height of the submodule bumps 40, the ground plane on the module substrate 14 can be relatively far away from the bottom metal layer 44BL of the submodule substrate 36. If the bottom metal layer 44BL provides one or more inductors / transformers, omitting the top components 16 underneath the submodule substrate 36 can ensure a high Q for the inductors / transformers at the bottom of the submodule substrate 36.

[0057] Herein, to form the submodule bumps 40 on the corresponding bottom metal pads 44BP, respectively, a patterned mask layer 50 may be used to define the locations of the submodule bumps 40 as well as to protect the bottom surface of the submodule substrate 36. The patterned mask layer 50 may be formed of a resin-based material, a polymeric material, or any other appropriate material, and may have a thickness between 5 pm and 20 pm, or in some cases between 5 pm and 10 pm. The patterned mask layer 50 is formed directly underneath the bottom surface of the submodule substrate 36 and at least exposes a portion of each bottom metal pad 44BP used to accommodate the submodule bumps 40. Since the submodule substrate 36 has the planarized bottom surface and the patterned mask layer 50 is very thin, the formation of the patterned mask layer 50 on the bottom surface of the submodule substrate 36 will still maintain a substantially flat plane, with negligible impact on the clearance of the submodule1 relative to the top components 16 underneath. Additionally, the patterned mask layer 50 may provide mechanical support to the low-profile submodule substrate 36 during a molding process of forming the submodule mold compound 42 (more details are described below). In other words, the portions of the bottom surface of the submodule substrate 36 covered by the patterned mask layer 50 may be the portions of the submodule substrate 36 that require additional support during the molding process of the submodule mold compound 42. The patterned mask layer 50 may also include continuous or discrete sections to cover certain portions of the bottom surface of the laminate body 36B and certain portions of the bottom metal layer 44BL (e.g., certain bottom metal traces 44BT) in addition to partially covering each bottom metal pad 44BP.

[0058] Note that, if the stiffening layer 48 is present in the submodule 12, the top surface of the submodule 12 is the top surface of the stiffening layer 48, and the side surface of the submodule 12 is a combination of a side surface of the submodule substrate 36, a side surface of the submodule mold compound 42, and a side surface of the stiffening layer 48. If the stiffening layer 48 is omitted in the submodule 12 and the submodule mold compound 42 fully encapsulates the submodule components 38 in the submodule 12, the top surface of the submodule 12 is the top surface of the submodule mold compound 42, and the side surface of the submodule 12 is a combination of the side surface of the submodule substrate 36 and a side surface of the submodule mold compound 42 (not shown). A bottom side of the submodule 12 is composed of the submodule bumps 40, portions of the bottom surface of the submodule substrate 36, and the patterned mask layer 50. In some embodiments, a thin coating layer (e.g., formed from organic solderability preservatives) may be applied to cover the entire bottom side of the submodule 12 (not shown), which is configured to enable each submodule bump 40 (e.g., each submodule bump 40 is a copper pillar) to have a solderable surface.

[0059] In this illustration, the top mold compound 22 is formed on the top side of the module substrate 14 to encapsulate any portion of the top metal layer 26TL not covered by the submodule 12 or the top components 16, to fullyencapsulate each top component 16 and underfill any top component 16 if it is a flip-chip die. The top mold compound 22 also encapsulates the side surface of the submodule 12 without covering the top surface (e.g., the top surface of the stiffening layer 48) of the submodule 12, encapsulates each submodule bump 40 of the submodule 12, and fills gaps between the submodule 12 and any top component 16 that is underneath the submodule substrate 36 and surrounded by the submodule bumps 40. In some embodiments, the top mold compound 22 may fully encapsulate the submodule 12 including the top surface of the submodule 12 (not shown). The top mold compound 22 may be an organic epoxy resin system or the like. The top mold compound 22 and the submodule mold compound 42 may be formed of a same or different material.

[0060] When the multi-level SIP module 10 is a double-side module, the bottom component 18 and the bump structures 20 are attached to the bottom side of the module substrate 14. For a non-limiting example, the bottom component 18 is a flip-chip die, which includes die solder balls 52 (for clarity and simplicity, only one solder ball of the bottom component 18 is labeled with a reference number) attached to corresponding bottom metal pads 26BP on the bottom side of the module substrate 14 (referring back to Figure 1 A). The bump structures 20, which protrude from the bottom side of the module substrate 14 and surround the bottom component 18, are copper posts. Each bump structure 20 is formed on a corresponding bottom metal pad 26BP on the bottom surface of the laminate body 14B of the module substrate 14. In different applications, there might be more bottom components 18 attached to the bottom side of the module substrate 14 via corresponding bottom metal pads 26BP. The bottom component 18 may be another electrical component, such as an SMD, a wirebonding die, a flip-chip die with die copper pillars, a Si device, a PA, or a passive electronic component, while each bump structure 20 may be a solder ball (not shown). The bottom component 18 and the bump structures 20 might be mounted to the bottom metal pads 26BP with or without an adhesive material (not shown). The bottom component 18 and the bump structures 20 might be arranged in a different horizontal layout. The bottom component 18, the bumpstructures 20, the top components 16, and the submodule 12 are electrically connected through the metal layers 26 and the vias of the module substrate 14.

[0061] n this illustration, the bottom mold compound 24 is formed on the bottom side of the module substrate 14 to encapsulate any portion of the bottom metal layer 26BL not covered by the bottom component 18 or the bump structures 20. The bottom mold compound 24 also encapsulates sides of the bottom component 18 and sides of each bump structure 20, and underfills the bottom component 18 if it is a flip-chip die. As such, a backside of the bottom flipchip die 18 and an end surface of each bump structure 20 are exposed through the bottom mold compound 24. In some embodiments, the bottom mold compound 24 may fully encapsulate the bottom component 18 (not shown). The bottom mold compound 24 may be an organic epoxy resin system or the like. The top mold compound 22 and the bottom mold compound 24 may be formed of a same or different material.

[0062] Herein, a top surface of the multi-level SIP module 10 is a combination of a top surface of the top mold compound 22 and a top surface of the submodule 12. If the stiffening layer 48 is present in the submodule 12, a top surface of the stiffening layer 48 is the top surface of the submodule 12. If the stiffening layer 48 is omitted in the submodule 12 and the submodule mold compound 42 fully encapsulates the submodule components 38 in the submodule 12, the top surface of the multi-level SIP module 10 is a combination of the top surface of the top mold compound 22 and a top surface of the submodule mold compound 42 of the submodule 12 (not shown). If the submodule 12 is fully encapsulated by the top mold compound 22, the top surface of the multi-level SIP module 10 is the top surface of the top mold compound 22 (not shown). A side surface of the multi-level SIP module 10 is a combination of a side surface of the top mold compound 22, a side surface of the module substrate 14, and a side surface of the bottom mold compound 24 (if it exists). A bottom side of the multi-level SIP module 10 is the bottom side of the module substrate 14 (if the multi-level SIP module precursor 64 is a single side module, not shown) or is a combination of the bottom surface of the bottom moldcompound 24, the backside of the bottom component 18 (if exposed), and the end surface of each bump structure 20 (if the multi-level SIP module precursor 64 is a double side module).

[0063] In some embodiments, the multi-level SIP module 10 may be shielded by a module shielding structure 54 to be a shielded multi-level SIP module 10S. The module shielding structure 54 directly and completely covers the top surface and the side surface of the multi-level SIP module 10 without covering the bottom side of the multi-level SIP module 10. Herein and hereafter, completely covering a surface refers to covering at least 99% of such surface. If the stiffening layer 48 is present in the submodule 12, the module shielding structure 54 is in contact with the top surface of the stiffening layer 48, and the stiffening layer 48 is configured to prevent the module shielding structure 54 from being electrically coupled to the submodule components 38. If the stiffening layer 48 is omitted in the submodule 12 and the submodule mold compound 42 fully encapsulates the submodule components 38 in the submodule 12, the module shielding structure 54 is in contact with the top surface of the submodule mold compound 42, and the certain portion of the submodule mold compound 42, which is positioned vertically above the submodule components 38, is configured to prevent the module shielding structure 54 from being electrically coupled to the submodule components 38.

[0064] The module shielding structure 54 may include multiple shielding layers, each of which may be formed of copper, aluminum, silver, gold, stainless steel, nickel or other conductive materials. Exemplary implementations of the module shielding structure 54 can be found in U.S. Patent Application Publication No. 2023 / 024,7814, COMPARTMENTALIZED SHIELDING OF A MODULE UTILIZING SELF-SHIELDED SUB-MODULES, which is incorporated herein by reference.

[0065] As described above, to achieve the low-profile submodule 12, the submodule substrate 36 includes a limited number of the metal layers 44 (e.g., only 2-5 metal layers 44), where the bottom metal layer 44BL is embedded in the laminate body 36B and shares the same planarized bottom plane with thelaminate body 36B, while the top metal layer 44TL protrudes from the top surface of the laminate body 36B. In different applications, the metal layers 44 may be laid out differently relative to the laminate body 36B, where the bottom metal layer 44BL instead of the top metal layer 44TL protrudes from the laminate body 36B, as illustrated in Figure 2.

[0066] Herein, the submodule substrate 36 still includes 2~5 metal layers 44 and has a thickness between 70 pm and 100 pm. The laminate body 36B of the submodule substrate 36 is still composed of PPG layers and alternating vertically with the metal layers 44. For the purpose of this illustration, the top metal layer 44TL is embedded within the laminate body 36B but not fully covered by the laminate body 36B. In other words, the top metal layer 44TL is exposed through the laminate body 36B without protruding from the top surface of the laminate body 36B. The laminate body 36B and the top metal layer 44TL share a planarized top plane. The top metal layer 44TL includes the top metal pads 44TP to accommodate the submodule components 38 (only one top metal pad is labeled with a reference number for clarity and simplicity). The top metal layer 44TL may also include other top metal features (not shown for clarity and simplicity), such as the top routing lines to connect between the top metal pads 44TP and / or to provide passive components (inductors / capacitors / resistors). The internal metal layer 44IL is still embedded in the laminate body 36B and electrically connected to both the top metal layer 44TL and the bottom metal layer 44BL through vias (not shown for clarity and simplicity). The internal metal layer 44IL may include various metal features (e.g., pads, traces, etc..), which are designed to provide internal electrical connections and / or passive components (inductors / capacitors / resistors).

[0067] Additionally, the bottom metal layer 44BL is formed on the bottom surface of the laminate body 36B (i.e., protruding from the bottom surface of the laminate body 36B). The bottom metal layer 44BL includes the bottom metal pads 44BP (only one bottom metal pad is labeled with a reference number for clarity and simplicity) to accommodate the submodule bumps 40 and other bottom metal features (not shown). Herein, if the vertical distance D1 betweenthe bottom surface of the laminate body 36B of the submodule substrate 36 and the top surface of each of the first top components 16-1 is still expected to be 20 pm and 30 pm, then no portion of the bottom metal layer 44BL can overlap horizontally with any first top component 16-1 underneath the submodule substrate 36. Because the bottom metal layer 44BL protrudes from the bottom surface of the laminate body 36B, any horizontal overlap between the bottom metal layer 44BL and the first top components 16-1 will reduce the clearance of the submodule substrate 36 relative to the first top components 16-1 underneath the submodule substrate 36. The reduced clearance will raise technical challenges in filling it with a mold compound, which may lead to reliability issues. Note that, since the bottom metal layer 44BL protrudes from the bottom surface of the laminate body 36B, the submodule substrate 36 does not have a planarized bottom surface. The patterned mask layer 50 may only partially cover each bottom metal pad 44BP (to accommodate a corresponding submodule bump 40). It is because even if the patterned mask layer 50 extends to cover portions of the bottom surface of the laminate body 36B, it still cannot provide a substantially flat surface and thus cannot provide mechanical support for the submodule substrate 36 in a molding process.

[0068] Regardless of the layout of the metal layers 44 relative to the laminate body 36B, at least one metal layer 44 might be formed by ETS technology. One of the top metal layer 44TL and the bottom metal layer 44BL always protrudes vertically from a corresponding boundary surface of the laminate body 36B (i.e., a top surface or the bottom surface of the laminate body 36B, respectively), while another one of the top metal layer 44TL and the bottom metal layer 44BL is embedded in the laminate body 36B and exposed through the laminate body 36B, and shares a common planarized plane with the laminate body 36B. For a non-limiting example, when the top metal layer 44TL protrudes from the top surface of the laminate body 36B and the bottom metal layer 44BL is embedded in the laminate body 36B to share the planarized bottom plane with the laminate body 36B, only the bottom metal layer 44BL is formed by ETS technology. When the bottom metal layer 44BL protrudes from the bottom surface of the laminatebody 36B and the top metal layer 44TL is embedded in the laminate body 36B to share the planarized top plane with the laminate body 36B, only the top metal layer 44TL is formed by ETS technology,

[0069] In some applications, one or more of the top components 16 and / or one or more submodule components 38 may be radiative components that can generate eddy radio-frequency currents negatively impacting the overall module performance, or be electronic components that are superiorly sensitive to external interference (e.g., BAW resonators / filters or SAW resonators / filters). Therefore, it might be desired to provide extra isolation inside the multi-level SIP module 10. As illustrated in Figure 3, a submodule side shielding structure 56 is combined with the module shielding structure 54 to isolate the submodule components 38 within the submodule 12 from the top components 16 outside the submodule 12.

[0070] In detail, the submodule side shielding structure 56 directly and completely covers the side surface of the submodule 12 (i.e., the combination of the side surface of the submodule substrate 36, the side surface of the submodule mold compound 42, and the side surface of the stiffening layer 48 if the stiffening layer 48 is present) and is in contact with the module shielding structure 54. Due to the requirements for electrical connections and the complexity of fabrication, the bottom side of the submodule substrate 36 and the submodule bumps 40 remain uncovered by any shielding structure. Herein, when the module shielding structure 54 is grounded, the submodule side shielding structure 56 is also grounded. The submodule 12 is individually shielded (except the bottom side of the submodule substrate 36 and the submodule bumps 40) by the combination of the module shielding structure 54 and the submodule side shielding structure 56. As a result, the electromagnetic field generated inside the submodule 12 (e.g., generated by the submodule components 38) will have no or negligible impact on electronic components outside the submodule 12 (e.g., the second top component 16-2 and the third top component 16-3) and / or the electromagnetic field outside the submodule 12 will not affect the submodule components 38 shielded inside the submodule 12. Additionally, the submoduleside shielding structure 56 of the submodule 12 may also prevent / partially prevent electromagnetic radiation of components on one side of the submodule 12 (e.g., the second top component 16-2 or the third top component 16-3) from interfering with other components on the opposite side of the submodule 12 (not shown).

[0071] The module shielding structure 54 and the submodule side shielding structure 56 may have a same layer arrangement with same layer materials, or have the same layer arrangement with different layer materials, or have different layer arrangements with different layer materials. The submodule side shielding structure 56 may include multiple shielding layers, each of which may be formed of copper, aluminum, silver, gold, stainless steel, nickel or other conductive materials. Exemplary implementations of the submodule side shielding structure 56 can also be found in U.S. Patent Application Publication No. 20230247814, COMPARTMENTALIZED SHIELDING OF A MODULE UTILIZING SELFSHIELDED SUB-MODULES, which is incorporated herein by reference.

[0072] Figure 4 provides a flow diagram that illustrates an exemplary process for manufacturing the submodule 12 according to some embodiments of the present disclosure. Figures 5A-1 1 illustrate exemplary steps associated with the manufacturing process of the submodule 12 provided in Figure 4. Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in Figures 5A-11 .

[0073] Initially, the submodule substrate 36 with the patterned mask layer 50 is provided as illustrated in Figures 5A and 5B (step 102). Herein, the submodule substrate 36 includes the laminate body 36B composed of PPG layers (not shown) and the metal layers 44 alternating vertically with the PPG layers. The submodule substrate 36 may include 2~5 metal layers 44 and has a thickness between 70 pm -100 pm (from the top metal layer 44TL to the bottom metal layer 44BL). In some embodiments, the top metal layer 44TL is formed over the top surface of the laminate body 36B (i.e., protruding from the top surface of thelaminate body 36B), the bottom metal layer 44BL is embedded within the laminate body 36B and shares the same planarized bottom plane with the laminate body 36B (i.e., the bottom metal layer 44BL is exposed through the laminate body 36B without protruding from the bottom surface of the laminate body 36B), as illustrated in Figure 5A. Herein, the embedded bottom metal layer 44BL may be formed by ETS technology, which allows for very fine feature sizes to form patterned metal features (e.g., inductors / transformers). In some embodiments, the top metal layer 44TL is embedded within the laminate body 36B and shares the same planarized top plane with the laminate body 36B (i.e., the top metal layer 44TL is exposed through the laminate body 36B without protruding from the top surface of the laminate body 36B), while the bottom metal layer 44BL is formed over the bottom surface of the laminate body 36B (i.e., protruding from the bottom surface of the laminate body 36B), as illustrated in Figure 5B. Herein, the embedded top metal layer 44TL may be formed by ETS technology.

[0074] Regardless of the layout of the metal layers 44 relative to the laminate body 36B, the metal layers 44 may also include one or more internal metal layers 44IL, which are embedded in the laminate body 36B and electrically connected to both the top metal layer 44TL and the bottom metal layer 44BL through vias (not shown for clarity and simplicity). Each of the metal layers 44 may include various metal features, such as metal pads (e.g., the top metal pads 44TP, the bottom metal pads 44BP), routing lines, and / or metal traces (e.g., the bottom metal traces BT) as described above. The patterned mask layer 50 is always formed underneath the bottom surface of the laminate body 36B to at least define the locations of the submodule bumps 40 that will be formed in a subsequent step. When the submodule substrate 36 has a flat bottom surface (i.e., the bottom metal layer 44BL is embedded in the laminate body 36B and shares the same planarized bottom plane with the laminate body 36B), in addition to partially covering each bottom metal pad 44BP (i.e., exposing a portion of each bottom metal pad 44BP to accommodate one corresponding submodule bump 40), the patterned mask layer 50 may also cover certain portions of the bottom surface ofthe laminate body 36B and certain portions of the bottom metal layer 44BL (e.g., certain bottom metal traces 44BT) to provide support for the submodule substrate 36 during a subsequent molding process (more details are described below). On the other hand, when the submodule substrate 36 has an uneven bottom side (i.e., the bottom metal layer 44BL protrudes from the bottom surface of the laminate body 36B), the patterned mask layer 50 may only partially cover each bottom metal pad 44BP (i.e., exposing a portion of each bottom metal pad 44BP to accommodate one corresponding submodule bump 40) without extending horizontally to cover the bottom surface of the laminate body 36B. The patterned mask layer 50 may be formed of a resin-based material, a polymeric material, or any other appropriate material, and has a thickness between 5pm and 15pm.

[0075] Next, one or more submodule components 38 are attached to the top side of the submodule substrate 36 (step 104), as illustrated in Figure 6 (the following steps take the submodule substrate 36 illustrated in Figure 5A as an example). The attachment may be implemented by surface mount technology (SMT), which includes placement, reflow, wash, and dry. For the purpose of this illustration, the submodule components 38 are four flip-chip dies with the solder balls 46 that are directly connected to the corresponding top metal pads 44TP, respectively. In different applications, there might be fewer or more submodule components 38 attached to the top side of the submodule substrate 36 via the corresponding top metal pads 44TP. Each submodule component 38 may have an initial thickness between 30 pm and 200 pm, and may be any suitable electrical component, such as a BAW resonator / filter, a SAW resonator / filter, a flip-chip die with solder balls, an SMD, a wire-bonding die, a flip-chip die with die copper pillars, a Si device, a PA, and / or a passive component.

[0076] After assembling the submodule components 38, the submodule mold compound 42 is then applied over the top side of the submodule substrate 36 to provide a molded submodule precursor 58 (step 106), as illustrated in Figure 7. The submodule mold compound 42 fully encapsulates each submodule component 38. If any submodule component 38 is a flip-chip die, the submodulemold compound 42 also underfills the submodule component 38 (e.g., fills gaps among the solder balls 46 of the submodule component 38). The submodule mold compound 42 may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation. A curing process (not shown) is then used to harden the submodule mold compound 42 depending on which material is used to form the submodule mold compound 42.

[0077] As mentioned above, when the submodule substrate 36 has a flat bottom surface (i.e., the bottom metal layer 44BL is embedded in the laminate body 36B and shares the same planarized bottom plane with the laminate body 36B), the patterned mask layer 50 may not only partially cover each bottom metal pad 44BP, but also cover certain portions of the bottom surface of the submodule substrate 36. These areas covered by the patterned mask layer 50 are likely to be fragile parts of the thin submodule substrate 36, and the patterned mask layer 50 provides support to the submodule substrate 36 during the molding step. Since the patterned mask layer 50 is very thin, the formation of the patterned mask layer 50 on the bottom surface of the submodule substrate 36 will still maintain a substantially flat plane.

[0078] A grinding step is then applied to planarize a top surface of the molded submodule precursor 58 (step 108), as illustrated in Figure 8. In some applications, this grinding step may also be used to thin down the submodule mold compound 42 to achieve a desired thickness of the molded submodule precursor 58, such as between 130 pm and 200 pm, and in some cases between 130 pm and 150 pm. If the submodule components 38 are silicon-based flip-chip dies, the submodule components 38 can also be ground at the same time to achieve the desired thickness of the molded submodule precursor 58. Before the grinding step, each submodule component 38 may have the initial thickness between 30 pm and 200 pm, while after the grinding step, each submodule component 38 may have a thickness between 30 pm and 100 pm. In addition, after the grinding step, the backside of each submodule component 38 may be exposed through the submodule mold compound 42 (i.e., a top surface of themolded submodule precursor 58 is a combination of a top surface of the submodule mold compound 42 and the backside of each submodule component 38) or each submodule component 38 may still be fully encapsulated by the submodule mold compound 42 (i.e., the top surface of the molded submodule precursor 58 is the top surface of the submodule mold compound 42, not shown).

[0079] Herein, if the final submodule 12 is to be shielded before being assembled into the multi-level SIP module 10, each submodule component 38 should not be exposed before applying a shielding structure, so as to ensure that the submodule components 38 are not electrically coupled to the shielding structure covering the molded submodule precursor 58. In the case that the backside of each submodule component 38 is exposed through the submodule mold compound 42 (i.e., the top surface of the molded submodule precursor 58 is the combination of a top surface of the submodule mold compound 42 and the backside of each submodule component 38), the stiffening layer 48 may be directly placed over the top surface of the molded submodule precursor 58 to fully cover the backside of each submodule component 38 (step 1 10), as illustrated in Figure 9. In the case that each submodule component 38 is completely encapsulated by the submodule mold compound 42, the stiffening layer 48 may be omitted (not shown). The stiffening layer 48 may be a non- conductive protective film (e.g., ADWILL LC Tape) with an initial thickness between 10 pm and 50 pm. The stiffening layer 48 can be thinned after the final submodule 12 is assembled into the multi-level SIP module 10, therefore, the initial thickness of the stiffening layer 48 may be relatively thick to provide support to the final submodule 12 during a subsequent module molding step (more details are described below).

[0080] Next, the submodule bumps 40 are attached to the submodule substrate 36 to provide the submodule 12 (step 1 12), as illustrated in Figure 10. Each submodule bump 40 is connected to a corresponding bottom metal pad 44BP exposed through the patterned mask layer 50. The submodule bumps 40 provide a stand-off space underneath the submodule substrate 36. As such, by carefully designing the size of the submodule bumps 40, the stand-off spaceunderneath the submodule substrate 36 can be large enough to accommodate electronic components (e.g., the first top components 16-1 ) during the module assembly. The submodule bumps 40 are conductive and may be solder balls or copper pillars (not shown). Each submodule bump 40 may have a height between 25 pm and 150 pm and a diameter between 90 pm and 200 pm. The submodule bumps 40 are configured to be electrically connected to the submodule components 38 through the metal layers 44 and the vias of the submodule substrate 36.

[0081] Herein, if the stiffening layer 48 is present in the submodule 12, the top surface of the submodule 12 is the top surface of the stiffening layer 48, and the side surface of the submodule 12 is the combination of the side surface of the submodule substrate 36, the side surface of the submodule mold compound 42, and the side surface of the stiffening layer 48. If the stiffening layer 48 is omitted in the submodule 12 and the submodule mold compound 42 fully encapsulates the submodule components 38 in the submodule 12, the top surface of the submodule 12 is the top surface of the submodule mold compound 42, and the side surface of the submodule 12 is a combination of the side surface of the submodule substrate 36 and a side surface of the submodule mold compound 42 (not shown). The bottom side of the submodule 12 is composed of the submodule bumps 40, portions of the bottom surface of the submodule substrate 36, and the patterned mask layer 50. In some embodiments, a thin coating layer (e.g., formed from organic solderability preservatives) may then be applied to cover the entire bottom side of the submodule 12 (not shown), which is configured to enable each submodule bump 40 (e.g., each submodule bump 40 is a copper pillar) to have a solderable surface.

[0082] Optionally, the submodule 12 may be shielded by an intact submodule shielding structure 56JN (step 1 14) before being assembled into the multi-level SIP module 10, as illustrated in Figure 11 . The intact submodule shielding structure 56_IN is continuously and completely covering the top surface and the side surface of the submodule 12 without covering the submodule bumps 40, the patterned mask layer 50, or the bottom side of the submodule substrate 36. Theintact submodule shielding structure 56JN includes the submodule side shielding structure 56, which covers the side surface of the submodule 12, and a submodule top shielding structure 56T, which covers the top surface of the submodule 12 and directly connects the submodule side shielding structure 56. The submodule top shielding structure 56T and the submodule side shielding structure 56 are formed in a same shielding process and have a same layer arrangement with the same materials (as described above). Lastly, the submodule 12 may be packaged in tape-and-reel for subsequent assembly into the multi-level SIP module 10 (step 116, not shown).

[0083] Figure 12 provides a flow diagram that illustrates an exemplary process for manufacturing the multi-level SIP module 10 using the submodule 12 according to some embodiments of the present disclosure. Figures 13-20 illustrate exemplary steps associated with the manufacturing process of the multilevel SIP module provided in Figure 12. Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in Figures 13-20.

[0084] Firstly, one or more top components 16 are attached to the top side of the module substrate 14 (step 202), as illustrated in Figure 13. The module substrate 14 includes the laminate body 14B composed of PPG layers and the multiple metal layers 26 alternating vertically with the PPG layers (not shown for clarity and simplicity). The multiple metal layers 26 include the top metal layer 26TL on the top surface of the laminate body 14B, the bottom metal layer 26BL on the bottom surface of the laminate body 14B, and multiple internal metal layers embedded in the laminate body 14B (not shown for clarity and simplicity). For the purpose of this illustration, the top components 16 include two first top components 16-1 , one second top component 16-2, and one third top component 16-3. Each first top component 16-1 is a flip-chip die with the solder balls 30, the second top component 16-2 is an SMD, and the third top component 16-3 is a flip-chip die with the solder balls 32. The top components 16 are mounted to themodule substrate 14 by attaching to the corresponding top metal pads 26TP of the top metal layer 26TL with or without an adhesive material (e.g., the second top component, SMD, 16-2 is mounted to the corresponding top metal pad 26TP with the top adhesive material 34, while the first and third top components, flipchip dies with solder balls, 16-1 and 16-3 are directly attached to the corresponding top metal pads 26TP).

[0085] Next, the submodule 12 with the intact submodule shielding structure 56JN (if present) is attached to the top side of the module substrate 14 (step 204), as illustrated in Figure 14. Each submodule bump 40 is connected to a corresponding top metal pad 26TP of the top metal layer 26TL. For the purpose of this illustration, the submodule 12 caps the first top components 16-1 , which are positioned vertically between the module substrate 14 and the submodule substrate 36, and surrounded by the submodule bumps 40. In different applications, there might be more submodules 12 attached to the module substrate 14, and each submodule 12 may not cap any top components 16 or may cap more top components 16 on the top side of the module substrate 14. If there is at least one top component 16 positioned vertically between the module substrate 14 and the submodule substrate 36, the vertical distance D1 between the bottom surface of the laminate body 36B of the submodule substrate 36 and a top surface of the at least one top component 16 may be between 10 pm and 50 pm, or between 20 pm and 30 pm. In other words, the final height of each submodule bump 40 is approximately 10 pm to 50 pm or 20 pm to 30 pm greater than the height of the at least one top component 16. When the laminate body 36B and the bottom metal layer 44BL of the submodule substrate 36 share a planarized bottom plane (i.e., the submodule substrate 36 has the planarized bottom surface), the clearance of the submodule 12 relative to the top components 16 underneath can still be maintained even if the patterned mask layer 50 is added to the bottom surface of the submodule substrate 36 (the patterned mask layer 50 has a thickness between 5 pm and 20 pm, or in some cases between 5 pm and 10 pm). In some embodiments, the attachment of thesubmodule 1 may be implemented by SMT picking and placing the submodule 12 from tape and reel and reflowing the submodule bumps 40.

[0086] After cleaning residues on the top side of the module substrate 14, the top mold compound 22 is applied over the top side of the module substrate 14 to provide a top molded module precursor 60 (step 206), as illustrated in Figure 15. The top mold compound 22 encapsulates any portion of the top metal layer 26TL not covered by the submodule 12 or the top components 16, fully encapsulates each top component 16 (underfills any top component 16 if it is a flip-chip die), fully encapsulates the submodule 12, and fills gaps between the submodule 12 and any top component 16 that is underneath the submodule substrate 36 of the submodule 12. The top mold compound 22 may be an organic epoxy resin system or the like, and may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation. Recall that the stiffening layer 48 (if present) within the submodule 12 has a relatively thick initial thickness, such that the stiffening layer 48 helps to prevent the submodule 12 from becoming deformed during this molding step. A curing process (not shown) is then used to harden the top mold compound 22 depending on which material is used to form the top mold compound 22.

[0087] If the final multi-level SIP module 10 is a double-sided structure, one or more bottom components 18 and the bump structures 20 are attached to the bottom side of the module substrate 14 (step 208), as illustrated in Figure 16. For the purpose of this illustration, there is only one bottom component 18 mounted to the module substrate 14 and surrounded by the bump structures 20. The bottom component 18 is a flip-chip die, which includes the die solder balls 52 attached to the corresponding bottom metal pads 26BP of the bottom metal layer 26BL, while each bump structure 20 is a copper post, which is formed on a corresponding bottom metal pad 26BP of the bottom metal layer 26BL and protrudes from the bottom side of the module substrate 14. In different applications, there might be more bottom components 18 attached to the bottom side of the module substrate 14 via the corresponding bottom metal pads 26BP.The bottom component 18 may be another electrical component, such as an SMD, a wire-bonding die, a flip-chip die with die copper pillars, a Si device, a PA, or a passive electronic component, and each bump structure 20 may be a solder ball (not shown). The bottom component 18 and the bump structures 20 might be attached to the bottom metal pads 26BP with or without an adhesive material (not shown). The bottom component 18 and the bump structures 20 might be arranged in a different horizontal layout. The bottom component 18, the bump structures 20, the top components 16, and the submodule 12 are electrically connected through the metal layers 26 and the vias (not shown) of the module substrate 14.

[0088] After cleaning residues on the bottom side of the module substrate 14, the bottom mold compound 24 is applied over the bottom side of the module substrate 14 to provide a double molded module precursor 62 (step 210), as illustrated in Figure 17 (if the final multi-level SIP module 10 is a single sided module, this step will be omitted). The bottom mold compound 24 encapsulates any portion of the bottom metal layer 26TL not covered by the bottom component 18 or the bump structures 20, fully encapsulates the bottom component 18 (underfills the bottom component 16 if it is a flip-chip die), and fully encapsulates each bump structure 20. The bottom mold compound 24 may be an organic epoxy resin system or the like, and may be formed of a same material as or a different material from the top mold compound 22. The bottom mold compound 24 may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation. A curing process (not shown) is then used to harden the bottom mold compound 24 depending on which material is used to form the bottom mold compound 24.

[0089] The bottom mold compound 24 is then thinned down to expose each bump structure 20 through the bottom mold compound 24 (step 212), as illustrated in Figure 18. The thinning step may be done with a grinding process. If the bottom component 18 is a silicon-based flip-chip die, the bottom component 16 can also be ground at the same time as the bottom mold compound 24 untileach bump structure 20 is exposed through the bottom mold compound 24.After the thinning step, the side surface of the bottom component 18 and the side surface of each bump structure 20 are still encapsulated by the bottom mold compound 24. In some embodiments, the backside of the bottom component 18 may be exposed through the bottom mold compound 24 and shares a same flat bottom plane with the bottom mold compound 24 and each bump structure 20. In some applications, the bottom component 18 may be shorter than the bump structures 20, such that, after the thinning step, the bottom component 18 is still fully encapsulated by the bottom mold compound 24. Alternatively, this thinning step is omitted, if the end surface of each bump structure 20 is always exposed during the molding process of the bottom mold compound 24.

[0090] Next, the top mold compound 22 of the double molded module precursor 62 is thinned down to provide the multi-level SIP module 10 with a target thickness (step 214), as illustrated in Figure 19. If the submodule 12 is shielded by the intact submodule shielding structure 56JN, the top mold compound 22 is thinned down at least until the stiffening layer 48 of the submodule 12 and a cross-section surface of the submodule side shielding structure 56 at the periphery of the submodule 12 are exposed. Recall that the stiffening layer 48 may have a relatively thick initial thickness, such that the stiffening layer 48 may also be thinned down (without complete removal) at the same time as the top mold compound 22 to meet the final module thickness target. Herein, the submodule top shielding structure 56T of the intact submodule shielding structure 56JN is completely removed, and only the side surface of the submodule 12 is covered by the submodule side shielding structure 56. The thinning step may be done with a grinding process. Typically, each top component 16 has a lower height than the submodule 12, and therefore, each top component 16 is still encapsulated by the top mold compound 22 after the thinning step. The top surface of the multi-level SIP module 10 is the combination of the top surface of the top mold compound 22, the top surface of the stiffening layer 48 of the submodule 12, and the cross-section surface of the submodule side shielding structure 56. The side surface of the multi-level SIP module 10 isthe combination of the side surface of the top mold compound 22, the side surface of the module substrate 14, and the side surface of the bottom mold compound 24 (if present). The bottom side of the multi-level SIP module 10 is the bottom side of the module substrate 14 (if the multi-level SIP module 10 is a single side module) or is the combination of the bottom surface of the bottom mold compound 24, the backside of the bottom component 18 (if exposed), and the end surface of each bump structure 20 (if the multi-level SIP module 10 is a double side module).

[0091] Lastly and optionally, the module shielding structure 54 may be applied to the multi-level SIP module 10 to form the shielded multi-level SIP module 10S (step 216), as illustrated in Figure 20. The module shielding structure 54 directly and completely covers the top surface and the side surface of the multi-level SIP module 10, while the bottom side of the multi-level SIP module 10 is exposed. The module shielding structure 54 is in contact with the submodule side shielding structure 56, and the submodule 12 is individually shielded inside the multi-level SIP module 10 (except the bottom side of the submodule 12) by the combination of the module shielding structure 54 and the submodule side shielding structure 56.

[0092] According to aspects disclosed herein, multi-level SIP modules and methods for manufacturing the multi-level SIP modules to achieve high electronic density, low-profile, and small footprint may be provided in or integrated into any processor-based electronics. Examples, without limitation, include a base station, a military application device, a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digitalvideo disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0093] With reference to Figure 21 , the concepts described above may be implemented in various types of communication devices 300, such as those listed in the previous paragraph. The communication device 300 will generally include a control system 302, a baseband processor 304, transmit circuitry 306, receive circuitry 308, antenna switching circuitry 310, multiple antennas 312, and user interface circuitry 314. Herein, at least one or any combination of the control system 302, the baseband processor 304, the transmit circuitry 306, and the receive circuitry 308 may be implemented in the multi-level SIP module 10 / 1 OS (e.g. implemented in the one or more top components 16, one or more bottom components 18, and / or one or more submodule components 38) as shown in Figures 1 A-1 B, 2, 3, and 20, and described above.

[0094] In a non-limiting example, the control system 302 can be a field- programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In this regard, the control system 302 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 308 receives radio frequency signals via the antennas 312 and through the antenna switching circuitry 310 from one or more base stations. A low noise amplifier and a filter of the receive circuitry 308 cooperate to amplify and remove broadband interference from the received signal for processing. Down conversion and digitization circuitry (not shown) will then down convert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0095] The baseband processor 304 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 304 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0096] For transmission, the baseband processor 304 receives digitized data, which may represent voice, data, or control information, from the control system 302, which it encodes for transmission. The encoded data is output to the transmit circuitry 306, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 312 through the antenna switching circuitry 310. The multiple antennas 312 and the replicated transmit and receive circuitries 306, 308 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0097] It is contemplated that any of the foregoing aspects, and / or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein.

[0098] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A multi-level system-in-package (SIP) module comprising:• a module substrate;• a submodule attached to a top side of the module substrate, wherein:• the submodule includes a submodule substrate, at least one submodule component, and a plurality of submodule bumps;• the submodule substrate includes at least a laminate body, a top metal layer, and a bottom metal layer, wherein one of the top metal layer and the bottom metal layer protrudes vertically from a corresponding boundary surface of the laminate body, while another one of the top metal layer and the bottom metal layer is embedded in the laminate body and exposed through the laminate body, and shares a flat plane with the laminate body; and• the at least one submodule component is mounted to a top side of the submodule substrate via the top metal layer, while the plurality of submodule bumps is connected to the bottom metal layer on a bottom side of the submodule substrate and extends towards the top side of the module substrate, which provides a stand-off space that is vertically between the submodule substrate and the module substrate; and• at least one top component attached to the top side of the module substrate.

2. The multi-level SIP module of claim 1 wherein:• the top metal layer protrudes vertically from a top surface of the laminate body; and• the bottom metal layer is embedded in the laminate body and exposed through the laminate body, and the bottom side of the submodule substrate is a flat surface composed of a bottom surface of the laminate body and a bottom surface of the bottom metal layer.

3. The multi-level SIP module of claim 2 wherein the bottom metal layer is formed by an embedded trace substrate (ETS) technology and at least includes bottom metal pads to accommodate the plurality of submodule bumps, and patterned metal features.

4. The multi-level SIP module of claim 3 wherein:• the submodule further includes a patterned mask layer, which is formed on the bottom side of the submodule substrate and has a thickness between 5 pm and 20 pm; and• the patterned mask layer partially covers each of the bottom metal pads to define locations to mount the plurality of submodule bumps, respectively.

5. The multi-level SIP module of claim 4 wherein the patterned mask layer further covers certain portions of the bottom side of the submodule substrate other than the bottom metal pads.

6. The multi-level SIP module of claim 1 wherein:• the top metal layer is embedded in the laminate body and exposed through the laminate body, and the top side of the submodule substrate is a flat surface composed of a top surface of the laminate body and a top surface of the top metal layer; and• the bottom metal layer protrudes vertically from a bottom surface of the laminate body.

7. The multi-level SIP module of claim 6 wherein:• the top metal layer is formed by an embedded trace substrate (ETS) technology and at least includes top metal pads to accommodate the at least one submodule component; and• the bottom metal layer at least includes bottom metal pads, each of which is configured to accommodate a corresponding one of the plurality of submodule bumps and protrudes vertically from the bottom surface of the laminate body.

8. The multi-level SIP module of claim 7 wherein:• the submodule further includes a patterned mask layer, which is formed on the bottom side of the submodule substrate and has a thickness between 5 pm and 20 pm; and• the patterned mask layer only partially covers each of the bottom metal pads to define locations to mount the plurality of submodule bumps, respectively.

9. The multi-level SIP module of claim 1 further comprising a top mold compound, wherein:• the submodule further includes a submodule mold compound that is formed on the top side of the submodule substrate to surround the at least one submodule component; and• the top mold compound is formed on the top side of the module substrate to fully encapsulate the at least one top component and to surround the submodule.

10. The multi-level SIP module of claim 9 wherein the top mold compound and the submodule mold compound are formed from different materials.1 1 . The multi-level SIP module of claim 9 wherein:• the at least one top component includes a first top component, which is positioned in the stand-off space vertically between the bottom side of the submodule substrate and the top side of the module substrate, and surrounded by the plurality of submodule bumps; and• a gap between the bottom surface of the laminate body of the submodule substrate and a top surface of the first top component has a vertical distance between 10 pm and 50 pm and is filled with the top mold compound.

12. The multi-level SIP module of claim 11 wherein the at least one top component further includes a second top component, which is positioned horizontally outside the submodule.

13. The multi-level SIP module of claim 9 wherein:• the at least one top component is positioned horizontally outside the submodule;• no electronic component is surrounded by the plurality of submodule bumps and positioned vertically between the bottom side of the submodule substrate and the top side of the module substrate; and• each of the plurality of submodule bumps has a same height of at least 25 pm.

14. The multi-level SIP module of claim 9 wherein:• the at least one submodule component is a flip-chip die;• the submodule mold compound surrounds and underfills the at least one submodule component without covering a backside of the at least one submodule component;• the submodule further includes a stiffening layer, which is formed over the submodule mold compound to encapsulate the backside of the at least one submodule component, wherein a top surface of the submodule is a top surface of the stiffening layer, and a side surface of the submodule is a combination of a side surface of the submodule substrate, a side surface of the submodule mold compound, and a side surface of the stiffening layer; and• the top mold compound at least surrounds and underfills the submodule without covering the top surface of the submodule, wherein the submodule does not vertically extend beyond a top surface of the top mold compound.

15. The multi-level SIP module of claim 14 further comprising a module shielding structure, wherein:• the top surface of the top mold compound and the top surface of the submodule are coplanar; and• the module shielding structure directly and continuously covers a combination of the top surface of the top mold compound and the top surface of the submodule, and a combination of a side surface of the top mold compound and a side surface of the module substrate.

16. The multi-level SIP module of claim 15 further comprising a submodule side shielding structure, wherein:• the submodule side shielding structure directly and completely covers the side surface of the submodule, and the top mold compound surrounds the submodule side shielding structure;• a cross-sectional surface of the submodule side shielding structure is exposed through the top mold compound at a periphery of the submodule, and is coplanar with the top surface of the top mold compound and the top surface of the submodule; and• the module shielding structure is in contact with the submodule side shielding structure.

17. The multi-level SIP module of claim 1 further comprising at least one bottom component and a plurality of bump structures, wherein the at least one bottom component and the plurality of bump structures are attached to a bottom side of the module substrate, which is opposite from the top side of the module substrate.

18. The multi-level SIP module of claim 17 further comprising a bottom mold compound, wherein:• the bottom mold compound surrounds each of the plurality of bump structures without covering an end surface of each of the plurality of bump structures, wherein a bottom surface of the bottom mold compound and the end surface of each of the plurality of bump structures are coplanar; and• the bottom mold compound at least surrounds the at least one bottom component, wherein the at least one bottom component does not vertically extend beyond the bottom mold compound.

19. The multi-level SIP module of claim 1 wherein the submodule has a thickness between 200 pm and 350 pm.

20. A communication device comprising:• a control system;• a baseband processor;• receive circuitry; and• transmit circuitry, wherein at least one or any combination of the control system, the baseband processer, the transmit circuitry, and the receive circuitry is implemented in a multi-level SIP module, which at least includes a module substrate, a submodule, and at least one top component, wherein:• the submodule and the at least one top component are attached to a top side of the module substrate;• the submodule includes a submodule substrate, at least one submodule component, and a plurality of submodule bumps;• the submodule substrate includes at least a laminate body, a top metal layer, and a bottom metal layer, wherein one of the top metal layer and the bottom metal layer protrudes vertically from a corresponding boundary surface of the laminate body, while another one of the top metal layer and the bottom metal layer is embedded in the laminate body and exposed through the laminate body, and shares a flat plane with the laminate body; and• the at least one submodule component is mounted to a top side of the submodule substrate via the top metal layer, while the plurality of submodule bumps is connected to the bottom metal layer on a bottom side of the submodule substrate and extends towards the top side of themodule substrate, which provides a stand-off space that is vertically between the submodule substrate and the module substrate.21 . A method of manufacturing a multi-level SIP module comprising:• forming a submodule, which includes a submodule substrate, at least one submodule component, and a plurality of submodule bumps, wherein:• the submodule substrate includes at least a laminate body, a top metal layer, and a bottom metal layer, wherein one of the top metal layer and the bottom metal layer protrudes vertically from a corresponding boundary surface of the laminate body, while another one of the top metal layer and the bottom metal layer is embedded in the laminate body and exposed through the laminate body, and shares a flat plane with the laminate body; and• the at least one submodule component is mounted to a top side of the submodule substrate via the top metal layer, while the plurality of submodule bumps is mounted to a bottom side of the submodule substrate via the bottom metal layer;• attaching at least one top component to a top side of a module substrate; and• attaching the submodule to the top side of the module substrate, wherein each of the plurality of submodule bumps extends from the bottom side of the submodule substrate towards the top side of the module substrate, which provides a stand-off space that is vertically between the submodule substrate and the module substrate.

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