Methods and systems for integer invertible discrete trigonometric transforms

Abstract

An aspect of the present disclosure relates to method for generating an invertible integer discrete Fourier transform of at least one signal. The method comprises processing a first and second input vector with a dual input integer discrete Fourier transform, intDFT, to form a first and second intDFT vector corresponding to the first and second input vector, wherein each intDFT vector comprises complex-valued samples and wherein the dual input intDFT is implemented using three multi-dimensional lifting steps with integer rounding. Each lifting step comprises performing a discrete Fourier transform or inverse discrete Fourier transform of one of the first and second input vectors followed by integer rounding and addition of the integer rounded result to the other one of the first and second input vectors. The method further comprises forming at least one output intDFT vector based on at least one of the first and second intDFT vectors.

Description

METHODS AND SYSTEMS FOR INTEGER INVERTIBLE DISCRETE TRIGONOMETRIC TRANSFORMSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to European Patent Application No. 24209570.1, filed October 29, 2024 and US provisional application 63 / 713,197, filed October 29, 2024, each of which is incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates to methods and systems performing integer invertible trigonometric transforms, such as a discrete cosine transform or discrete sine transform, of signals.BACKGROUND

[0003] In data coding applications data may be coded using lossy coding schemes or lossless coding schemes. Especially for lossless coding schemes transform based coding can be more efficient than time domain coding, such as linear predictive coding, depending on the signal distribution. Additionally, when the data to be coded comprises a plurality of time domain samples which are divided into a sequence of non-overlapping blocks it is desirable to use the same transform type for both lossy and lossless coding schemes. For example, multimedia signals such audio or video signals, biomedical signals, or general pulse code modulated signals may be suitable for non-overlapping block transform coding.

[0004] For lossless coding integer transformations that map integers to integers have become popular.GENERAL DISCLOSURE

[0005] To ensure that the same transformation results on both the encoder side and decoder side fixed-point transform implementation may be used. However, a drawback with existing fixed-point integer transformation for data coding is that integer transforms based on recursion require a number of rounding operations wherein the number of rounding operations is proportional to the logarithm of the transform size. Since each rounding step reduces the fidelity, recursion based integer transforms become impractical to use for large transform sizes, such as transform sizes exceeding e.g. 256 or 512 samples. Additionally, in solutions applying a floattransformation followed by integer rounding the resulting transform may as such be an integer transform, but this type of transform is in general not integer invertible and deterministic making it impossible to realize a lossless transformation. For example, the precision of the floating point calculations and / or the integer rounding may be implementation dependent meaning that float transformation followed by integer rounding will in general not yield the same result which makes the transform non-deterministic. Additionally, even if the transform is made deterministic, this does not immediately result in a transform which is integer invertible.

[0006] For the Type IV Discrete Cosine Transform multi-dimensional lifting may be used to reduce the number of rounding operations. However, DCT-IV has an even / odd extension property which makes it ill-suited for coding of non-overlapping blocks.

[0007] Type II Discrete Cosine Transform features an even / even extension which is better suited for block coding (e.g. coding of non-overlapping blocks), but integer invertible implementations of DCT-II are limited to very small transform sizes, such as e.g. size 8 or 16.

[0008] Accordingly, there is a need for a new and improved method for lossless transform coding which overcomes at least some of the drawbacks mentioned above.

[0009] According to a first aspect, there is provided a computer implemented method for generating an invertible integer discrete Fourier transform of at least one signal. The computer implemented method comprises, obtaining a first sequence of samples being associated with the at least one signal and forming a first and second input vector based on at least the first sequence of samples. The method further comprises processing the first and second input vector with a dual input integer discrete Fourier transform, intDFT, to form a first and second intDFT vector corresponding to the first and second input vector, wherein each intDFT vector comprises complex-valued samples and wherein the dual input intDFT is implemented using three multidimensional lifting steps with integer rounding, wherein each lifting step comprises performing a discrete Fourier transform or inverse discrete Fourier transform on a first lifting step input vector followed by integer rounding and addition of the integer rounded result to or from a second lifting step input vector. The method further comprises forming at least one output intDFT vector based on at least one of the first and second intDFT vectors.

[0010] The first sequence of samples may in general be complex-valued. It is also envisaged that the first sequence of samples are real-valued samples. In some implementations the first sequence of samples are integers. In some implementations, the at least one signal is integer rounded to form a signal with integer samples. For example, the input signal is an integer valued signal (e.g. a PCM signal) and the first sequence of samples comprises integer valued samples.

[0011] The first and second sequence may be a subset of the samples of a same signal or a subset of samples of respective different signal. In cases where the first and second sequence are samples of the same signal the first and second sequence may be the odd and even samples of an original sequence of the same signal. In some implementations, the at least one signal is divided into a plurality of sequences (or blocks) and each sequence is transformed into an intDFT representation. The plurality of sequences (or blocks) may be non-overlapping.

[0012] Forming the at least one output intDFT vector based on at least one of the first and second intDFT vectors may comprise using the first or second intDFT vector as the output intDFT. For example, each intDFT vector may form a respective intDFT output vector. As another example, the first and second intDFT vectors are combined to form a single output intDFT vector.

[0013] In some embodiments, the method further comprises converting the at least one output intDFT vector to an integer discrete trigonometric transform, intDTT, vector using a plurality of integer invertible processing steps. The plurality of integer invertible processing steps may e.g. comprise a plurality of lifting steps.

[0014] Hereby, a computationally efficient integer discrete trigonometric transform intDTT may be achieved by utilizing a dual input intDFT. In some examples, the intDTT is a discrete cosine transform (DCT) or discrete sine transform (DST). To transform the intDFT to an intDTT the at least one output intDFT vector is scaled with a complex factor, wherein the complex factor is implemented using a factorization into lifting steps.

[0015] According to a second aspect, there is provided a computer implemented method for transforming intDFT samples to integer samples (e.g. time domain samples or spatial domain samples, such as pixel data). The computer implemented method comprises obtaining at least one sequence of input intDFT samples. The computer implemented method further comprises forming a first and second input intDFT vector based on the at least one sequence of input intDFT samples and processing the first and second input intDFT vectors with a dual input inverse integer discrete Fourier transform, intIDFT, to form a first and second intIDFT vector corresponding to the first and second input intDFT vector, wherein each intIDFT vector comprises complex-valued samples, wherein the dual input intIDFT is implemented using three multi-dimensional lifting steps with integer rounding, wherein each lifting step comprises performing a discrete Fourier transform or inverse discrete Fourier transform on a first lifting step input vector followed by integer rounding and addition or subtraction of the integer rounded result to or from a second lifting step input vector. The method further comprises forming at least one output sequence of samples based on the first and second intIDFT vector.

[0016] That is, dual input intDFT may be inverted to form a dual input intIDFT. It is understood that any other processing units used in connection to the first aspect (for example to transition to an intDTT, for performing intDFT of real- valued inputs, or splitting a single input signal into two signals) may be inverted and used together with the intIDFT in an analogous manner to how these processing units are used with the intDFT. For example, the dual input intIDFT may be used to form an inverse intDTT (such as an inverse intDCT or intDST) and / or to form an inverse intDFT adapted for real-valued input signals. In general, the intIDFT transforms transform domain samples into a non-transform domain. The non-transform domain may e.g. be a time domain or spatial domain wherein the transform domain is a frequency domain such as an intDFT domain or intDTT domain.

[0017] According to a third aspect, there is provided a computer program product comprising instructions which, when the program is executed by a computer, causes the computer to carry out the method according to the first or second aspect.

[0018] According to a fourth aspect, there is provided a computer-readable storage medium storing the computer program according to the third aspect.

[0019] According to a fifth aspect, there is provided an encoder comprising a processor and memory, wherein the processor is configured to perform the method according to the first aspect.

[0020] According to a sixth aspect, there is provided a decoder comprising a processor and memory, wherein the processor is configured to perform the method according to the second aspect.

[0021] The second to sixth aspect features the same or equivalent benefits as the first aspect. Any functions described in relation to a computer implemented method, may have corresponding features in a decoder, encoder or computer program product.BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Embodiments of the present invention will be described in more detail with reference to the appended drawings.

[0023] Figure 1A is a block diagram illustrating an encoding system according to some implementations.

[0024] Figure 1B is a block diagram illustrating a decoding system according to some implementations.

[0025] Figure 2 is a block diagram illustrating a dual input integer discrete Fourier transform, intDFT, processing unit according to some implementations.

[0026] Figure 3A is a block diagram illustrating a dual input intDFT processing unit implemented using multi-dimensional lifting steps according to some implementations.

[0027] Figure 3B is a block diagram illustrating the multi-dimensional lifting steps of the dual input intDFT processing unit in further detail.

[0028] Figure 4 is a block diagram illustrating a real- valued intDFT processing system, according to some implementations.

[0029] Figure 5 is a block diagram illustrating a complex rotations unit, according to some implementations.

[0030] Figure 6A is a block diagram illustrating an integer discrete trigonometric transform, intDTT, processing system according to some implementations.

[0031] Figure 6B is a block diagram illustrating two intDTT processing systems operating in parallel, allowing a dual input intDFT processing unit to be used.

[0032] Figure 6C is a block diagram illustrating one leg of two intDTT processing systems operating in parallel, according to some implementations.

[0033] Figure 6D is a block diagram illustrating an alternative complex rotations unit, according to some implementations.

[0034] Figure 6E is a block diagram illustrating one leg of two intDTT processing systems featuring a liftable unitary map processing unit, according to some implementations.

[0035] Figure 7A is a block diagram showing a processing system allowing a single input vector to be processed with the dual input intDFT processing unit by splitting and recombining the single input vector according to some implementations.

[0036] Figure 7B is a block diagram showing an intDTT processing system for processing a single input vector, according to some implementations.

[0037] Figure 8 is a block diagram illustrating a dual input inverse integer discrete Fourier transform (intIDFT) unit according to some implementations.DETAILED DESCRIPTION

[0038] Embodiments of the present invention will be described in the following with reference to an example encoding and decoding architecture. It is noted that the invention is not limited to this particular architecture. On the contrary, entropy coding according to embodiments of the present invention may be useful for encoding and decoding any signal, and is particularly useful in any lossless coding architecture.

[0039] Systems and methods disclosed in the present application may be implemented as software, firmware, hardware or a combination thereof. In a hardware implementation, the division of tasks does not necessarily correspond to the division into physical units; to thecontrary, one physical component may have multiple functionalities, and one task may be carried out by several physical components in cooperation.

[0040] The computer hardware may for example be a server computer, a client computer, a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a smartphone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that computer hardware. Further, the present disclosure shall relate to any collection of computer hardware that individually or jointly execute instructions to perform any one or more of the concepts discussed herein.

[0041] Certain or all components may be implemented by one or more processors that accept computer-readable (also called machine-readable) code containing a set of instructions that when executed by one or more of the processors carry out at least one of the methods described herein. Any processor capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken are included. Thus, one example is a typical processing system (i.e. a computer hardware) that includes one or more processors. Each processor may include one or more of a CPU, a graphics processing unit, and a programmable DSP unit. The processing system further may include a memory subsystem including a hard drive, SSD, RAM and / or ROM. A bus subsystem may be included for communicating between the components. The software may reside in the memory subsystem and / or within the processor during execution thereof by the computer system.

[0042] The one or more processors may operate as a standalone device or may be connected, e.g., networked to other processor(s). Such a network may be built on various different network protocols, and may be the Internet, a Wide Area Network (WAN), a Local Area Network (LAN), or any combination thereof.

[0043] The software may be distributed on computer readable media, which may comprise computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to a person skilled in the art, the term computer storage media includes both volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, physical (non-transitory) storage media in various forms, such as EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, it is well known to the skilled person that communication media(transitory) typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

[0044] Figure 1a is a block diagram illustrating an encoding system 1 for encoding a signal x(n). The encoding system 1 comprises an integer discrete transform (intT) processing unit 2 and a subsequent entropy coding unit 3.

[0045] The signal x(n) is a data signal comprising a sequence of samples representing data, for example audio data or biomedical data. For example, the signal x(n) is a time domain signal representing a time domain audio signal or a time domain biomedical signal. A time domain audio signal comprises a plurality of audio samples, wherein each sample is separated in time from its neighboring samples.

[0046] A biomedical signal in the context of the present disclosure may be a signal that relates to physiological information, and the signal may be electrical, physical or biochemical. The biomedical signal may relate to biological systems and conditions, examples of which may include Electrocardiography (ECG) data, Electroencephalography (EEG) data, Electromyography (EMG) data, and Photoplethysmogram (PPG) data, or signals for blood sugar level, heart rate, body temperature, respiratory rate and oxygen saturation. Further, a biomedical signal may comprise one or more channels of time domain biomedical signal samples. In other examples, the biomedical signals may relate to muscle and / or skin measurements. Any other medical signal and / or physical response would also be understood to be comprised by this definition.

[0047] The encoding system 1 may for example be implemented in a biomedical measurement device, configured to detect biomedical data. The decoding system 4, which will be described below, may be implemented in a biomedical monitoring device, configured to receive the biomedical data.

[0048] As another example, the samples of the signal x(n) are distributed along a spatial dimension with each sample indicating a property at a position in space. For example, the signal x(n) represents an image with each sample representing a value (e.g. color, brightness, etc.) associated with an individual pixel of that image.

[0049] Irrespective of the type of data the signal x(n) represents, the signal x(n) may be transformed into a transform domain signal y(n) = T[x(n)] to make the signal more suitable for efficient transmission in a bitstream B. To make the transform and transmission lossless, the transform T is reversible and deterministic allowing a copy of the data signal x(n) to be recreated from the transform domain samples y(n) = T[x(n)]. It is noted that in this general example, both the signal x and the transform domain representation y share the same indexationn. I’he indexes may be the same if the transformed signal is in the same domain as the original signal. However, it also understood that in other implementations (for example if the transform changes the domain of the signal) the sample indexes may be different.

[0050] The transformation y(n) of the signal x(n) is performed by the transformation unit 2 which is configured to perform an integer invertible discrete transform T to form the transform representation intT. For example, the integer discrete transform T may be a discrete Fourier transform (intDFT) or an integer discrete trigonometric transform (intDTT) such as an integer discrete cosine transform of type II (intDCT-II) or an integer discrete sine transform of type II (intDST-II) extracted in accordance with embodiments described herein.

[0051] The intT representation (i.e. samples y(n)) may be transmitted directly in a bitstream B, or as shown in FIG. 1 A, the intT representation is encoded with an entropy encoder 3 prior to being included in the bitstream B. The entropy encoder 3 may be configured to apply Huffman coding or Golomb-Rice coding to the transform samples y(n). As yet another example, the entropy encoder 3 is configured to apply the coding scheme as disclosed in U. S. Provisional Patent Application No. 63 / 713,209, titled “Entropy Coding Combining Huffman and Golomb-Rice Coding”, filed by Applicant Dolby Laboratories Licensing Corporation on October 29, 2024, naming Mark S. Vinton as inventor, which is herewith incorporated by reference in its entirety.

[0052] The bitstream B may be stored. The bitstream B may be conveyed to a receiving device comprising a decoding system as shown in FIG. 1B. The decoding system 4 may comprise an entropy decoder 5 as shown in FIG. 1B which decodes the entropy coding to form the representation intT. Alternatively, if entropy coding is not used, the entropy decoder 5 (and entropy encoder 3 in the encoding system 1) may be omitted.

[0053] The transform representation intT comprising samples y(n) is provided to an inverse transform unit 6 which is configured to perform the inverse transformation T-1to recreate a version x'(n) of the original data signal x(n). If the transformation T is deterministic and integer invertible the recreated version x'(n) of the original signal x(n) may be a perfect (lossless) recreation of the original signal x(n). That is x(n) = x’(n). However, it is also envisaged that in order to conserve data and / or reduce the bitrate various lossy transformations may be derived from the lossless transformation. For example, the transform domain samples y(n) output by the transform T may be quantized and / or approximated using parameters in the encoder. On the decoder side, the quantized and / or parameter approximated representation of the samples y(n) may be dequantized and / or recreated from the parameters, wherein the quantization / dequantization process and / or parameter reconstruction are lossy processes.

[0054] The encoding and decoding systems 1, 4 of FIGS. 1A-B may be implemented in a wide variety of devices, ranging from high-performance network servers (e.g. in the cloud) to more computationally constrained devices such as laptops, tablets, smartphones, smartwatches or any loT device or wireless sensor. There is therefore a need for implementing the transformation unit 2 and inverse transformation unit 6 in computationally efficient manners to allow the decoding and encoding units to reduce processing latency and / or reduce power consumption.

[0055] In the following, various systems and processing units for obtaining invertible integer transforms, such as intDFT, intDTT, intDCT-II and intDST-II will be described using block diagrams. It is understood that any processing block presented may be implemented as a step in a method or in a processing unit in a processing system configured to perform the processing method. Each processing system or processing unit may be implemented in hardware or software.

[0056] In some implementations, the integer invertible discrete transform T is an integer invertible discrete Fourier transform, an intDFT.

[0057] FIG. 2 is a block diagram illustrating an intDFT processing system 10 for transforming two signals x1(n) and x2(n) to their respective integer discrete Fourier transforms inlDI 'I’Ixj (n) | and inlDIT|x2(n)]. The discrete Fourier transform (DFT) labeled F maps x X from to itself and the DFT is defined asNotably, the DFT also brings a change index, from n to k. The inverse DFT, or F1, may be defined as

[0058] Using equation 1, the intDFT of signals %i(n) and x2(n) may be extracted, and in the following the intDFT of each signal is labeled Xi (k) and X2( / c). Equation 2 may subsequently be used to transform X^k) and X2(k) back into signals %i(n) and x2(n).

[0059] From equations 1 and 2 it can be found that the difference between the intDFT (F) and the inverse intIDFT (F1) is the sign of the complex exponential e-j2πkn / M. Mathematically, this relationship may be expressed as (x) = (F-1[x*])* with the asterisk * indicating complex conjugation. Hereby, an intDFT of two signals x₁(n), x2(n) in parallel is mathematically equivalent to determining the intDFT of the first signal x₁(n) and the intIDFT of the second signal x2(n) if complex conjugation is applied prior to and after processing the second signal x2(n) with the intIDFT. This is shown in FIG. 2 where an intDFT processing unit 13 configuredto process the first (in general complex-valued) signal %i(n) with M number of samples as the transform size to yield a first intDFT vector and the second (in general complex- valued signal) signal x2(n) with M number of samples as the transform size is processed with a first complex conjugation unit 1 la configured to output the complex conjugate of x2(n). an inverse intDFT processing unit 14 configured to extract the inverse intDFT. and a second complex conjugation unit 1 lb configured to output the complex conjugate of its input to yield the second intDFT vector.

[0060] The intDFT processing unit 13 and inverse intDFT processing unit 14 form a processing unit pair 12 which may be converted to three multi-dimensional lifting steps with integer rounding to form a dual input intDFT processing system 10’ as shown in FIG. 3 A. The intDFT processing system 10 of FIG. 2 and intDFT processing system 10’ of FIG. 3A are equivalent in terms of both systems resulting in integer discrete Fourier transforms of their two input signals, however the intDFT processing system 10’ has the advantage of being integer based, deterministic and invertible.

[0061] Each of the three multi-dimensional lifting steps comprises either an inverse discrete Fourier transform (IDFT) processing unit 23a, 23b followed by an integer rounding unit 24a, 24c or a DFT processing unit 25 followed by an integer rounding unit 24b. Each IDFT unit 23a, 23b and DFT unit 25 is configured to perform an IDFT or DFT of its input. To form an integer invertible process the IDFT and DFT units 23a, 23b, 25 may be configured to be deterministic and output the same result for a same given input. This allows the signal input to the intDFT processing system 10’ to be reconstructed in a lossless fashion at the output of the corresponding integer inverse discrete Fourier transform, intIDFT (see e.g. FIG. 8). Accordingly, when using the intDFT and intIDFT in a corresponding encoder and decoder, an input signal to the encoder may be reconstructed in a lossless fashion by the decoder. To achieve deterministic operation of the IDFT unit 23a, 23b and DFT unit 25, each unit may be configured to operate using fixed-point arithmetic.

[0062] The (e.g. fixed-point) output of each DFT or IDFT unit may be rounded to an integer using the subsequent rounding units 24a-c. Each rounding unit 24a-c being e.g. configured to round the output to the nearest integer. As further options, each rounding unit 24a-c is configured to perform a floor rounding operation or ceiling rounding operation. Notably, each rounding unit used in embodiments of the present disclosure are all of the same type. That is, each lifting step or multiplication of the present embodiments are followed by rounding, and the rounding process is the same each time, and the same in both the intDFT processing system 10’ and intIDFT (e.g. as implemented in a corresponding encoder and decoder). There are many options for performing integer rounding, any of which may be used, as long as the same type ofinteger rounding is used in the intDFT and intIDFT processing systems, e.g., as implemented in a corresponding encoder and decoder.

[0063] As mentioned above, the DFT and IDFT processing units 23a-b, 25 may be fixed-point implementations of the DFT and IDFT. The fixed-point implementations may be deterministic. For example, to realize fixed-point deterministic DFT and IDFT processing units 23a-b, 25 these may be implemented as integer DFTs and IDFTs configured to operate with fixed-point arithmetic which has a bit depth which is at least 50% higher than the bit depth of the input signal(s) or preferably at least double the bit depth of the input signal(s). For example, if the input signals comprise samples with a bit depth of 16 each DFT and IDFT unit may operate with 24 bit fixed point arithmetic (corresponding to a 50% higher bit rate than the input signals), operate with 32 bit fixed point arithmetic (corresponding to double the bit rate of the input signals) or operate with 64 bit fixed point arithmetic (corresponding to four times the bit rate of the input signals). To achieve integer deterministic and invertible properties each DFT and IDFT unit may preferably operate with fixed point implementations having the same bit depth.

[0064] The same may also apply to each multiplication which is performed with a fixed-point arithmetic which has a bit depth which is at least 50% higher than the bit depth of the input signal(s) or preferably at least double the bit depth of the input signal(s). In one example implementation, the bit depth of each multiplication and DFT / IDFT unit is at least double the bit depth of the input signal(s) being processed. For example, the input signal(s) have samples with a bit depth of 32 bits and each multiplication is performed with fixed-point arithmetic having a bit depth of 64 bits.

[0065] Both at the input and output of the multi-dimensional lifting steps the second signal x2(n) further undergoes complex conjugation in complex conjugation units 11a, 11b. The first signal t(n) is also negated in negation unit 26 after having been processed with the three multidimensional lifting steps, as shown in FIG. 3 A. The complex conjugation unit 11a defines a preprocessing stage to the three multi-dimensional lifting stages and the complex conjugation unit 11b together with the negation unit 26 forms a post-processing stage.

[0066] To further describe the operation of the dual input intDFT processing system 10’ of FIG. 3A the processing of two input vectors (e.g. extracted from a respective signal or from the same signal),and x2will now be described. Each vector x and x2comprises N samples with index n = 0, 1, 2... N — 1. In general, each of the three multi-dimensional lifting steps operates on a first and second lifting step input vector which are based on the input vectorsx2, complex conjugations thereof or the output of preceding multi-dimensional lifting steps.

[0067] The second vector x2is provided to complex conjugation unit Ila which outputs the complex conjugate of the second vector x2. The output of complex conjugation unit 11a isprovided as a first lifting step input vector to the IDFT unit 23a of the first multi-dimensional lifting stage. The IDFT unit 23a takes the N samples of the first lifting step input vector as an input and outputs the N sample IDFT transform of its input. The IDFT transform is provided to rounding unit 24a which integer rounds each sample of its input and outputs a vector of N integers which are elementwise added to the first vectorat summation point 27a. The first vector hereby forms a second lifting step input vector.

[0068] The output sum of summation point 27a is provided as first lifting step input vector to the second lifting step. The second lifting step starts with a DFT unit 25 which outputs the N sample DFT of its N sample input to a subsequent rounding unit 24b. Rounding unit 24b outputs a sequence of integers formed by integer rounding its input. The vector of integers output by rounding unit 24b are subtracted elementwise from a second lifting step input vector (here the output of complex conjugation unit 1 la) at summation point 27b. The output of summation point 27b is provided to negation unit 26 which negates all samples to form the first intDFT vector X being the first intDFT vector generated from the first vector x1.

[0069] The output from summation point 27b is provided as a first lifting step input vector to the IDFT unit 23b of the third lifting stage. The IDFT unit 23b outputs the N sample inverse DFT transform of its N sample input. The inverse DFT transform is provided to rounding unit 24c which rounds its input and outputs a vector of integers which are elementwise added to the output of summation point 27a (forming a second lifting step input vector) at summation point 27c. The output of summation point 27c is complex conjugated at complex conjugation unit 1 lb and the output of complex conjugation unit 1 lb forms the second intDFT vector X2being the integer discrete Fourier transform, intDFT, of the second vector x2.

[0070] Notably, all steps performed in the dual input DFT processing system 10’ of FIG.3A may be realized using integer deterministic and integer invertible steps. For example, complex conjugation, addition, subtraction, negation and DFT / IDFT followed by integer rounding as shown in FIG. 3A form an overall integer invertible process.

[0071] In general, any function f is integer invertible if y1=+ f(x2) and y2= x2is equivalent to x2= y2and x1= y1— f(y2). For example, using these properties samples x1, x2are mapped to samples y1, y2and this process can be reversed, so as to e.g. recover samples x1from samples y by subtracting / (y2) from y. The function f may in this case be a DFT or IDFT process followed by integer rounding (as in any of the multi-dimensional lifting steps of FIG. 3A) and from this it follows that if the input samples x, x2are integers, the output y1, y2will also be integers. Since the DFT and IDFT described in equation 1 and 2 above comprises at least one sample which maps to itself (disregarding the normalization scaling) the DFT and IDFT followed by rounding may be used to form invertible lifting steps.

[0072] The multi-dimensional lifting steps are shown in further detail in FIG. 3B. Each DFT processing unit 25 and IDFT processing unit 23a, 23b is configured to take the N samples of the relevant signal x, x2and generate the DFT or IDFT as an output, which also comprises N samples. Each of the resulting N samples are rounded as illustrated with rounding units R. FIG.3B also illustrates that the negation in negation unit 26 and summation / subtraction at summation points 27a-c are done on a sample-by-sample (i.e. elementwise) basis. In FIG. 3B, N = 4, but this is merely an example suitable for illustration. In some implementations, the transform size at which the input signal / vectors is processed is at least 512, at least 1024 or at least 2048 samples. For example, the input signal / vectors are divided into frames having at least 512, at least 1024 or at least 2048 samples wherein the frames are processed separately by the dual input intDFT processing unit 10’. Each IDFT 23a, 23b processing unit and DFT processing unit 25 may thus operate with a transform size of at least 512 samples, at least 1024 samples or at least 2048 samples.

[0073] It is noted that the multi-dimensional lifting steps of the processing system 10’ of FIG. 3A and 3B may be described using a matrix operationwhich can be factorized intoif the complex conjugation stages are disregarded. From the factorization in equation 4, it holds that the process is integer invertible for any n x n implementation of the identity matrix lnand transform T. Here, the transform T is the discrete Fourier transform, DFT.

[0074] The dual input intDFT processing system 10’ of FIGS. 3 A and 3B may be used to form a dual input inverse integer discrete Fourier transform intIDFT as will be described in further detail below, in connection with FIG. 8. In short, to obtain an intIDFT processing system the horizontal signal flow paths of FIG. 3 A or 3B are reversed. That is, the input vectors are now the intDFT vectors X1, X2and the output becomes the sample vectorsand x2. Additionally, the sign of the vertical paths into summation points 27a-c are reversed. More specifically, in the intIDFT processing system summation points 27a and 27c perform subtraction and summation point 27b performs addition.

[0075] The DFT and IDFT processing units 23a, 23b, 25 of the dual input intDFT processing system 10’ (or its intIDFT variant) may employ any form of DFT algorithm as long as they are deterministic, a property which can be achieved through fixed-point arithmetic implementations. For instance, the DFT or IDFT processing units 23a, 23b, 25 may employ afast Fourier transform (FFT) or other type of Fourier transform which is computationally efficient, as long as the transforms are deterministic.

[0076] In some implementations, the input signals are complex-valued.

[0077] In some implementations, the input signals are real- valued signals comprising an even number N samples. For such real-valued input signals the dual input intDFT processing system 10’ may be made even more efficient if certain extra processing steps are taken. FIG. 4 is a block diagram illustrating the processing units for generating the intDFT of a real-valued input vector x using the dual input intDFT processing system 10’ in real-valued intDFT processing system 40.

[0078] Assuming an N sample real-valued input vector x, where N is a multiple of four, it holds that the intDFT vector X of x is conjugate symmetric X[— k] = X*[fc] and periodic with period N. It follows that X[0] and X[N / 2] are real-valued and that X is defined completely by X[0] and X[ / V / 2] together with the N / 2 — 2 complex-valued samples at indices k =1,2,.. / V / 2 — 1. Hereby, the intDFT of the N sample real-valued input signal may be described completely by the two real-valued samples and the N / 2 — 2 complex-valued samples.

[0079] These properties are utilized in the real- valued intDFT processing system 40 of FIG. 4 which incorporates the dual input intDFT processing unit of FIGS. 3A-B. The input vector x ∈ ℝNis first provided to a DFT pre-shuffle stage 41. The DFT pre-shuffle stage 41 is configured to perform an even / odd complexification of the input vector x by computing:and subsequently forming the DFT pre-shuffled output xsasxsxs,real "b ixs,imag(6) wherein i denotes the imaginary unit. Hereby, the pre-shuffled vector xsis formed by summing the even and odd samples of x as real parts and imaginary parts respectively. Accordingly, the pre-shuffled vector xshas IV / 2 samples, wherein each sample is in general complex-valued. That is, xs∈ ℂN / 2.

[0080] The pre-shuffled vector xsis provided as input to the integer DFT module 10’ which is configured to compute the intDFT of xs. The intDFT may be realized using the dual input intDFT processing unit 10’ of FIG. 3 A or FIG. 3B. For example, it is possible to split the vector xsinto two parts, process these two parts with the dual input intDFT 10’ of FIGS. 3A-B to get two intDFT split vector outputs, and combine the two intDFT split vectors, as will be described below, in connection to FIGS. 7A-B. On the other hand, when two input signals are available two instances of the real-valued intDFT processing system 40 are used in parallel wherein the DFT stages are combined into a single dual input intDFT processing unit 10 inaccordance with FIGS. 3A-B, as also will be described below. In FIG. 4 only one instance of the real-valued intDFT processing system 40 is shown, but it is understood that a second signal is processed with an analogous processing system wherein the dual input intDFT processing unit 10’ is shared.

[0081] In any case, the intDFT processing unit 10’ is configured to output a vector which is now referred to as a preliminary output intDFT vector XPwhich is the intDFT of the shuffled input. In the case of two processing systems 40 operating in parallel, the dual input intDFT processing unit 10’ outputs two preliminary output intDFT vectors which are processed analogously. For simplicity, only one preliminary output vector will be discussed here.

[0082] The preliminary output vector XPin general comprises N / 2 complex-valued samples with index k = 0, 1,... N / 2 — 1. Post-processing units 42, 43, 44, 45 are configured to process the N / 2 samples of XPto form the output intDFT vector X being the intDFT of x. It is noted that XPis the intDFT of a pre-shuffled version of x. namely the intDFT of xs, but since the intDFT of x (herein denoted X) is sought, various post-processing steps may be performed to find X from XP.

[0083] Firstly, it is noted that index 0 and N / 2 of X should be real. Hereby, X (0) and X( / V / 2) are extracted from XPaswhere Re [a] and Im[a] denotes the real and imaginary part of a, respectively. This processing is performed by real rotation unit 42. Preferably, the real rotation unit 42 is further configured to apply a normalization, by scaling X(0) and X( / V / 2) by 1 / 2.

[0084] The complex rotations unit 43 is configured to operate pairwise on samples k = 1,..., N — 1 of XPand computes a complex rotated version XP rotof XPasIt is further possible to calculatewherein k in equations 8 and 9 is varied from 0 to / V / 4. Hereby XP,rot(k) is obtained for indexes 1 to N / 4 and X*P rot(k) is obtained for indexes / V / 4 to N / 2 — 1. Preferably, the complex rotations unit 43 is configured to normalize XP rotwith a factor of 1 / - / 2. It is noted that equations 8 and 9 may be factorized into integer invertible lifting steps, as will be described below.

[0085] A special case is also noted for XP rotof index k — N / 4 which may be obtained trivially asThe complex conjugation unit 44 is configured to perform this conjugation operation for sample index k = N / 4.

[0086] DFT post-shuffling unit 45 is configured to obtain the output from the complex rotations unit 43 and the output from the complex conjugation unit 44 so as to combine these to form samples k = 1, 2,... N / 2 — 1. Notably, the / V / 4 to N / 2 — 1 samples output by the complex rotation module are complex conjugated and concatenated to samples 1 to N / 4.Optionally, if N is a multiple of four, the simple extraction of XP,rot(N / 4) in accordance with equation 10 is also concatenated in the DFT post-shuffling unit 45.

[0087] As a result, N / 2 — 1 complex-valued samples and two real-valued samples (k = 0 and k — N / 2) are obtained as the output from the real-valued intDFT processing system 40. Notably, the DFT pre-shuffle unit 41 and post-processing units 42, 43, 44, and 45 allow the N sample intDFT of an N sample real-valued input to be obtained via an N / 2 complex -valued intDFT.

[0088] It is further noted that each processing step performed in any of the processing units 41, 42, 43, 44, 45 may be integer invertible, e.g. expressed as lifting steps. Processes such as shuffling, adding, subtracting and complex conjugation are trivially integer invertible.Additionally, integer rounding is implemented after each multiplication with a complex variable and / or after each multiplication in the lifting steps to realize fully integer invertible operation.

[0089] FIG. 5 illustrates how the pairwise sample processing in complex rotations unit 43 may be implemented using integer invertible lifting steps. The complex rotations unit 43 may be formed using first real rotation unit 431, a twiddle unit 432 and a second real rotation unit 433. Each real rotation unit 431, 433 is configured to apply real rotation in the form of multiplying a pair of samples with a rotation matrix[cos α -sin αThe rotation matrix of equation 11 may be factorized into lifting steps in accordance with [cos α -sin α] [1 b]

[0010] [1 b][sin α cos α]

[0001] [-1 1] [0 -1]wherein a = sin a and b = (cos a — 1) / sin a. In some implementations, the angle a is selected for all lifting steps to be on the range — n / 2 < a < n / 2. This selection of a results in absolute values of a and b less than or equal to one which simplifies the fixed-point implementation of the lifting steps. The angle a may be selected for all lifting steps of any processing unit or processing system described herein to be on the range —n / 2 < a < n / 2. That is, this is not limited to the lifting steps of complex rotations unit 43.

[0090] The twiddle unit 432 is configured to multiply each sample with a complex factor w with |w| = 1. The complex multiplication may be followed by integer rounding. For example, in equation 8 and 9 above the term [XP(k) — (which in it self is obtainable viareal rotation and conjugation acting on samples XP(k), XP(N-k)] is multiplied with a complexexponential having an absolute value of one, and this complex exponential multiplication may be achieved by the twiddle unit 432.

[0091] Every multiplication with a complex factor may also be expressed with a rotation matrix in accordance with equation 11 and which in turn is factorizable into lifting steps in accordance with equation. The difference between a real rotation and a complex factor multiplication is that the rotation matrix (factorized into lifting steps) is applied in the real-complex plane, operating on the real and imaginary part of a single complex-valued sample whereas the real rotation operates on a pair of real-valued samples. After complex factor multiplication the twiddle unit 432 may be configured to perform normalization and integer rounding.

[0092] Turning back to FIG. 5, it is illustrated how one pair of complex samples of XPare transformed into XP rotusing a real rotations and twiddling operation, which are integer invertible and deterministic processes. This process is repeated for multiple pairs of samples to construct XP rotfor all A: = 1, 2,... N / 2 — 1.

[0093] FIG. 6A shows a block diagram illustrating an intDTT processing system 70 configured to transform a real-valued input vector x into a real-valued intDTT vector X. The intDTT processing system 70 comprises an instance of the real- valued intDFT processing system 40 equivalent to the real-valued intDFT processing system 40 of FIG. 4, which in turn comprises the dual input intDFT processing unit 10’ of FIGS. 3A-B. As mentioned above, the dual input intDFT processing unit 10’ allows two signals to be processed in parallel or allows a single signal to be split into two parts which are processed in parallel. The latter case is described in more detail below, in connection with FIGS. 7A-B.

[0094] In FIG. 6B, a block diagram illustrating two instances of the intDTT processing system 70 is shown, for transforming two real-valued input vectors x and x2into respective intDTTs. For example the intDTTs are intDCTs or intDSTs. The processing of the two vectors x and x2is performed in parallel, with two real-valued intDFT processing systems 40 (see FIG.4) implemented in parallel, as parallel real-valued processing system 72. The intDFT processing of each real-valued intDFT processing system 40 are combined to and implemented using the dual input intDFT processing unit 10’ of FIGS. 3A-B.

[0095] To transform the output intDFT vector from each real-valued intDFT processing system 40 into an intDTT vector, the intDFT is processed with a plurality of integer invertible (e.g. lifting) steps. The integer invertible processing steps comprises processing the intDFT vector with a twiddle unit 73. The twiddle unit 73 is configured to scale a plurality of the intDFT output vector samples with a complex factor. As mentioned above the twiddle unit 73 may be implemented using lifting steps. The complex scaling factor may bee~ink / (.2N) The plurality of vector samples may comprise samples k = 1,2,... N / 2 — 1 of the generally complex-valued intDFT vector CN. As indicated above, samples k = 0 and k = N / 2 are real-valued and these may not be processed by the twiddle unit 73. This is indicated in FIG. 6B with two real-valued samples 1R2not being processed by the twiddle unit 73.

[0096] The N / 2 — 1 complex-valued samples output by the twiddle unit 73 arc provided together with the two ( / c = 0 and k = N / 2) real-valued samples to a DTT post-shuffle unit 74 which is configured to perform a post-shuffle operation to yield N real-valued samples that form an intDTT representation of the input vectors x±and x2, respectively.

[0097] In some implementations, the real-valued input vectors x1and x2are first preshuffled with DTT pre-shuffling unit 71. Whereby it is the DTT pre-shuffled samples which are input to the real-valued intDFT processing systems 40. That is, it is DTT pre-shuffled samples which are obtained as input to the real-valued intDFT processing system 40 of FIG. 4.

[0098] By appropriately configuring the DTT pre-shuffle and DTT post-shuffle operations implemented by the DTT pre-shuffling unit 71 and DTT post-shuffling unit 74 the resulting intDTT becomes an intDCT type II or intDST type II as will now be described, starting with the intDCT type II.

[0099] In general, an orthonormal intDCT type II is a map C: x >-> X from ℝNto itself defined by

[0100] To obtain an orthonormal intDCT type II the DTT pre-shuffle operation in the DTT pre-shuffle unit 71 is set to a DCT pre-shuffling mode. In the DCT pre-shuffling mode the input x is shuffled to form an output xsin accordance withwherein the operation [z] denotes the integer part of the variable z.

[0101] The DTT post-shuffle operation in the DTT post-shuffle unit 74 is analogously set to a DCT post-shuffling mode. In the DCT post-shuffling mode the N / 2 — 1 complex-valued samples with indices k = 1,2,... N / 2 — 1 (also referred to as intermediate samples) and the peripheral real-valued samples at k = 0 and k = N / 2 of the (twiddled) intDFT vector are concatenated to form an intDCT vector wherein intDCT vector comprises the samples in the order of (starting from the first sample 0 and going towards sample N) the first real- valued sample k = 0, the real parts of the N / 2 — 1 intermediate samples, the second real-valued sample k = N / 2, and then negative of the imaginary parts of the N / 2 — 1 intermediate samples wherein the last part, the negative of the imaginary parts of the N / 2 — 1 intermediate samples, are taken in the reverse order.

[0102] As an example, a (twiddled) intDFT vector with five samples at sample indexes k = 0, 1, 2, 3, 4 = N / 2 is considered. The samples of this exemplary sequence have values —66 + Oi, —25 — 2 Of, —55 — 771, —2 — 24i, 15 + Oi respectively, going from index k = 0 to k = 4. The intDCT vector output by the DTT post-shuffle unit 74 comprises eight real-valued samples being -66, -25, -55, -2, 15, 24, 77, 20 respectively, going from index k = 0 to index k = 7.

[0103] As seen in FIG. 6B, all steps are orthogonal and either trivially integer invertible or factorizable in lifting steps whereby an integer invertible approximation of DCT-II results upon rounding in all lifting steps. Additionally, the real-valued intDFT processing system 40 and the dual input intDFT' processing unit 10’ are implemented in the intDTT processing system 70 and also include either trivially integer invertible processing steps or processing steps which are factorizable in lifting steps whereby an integer invertible approximation is obtained after rounding. Hereby, the intDCT vector is obtained using a fully integer invertible and deterministic transformation process which leverages a computationally efficient dual input intDFT implementation alongside efficiency enhancement brought by using a real-valued input signal to achieve a half-size intDFT vector.

[0104] Turning to the intDST type II alternative it is noted that an orthonormal intDST type II is a map S: x ↦ X from ℝNto itself defined by

[0105] To obtain an orthonormal intDST type II the DTT pre-shuffle operation in the DTT pre-shuffle unit 71 is set to a DST pre-shuffling mode. In the DST pre-shuffling mode the input x is shuffled to form an output xsin accordance withand as seen by comparing equation 14 with equation 16, the DST pre-shuffling mode is similar to the DCT pre-shuffling mode, the difference being that when the samples of x having an index exceeding (N + l) / 2 are brought into xsas odd samples in reverse order there is a negation of the samples for the intDST-II case, as indicated by the negative sign of the — x(2N — 2n — 1) term in equation 16.

[0106] The DTT post-shuffle operation in the DTT post-shuffle unit 74 is analogously set to a DST post-shuffling mode. In the DST post-shuffling mode the 7V / 2 — 1 complex-valued samples with indices k = 1,2,... N / 2 — 1 (also referred to as intermediate samples) and the peripheral real- valued k = 0 and k = N / 2 samples are concatenated to form an intDST vector. The intDST vector comprises the samples of the twiddled intDFT vector in the order of (starting from the first sample 0 and going towards the last sample N) the negative of the imaginary parts of the N / 2 — 1 intermediate samples, the second real-valued sample k = N / 2, the real parts of the N / 2 — 1 intermediate samples wherein the real parts of the N / 2 — 1 intermediate samples are taken in reverse order, and the first real- valued sample k = 0.

[0107] As an example, a (twiddled) intDFT vector with five samples at sample indexes k = 0, 1, 2, 3, 4 = N / 2 is considered. The samples of this exemplary sequence have values —22 + Oi, — 16 + 53i, 8 + 16i, — 9 + 19 i, —4 + 01 respectively, going from index k = 0 to index k = 4. The intDST vector output by the DTT post-shuffle unit 74 operating in the DST mode comprises eight real-valued samples being -53, -16, -19, -4, -9, 8, -16, -22 respectively, going from index k = 0 to index k = 7.

[0108] It is noted that also in the intDST-II case, all processing steps are orthogonal and either trivially integer invertible or factorizable in lifting steps whereby an integer invertible approximation of intDST-II results upon rounding in all lifting steps.

[0109] FIG. 6C illustrates one leg of the dual input intDTT processing system 70 wherein the real input intDFT processing system 40 has been expanded to show its processing steps. As seen, even though this leg utilizes the intDFT of a single signal it cooperates with a second leg which generates an intDTT of another input signal. Hereby, the dual input intDFT processing unit of FIGS. 3A-B may be leveraged. The dual input and dual output signals are pre-processed and post-processed with respective integer invertible processing steps in processing units 71, 41,42, 43, 44, 45, 73 and 74 to form the intDTT of each input vector (e.g. the intDCT-II or intDST-II depending on the operational modes of the DTT pre- and post-shuffle units 71, 74).

[0110] In some implementations, the complex rotations unit 43 is configured to apply a real rotation, followed by a twiddle which in turn is followed by another real rotation, as described in connection with FIG. 5 above. In some implementations, the complex rotation processing unit 43 is replaced with an alternative complex rotation processing unit 43’ as shown in FIG. 6D. The alternative complex rotations unit 43’ uses two processing units 435, 432 instead of three, and fewer processing units will overall entail fewer integer rounding steps which makes it possible to more closely mimic a float valued transformation. Additionally, fewer processing units may make the transformation more computationally efficient.

[0111] The alternative complex rotations unit 43’ is configured to perform a processing of its input to form its output, wherein the processing corresponds toeia[ cos a —i sin alL-i sin a cos a J ’Multiplication with the complex factor eiais tended to by the twiddle processing unit 432 and the complex- valued rotation matrix of equation 18 titled ‘liftable unitary map’ is applied by the liftable unitary map processing unit 435. The liftable unitary map matrix may be factorized into lifting steps ascos a — i sin l [1 d] [1 01 [1 d]sin a cos a J 1.0 1J 1J Lo 1-1wherein c = — i sin a, and d = i (cos a — 1) / sin a. Here it is again noted that the liftable unitary map of equation 18 is unitary and integer invertible upon integer rounding of multiplication results. The same applies to the complex factor multiplication performed by the twiddle unit 432. As described above, complex factor multiplication may be performed using a rotation matrix acting on real and imaginary parts, which is factorizable into invertible lifting steps.

[0112] The complex factor of the twiddle processing unit 432 may further be combined with the complex factor of the twiddle processing unit 73 of FIG. 6C located downstream of the complex rotations unit 43. Accordingly, it is envisaged that a dual input intDTT processing system as shown in FIG. 6E can be used, wherein the liftable unitary map unit 435 has been used to replace the complex rotations unit 43 of FIG. 6C forming a modified real valued intDFT processing system 40’. The twiddle processing unit 73 of FIG. 6C is replaced with a modified twiddle unit 73’ combining the complex factor multiplication of the twiddle processing unit 73 and the complex rotations unit 43. A benefit of the intDTT processing system of FIG. 6E is that it uses fewer lifting steps as compared to the dual input intDTT processing system of FIG. 6C.

[0113] As mentioned above, the processing systems described herein may be adapted for processing a single input signal or a dual input signals. For dual input signal, dual instances of the real-valued intDFT processing system or dual instances of the intDTT processing systems are run in parallel with each parallel system operating on vectors extracted from each respective signal. It has however been found that even a single input signal may be processed by the dual input intDFT processing unit 10’ of FIGS. 3A-B. Hereby, single input implementations of the intDFT processing unit of FIGS. 3A-B, single input implementations of the real- valued intDFT processing system of FIG. 4 and single input implementations of the intDTT processing system of FIGS. 6C and 6E are envisaged.

[0114] More specifically, the samples of a single input signal may be split into two vectors which are processed with the dual input intDFT processing system 10’ to from two split intDFT vectors. The two split intDFT vectors are then postprocessed to form a single intDFT vector representing the intDFT of the input signal samples.

[0115] FIG. 7 A is a block diagram illustrating a processing system 30 for obtaining the intDFT vector of a single input vector (which may be complex- valued or real-valued) using a dual input intDFT processing unit 10’ as described in connection with FIGS. 3A-B. The single input signal x is provided to a single input splitting unit 31 which is configured to split the single input signal x to one odd input signal x° [n] = x[2n + 1] and one even input signal xe[n] = x[2n]. If the input signal x comprises an even number of samples, the even input signal xeand odd input signal x° comprises the same number of samples, i.e. half the number of samples of the input signal x, respectively. In FIG. 7A the input signal x comprises complex- valued samples. It is however understood that in some implementations the input signal x may comprise only real-valued samples whereby the real-valued intDFT of FIG. 4 may be applied.

[0116] Turning back to FIG. 7A, the single input splitting unit 31 obtains the samples CKof an input signal and is configured to output two vectors, an odd vector x° EK / 2carrying the odd samples of the input vector x and an even vector xeE < CK^2carrying the even samples of the input vector x.

[0117] The odd vector x° and even vector xeare now input to the dual input intDFT processing unit 10’ of FIGS. 3A-B to yield two corresponding split intDFT vectors, XeE <K 2and X° E CK / 2. The two split intDFT vectors Xeand X° are now postprocessed by processing units 32, 33, 34 configured to form an intDFT vector X corresponding to the input signal x. In general, the two half-portions of X, namely X for k = 0,1,... K / 2 — 1 and X for k =K / 2, K / 2 + 1,... K — 1, may be obtained from the two split intDFT vectors Xeand X° as

[0118] steps and multiplication with a complex factor, which also is achievable via lifting steps. Firstly, X° is provided to twiddle unit 32 which is configured to pre-multiply each sample with the i2itkcomplex factor i and then apply the twiddle factor ie k~. The output from twiddle unit 32 is provided to real rotation unit 33 alongside Xe. The real rotation unit 33 is configured to apply a real rotationcos a — sinal > [1 b] [1 01 [1 blin a cos a J 1-0 1-1 La 1-1 Lo 1-1with a = 7r / 4 to Xeand X° (after twiddling). The result of the real rotation is further scaled with 1 / 2 to yield the two half-portions of X according to equation 19 above. Finally, the single input combining stage 34 is configured to concatenate the half-portions X[k] fromequation 19 to form X[k] G CK.

[0119] FIG. 7B illustrates a block diagram of an intDTT processing system 70 for processing a single input signal and utilizing a real-valued intDFT processing system 40 (see FIG. 4). As seen, the single input processing system 30 of FIG. 7A replaces the dual input intDFT 10" of FIG. 6C. Other than this difference, the single input intDTT processing system of FIG. 7B is equivalent to the intDTT processing system of FIG. 6C.

[0120] In the single input intDTT processing system a real- valued input signal x G IRWis obtained and pre-shuffled in the pre-shuffle DTT unit 71 to form a DTT pre-shuffled input vectorXDTT, SEThe DTT pre-shuffled input vector xDTTsis provided to the pre-shuffle DFT unit 41 which is configured to shuffle the DTT pre-shuffled input vector xDTTsto form a DFT shuffled input vector xDFT sG CW / '2having half as many samples as the real-valued DTT preshuffled input vector xDTT swherein the samples of the DFT shuffled input vector xDFTsare complex-valued.

[0121] The DFT shuffled input vector xDFT sis provided to the single input split unit 31 configured to split the complex- valued DFT shuffled input vector xDFT sinto an odd input vector x° G Cw / 4and even vector xeG Cw / 4. The odd input vector x° and even input vector xeare input to the dual input intDFT processing unit 10’ to yield two corresponding split intDFT vectors, XeG (Cw / 4and X° G Cw / 4. Processing units 32 and 33 form the matrix of equation 19 above and the single input combine unit 34 is configured to concatenate X [k] and X [k +from equation 19 to form the full intDFT vector X[k],

[0122] Since the input signal in FIG. 7B is real-valued the intDFT vector is a preliminary intDFT vector which is transformed into an output intDFT vector by processing units 42, 43, 44, 45 wherein the output intDFT vector has two real- valued samples and in general N / 2 — 1 complex-valued samples. By finally processing the output intDFT vector with twiddle unit 73 and 74 the real- valued intDTT vector is generated.

[0123] Comparing the block diagram of FIG. 6C illustrating a dual input intDTT processing system 70 with the block diagram of FIG. 7B illustrating a single input intDTT processing system 70 yields that the single input intDTT processing system comprises all processing units of the dual input intDTT processing system and, additionally, split and combine processing units 31, 34, twiddle processing unit 32 and real rotation unit 33. Accordingly, the dual input intDTT processing system may be computationally more efficient compared to the single input intDTT processing system in terms of number of multiplications, lifting steps and integer rounding steps per processed signal. That is, the dual input intDTT processing system may be realized using fewer of these steps per signal than the single input intDTT processing system.

[0124] FIG. 8 is a block diagram illustrating a dual input inverse integer discrete Fourier transform (intIDFT) processing unit 20’. As described above in connection with FIGS. 3A-B the intIDFT processing unit 20’ applies the same processing as that of the dual intDFT processing unit 10’ but in reverse and with the signs of the vertical inputs to the summation points being reversed. Using the dual input intIDFT, a real-valued intIDFT may be realized by reversing the processing of FIG. 4. Similarly, a real-valued integer inverse discrete trigonometric transform (intIDTT) may be realized by reversing the processing of FIG. 6C (for dual inputs) and FIG. 7B for a single input.

[0125] FIG. 8 shows the dual input intIDFT processing unit 20’ and it is further noted that all other processing steps (e.g. real rotation, complex rotation, unitary map lifting and multiplication with a complex factor) are all invertible as well either trivially or by virtue of being expressed as lifting steps.

[0126] When operating in the inverse mode, each shuffling process or split / combine process is simply the reverse of its forward mode described above.

[0127] For example, when operating in the inverse mode, the single input split 31 of FIG.7A takes two CK / 2vectors as input and outputs a single CKvector wherein the samples of the two <K 2vectors form the odd and even samples of the single CKvector. Similarly, when operating in the inverse mode, the single input combine unit 34 of FIG. 7A takes a CKvector as input and outputs a two half-size vectors having samples k and k + K / 2 for k = 0,... K / 2 — 1 as the output.

[0128] The DTT and DFT pre- and post- shuffle operations performed in the corresponding processing units may also be inverted. For example, when the DTT post-shuffle unit 74 of FIGS. 6A-C, 6E and 7B is set to the DCT post-shuffling mode and operates in the inverse it obtains a vector with N real-valued samples and forms a vector with two real-valued samples and N / 2 — 1 complex values. More specifically, when operating in inverse DCT mode the DTT post-shuffle unit 74 takes the real- valued sample at index k = 0 and k = N / 2 of its input and forms the real-valued samples at k = 0 and k = N / 2 and the DTT post-shuffle unit 74 takes the k = 1,2,... N / 2 — 1 samples of its input as the real parts of samples k = 1,2,... N / 2 — 1 of its output and takes the last N / 2 — 1 samples in reverse order of its input as the imaginary part of samples k = 1,2,... N / 2 — 1 of its output with a negative sign.

[0129] Similarly, when operating in inverse DST mode the DTT post-shuffle unit 74 takes the real- valued sample at index k = N — 1 and k = N / 2 — 1 of its 1R / Vinput and forms the real- valued samples at k = 0 and k = N / 2 and the DTT post-shuffle unit 74 takes the k = 0,1,... N / 2 — 2 samples of its input as the imaginary part of samples k = 1,2,... N / 2 — 1 of its output with a negative sign. The DTT post-shuffle unit 74 takes the samples k = N / 2, N / 2 + 1,... N — 2 in reverse order of its input as the real part of samples k = 1,2,... N / 2 — 1 of its output.

[0130] The pre-shuffle DTT processing unit 71, when operating in the inverse DCT or inverse DST mode, performs the inverse of the shuffling procedure of equations 14 or 16.

[0131] As a further example, when the post-shuffle DFT processing unit 45 of FIG. 4 operates in the inverse mode it again reverses index address and performs conjugation. As yet another example, when the pre-shuffle DFT processing unit 41 of FIG. 4 operates in the inverse mode it takes the real part of the CN / 2vector samples and forms the even samples of thewoutput vector and takes the imaginary part of the (Cw / 2vector samples as real values to form the odd samples of the IRiwoutput vector.

[0132] Furthermore, since each real rotation is formulated using a rotation matrix factorizable into lifting steps in the forward transform, the inverse of this rotation matrix is found by obtaining the inverse of each individual lifting step. Similarly, each multiplication / scaling with a complex factor may be expressed as a rotation in the real-complex plane which also is factorizable into lifting steps which can be individually inverted to find the inverse process.

[0133] The inverse of multiplication with the complex unit i is defined as multiplication with — i. It is noted that this process is integer invertible since it in essence relates to a change of sign and a shuffling.

[0134] The person skilled in the art realizes that the present disclosure by no means is limited to the preferred embodiments described above. On the contrary, many modifications andvariations are possible within the scope of the appended claims. For example, while certain efficiency improvements are obtained for real-valued input vectors, input vectors having an even number of samples or input vectors having a number of samples being a multiple of four it is understood that the processing units and systems described may be generalized to operate on any number of samples which e.g. are complex, and / or not a multiple of two and / or four.

[0135] Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the disclosure discussions utilizing terms such as “processing”, “computing”, “calculating”, “determining”, “analyzing” or the like, refer to the action and / or processes of a computer hardware or computing system, or similar electronic computing devices, that manipulate and / or transform data represented as physical, such as electronic, quantities into other data similarly represented as physical quantities.

[0136] It should be appreciated that in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects he in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention. Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those skilled in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0137] Furthermore, some of the embodiments are described herein as a method or combination of elements of a method that can be implemented by a processor of a computer system or by other means of carrying out the function. Thus, a processor with instructions for carrying out such a method or element of a method forms a means for carrying out the method or element of a method. Note that when the method includes several elements, e.g., several steps, no ordering of such elements is implied, unless specifically stated. Furthermore, an element described herein of an apparatus embodiment is an example of a means for carrying out the function performed by the element for the purpose of carrying out the embodiments of the invention. In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details.In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0138] The person skilled in the art realizes that the present invention by no means is limited to the preferred embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims. For example, and as indicted above, the entropy encoding / decoding disclosed herein may be combined with (preceded by or succeeded by) appropriate signal transforms. Also, the division of the input signal in step SI may be more elaborate than a division into equal segments. For example, portions of the input signal with small amplitude variation may be included in a relatively larger sub-region.

[0139] Various aspects may be appreciated from the following enumerated example embodiments (EEEs):

[0140] EEE 1. A computer implemented method for generating an invertible integer discrete Fourier transform of at least one signal comprising:obtaining a first sequence of samples being associated with the at least one signal; forming a first and second input vector based on at least the first sequence of samples;processing the first and second input vector with a dual input integer discrete Fourier transform, intDFT, to form a first and second intDFT vector corresponding to the first and second input vector, wherein each intDFT vector comprises complex-valued samples, wherein said dual input intDFT is implemented using three multi-dimensional lifting steps with integer rounding, wherein each lifting step comprises performing a discrete Fourier transform or inverse discrete Fourier transform on a first lifting step input vector followed by integer rounding and addition or subtraction of the integer rounded result to or from a second lifting step input vector; andforming at least one output intDFT vector based on at least one of the first and second intDFT vectors.

[0141] EEE 2. The method according to EEE 1, wherein the dual input intDFT comprises a pre-processing stage preceding the three multi-dimensional lifting steps, wherein the preprocessing stage comprises an input complex conjugation stage that outputs the complex conjugate of the second input vector to the three multi-dimensional lifting steps.

[0142] EEE 3. The method according to EEE 1 or EEE 2, wherein the dual input intDFT comprises a post-processing stage succeeding the three multi-dimensional lifting steps, wherein the post-processing stage comprises an output complex conjugation stage that outputs thecomplex conjugate of a second output vector of the two outputs of the three multi-dimensional lifting steps.

[0143] EEE 4. The method according to EEE 3, wherein the post-processing further comprises an output negation stage that outputs the negative of the other one of the two outputs of the three multi-dimensional lifting steps.

[0144] EEE 5. The method according to any of the preceding EEEs, further comprising:converting the at least one output intDFT vector to an integer discrete trigonometric transform, intDTT, vector using a plurality of integer invertible processing steps.

[0145] EEE 6. The method according to EEE 5, wherein one of the plurality of integer invertible processing steps comprises:scaling a plurality of samples of the at least one output intDFT vector with a respective complex value.

[0146] EEE 7. The method according to EEE 6,wherein the output intDFT vector comprises N / 2 samples: andwherein scaling the plurality samples with the respective complex value comprising scaling samples k = 1, 2, 3,... N / 2-1 of the output intDFT vector with the respective complex value.

[0147] EEE 8. The method according to EEE 6 or EEE 7, wherein the respective complex value has an absolute value less than or equal to one.

[0148] EEE 9. The method according to any of EEEs 5 - 8, wherein one of the integer invertible processing steps comprises:performing DTT post-shuffling the samples of the output intDFT vector.

[0149] EEE 10. The method according to EEE 9, wherein the integer discrete trigonometric transform is an integer discrete cosine transform of type II, intDCT-II, wherein the at least one output intDFT vector comprises N / 2 samples with index k = 0, 1, 2,... N / 2 wherein samples k = 0 and k = N / 2 of the at least one output intDFT vector are real-valued samples and the remaining N / 2 - 1 samples are intermediate samples, and wherein the DTT post-shuffling comprises:concatenating the real-valued sample k = 0 sample and the real parts of the N / 2 - 1 intermediate samples and the real-valued sample k = N / 2 and the negative of the imaginary parts of the N / 2 - 1 intermediate samples taken in reverse order.

[0150] EEE 11. The method according to EEE 10, wherein forming the first and second input vectors comprises:obtaining a second sequence of samples;performing DTT pre-shuffling of the samples of the first sequence of samples and performing DTT pre-shuffling of the samples of the second sequence of samples, wherein the DTT pre-shuffling comprises:concatenating the even samples of the first / second sequence in order with the odd samples of the first / second sequence in the reverse order.

[0151] EEE 12. The method according to EEE 10, further comprising:performing DTT pre-shuffling of the samples of the first sequence of samples, the DTT pre-shuffling comprising concatenating the even samples of the first / second sequence in order with the odd samples of the first / second sequence in the reverse order; andsplitting the DTT pre-shuffled original sequence of samples into odd and even samples, wherein the even samples form the first input vector and the odd samples form the second input vector.

[0152] EEE 13. The method according to EEE 9, wherein the integer discrete trigonometric transform is an integer discrete sine transform of type II, intDST-II, wherein the at least one output intDFT comprises N / 2 samples with index k = 0, 1, 2,... N / 2 wherein samples k = 0 and k = N / 2 of the at least one output intDFT are real-valued and the remaining N / 2 - 1 are intermediate samples, and wherein the DTT post- shuffling comprises:concatenating the negative of the imaginary parts of the N / 2 - 1 intermediate samples and the real-valued sample k = N / 2 and the real parts of the N / 2 - 1 samples of the intermediate samples taken in reverse order, and the real-valued sample of k = 0.

[0153] EEE 14. The method according to EEE 9, wherein forming the first and second input vector comprises:obtaining a sequence of samples;performing DTT pre-shuffling of the samples of the first sequence of real-valued samples and performing DTT pre-shuffling of the second sequence of real-valued samples, wherein the DTT pre-shuffling comprises:concatenating the even samples of the first / second sequence in order with the negative of the odd samples of the first / second sequence in the reverse order.

[0154] EEE 15. The method according EEE 9, further comprising:performing DTT pre-shuffling of the samples of the first sequence of samples, the DTT pre-shuffling comprising concatenating the even samples of the first / second sequence in order with the negative of the odd samples of the first / second sequence in the reverse order; and splitting the DTT pre-shuffled first sequence of samples into odd and even samples, wherein the even samples form the first input vector, and the odd samples form the second input vector.

[0155] EEE 16. The method according to any of the preceding EEEs, further comprising:splitting the first sequence of samples into odd and even samples, wherein the even samples form the first input vector and the odd samples form the second input vector; and performing integer invertible processing steps on the first and second intDFT vector to form processed first and second intDFT vectors; andcombining the processed first and second intDFT vectors to form the at least one output intDFT vector.

[0156] EEE 17. The method according to any of EEEs 1 - 15, further comprising:obtaining a second sequence of samples, wherein the first sequence of real-valued samples is associated with a first signal and the second sequence of real-valued samples is associated with a second signal.

[0157] EEE 18. The method according to EEE 17, wherein the output intDFT vector is equal to the first intDFT vector.

[0158] EEE 19. The method according to EEE 20, further comprising:forming a second output intDFT vector based on the second intDFT vector.

[0159] EEE 20. The method according to any of the preceding EEEs further comprising:forming at least one preliminary output intDFT vector based on the first and / or second intDFT vectors; andpostprocessing the at least one preliminary output intDFT vector with integer invertible processing steps to form the at least one output intDFT vector.

[0160] EEE 21. The method according to EEE 20, wherein the at least one preliminary output intDFT vector comprises N / 2 complex-valued samples, andwherein the integer invertible processing steps of the postprocessing comprises at least one real rotation applied to sample k = 0 of the at least one preliminary output intDFT vector to form sample 0 and / or sample N / 2 of the at least one output intDFT vector.

[0161] EEE 22. The method according to EEE 20 or EEE 21 wherein the at least one preliminary output intDFT vector comprises N / 2 samples,wherein the integer invertible processing steps of the postprocessing comprises applying at least one complex rotation pairwise to at least one pair of samples in the range of 1 to N / 2 - 1 of the at least one preliminary output intDFT vector to form samples in the range of 1 to N / 2 - 1 in the at least one output intDFT vector.

[0162] EEE 23. The method according to EEE 22, wherein the complex rotation comprises multiplication with a complex factor and integer rounding.

[0163] EEE 24. The method according to any of EEEs 21 - 23, wherein the real rotation and / or complex rotation is normalized with a normalization factor.

[0164] EEE 25. The method according to any of EEEs 20 - 24, wherein the integer invertible processing steps of the postprocessing comprises determining sample N / 4 of the at least one output intDFT vector as the complex conjugate of sample N / 4 of the at least one preliminary output intDFT vector.

[0165] EEE 26. The method according to any of EEEs 20 - 25, further comprising:performing a DFT pre-shuffling of at least one of the first and second input vector; and wherein the integer invertible processing steps of the postprocessing further comprises:performing a DFT post-shuffling of the at least one preliminary output intDFT vector.

[0166] EEE 27. The method according to EEE 26, wherein the DFT pre-shuffling comprises combining the even and odd samples as real and imaginary parts, respectively, of the at least one of the first and second input vectors to form a complex-valued vector with half as many elements.

[0167] EEE 28. The method according to EEE 26 or 27, the DFT post-shuffling comprises reversing addresses and conjugating.

[0168] EEE 29. The method according to any of the preceding EEEs, wherein the at least one signal is a biomedical signal.

[0169] EEE 30. The method according to EEE 29, wherein the biomedical signal is an electrocardiogram, ECG, an electroencephalogram, EEG, or an electromyogram, EMG.

[0170] EEE 31. The method according to any of the preceding EEEs, further comprising:encoding the intDFT vector and / or intDTT vector with entropy code to form an encoded intDFT vector and / or encoded intDTT vector; andfomring a bitstream based on the encoded intDFT vector and / or intDTT vector.

[0171] EEE 32. The method according to any of the preceding EEEs, wherein the discrete Fourier transform or inverse discrete Fourier transform is a fixed-point implementation.

[0172] EEE 33. A computer implemented method for generating at least one signal from at least one invertible integer discrete Fourier transform vector comprising:obtaining at least one sequence of input intDFT samples;forming a first and second input intDFT vector based on the at least one sequence of input intDFT samples;processing the first and second input intDFT vectors with a dual input inverse integer discrete Fourier transform, intIDFT, to form a first and second intIDFT vector corresponding to the first and second input intDFT vector, wherein each intIDFT vector comprises complex-valued samples, wherein said dual input intIDFT is implemented using three multi-dimensional lifting steps with integer rounding, wherein each lifting step comprises performing a discrete Fourier transform or inverse discrete Fourier transform on a first lifting step input vector followed by integer rounding and addition or subtraction of the integer rounded result to or from a second lifting step input vector;forming at least one output sequence of samples based on the first and second intIDFT vector.

[0173] EEE 34. A computer program product comprising instructions which, when the program is executed by a computer, causes the computer to carry out the method according to any of the preceding EEEs.

[0174] EEE 35. A computer-readable storage medium storing the computer program according to EEE 34.

[0175] EEE 36. An encoder comprising a processor and memory, wherein the processor is configured to perform the method according to any of EEEs 1 - 32.

[0176] EEE 37. A decoder comprising a processor and memory, wherein the processor is configured to perform the method according to EEE 33.

Claims

CLAIMS1. A computer implemented method for generating an invertible integer discrete Fourier transform of at least one signal comprising:obtaining a first sequence of samples being associated with the at least one signal; forming a first and second input vector based on at least the first sequence of samples; processing the first and second input vector with a dual input integer discrete Fourier transform, intDFT, to form a first and second intDFT vector corresponding to the first and second input vector, wherein each intDFT vector comprises complex-valued samples, wherein said dual input intDFT is implemented using three multi-dimensional lifting steps with integer rounding, wherein each lifting step comprises performing a discrete Fourier transform or inverse discrete Fourier transform on a first lifting step input vector followed by integer rounding and addition or subtraction of the integer rounded result to or from a second lifting step input vector; andforming at least one output intDFT vector based on at least one of the first and second intDFT vectors.

2. The method according to claim 1, wherein the dual input intDFT comprises a pre-processing stage preceding the three multi-dimensional lifting steps and / or a post-processing stage succeeding the three multi-dimensional lifting steps,wherein the pre-processing stage comprises an input complex conjugation stage that outputs the complex conjugate of the second input vector to the three multi-dimensional lifting steps, andwherein the post-processing stage comprises an output complex conjugation stage that outputs the complex conjugate of a second output vector of the two outputs of the three multidimensional lifting steps.

3. The method according to any of the preceding claims, further comprising:converting the at least one output intDFT vector to an integer discrete trigonometric transform, intDTT, vector using a plurality of integer invertible processing steps.

4. The method according to claim 3, wherein one of the plurality of integer invertible processing steps comprises:scaling a plurality of samples of the at least one output intDFT vector with a respective complex value.

5. The method according to claim 4, wherein one of the integer invertible processing steps comprises:performing DTT post-shuffling the samples of the output intDFT vector.

6. The method according to claim 5, wherein the integer discrete trigonometric transform is an integer discrete cosine transform of type II, intDCT-II, wherein the at least one output intDFT vector comprises N / 2 samples with index k = 0, 1, 2,... N / 2 wherein samples k = 0 and k = N / 2 of the at least one output intDFT vector are real-valued samples and the remaining N / 2 - 1 samples are intermediate samples, and wherein the DTT post-shuffling comprises:concatenating the real-valued sample k = 0 sample and the real parts of the N / 2 - 1 intermediate samples and the real-valued sample k = N / 2 and the negative of the imaginary parts of the N / 2 - 1 intermediate samples taken in reverse order.

7. The method according to claim 5, wherein the integer discrete trigonometric transform is an integer discrete sine transform of type II, intDST-II, wherein the at least one output intDFT comprises N / 2 samples with index k = 0, 1, 2,... N / 2 wherein samples k = 0 and k = N / 2 of the at least one output intDFT are real-valued and the remaining N / 2 - 1 are intermediate samples, and wherein the DTT post- shuffling comprises:concatenating the negative of the imaginary parts of the N / 2 - 1 intermediate samples and the real-valued sample k = N / 2 and the real parts of the N / 2 - 1 intermediate samples taken in reverse order, and the real-valued sample of k = 0.

8. The method according to any of the preceding claims, further comprising:splitting the first sequence of samples into odd and even samples, wherein the even samples form the first input vector and the odd samples form the second input vector; and performing integer invertible processing steps on the first and second intDFT vector to form processed first and second intDFT vectors; andcombining the processed first and second intDFT vectors to form the at least one output intDFT vector.

9. The method according to any of claims 1 - 7, further comprising:obtaining a second sequence of samples, wherein the first sequence of real- valued samples is associated with a first signal and the second sequence of real-valued samples is associated with a second signal.

10. The method according to any of the preceding claims further comprising:forming at least one preliminary output intDFT vector based on the first and / or second intDFT vectors; andpostprocessing the at least one preliminary output intDFT vector with integer invertible processing steps to form the at least one output intDFT vector.

11. The method according to claim 10, wherein the at least one preliminary output intDFT vector comprises N / 2 complex-valued samples, andwherein the integer invertible processing steps of the postprocessing comprises at least one of:applying a real rotation to sample k = 0 of the at least one preliminary output intDFT vector to form sample 0 and / or sample N / 2 of the at least one output intDFT vector, and applying at least one complex rotation pairwise to at least one pair of samples in the range of 1 to N / 2 - 1 of the at least one preliminary output intDFT vector to form samples in the range of 1 to N / 2 - 1 in the at least one output intDFT vector.

12. The method according to claim 11, wherein the real rotation and / or complex rotation is normalized with a normalization factor.

13. The method according to any of the preceding claims, wherein the at least one signal is a biomedical signal.

14. The method according to any of the preceding claims, further comprising:encoding the intDFT vector and / or intDTT vector with entropy code to form an encoded intDFT vector and / or encoded intDTT vector; andforming a bitstream based on the encoded intDFT vector and / or intDTT vector.

15. A computer implemented method for generating at least one signal from at least one invertible integer discrete Fourier transform vector comprising:obtaining at least one sequence of input intDFT samples;forming a first and second input intDFT vector based on the at least one sequence of input intDFT samples;processing the first and second input intDFT vectors with a dual input inverse integer discrete Fourier transform, intIDFT, to form a first and second intIDFT vector corresponding to the first and second input intDFT vector, wherein each intIDFT vector comprises complex-valued samples, wherein said dual input intIDFT is implemented using three multi-dimensional lifting steps with integer rounding, wherein each lifting step comprises performing a discrete Fourier transform or inverse discrete Fourier transform on a first lifting step input vector followed by integer rounding and addition or subtraction of the integer rounded result to or from a second lifting step input vector;forming at least one output sequence of samples based on the first and second intIDFT vector.

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