Subtractive microfluidics in complementary metal oxide semiconductors

Abstract

A microfluidic device includes a complementary metal oxide semiconductor (CMOS) device comprising a substrate, a transistor layer, routing layers, and etchable metal layers, and a functional microfluidic layer having one or more channels formed after removal of at least a portion of one or more of the etchable metal layers. A method of forming a microfluidic layer includes forming a complementary metal oxide semiconductor (CMOS) device having one or more etchable metal layers, etching at least one of the etchable metal layers to remove at least one of the etchable metal layers, and forming a functional microfluidic device having one or more channels in regions in which the at least one etchable metal layer has been etched.

Description

Patent Application U Cal No. BK-2025-041-2 MN No. 407869-0224SUBTRACTIVE MICROFLUIDICS IN COMPLEMENTARY METAL OXIDE SEMICONDUCTORSTECHNICAL FIELD

[0001] This disclosure relates to integrating complementary metal-oxide semiconductor (CMOS) technology with microfluidics, more particularly to integrating subtractive microfluidics.BACKGROUND

[0002] Integrating microelectronics with microfluidics, especially those implemented in silicon-based CMOS technology, has driven the next generation of in vitro diagnostics. This CMOS / microfluidics platform offers close interfaces between electronics and biological samples and tight integration of readout circuits with multi-channel microfluidics, both of which are crucial factors in achieving enhanced sensitivity and detection throughput. Importantly, conventionally bulky benchtop instruments are now being transformed into millimeter-sized form factors at low cost, making the deployment for Point-of-Care (PoC) applications feasible.

[0003] Conventional CMOS / microfluidics integration has typically followed a “modular” approach, where the CMOS electronics package and the microfluidics are prepared separately and then attached through in-house assembly. One may think of this as an additive manufacturing approach. However, such an approach suffers from significant misalignment between the microfluidics and the sensing transducers on the chip, especially when the transducer sizes are reduced or the microfluidic channel width shrinks. The full potential of CMOS parallel readout has not been fully realized.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIGs. 1A-1B show a diagram of an embodiment of a CMOS subtractive microfluidics process.

[0005] FIGs. 2A-2C show an embodiment of a CMOS subtractive microfluidics process.

[0006] FIGs. 3 A-3B show embodiments of fluidic structures before and after removal of a metal layer.

[0007] FIG. 4 shows an embodiment of an assembly flow.

[0008] FIGs. 5A-5B show embodiments of a subtractive fluidics process with integrated sensors.

[0009] FIGs. 6A-6D show graphs of measurements of different parameters for embodiments of a CMOS subtractive microfluidics.

[0010] FIGs. 7A-7B show embodiments of a Hall sensor.

[0011] FIG. 8 shows a graph of measured Hall sensor responses.

[0012] FIG. 9 shows an embodiment of a CMOS subtractive microfluidics device with integrated impedance readout.

[0013] FIG. 10 shows a schematic of an embodiment of an amplifier in a transimpedance amplifier.

[0014] FIG. 11 shows a graphic of impedance sensing of saline buffers at different ionic strengths.

[0015] FIG. 12 shows a process flow for an alternative embodiment of an electrode configuration.

[0016] FIG. 13 shows an embodiment of a microfluidic device with ionic current flow.

[0017] FIGs. 14A-14B show embodiments of microfluidic devices using single-photo avalanche diodes (SPADs).

[0018] FIGs. 15A-15C show embodiments of devices using SPADs.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The embodiments herein comprise a microfluidics platform embedded within a silicon chip implemented in CMOS technology. The platform utilizes a one-step wet etching method to create fluidic channels by selectively removing CMOS back-end-of-line (BEOL) routing metals. The discussion here refers to this as "subtractive" microfluidics, to complement those fabricated with additive manufacturing.

[0020] The embodiments include many types of structures. The discussion here includes three exemplary structures. There structures provide examples of both an 180-nm CMOS, and a 65-nm CMOS chip, with the understanding that the embodiments apply to all types of CMOS technology. The exemplary structures include passive microfluidics in the form of amicro-mixer and a 1 :64 splitter, fluidic channels with embedded ion-sensitive field-effect transistors (ISFETs) and Hall sensors, single-photon avalanche diodes (SPADs), integrated on-chip impedance-sensing readout circuits including voltage drivers and a fully differential transimpedance amplifier (TIA). Sensors and transistors are functional pre- and post-etching with minimal changes in performance. The CMOS subtractive microfluidics technique of the embodiments enables tight integration of fluidics and electronics, paving the way for future small-size, high-throughput lab-on-chip (LOC) devices.

[0021] The embodiments involve a novel CMOS / microfluidics system utilizing "subtractive" manufacturing. The embodiments use the metal routings from the standard back-end-of-line (BEOL) in the CMOS process as a sacrificial layer for the microfluidic channel after wetetching-based removal, as shown FIG. 1 A. The left side of FIG. 1 A shows a transistor layer 10 of a substrate with the completed metal layers including the final metal layer 12. After a wet etch, the metal layer 12 has been removed and replaced with a microfluidic channel structure 14.

[0022] FIG. IB shows a comparison between traditional CMOS manufacturing, with the metal layers Ml through M6. This device would then have the microfluidics module attached. This method allows for direct and tight integration of fluidic channels with readout and control circuits, mitigating the aforementioned misalignment issues. By taking advantage of the fine-line lithography in CMOS foundries, the embodiments easily promote high channel counts and enable direct scaling of the microfluidics geometry toward sub-micron levels. The devices mentioned above rely upon the base device of a substrate with a transistor layer, routing layers, passivation layer 18, and then microfluidic channels 16 in place of at least a portion of the M6, referred to here as the outer, metal layer.

[0023] Etching the metallization in CMOS to form fluidic channels with acidic etchants is a non-trivial process. The etch rate can be significantly reduced due to diffusion limits, especially when there are only two access ports: the inlet and the outlet. Previously approaches leveraged hydraulic pressure to promote turbulence and enhancing diffusion rates, which sped up the etch rate by ten times, as disclosed in Weng, W.-Y., and Chien, J - C.: ‘Impedance Sensing in CMOS-Embedded Microfluidics Using BEOL Electrodes’, Journal of Microelectromechanical Systems, 2024, 33, (1), pp. 110-117, “Weng, et al.” However, for complex microfluidic structures, such as meander micro-mixers and fluidic splitters at high splitting ratios (N > 16), complete removal is nearly impossible, even withmultiple days of incubation in the etchant at elevated temperatures. The embodiments herein solve the issue by adding small “pad openings” along the fluidic channels to introduce more access ports as shown in FIGs. 2A-2B.

[0024] FIG. 2A shows a perspective view of the structure 20 prior to the sealing layer. The side view along line A-B shows the unetched metal layer 22, the passivation layer 24, and the pad openings such as 26. As shown in FIG. 2B, the side view along line A’-B’ from the upper diagram shows the sealing layer 28. The metal layer 24 has been replaced with fluidic channel 29. In one embodiment, the sealing layer comprises a PDMS (poly dimethyl siloxane) slab. To prevent fluid leakage from these ports, the process of the embodiments further seals these openings using PDMS microfluidics in the final system assembly as discussed below. The extra openings can create pockets to trap air. Application of hydraulic pressure causes these bubbles so dissolve into the sealing layer. In one embodiment, the process involves applying hydraulic pressure for 15 minutes.

[0025] The approaches of the embodiments, embedding fluidic channels directly within a CMOS chip by selectively removing back-end metal routing offers a superior dimensional control and alignment precision. This result is achieved with a single-step post-CMOS wetetch. The process is simple, requires no complex post-processing, and can realize 3D fluidic networks by leveraging multilayer metallization. Prior work, reference [1] cited below, demonstrated subtractive microfluidics with several -pm -wide channels. The embodiments here achieve, for the first time, the creation of 100-nm-wide, 220-nm-tall nanofluidic channels, as well as vertical channels using 360-nm * 360-nm-sized vias, without altering transistor I-V characteristics after 4 days of etchant immersion. FIG. 2C shows a channel with a 100-nm wide channel 30 having a length of 50 pm 31. This capability was demonstrated in a TSMC 65-nm process with a copper-based BEOL and opens new opportunities for highly sensitive nanofluidic-based biosensing.

[0026] FIGs. 3A-3B shows examples of successfully etched micro-mixer and 1 :64 fluidic splitter designed in 180-nm CMOS with successful function demonstration. FIG. 3 A shows a micromixer structure before and after etching in the left and middle panels. The structure includes the micromixer 32 at the outlet, and two inlet structures 33 and 34. The right panel shows two different dyes in regions 36 and 38 at the inlets and the mixed dyes at region 40. In an experiment, blue dye was used in region 36 and yellow dye was used in region 38, so the resulting mixing formed green dye.

[0027] FIG. 3B shows a microfluidic 1 :64 splitter, with a magnified region showing the pad opening at 42. The center panel shows the splitter after etching 44, and the right panel shows beads such as 46 traversing the splitter.

[0028] FIG. 4 shows an embodiment of the process flow. A CMOS chip 50 is embedded within a printed circuit board (PCB) 52 using a water-resistant adhesive 54 to level the PCB surface. The adhesive 54, such as an epoxy, also protects the wire bonds 56 that provide electrical access. An elastic, microfluidic structure 58, such as PDMS, delivers the etchant and heated with a heating resistor 60 mounted to the backside of the PCB. An acrylic or other material board 62 applies hydraulic pressure through fasteners such as screws 64. This promotes etchant diffusion.

[0029] In one experiment, the process removed the metallization from 27 different-designed fluidic structures at varying metal layer in four days. The 1 :64 splitter similar to the one mentioned above but in 65-nm CMOS took longer because of the long, complex routing. Due to the longer etch times, the inventors characterized the transistor I-V properties throughout the etching process. The inventors used a trans=impedance amplifier (TIA) to continuously monitor transistor drain currents.

[0030] The experiment involved two approaches to determine the complete removal of the 100-nm-width fluidics. First, the inventors utilized a 3D scanning laser microscope and integrated the reflected laser (1 = 405 nm) intensity 1 pm above and below the target metal layer. Residue metal reflects brightly in the image in contrast to hollow fluidic channels and can achieve spatial resolution equal or less than the laser wavelength. Next, the inventors verified the fluidic passage by monitoring green dye flowing through the channel. Vertical fluidics are also successfully implemented by etching away vias connecting metal layers M8 and M9.

[0031] The experiment included measuring the transistor IDS-VGS characteristics of thin- oxide NMOS and PMOS, and thick-oxide PMOS. The changes across four days were found to be 0.3%, 1.9%, and 0.5%, respectively, which are within measurement precision. This leads to the conclusion that prolonged etching does not impact transistor performance. Table I provides a comparison to other prior works. In the table, the references are: [1] W.-Y. Weng, A. Di, X. Zhang, Y.-C. Tsai, Y.-T. Hsiao, and J.-C. Chien, IEDM2024, pp. 1-4; [2] W.-Y. Weng, H.-Y. Hou, Y.-J. Chao, S.-J. Liaw, and J.-C. Chien, MEMS 2023, pp. 558-561; [3] H. Meng, MIT Thesis, (2018), pp. 1-226; AndTable I. Comparisons to prior work

[0032] The microfluidic structures use sensors in the processing and analysis of the various fluids in the structures. One embodiment employs ISFETs, shown in FIG. 5 with an equivalent schematic and side view. The embodiment shown employs two ISFETs 70 and72 in one fluidic channel 74. Each ISFET is connected to its own sensing channel 76 and 78. The bottom side view of the structure shows channel 74, passivation layer 80, the metal layer MX, where the X is whatever metal layer is being used, sensing area 82. The two sensing areas 80 and 82 connected to the ISFETs may have different sensing areas.

[0033] In one embodiment, the ISFETs are implemented using thick-oxide NMOS transistors with a W / L ratio of lpm / 350 nm. Their gates are extended to a metal layer MX, in this example M5, which is isolated from the fluidic channel layout in M6 using the default 1-prn thick oxide from the foundry. This dielectric layer also serves as a charge-sensing membrane. One embodiment defines the sensor area by the area of M5. One embodiment implements two ISFETs in the same fluidic channel. One embodiment has M5 areas of 6 pm x 12 pm and 6 pm x 24 pm, respectively. This area difference results in different coupling capacitances and, consequently, different attenuation factors formed by the capacitive dividers, as represented by the equivalent schematic in FIG 5.

[0034] Analysis shows a worst-case attenuation factor of 0.55 x compared to the ideal Nemst equation when sensing pH (59mV / pH sensitivity). The ISFETs' drain currents were measured with the off-chip transimpedance amplifier (TIA) mentioned above. The gate voltage was provided by electrode 88 in direct contact with the ionic solutions. In one embodiment theelectrode is platinum (Pt). The Pt potential is pulsed between 0 and 3 V at 0.2 Hz to minimize the drifts through periodic resets. The nominal drain bias is set to 1.0V.

[0035] FIGs. 6A-6D shows the measurement results of microfluidics-embedded ISFETs at different pH levels from 4 to 10 using standard solutions from Hanna Instruments (HI5710- 11PB). Two ISFETs were measured simultaneously, and their sensitivities compared. The ISFET with a 2* larger M5 area demonstrated a 1.2x increase in sensitivity. Drift is indeed observed, as shown in FIG. 6C, but can be effectively canceled by performing a differential operation using a pair of ISFETs formed with NMOS and PMOS. FIG. 6D shows the power spectral density (PSD) of the current noise at ISFET output. Measurements of the embodiments show a flicker noise comer of 30 kHz, a combined contribution from both ISFETs and chemical noise.

[0036] Some embodiments may employ Hall sensors. FIG. 7 A shows embodiments of Hall sensors implemented using N-well resistors, in this embodiment having a width of 5 pm. Two different layout styles are implemented for study purposes, shown in FIG. 7A, with a first layout being shown at 90, and the other at 92, each having their own sensing channel 96 and 98. The sensing areas are implemented in one of the lower metal layers 94. In one embodiment, to maximize sensitivity, the microfluidics for the Hall sensors are implemented in the lower M2 instead of M6. Note that the etching technique of the embodiments can remove metal down to Ml, as shown in FIG. 7B. While this embodiment refers to M2, the sensors may be implemented in any metal layer. The dimension shown under each metal layer are shown as examples not intended to imply that the metal layers are required to have specific dimensions.

[0037] In one embodiment, the Hall sensors were biased at 1.0V and the Hall voltages are measured using instrumentation amplifiers 100 and 102 at a gain of 1000 V / V, followed by oscilloscope captures. A thin on-chip M2 wire was routed in proximity to the Hall sensor to electromagnetically modulate the magnetic fields locally for sensor calibration. The fluidic channel was located in M2 having a thickness = 0.53 pm in the embodiment, the device requires the longest time to complete metal removal (> 3 days).

[0038] FIG. 8 shows the Hall sensors responses to different magnetic fields (0 ~ 5mT, generated by running DC currents in the on-chip routing in proximity to the Hall sensors) before and after metal etching. Consistent sensitivity is observed, but the etching process appears to introduce extra offset voltages. Fortunately, this offset voltage can be compensatedthrough circuit techniques such as correlated double sampling (CDS). The successful embedding of Hall sensors opens the way for flow cytometry using magnetic beads or nanoparticles as labels.

[0039] FIG. 9 shows the schematic of the fully-differential impedance readout circuits, a perspective view of the device, and a cross section along line A-B. The unique aspect of the design of the embodiments is the use of “vias” such as 104 between M5 and M6 to form liquid-interfacing electrodes, exposed by removing the M6 fluidic channel. The inventors have demonstrated in Weng, et. al., that these via electrodes can achieve more stable recording compared with Ag / AgCl pseudo reference electrodes. To avoid over-etching, the process monitors the electrode impedance in real-time with the on-chip impedance-sensing circuit and stop the etching once an “open” circuit is observed from the readout. Slight overetching is inevitable, yet measurements indicate that the electrode stability can still be maintained.

[0040] Other circuits in the signal chain 105 include two unity-gain buffers, in one embodiment delivering a differential sinusoidal drive of 0.4 Vpp at 100 kHz to the electrodes and a resistive-feedback TIA with a current-reuse cascode amplifier shown in FIG. 10, with common mode feedback (CMFB). The TIA consumes 0.4 mA from a 1.8-V supply and has a bandwidth of 1.2 MHz, set by the R (= 1 MQ) and C (= 133 fF) in the feedback network. The measured input-referred noise current is 0.15 pA / ^Hz. The buffer employs a two-stage architecture to maximize the voltage swing while consuming 0.25 mA of current each. The output is oversampled and demodulated off-chip numerically in Matlab.

[0041] FIG. 1 Ishows a plot of the measured impedances (|Z|@100kHz|) of saline buffers at different ionic strengths (from l x to 5x). The results are repeatable across two additional devices, verifying functional circuits post-etching. The measurements indicate higher noise at high ionic strengths, showing that the major noise source in the system could be the chemical noise at the liquid-solid interface. Future applications include rapid detection of single bacteria cells in flow.

[0042] Variations and modifications to the structures and methods of the embodiments. FIG. 12 and FIG. 13 show an alternative embodiment of electrodes used for impedance sensing. FIG. 12 provides an illustrative processing flow. First, the backend-of-line (BEOL) metal routings are utilized to define the fluidic channel 106. Then one or more, more than likely two, additional metal pads are positioned adjacent to the microfluidic inlet and outlet. Thesemetal pads will be serving as the electrodes and are directly connected to the impedancesensing circuitry. To protect the “electrode pads” prior to etching, a temporary passivation layer is applied. As shown in the middle of the figure, Kapton tape 116 is shaped and applied as a protective mask. The CMOS chip is then submerged in an acidic solution to selectively remove metal, thereby creating the hollow fluidic channel. Following etching, the Kapton tape is removed, and the device 118 is packaged and wire-bonded to a printed circuit board (PCB) for integration, as detailed previously.

[0043] A PDMS microfluidic structure, specifically patterned using a mold fabricated using SU-8 photoresist to ensure the ionic solution will flow over these two “electrode pads,” is then aligned with the CMOS chip to facilitate sample delivery, shown in FIG. 13.

[0044] This configuration ensures that the electrical signals, injected through Vstimuius, in the form of ionic currents, are transmitted through the fluids and detected by the transimpedance amplifier (TIA) receiver show at the other end of the channel. From the measured current, real-time changes in the impedance are extracted. The Vstimuius can be a DC voltage or an AC voltage with frequency ranging from 1 kHz ~ 100+ MHz at an amplitude ranging from lOmV to IV.

[0045] In another variation, the device may integrate photodiodes positioned beneath, or otherwise adjacent, the fluidic channels.

[0046] SPAD-based fluorescence lifetime detection offers highly sensitive optical readout and is an attractive modality for point-of-care diagnostics. Conventional microfluidic assemblies rely on overlaying a single fluidic channel, usually hundreds of pm wide, on top of a SPAD-array as shown in FIG. 14 A.

[0047] Recent efforts have explored forming fluidic channels within CMOS dies. For instance, one approach used a combined RIE / XeF? etch to remove polysilicon in the lowest routing layer, reducing the sample-to-APD (avalanche photodiode) distance. The same process was also used to etch channels above SPADs, but fluidic flow and functional testing were not demonstrated. The embodiments here employ the subtractive microfluidics concept to define channels directly above SPADs fabricated through an 180-nm CMOS process. The channels are lithographically defined by metal-layer layout, ensuring nanometer precision. Fabrication required only a single-step wet etch and completes within 24 hours.

[0048] FIG. 14B shows a structure in accordance with the embodiments, where the inlets such as 120 and outlets such as 122 feed into etched microchannels such as 124. This brings the solution much closer to the SPADs such as 126, making for a more accurate reading. This arrangement of the etched channels being much closer is referred to here as the channels being directly adjacent the photodiodes. By pulsing laser excitation light from above the chip for short durations, fluorescence emissions from fluorescent beads or fluorophores in flow are captured by the underlying SPADs. This versatile optofluidic platform is well-suited for various applications, including chip-scale flow cytometry. Importantly, each fluidic channel is aligned to a dedicated SP D or SP D array, enabling parallelized microfluidics. As far as the inventors know, this represents the first demonstration of CMOS subtractive microfluidics integrated with SPAD sensors.

[0049] In an embodiment, the SPADs are operated in Geiger mode. A single photon triggers avalanche breakdown, generating a current pulse, which is amplified and then digitized through pulse counting. The time delay between a laser excitation pulse and a photon detection event is used to construct a time-correlated single photon counting (TCSPC) histogram, which is analyzed to extract the fluorescence lifetime (Fig. 4). We designed and tested three types of SPADs with active-area diameters of 24, 9, and 4 pm. The 6 pm-wide, 4.6 pm-tall fluidic channels are implemented in the M6 layer above the SPAD devices. The SPADs can be distributed along a single fluidic channel to enable repeated measurements with analyte in flow and can be distributed along parallel channels for throughput enhancement. Additionally, angle sensitive gratings can be used to improve signal purity and reduce crosstalk between neighboring fluidic channels. Positioning the analyte directly above the SPADs enhanced the local collection efficiency. The wet-etching process of the embodiments can remove lower metal layers (e.g., Ml)to further minimize the fluorophore- detector distance to within 1 pm.

[0050] In an experiment, the M6 aluminum traces were removed using ammonium persulfate at 90 °C for 24 hours. A photon-counting setup was designed to characterize the devices. The SPADs were illuminated using a gain-switched pulsed laser (1 = 405 nm, Pout = 10 mW, a 10-MHz repetition rate, and 4-ns pulse width). The laser was positioned a few centimeters above the chip, which was wirebonded to a PCB. Outputs were routed to a transimpedance amplifier (TIA) for signal amplification and digitized via photon counting using an FPGA- based instrument. The experiment demonstrated simultaneous measurements from two SPADs located under separate fluidic channels. When tested with 50 nM Qdot 605 quantumdots (QDs), the occupied channel exhibited an increase in fluorescence lifetime, while the adjacent channel remained unchanged.

[0051] FIG. 15A shows a cross-section of a SPAD embodiment, and FIG. 15B shows the doping layers. The SPADs are formed out of n+material such as 132, and p+material such as 130. The structure has n-wells (NW) such as 140 and p-wells (PW) such as 138, separated using shallow trench isolation 134, and a deep n-well (DNW) 136. The corresponding shading applies in the doping structure show in FIG. 15B and FIG. 15C.

[0052] The embodiments provide a subtractive microfluidics concept in CMOS technology. They leverage the fine-line lithography capabilities offered by the semiconductor foundries and a single-step wet-etching process and embed microfluidic channels within a silicon chip in close proximity to the sensing electronics. This showcases the potential for tightly integrated, high-performance lab-on-chip devices.

[0053] All features disclosed in the specification, including the claims, abstract, and drawings, and all the steps in any method or process disclosed, may be combined in any combination, except combinations where at least some of such features and / or steps are mutually exclusive. Each feature disclosed in the specification, including the claims, abstract, and drawings, can be replaced by alternative features serving the same, equivalent, or similar purpose, unless expressly stated otherwise.

[0054] Additionally, this written description makes reference to particular features. It is to be understood that the disclosure in this specification includes all possible combinations of those particular features. For example, where a particular feature is disclosed in the context of a particular aspect, that feature can also be used, to the extent possible, in the context of other aspects.

[0055] Also, when reference is made in this application to a method having two or more defined steps or operations, the defined steps or operations can be carried out in any order or simultaneously, unless the context excludes those possibilities.

[0056] Although specific aspects of this disclosure have been illustrated and described for purposes of illustration, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited except as by the appended claims.

Claims

CLAIMS:

1. A microfluidic device, comprising: a complementary metal oxide semiconductor (CMOS) device comprising a substrate, a transistor layer, routing layers, and etchable metal layers; and a functional microfluidic layer having one or more channels residing on a region formed from removal of at least a portion of one or more of the etchable metal layers.

2. The microfluidic device as claimed in claim 1, wherein the functional microfluidic layer forms at least one of a microfluidic micro-mixer and a microfluidic splitter.

3. The microfluidic device as claimed in claim 1, wherein the functional microfluidic layer forms a Hall sensor.

4. The microfluidic device as claimed in claim 1, wherein the functional microfluidic layer comprises impedance-sensing circuitry and readout circuits.

5. The microfluidic device as claimed in claim 4, wherein the impedance-sensing circuitry comprises one or more additional pads positioned adjacent at least one of an inlet and an outlet of one of the one or more channels in the microfluidic layer, one or more of the additional pads being electrically connected to the impedance-sensing circuitry.

6. The microfluidic device as claimed in claim 4, wherein the impedance-sensing circuitry comprises a transimpedance amplifier at one end of the one channel.

7. The microfluidic device as claimed in claim 1, further comprising one or more photodiodes positioned adjacent to one of the one or more channels in the microfluidic layer, wherein the channels in the microfluidic layer are etched into the microfluidic layer to cause the one channel to reside directly adjacent the photodiodes.

8. The microfluidic device as claimed in claim 7, wherein the photodiodes comprise single-photon avalanche photodiodes.

9. The microfluidic device as claimed in claim 1, wherein at least one channel has a width of 100 nanometers.

10. A method of forming a microfluidic layer, comprising: forming a complementary metal oxide semiconductor (CMOS) device having one or more etchable metal layers; etching at least one of the one or more etchable metal layers to remove at least a portion of one of the etchable metal layers; and forming a functional microfluidic device having one or more fluidic channels in a region where the one or more etchable metal layers have been etched.

11. The method as claimed in claim 10, wherein etching the one or more etchable metal layers comprises forming pad openings along channels of the functional microfluidic device, and sealing the pad openings.

12. The method as claimed in claim 10, wherein etching at least one of the etchable metal layers comprises heating an etchant used for the etching using at least one on-device electronic heater.

13. The method as claimed in claim 10, further comprising embedding ion-sensitive field effect transistors near the fluidic channels.

14. The method as claimed in claim 10, wherein etching the at least one of the etchable metal layers comprises etching several etchable metal layers and locating functional microfluidic channels in a last metal layer etched.

15. The method as claimed in claim 14, wherein the functional microfluidic channels comprise part of a Hall sensor.

16. The method as claimed in claim 10, wherein the functional microfluidic device comprises impedance readout circuits, and the method further comprises forming liquidinterfacing electrodes by forming via electrodes between two of the etchable metal layers.

17. The method as claimed in claim 16, wherein forming liquid-interfacing electrodes comprises: forming one or more electrodes in a region corresponding to a location where an inlet and an outlet of the one or more channels will be formed; and passivating the one or more electrodes prior to etching at least one of the etchable layers with a passivation layer; and removing the passivation layer after the etching.

18. The method as claimed in claim 10, further comprising positioning one or more photodiodes adjacent the one or more channels, and etching the one or more channel into a substrate of the microfluidic device to position the one or more channels directly adjacent the photodiodes.

19. The method as claimed in claim 10, wherein etching at least one of the etchable metal layers to remove at least a portion of one of the etchable metal layers comprises etching at least one of the metal layers to form a channel having a width of 100 nanometers.

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