Computing task processing method for electronic device, and electronic device and apparatus, and medium

Abstract

Provided in some embodiments of the present disclosure are a computing task processing method for an electronic device, and an electronic device and apparatus, and a medium. On the basis of the embodiments of the present disclosure, the electronic device comprises a plurality of processing units performing parallel computing. The method comprises: for a computing task of parallel computing by a plurality of processing units, according to the plurality of processing units, dividing threads comprised in the computing task, and providing thread information to the plurality of processing units; and on the basis of the provided thread information, processing the threads of the computing task by using the plurality of processing units.

Description

Computational task processing methods for electronic devices, electronic devices, apparatuses and media Technical Field

[0001] Embodiments of this disclosure relate to a computing task processing method for an electronic device, an electronic device, an apparatus, and a medium. Background Technology

[0002] With the development of general-purpose computing scenarios, higher demands are being placed on the computing power, processing efficiency, and bandwidth of electronic devices. How to achieve hardware-software co-design for electronic devices and provide high-performance devices has become an important research direction. For example, for computationally intensive tasks, multiple processors are typically required for parallel computing to improve efficiency.

[0003] Summary of the Invention

[0004] Some embodiments of this disclosure provide a computing task processing method, electronic device, apparatus, and medium for an electronic device, which can divide a computing task into multiple processing units, enabling the processing units to perform parallel computing according to the provided thread information, thereby assigning specific processing units to threads in the computing task, assisting the hardware in making more reasonable task division, and improving processing efficiency.

[0005] According to a first aspect of the present disclosure, a method for processing computing tasks in an electronic device is provided, wherein the electronic device includes multiple processing units performing parallel computing. The method includes: for a computing task performed in parallel by the multiple processing units, dividing the threads included in the computing task into multiple processing units and providing thread information to the multiple processing units; and using the multiple processing units to process the threads of the computing task according to the provided thread information.

[0006] According to a second aspect of the present disclosure, an electronic device is provided, including a scheduler and a plurality of processing units for performing parallel computing, wherein the scheduler is configured to: for a computing task performed in parallel by the plurality of processing units, divide the threads included in the computing task into the plurality of processing units and provide thread information to the plurality of processing units; and the plurality of processing units are configured to: process the threads of the computing task according to the provided thread information.

[0007] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processing device; and a storage device configured to store one or more programs, wherein when the one or more programs are executed by the processing device, the processing device causes the processing device to perform the computational task processing method as described above.

[0008] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the computational task processing method as described above. Attached Figure Description

[0009] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0010] Figure 1 shows a schematic diagram of the hierarchical thread organization structure of computing tasks in related technologies;

[0011] Figure 2 shows a schematic flowchart of a computing task processing method according to an embodiment of the present disclosure;

[0012] Figure 3 shows a schematic diagram of the hierarchical thread organization structure of a computing task according to an embodiment of the present disclosure;

[0013] Figures 4A-4C illustrate an example of computational task partitioning according to an embodiment of the present disclosure;

[0014] Figure 5 shows a schematic flowchart for determining whether the number of threads in the x-direction is aligned;

[0015] Figure 6A illustrates a schematic diagram of misaligned computational task allocation according to an embodiment of the present disclosure;

[0016] Figures 6B-6C show another schematic diagram of misaligned assignment of computational tasks according to an embodiment of the present disclosure;

[0017] Figure 7 shows a schematic block diagram of an electronic device provided according to an embodiment of the present disclosure;

[0018] Figure 8 shows a schematic block diagram of an electronic device provided according to an embodiment of the present disclosure;

[0019] Figure 9 shows a schematic diagram of the structure of an electronic device according to some implementations of this disclosure; and

[0020] Figure 10 shows a schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure. Detailed Implementation

[0021] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0022] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0023] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0024] It should be noted that the concepts of "first," "second," etc., used in this disclosure are only used to distinguish different devices, modules, or units, and are not used to limit the order of functions performed by these devices, modules, or units or their interdependencies. The modifiers "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated in the context, they should be understood as "one or more." Furthermore, "a plurality of" used in this disclosure can refer to two or more.

[0025] It is understood that the technical terms and nouns used in this document have meanings known to those skilled in the art. To facilitate understanding of the present disclosure, the following explains the terminology and related technologies that may be involved in at least some embodiments of the present disclosure.

[0026] With the development of widespread general-purpose computing scenarios, higher demands are being placed on processor chips in terms of computing power, processing efficiency, and bandwidth. Therefore, how to achieve hardware-software co-design for electronic devices and provide high-performance electronic devices has become an important research direction.

[0027] To further improve computing performance, a method is proposed that multiple processors execute multiple operations simultaneously to enhance computational speed and efficiency. This parallel computing approach aims to solve large and complex computational problems by utilizing multiple processors or computers to process tasks in parallel, thereby significantly improving computing performance. To achieve parallel computing, electronic devices can be configured with multiple hardware processor chips (processor elements). For example, a hardware processor chip can be a single chip or a processor core within a chip, etc., without limitation. As an example, the electronic devices mentioned in this disclosure can be (including but not limited to) devices such as a Central Processing Unit (CPU) and an Accelerated Processing Unit (APU), etc., which will not be listed further here.

[0028] As an example, for a computational task, such as matrix operations (e.g., the MatAdd function), normalization operations (softmax function), etc., which require a large amount of computation, such as vector operations, a computationally intensive task can be divided into multiple threads and distributed to multiple processor chips in the aforementioned electronic device for processing, thereby improving computational efficiency and reducing computation time.

[0029] To achieve a unified abstract understanding of computational tasks for both hardware and programmers, computational tasks can be described as hierarchical thread organization structures, utilizing built-in thread variables to index data within the computational task. For example, when starting the kernel function, the programmer can provide parameters to the electronic device to describe the thread organization structure of the computational task, thereby constructing a thread structure model for that task. Figure 1 is provided for ease of understanding, illustrating a schematic diagram of a hierarchical thread organization structure for computational tasks in related technologies.

[0030] As shown in Figure 1, a computational task (or grid) can be represented as a three-dimensional organizational structure composed of multiple thread blocks. Furthermore, a thread block can be represented as a three-dimensional organizational structure composed of multiple threads; for example, this three-dimensional organizational structure can be understood as a cuboid as shown in Figure 1. The computational task includes all the threads that implement the current processing. This three-dimensional organizational structure composed of thread blocks can be described by three grid dimensions, such as gridDim.x, gridDim.y, and gridDim.z (only the x-direction dimension gridDim.x is shown in Figure 1). These three dimensions describe the number of thread blocks in the x, y, and z directions within the computational task. Similarly, a thread block can be described by three thread dimensions, such as blockDim.x, blockDim.y, and blockDim.z, which describe the number of threads in the x, y, and z directions within the thread block (only the x-direction dimension blockDim.x is shown in Figure 1). Based on the dimensional information provided above, the hierarchical thread organization structure of the computational task can be fully described.

[0031] In summary, the thread organization structure of a computation task can be constructed based on the dimension parameters `gridDim` and `blockDim`. As an example, based on these parameters, the total number of threads within the computation task can be obtained, expressed as (gridDim.x * blockDim.x) * (gridDim.y * blockDim.y) * (gridDim.z * blockDim.z), where `gridDim.x * blockDim.x` represents the number of threads in the x-direction, `gridDim.y * blockDim.y` represents the number of threads in the y-direction, and `gridDim.z * blockDim.z` represents the number of threads in the z-direction. Based on this information, programmers / compilers / processor chips can understand the overall thread organization structure of the computation task.

[0032] Based on the aforementioned hierarchical thread organization structure, the processor chip used for parallel computing also needs to know the specific location of a thread within the computing task (grid) in order to read data at the corresponding location and perform the corresponding computation. Therefore, for each computing task, it is also necessary to provide information indicating the position of a thread within the grid of the computing task. Based on this position information and the dimension parameters gridDim and blockDim used to describe the hierarchical thread organization structure of the computing task, the processor chip and programmers can uniformly identify and understand the threads being processed. Therefore, thread block indices blockIdx.x / blockIdx.y / blockIdx.z are introduced to specify the x / y / z indices of the thread block within the computing task (grid), respectively. Similarly, indices threadIdx.x / threadIdx.y / threadIdx.z are introduced to specify the x / y / z indices of each thread within the thread block, respectively. Schematic, Figure 1 only shows the thread block index blockIdx.x and the thread index threadIdx.x in the x direction.

[0033] As an example, the position information of a thread (e.g., thread 1) in a computation task (or grid) can be represented as the three-dimensional position coordinates (idx.x, idx.y, idx.z) of thread 1 in the computation task's grid, as shown below: idx.x = blockIdx.x * blockDim.x + threadIdx.x (1) idx.y = blockIdx.y * blockDim.y + threadIdx.y (2) idx.z = blockIdx.z * blockDim.z + threadIdx.z (3)

[0034] Wherein, blockIdx.x represents the x-direction index of the thread block to which thread 1 belongs in the grid, blockIdx.y represents the y-direction index of the thread block to which thread 1 belongs in the grid, blockIdx.z represents the z-direction index of the thread block to which thread 1 belongs in the grid, threadIdx.x represents the x-direction index of thread 1 in its thread block, threadIdx.y represents the y-direction index of thread 1 in its thread block, and threadIdx.z represents the z-direction index of thread 1 in its thread block. According to the calculation method shown in equations (1)-(3) above, the position information of thread 1 in the computing task can be obtained. Based on this position information, for example, the processor chip can perform corresponding data access to execute parallel computing.

[0035] However, with the explosive growth of computational workload in computing tasks (e.g., tasks, or grids as mentioned above), a single computing task often requires the collaborative work of multiple hardware processing units (processor elements: which can be a single chip, a core within a chip, etc.). Consequently, as the workload of computing tasks increases and the hardware structure becomes more complex, the two-tiered thread organization structure shown in Figure 1 becomes insufficient to meet the needs of task partitioning, necessitating a higher-dimensional index for task partitioning.

[0036] Furthermore, the hierarchical thread organization structure described above in conjunction with Figure 1 (e.g., the computation task / thread block / thread hierarchy shown in Figure 1) only allows programmers / compilers to abstractly divide computation tasks. However, it still cannot perceive how computation tasks are divided and executed by the hardware processing units in the electronic device. That is, it cannot determine which threads are handled by which hardware processing unit in the electronic device. This makes task division unknowable, and the electronic device needs to consume additional computing resources to plan how to distribute the thread blocks within the computation task to the various participating hardware processing units. As an example, electronic devices generally use default methods to divide the threads of computation tasks. However, this makes it difficult to guarantee a reasonable and balanced distribution of computational workload, which may produce a tailing effect and limit the computational efficiency of parallel computing. For example, some hardware processing units are allocated less computation and finish executing first, remaining idle, while other hardware processing units are allocated more computation and finish executing later, resulting in a waste of computing resources. In addition, electronic devices require additional computation to map the logical index coordinates of threads within the computation task to the physical memory of each hardware processing unit in order to complete the parallel computing process, which also limits the parallel computing performance of electronic devices.

[0037] To address the aforementioned technical problems, some embodiments of this disclosure provide a method for processing computational tasks in electronic devices. This method allocates computational tasks to multiple processing units, enabling hardware processing units to perform parallel computations based on provided thread information. This assigns specific processing units to threads within the computational task, assisting the hardware in more rational task partitioning and improving processing efficiency. Using the method provided by embodiments of this disclosure, the hardware in electronic devices can perform more rational computational task partitioning, resulting in a more even distribution of computational workload among the hardware processing units, reducing the aforementioned tailing effect, and avoiding resource consumption caused by default task partitioning by the electronic device. Furthermore, the hardware processing units in the electronic device can process threads of the computational task based on provided thread information to achieve parallel computation. Moreover, based on the provided thread information, the above task partitioning method is known to programmers / compilers, for example, it can assist programmers in more rational resource allocation based on the specific content of the programming, thereby achieving better computational performance and comprehensive planning of human-computer information.

[0038] Figure 2 shows a schematic flowchart of a computing task processing method for an electronic device according to an embodiment of the present disclosure. The method provided by the present disclosure will be described below with reference to Figure 2.

[0039] It is understood that the electronic device to which the embodiments of this disclosure apply may refer to a device that includes multiple processor chips capable of performing parallel computing, or a parallel computing device. As an example, the electronic device may refer to the aforementioned CPU, APU, etc. This disclosure does not limit the specific implementation of the electronic device.

[0040] As shown in Figure 2, the computing task processing method 100 for an electronic device may include steps S110 and S120. In step S110, for a computing task performed in parallel by multiple processing units, the threads included in the computing task are divided according to the multiple processing units, and thread information is provided to the multiple processing units. Here, a processing unit can refer to a processor chip in the electronic device used to perform parallel computing; for example, it can be a single chip or a processor core within a chip, etc., without limitation. This step S110 is used to allocate computing tasks according to processing units. In step S120, the multiple processing units process the threads of the computing task according to the provided thread information. Therefore, the method of this disclosure enables hardware processing units to perform parallel computing according to the provided thread information, thereby specifying specific processing units for the threads in the computing task, assisting the hardware in making more reasonable task divisions, and improving processing efficiency.

[0041] According to some embodiments of this disclosure, dividing the threads included in a computing task into multiple processing units includes: dividing the threads included in the computing task into thread blocks, each thread block including one or more threads; and allocating the threads included in the computing task to multiple processing units on a thread block basis, wherein threads belonging to the same thread block are allocated to the same processing unit.

[0042] Based on the above processing method for computational tasks, the task volume is divided into thread blocks. This ensures that threads within the same thread block are assigned to the same processing unit, meaning all threads within the same thread block are processed by the same processing unit. In practical applications, the computation process of a thread block often requires data exchange and communication, while the computation processes between different thread blocks do not require interaction. Therefore, this disclosure proposes allocating tasks between processing units based on thread blocks. This minimizes data communication between processing units, thereby providing an efficient parallel data processing process. Data interaction between processing units requires a long data access path with significant latency, which is affected by data transmission bandwidth and other factors, inevitably reducing the processing efficiency of the device.

[0043] According to some embodiments of this disclosure, the thread information provided to the processing unit indicates the position information of the thread in the computing task, wherein the processing unit performs data access based on the position information of the thread it is processing in order to perform parallel computing.

[0044] According to some embodiments of this disclosure, a computing task is represented as a three-dimensional organizational structure based on processing units, the processing units corresponding to the computing task are represented as a three-dimensional organizational structure based on thread blocks, and the thread blocks are represented as a three-dimensional organizational structure based on threads. Thread information indicates the three-dimensional coordinates of a thread within the computing task. To assign specific processing units to threads within a computing task and assist hardware in more rational task partitioning, this disclosure proposes constructing a hierarchical thread organization structure for computing tasks based on processing units. That is, threads within a computing task are divided dimensionally based on processing units, thereby enabling processor chips and programmers to uniformly identify the threads of the processed computing tasks.

[0045] For ease of understanding, Figure 3 is provided, which illustrates a schematic diagram of the hierarchical thread organization structure of a computing task according to an embodiment of the present disclosure. As shown in Figure 3, the computing task (or grid) is first divided according to the processing elements (PEs) involved in the computation. The number of processing elements within the grid is represented by gridDim, which consists of three dimensional parameters: gridDim.x, gridDim.y, and gridDim.z, which describe the number of processing elements in the x, y, and z directions of the computing task, respectively. Schematic, Figure 3 only shows the dimensional parameter gridDim.x in the x direction, indicating that the computing task involves a total of gridDim.x processing elements in the x direction. That is, it can be understood that the computing task is processed by gridDim.x processing elements in the x direction.

[0046] Compared to the thread organization structure shown in Figure 1, an organizational hierarchy of processing units (PEs) has been added. This allows computing tasks to be described in the form of division according to processing units, thereby achieving a unified understanding of the thread information of computing tasks between processing units and programmers. After the task is divided, the corresponding processing unit can perform corresponding data access according to the allocated thread information to execute the parallel computing process.

[0047] Referring to Figure 3, the thread corresponding to one of the processing units (PEs) is further described as a three-dimensional organizational structure composed of thread blocks. Similarly, PEDim represents the number of thread blocks within the processing unit. PEDim consists of three dimensional parameters, namely PEDim.x, PEDim.y, and PEDim.z, which describe the number of thread blocks corresponding to the processing unit in the x, y, and z directions, respectively. That is, it can be understood as the number of thread blocks processed by the processing unit in the x, y, and z directions. Illustratively, Figure 3 only shows the dimensional parameter PEDim.x in the x direction, indicating that the processing unit includes a total of PEDim.x thread blocks in the x direction.

[0048] Referring to Figure 3, one of the thread blocks is further described as a three-dimensional organizational structure composed of threads. Similarly, `blockDim` represents the number of threads within the thread block. `blockDim` consists of three dimensional parameters: `blockDim.x`, `blockDim.y`, and `blockDim.z`, which describe the number of threads in the thread block in the x, y, and z directions, respectively. Illustratively, Figure 3 only shows the x-direction dimension parameter `blockDim.x`, indicating that the thread block includes `blockDim.x` threads in the x-direction.

[0049] Referring to Figure 3, based on the provided dimensional information gridDim, PEDim, and blockDim, the hierarchical thread organization structure of the computing task can be completely described, allowing programmers / compilers / processor chips to understand the overall thread organization structure of the computing task. As an example, built-in variables of threads can be used to index data within the computing task, thereby achieving accurate parallel computing. For instance, when starting the kernel function, the programmer can provide the above-mentioned parameters gridDim, PEDim, and blockDim to the electronic device to describe the thread organization structure of the computing task, thus constructing the thread structure model of that computing task. Based on the thread organization structure shown in Figure 3, threads within the computing task can be allocated to corresponding processing units, for example, in units of thread blocks.

[0050] Based on the provided dimension parameters gridDim, PEDim, and blockDim, corresponding index numbers can also be introduced to index processing units, thread blocks, and threads.

[0051] According to some embodiments of this disclosure, step S110, which divides the threads included in the computing task into multiple processing units and provides thread information to multiple processing units, includes: for the first thread among the threads included in the computing task, specifying the processing unit index of the first processing unit used to process the first thread in the computing task, specifying the thread block index corresponding to the first thread block to which the first thread belongs, and specifying the thread index of the first thread within its first thread block, and providing the processing unit index, thread block index, and thread index as thread information of the first thread to the first processing unit.

[0052] According to some embodiments of this disclosure, (PEIdx.x, PEIdx.y, PEIdx.z) represents the processing unit index of the first processing unit in the computing task. (blockIdx.x,blockIdx.y,blockIdx.z) represents the thread block index corresponding to the first thread block to which the first thread belongs, and (threadIdx.x,threadIdx.y,threadIdx.z) represents the thread index of the first thread within its first thread block. The three-dimensional coordinates (idx.x,idx.y,idx.z) of the first thread in the computation task are expressed as: idx.x = PEIdx.x * PEDim.x * blockDim.x + blockIdx.x * blockDim.x + threadIdx.x; (4) idx.y = PEIdx.y * PEDim.y * blockDim.y + blockIdx.y * blockDim.y + threadIdx.y; (5) idx.z = PEIdx.z * PEDim.z * blockDim.z + blockIdx.z * blockDim.z + threadIdx.z; (6)

[0053] Where (PEDim.x, PEDim.y, PEDim.z) represents the number of thread blocks contained in the x / y / z direction within the processing unit, and (blockDim.x, blockDim.y, blockDim.z) represents the number of threads contained in the x / y / z direction within the thread block. According to the calculation method shown in equations (4)-(6) above, the position information of the first thread in the computing task can be obtained. Based on this position information, for example, the processor chip can perform corresponding data access to execute parallel computing.

[0054] For ease of understanding, an example of task partitioning is provided, where gridDim.x = 2, gridDim.y = 2, gridDim.z = 1; PeDim.x = 1, PeDim.y = 3, PeDim.z = 1; blockDim.x = 8, blockDim.y = 1, blockDim.z = 1. Figures 4A-4C show schematic diagrams of task partitioning in Example 1 described by the above parameter values. Referring to the task (grid) shown on the left side of Figure 4A, gridDim.x = 2, gridDim.y = 2, gridDim.z = 1, it can be seen that the task is processed by 2 processing units in the x-direction, 2 processing units in the y-direction, and 1 processing unit in the z-direction. That is, the threads of this task are processed in parallel by 4 processing units, meaning the computational tasks are distributed among 4 processing units.

[0055] Next, referring to the schematic diagram of the processing unit (PE) on the right side of Figure 4A, PeDim.x = 1, PeDim.y = 3, PeDim.z = 1. Therefore, for the thread block processed by the processing unit, there is 1 thread block in the x-direction, 3 thread blocks in the y-direction, and 1 thread block in the z-direction. Referring to Figures 4B and 4C, for a thread block, blockDim.x = 8, blockDim.y = 1, blockDim.z = 1. Therefore, this thread block includes 8 threads in the x-direction, 1 thread in the y-direction, and 1 thread in the z-direction.

[0056] For Example 1 described above in conjunction with Figures 4A-4C, a single computation task includes (gridDim.x*PeDim.x*blockDim.x)*(gridDim.y*PeDim.y*blockDim.y)*(gridDim.z*PeDim.z*blockDim.z) = 16*6*1 = 96 threads. These 96 threads are allocated to 4 processing units for parallel computation, with each processing unit executing 3 thread blocks, and each thread block corresponding to 8 threads.

[0057] In summary, the embodiments according to this disclosure enable programmers / compilers to allocate resources reasonably and systematically among threads in a computing task based on information such as the computational load of each thread, the computational capability of the processing unit, and the characteristics of the tasks to be performed, such as matrix calculations. This facilitates more reasonable task division, improves processing efficiency, reduces the tailing effect caused by unreasonable allocation, and avoids the resource consumption caused by default task division by electronic devices. For example, after dividing the computation task into processing units, the corresponding thread information can be provided to each processing unit participating in the computation. This thread information can indicate the position of the thread in the computation task, thereby enabling the processing unit to perform data access based on the position information of the thread it is processing in order to perform parallel computation. The thread information indicating the position information may include the dimension parameters gridDim, PEDim, and blockDim of the computation task described above, as well as the corresponding index values, (PEIdx.x,PEIdx.y,PEIdx.z), (blockIdx.x,blockIdx.y,blockIdx.z), and (threadIdx.x,threadIdx.y,threadIdx.z).

[0058] When the hardware is provided with the three dimensions gridDim, PEDim, and blockDim, the total number of threads in each dimension of the computation task must be a multiple of gridDim * PEDim * blockDim. For example, in the example described in Figures 4A-4C, the number of threads within the thread blocks processed by each processing unit is the same, for example, 8 threads in the x-direction. If the total number of threads in the computation task is insufficient to meet the alignment requirements, padding is required to ensure the required number of threads is met. In real-world applications, if the number of threads cannot meet the implicit requirement of thread number alignment, the processing unit must force the task to start according to the thread number alignment requirement, i.e., padding the number of threads. This will generate more unnecessary power consumption and also requires allocating additional memory space to accommodate the task results of invalid threads.

[0059] According to some embodiments of this disclosure, the computing task processing method for an electronic device may further include: providing the total number of threads contained in the computing task in the x / y / z directions to multiple processing units, denoted as (dim_threads_of_grid_x, dim_threads_of_grid_y, dim_threads_of_grid_z). For example, dim_threads_of_grid_x indicates that the computing task includes dim_threads_of_grid_x threads in the x direction, dim_threads_of_grid_y indicates that the computing task includes dim_threads_of_grid_y threads in the y direction, and dim_threads_of_grid_z indicates that the computing task includes dim_threads_of_grid_z threads in the z direction.

[0060] By simply adding the above information, the hardware processing unit can become aware of misalignment in the number of threads within a computing task, i.e., the number of threads is insufficient to meet the alignment requirements. In this scenario, based on the dimension parameters gridDim, PEDim, and blockDim of the computation task described above, and their corresponding index values ​​(PEIdx.x, PEIdx.y, PEIdx.z), (blockIdx.x, blockIdx.y, blockIdx.z), and (threadIdx.x, threadIdx.y, threadIdx.z), and also including the total number of threads contained in the x / y / z directions within the computation task (dim_threads_of_grid_x, dim_threads_of_grid_y, dim_threads_of_grid_z), the processing unit can index and locate any thread within the computation task, i.e., know its position information within the computation task. This allows for corresponding data access. Furthermore, it enables thread indexing without needing to supplement the thread count to align the thread counts within each thread block, thus avoiding the adverse effects of the aforementioned alignment process, such as consuming additional useless computational resources and storage space.

[0061] In practical applications, we will take the example of the processing unit determining whether the number of threads in the x-direction is aligned. It can be understood that the processing process for other directions (i.e., the y-direction and the z-direction) is similar.

[0062] Figure 5 shows a schematic flowchart for determining whether the number of threads in the x direction is aligned. As shown in Figure 5, firstly, in step S101, the parameters are initialized, that is, remain_dim_threads_of_grid.x = dim_threads_of_grid.x, and PEIdx.x = 0, that is, the alignment of the threads of the first PE is determined. In step S102, for PEIdx.x = 0, the electronic device can first determine whether remain_dim_threads_of_grid.x is greater than PEDim.x * blockDim.x. If so, it can be determined that all threads within PEIdx.x = 0 are aligned (which can be understood as whether the number of threads can meet the thread parameters within the provided processing unit). As shown in Figure 5, step S103 instructs to split out a complete PEDim.x * blockDim.x in the x-direction, and use PEIdx.x as its x-direction index coordinate, and update it so that remain_dim_threads_of_grid.x = remain_dim_threads_of_grid.x - PEDim.x * blockDim.x, PEIdx.x = PEIdx.x + 1. Then, return to step S102 and continue the above judgment process. If not, proceed to step S104, which means splitting out the thread block corresponding to the last PE in the x direction and using PEIdx.x as its index coordinate in the x direction. Then, determine whether remain_dim_threads_of_grid.x == PEDim.x * blockDim.x, that is, whether remain_dim_threads_of_grid.x is equal to PEDim.x * blockDim.x.

[0063] If yes, proceed to step S105, indicating that the thread block corresponding to the last PE in the x-direction is fully aligned in the x-direction, completing the splitting in the x-direction. If no, proceed to step S106, indicating that the thread block corresponding to the last PE in the x-direction is not aligned in the x-direction. Using PEIdx.x as its x-direction index coordinate, the thread block partitioning process is required, and blockIdx.x needs to be initialized to 0 for the thread block determination process.

[0064] In step S107, it is determined whether `remain_dim_threads_of_grid.x` is greater than `blockDim.x`. If so, proceed to step S108, where a complete `blockDim.x` in the x-direction is extracted, and `blockIdx.x` is used as its x-direction index coordinate. The coordinates are updated so that `remain_dim_threads_of_grid.x` = `remain_dim_threads_of_grid.x` - `blockDim.x`, and `blockIdx.x` = `blockIdx.x` + 1. Then, the process returns to step S107 and continues the above determination.

[0065] If not, proceed to step S109 to complete the splitting of the last thread block in the x direction, using blockIdx.x as its x-direction index coordinate. If remain_dim_threads_of_grid.x = blockDim.x, then the last thread block is aligned.

[0066] According to the implementation described above, the electronic device can determine the thread misalignment within the computation task based on the provided dimension parameters gridDim, PEDim, and blockDim of the computation task, as well as the corresponding index values ​​(PEIdx.x, PEIdx.y, PEIdx.z), (blockIdx.x, blockIdx.y, blockIdx.z), and (threadIdx.x, threadIdx.y, threadIdx.z). In addition, it also includes the total number of threads contained in the x / y / z directions of the computation task (dim_threads_of_grid_x, dim_threads_of_grid_y, dim_threads_of_grid_z). Furthermore, it can perform corresponding data access based on thread information such as index values, while avoiding the thread padding operation required due to thread misalignment.

[0067] To facilitate understanding, a second example of computational task partitioning is provided, illustrating the case of misaligned partitioning. This example uses gridDim.x = gridDim.y = gridDim.z = 1; PEDim.x = PeDim.y = 2, PEDim.z = 1; blockDim.x = blockDim.y = 4, blockDim.z = 1; and dim_threads_of_grid.x = dim_threads_of_grid.y = 5, dim_threads_of_grid.z = 1. Figure 6A shows a schematic diagram of the computational task partitioning in Example 2, described by the above parameter values, illustrating the case of misaligned computational task allocation. In Example 2, for ease of description, gridDim.x = gridDim.y = gridDim.z = 1, indicating that the computational task corresponds to one processing unit. PEDim.x = PeDim.y = 2, PEDim.z = 1 indicates that the processing unit includes 1 thread block in the x and z directions and 2 thread blocks in the y direction. blockDim.x = blockDim.y = 4, blockDim.z = 1 indicates that within a thread block, there are 4 threads in the x and y directions and 1 thread in the z direction. dim_threads_of_grid.x = dim_threads_of_grid.y = 5, dim_threads_of_grid.z = 1 indicates that the computation task includes a total of 5 threads in each of the x and y directions and 1 thread in the z direction. Therefore, in Example 2, the total number of threads in the computation task is insufficient to meet the thread number alignment requirements within each thread block. As shown in Figure 6A, the number of threads contained in the 4 thread blocks of the computation task is different, representing a thread number misalignment situation. Within thread block (0,0,0), the threads are aligned, meaning the parameter requirements of blockDim.x = blockDim.y = 4 and blockDim.z = 1 are satisfied. However, within thread blocks (1,0,0), (0,1,0), and (1,1,0), the threads are not aligned, meaning the parameter requirements of blockDim.x = blockDim.y = 4 and blockDim.z = 1 are not satisfied. As shown in Figure 6A, based on the example parameters given above, even when the number of threads cannot be aligned, the processing unit can still index to the corresponding position in the computation task based on the provided thread information, i.e., the provided index values ​​and dimension information, thus satisfying the memory data access requirements during the computation process.

[0068] To facilitate understanding, a third example of a computational task partitioning is provided, describing the case of misaligned partitioning. Examples include: gridDim.x = 2, gridDim.y = 2, gridDim.z = 1; PeDim.x = 1, PeDim.y = 3, PeDim.z = 1; blockDim.x = 8, blockDim.y = 1, blockDim.z = 1; dim_threads_of_grid.x = 14, dim_threads_of_grid.y = 5, dim_threads_of_grid.z = 1.

[0069] Figures 6B-6C illustrate the computational task partitioning of Example 3, described by the above parameter values, to illustrate the case of misaligned computational task allocation. In Example 3, gridDim.x = gridDim.y = 2, gridDim.z = 1, indicating that the computational task corresponds to 4 processing units, that is, the computational task is processed in parallel by 4 processing units. PeDim.x = 1, PeDim.y = 3, PeDim.z = 1, indicating that the processing unit includes 1 thread block in the x and z directions and 3 thread blocks in the y direction. blockDim.x = 8, blockDim.y = 1, blockDim.z = 1, indicating that within the thread block, there are 8 threads in the x direction and 1 thread in the y and z directions. dim_threads_of_grid.x = 14, dim_threads_of_grid.y = 5, dim_threads_of_grid.z = 1 indicates that the computation task includes a total of 14 threads in the x-direction, 5 threads in the y-direction, and 1 thread in the z-direction. Refer to Figure 6B, which shows the thread composition of the computation task.

[0070] Therefore, in Example 3, the total number of threads in the computation task is insufficient to meet the thread number alignment requirements within each thread block. Referring to Figure 6C, the computation task is processed by four processing units (PEs), shown as PE(0,0,0), PE(1,0,0), PE(0,1,0), and PE(1,1,0). The alignment determination process is described in detail below.

[0071] First, for PE(0,0,0), taking the x-direction as an example, the electronic device can determine whether PE(0,0,0) meets the thread alignment requirements based on whether dim_threads_of_grid.x is greater than PEDim.x * blockDim.x. Currently, dim_threads_of_grid.x equals 14, and PEDim.x * blockDim.x = 8, thus meeting the requirements. A similar judgment process can be performed in the y-direction, and it can be concluded that both the thread block and the thread of PE(0,0,0) meet the alignment requirements, as shown in the upper left corner of Figure 6C.

[0072] For PE(1,0,0), updating the value of dim_threads_of_grid.x results in dim_threads_of_grid.x = dim_threads_of_grid.x - PEDim.x * blockDim.x = 14 - 8 = 6. This means that in the x-direction, there are 6 threads remaining to be processed by PE(1,0,0), which does not meet the requirement of a thread block including 8 threads in the x-direction; that is, the threads are misaligned. In embodiments according to this disclosure, for such thread misalignment, there is no need to manually supplement the missing threads (e.g., add 2 empty threads). Simply recording the corresponding thread index number enables the processing unit in the electronic device to perform parallel computation. Referring to the situation shown in the upper right corner of Figure 6C, the thread blocks (0,0,0), (0,1,0), and (0,2,0) corresponding to PE(1,0,0) only include 6 threads in the x-direction. Furthermore, since the updated dim_threads_of_grid.x no longer meets the alignment requirements, the judgment process in the x direction ends.

[0073] Next, for PE(0,1,0), similar to PE(0,0,0), a judgment is made in the x-direction to determine if the threads in the x-direction meet the alignment requirements. For the y-direction, the updated dim_threads_of_grid.y = dim_threads_of_grid.y - PEDim.y * blockDim.y = 5 - 3 = 2, meaning that the computation task has 2 remaining threads in the y-direction, insufficient to meet the thread alignment requirements. Similarly, in this case, the electronic device only needs to use the corresponding thread index number to enable parallel computation of the processing units within the electronic device. Referring to the situation shown in the lower left corner of Figure 6C, corresponding to PE(1,0,0), there are only 2 thread blocks in the y-direction. Furthermore, since the updated dim_threads_of_grid.y no longer meets the alignment requirements, the judgment process in the y-direction ends. It is understandable that for PE(1,1,0), the electronic device can perform similar processing and obtain the thread allocation situation shown in the lower right corner of Figure 6C.

[0074] In summary, this disclosure provides a computing task processing method for electronic devices, which can allocate computing tasks according to multiple processing units, enabling hardware processing units to perform parallel computing according to the provided thread information, thereby assigning specific processing units to threads in the computing task, assisting the hardware in making more reasonable task division, and improving processing efficiency.

[0075] By utilizing the method provided according to embodiments of this disclosure, the hardware in an electronic device can perform more rational division of computational tasks, resulting in a more even distribution of computational workload among various hardware processing units, reducing the aforementioned tailing effect, and avoiding resource consumption caused by default task division in the electronic device. Furthermore, the hardware processing units in the electronic device can process the threads of computational tasks based on provided thread information to achieve parallel computing. Moreover, based on the provided thread information, the above task division method is known to programmers / compilers; for example, it can assist programmers in making more rational resource allocation based on the specific content of the programming, thereby achieving better computational performance and comprehensive planning of human-computer information.

[0076] According to another aspect of this disclosure, an electronic device is also provided, which may include a scheduler for processing units and a plurality of processing units for performing parallel computing. Figure 7 shows a schematic block diagram of an electronic device provided according to an embodiment of this disclosure.

[0077] As shown in Figure 7, the electronic device 1000 may include a scheduler 1010 and multiple processing units 1020. As indicated above, the electronic device 1000 can be implemented as a CPU, APU, or similar form, without limitation. Multiple processing units can refer to two or more units; they can be a single chip, a processor core within a chip, or other hardware implementations, without limitation. According to an embodiment of this disclosure, the scheduler 1010 can be configured to: for a computational task performed in parallel by multiple processing units, divide the threads included in the computational task according to the multiple processing units, and provide thread information to the multiple processing units. The multiple processing units 1020 can be configured to: process the threads of the computational task according to the provided thread information.

[0078] According to some embodiments of this disclosure, the scheduler 1010 divides the threads included in the computing task into multiple processing units by: dividing the threads included in the computing task into thread blocks, each thread block including one or more threads; and allocating the threads included in the computing task to multiple processing units on a thread block basis, wherein threads belonging to the same thread block are allocated to the same processing unit.

[0079] According to some embodiments of this disclosure, thread information indicates the position information of a thread in a computing task, wherein the processing unit performs data access based on the position information of the thread it is processing in order to perform parallel computing.

[0080] According to some embodiments of this disclosure, a computing task is represented as a three-dimensional organizational structure based on processing units, the processing unit corresponding to the computing task is represented as a three-dimensional organizational structure based on thread blocks, the thread block is represented as a three-dimensional organizational structure based on threads, and the thread information indicates the three-dimensional coordinates of the thread in the computing task.

[0081] According to some embodiments of this disclosure, the scheduler 1010 divides the threads included in the computing task into multiple processing units and provides thread information to the multiple processing units, including: for a first thread among the threads included in the computing task, specifying the processing unit index of the first processing unit used to process the first thread in the computing task, specifying the thread block index corresponding to the first thread block to which the first thread belongs, and specifying the thread index of the first thread within its first thread block, and providing the processing unit index, thread block index, and thread index as thread information of the first thread to the first processing unit.

[0082] According to some embodiments of this disclosure, (PEIdx.x, PEIdx.y, PEIdx.z) represents the processing unit index of the first processing unit in the computing task, (blockIdx.x, blockIdx.y, blockIdx.z) represents the thread block index corresponding to the first thread block to which the first thread belongs, and (threadIdx.x, threadIdx.y, threadIdx.z) represents the thread index of the first thread within its first thread block. The three-dimensional coordinates (idx.x, idx.y, idx.z) of the first thread in the computing task are represented as follows:

[0083] idx.x=PEIdx.x*PEDim.x*blockDim.x+blockIdx.x*blockDim.x+threadIdx.x;

[0084] idx.y=PEIdx.y*PEDim.y*blockDim.y+blockIdx.y*blockDim.y+threadIdx.y;

[0085] idx.z=PEIdx.z*PEDim.z*blockDim.z+blockIdx.z*blockDim.z+threadIdx.z,

[0086] Where (PEDim.x, PEDim.y, PEDim.z) represents the number of thread blocks contained in the x / y / z direction within the processing unit, and (blockDim.x, blockDim.y, blockDim.z) represents the number of threads contained in the x / y / z direction within the thread block.

[0087] According to some embodiments of this disclosure, the scheduler 1010 may also be configured to provide the total number of threads contained in the computation task in the x / y / z direction to multiple processing units, denoted as (dim_threads_of_grid_x, dim_threads_of_grid_y, dim_threads_of_grid_z).

[0088] It is understood that the electronic device 1000 according to the embodiments of the present disclosure can implement the steps of the computing task processing method for an electronic device according to the embodiments of the present disclosure described above in conjunction with the accompanying drawings, and achieve similar technical effects, which will not be repeated here.

[0089] According to another aspect of this disclosure, an electronic device is also provided. FIG8 shows a schematic block diagram of the electronic device provided according to an embodiment of this disclosure. As shown in FIG9, the electronic device 2000 may include a processing device 2010 and a storage device 2020. The storage device 2020 is configured to store one or more programs, wherein when the one or more programs are executed by the processing device 2010, the processing device 2010 performs the steps of the computing task processing method for an electronic device according to an embodiment of this disclosure.

[0090] As one specific implementation, Figure 9 shows a schematic diagram of an electronic device structure.

[0091] Referring now to FIG9, a structural schematic diagram suitable for implementing the electronic device 3000 of the embodiments of the present disclosure is shown. It is understood that the electronic device 2000 according to the embodiments of the present disclosure can be specifically implemented in the structural form of the electronic device 3000 shown in FIG9. Furthermore, those skilled in the art will understand that the electronic device shown in FIG9 is merely an exemplary block diagram and should not impose any limitation on the function and scope of use of the embodiments of the present disclosure.

[0092] As shown in Figure 9, the electronic device 3000 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 3010, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 3020 or a program loaded from a storage device 3080 into a random access memory (RAM) 3030. The RAM 3030 also stores various programs and data required for the operation of the electronic device 3000. The processing unit 3010, ROM 3020, and RAM 3030 are interconnected via a bus 3040. An input / output (I / O) interface 3050 can also be connected to the bus 3040.

[0093] Typically, the following devices can be connected to the I / O interface 3040: input devices 3060, including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 3070, including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 3080, including, for example, magnetic tape, hard disk, etc.; and communication devices 3090. The communication device 3090 allows the electronic device 3000 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 9 shows an electronic device 3000 with various devices, it should be understood that it is not required to implement or possess all the devices shown. Alternatively, the electronic device 3000 can be implemented as a device with more or fewer components.

[0094] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of this disclosure may also provide a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing a computing task processing method according to embodiments of this disclosure. In such embodiments, the computer program can be downloaded and loaded from a network via a communication device 3090, or loaded from a storage device 3080, or loaded from a ROM 3020. When the computer program is executed by the processing device 3010, the above-described implementation steps defined in the computing task processing method of the embodiments of this disclosure are performed, thereby achieving the corresponding technical effects.

[0095] It should be noted that the computer-readable medium described above in this disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, (but not limited to) an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0096] In some embodiments of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, radio frequency (RF), etc., or any suitable combination thereof.

[0097] The aforementioned computer-readable medium may be included in the aforementioned electronic device or electronic apparatus, or it may exist independently without being assembled into the aforementioned electronic device or electronic apparatus.

[0098] The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to: for a computational task performed in parallel by multiple processing units, divide the threads included in the computational task into multiple processing units and provide thread information to the multiple processing units; and utilize the multiple processing units to process the threads of the computational task according to the provided thread information.

[0099] Computer program code that performs the operations of this disclosure can be written and implemented in one or more programming languages ​​or a combination thereof. These programming languages ​​include, but are not limited to, Compute Unified Device Architecture (CUDA) programming languages, and can also be object-oriented programming languages ​​such as Java, Smalltalk, and C++, or conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server.

[0100] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0101] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is also provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the computational task processing method as described above.

[0102] Schematic illustration is provided in FIG10, which shows a computer-readable storage medium according to an embodiment of the present disclosure. As shown in FIG10, a computer program 4010 may be stored in a computer-readable storage medium 4000 according to an embodiment of the present disclosure. When executed by an electronic device, the computer program 4010 is capable of implementing the process of the computing task processing method described above.

[0103] The above description, in conjunction with the accompanying drawings, describes a computing task processing method, electronic device, apparatus, and medium for an electronic device provided according to embodiments of the present disclosure. These methods enable the division of computing tasks into multiple processing units, allowing each processing unit to perform parallel computation based on provided thread information. This allows specific processing units to be assigned to threads within a computing task, assisting hardware in performing more rational task division and improving processing efficiency.

[0104] According to one or more embodiments of the present disclosure, a first aspect provides a method for processing computing tasks in an electronic device, wherein the electronic device includes multiple processing units performing parallel computing. The method according to the embodiments of the present disclosure includes: for a computing task performed in parallel by multiple processing units, dividing the threads included in the computing task into multiple processing units and providing thread information to the multiple processing units; and using the multiple processing units to process the threads of the computing task according to the provided thread information.

[0105] According to one or more embodiments of this disclosure, dividing the threads included in a computing task into multiple processing units includes: dividing the threads included in the computing task into thread blocks, each thread block including one or more threads; and allocating the threads included in the computing task to multiple processing units on a thread block basis, wherein threads belonging to the same thread block are allocated to the same processing unit.

[0106] According to one or more embodiments of this disclosure, thread information indicates the position information of a thread in a computing task, wherein a processing unit performs data access based on the position information of the thread it is processing in order to perform parallel computing.

[0107] According to one or more embodiments of this disclosure, a computing task is represented as a three-dimensional organizational structure based on processing units, the processing unit corresponding to the computing task is represented as a three-dimensional organizational structure based on thread blocks, the thread block is represented as a three-dimensional organizational structure based on threads, and thread information indicates the three-dimensional coordinates of the thread in the computing task.

[0108] According to one or more embodiments of this disclosure, dividing the threads included in a computing task into multiple processing units and providing thread information to multiple processing units includes: for a first thread among the threads included in the computing task, specifying the processing unit index of the first processing unit used to process the first thread in the computing task, specifying the thread block index corresponding to the first thread block to which the first thread belongs, and specifying the thread index of the first thread within its first thread block, and providing the processing unit index, thread block index, and thread index as thread information of the first thread to the first processing unit.

[0109] According to one or more embodiments of this disclosure, (PEIdx.x, PEIdx.y, PEIdx.z) represents the processing unit index of the first processing unit in the computing task, (blockIdx.x, blockIdx.y, blockIdx.z) represents the thread block index corresponding to the first thread block to which the first thread belongs, and (threadIdx.x, threadIdx.y, threadIdx.z) represents the thread index of the first thread within its first thread block. The three-dimensional coordinates (idx.x, idx.y, idx.z) of the first thread in the computing task are expressed as: idx.x = PEIdx.x * PEDim.x * blockDim.x + blockIdx.x * bl ockDim.x + threadIdx.x; idx.y = PEIdx.y * PEDim.y * blockDim.y + blockIdx.y * blockDim.y + threadIdx.y; idx.z = PEIdx.z * PEDim.z * blockDim.z + blockIdx.z * blockDim.z + threadIdx.z, where (PEDim.x, PEDim.y, PEDim.z) represents the number of thread blocks contained in the x / y / z direction within the processing unit, and (blockDim.x, blockDim.y, blockDim.z) represents the number of threads contained in the x / y / z direction within the thread block.

[0110] According to one or more embodiments of this disclosure, the method of the first aspect further includes: providing the total number of threads contained in the computation task in the x / y / z direction to a plurality of processing units, denoted as (dim_threads_of_grid_x, dim_threads_of_grid_y, dim_threads_of_grid_z).

[0111] According to one or more embodiments of the present disclosure, a second aspect provides an electronic device including a scheduler and a plurality of processing units for performing parallel computing, wherein the scheduler is configured to: for a computing task performed in parallel by the plurality of processing units, divide the threads included in the computing task into the plurality of processing units and provide thread information to the plurality of processing units; and the plurality of processing units are configured to: process the threads of the computing task according to the provided thread information.

[0112] According to one or more embodiments of the present disclosure, a third aspect provides an electronic device, including: a processing means; and a storage means configured to store one or more programs, wherein when the one or more programs are executed by one or more processing means, the processing means performs the computational task processing method as described above.

[0113] According to one or more embodiments of the present disclosure, a fourth aspect provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the computational task processing method for an electronic device as described above.

[0114] The above description is merely an exemplary embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0115] Furthermore, while some processing procedures according to embodiments of this disclosure are described in a specific order, this should not be construed as requiring these processes to be performed in the specific order shown or in a sequential order. In some cases, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0116] Although this disclosure has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for processing computational tasks in electronic devices, wherein, The electronic device includes multiple processing units that perform parallel computing, and the method includes: For a computational task performed in parallel by the multiple processing units, the threads included in the computational task are divided according to the multiple processing units, and thread information is provided to the multiple processing units; and The multiple processing units process the threads of the computation task based on the provided thread information.

2. The method according to claim 1, wherein, The step of dividing the threads included in the computing task according to the multiple processing units includes: The computational task is divided into thread blocks, with each thread block containing one or more threads; and The threads included in the computing task are allocated to the multiple processing units in units of thread blocks, wherein threads belonging to the same thread block are allocated to the same processing unit.

3. The method according to claim 2, wherein, The thread information indicates the position information of the thread in the computing task, wherein the processing unit performs data access based on the position information of the thread it is processing in order to perform parallel computing.

4. The method according to claim 1, wherein, The computing task is represented as a three-dimensional organizational structure based on processing units. The processing unit corresponding to the computing task is represented as a three-dimensional organizational structure based on thread blocks. The thread block is represented as a three-dimensional organizational structure based on threads. The thread information indicates the three-dimensional coordinates of the thread in the computing task.

5. The method according to claim 4, wherein, The step of dividing the threads included in the computing task into the plurality of processing units and providing thread information to the plurality of processing units includes: For the first thread among the threads included in the computing task, a processing unit index for the first processing unit in the computing task is specified, a thread block index corresponding to the first thread block to which the first thread belongs is specified, and a thread index of the first thread within the first thread block to which it belongs is specified. The processing unit index, the thread block index, and the thread index are then provided to the first processing unit as thread information of the first thread.

6. The method according to claim 5, wherein, (PEIdx.x, PEIdx.y, PEIdx.z) represents the processing unit index of the first processing unit in the computing task, (blockIdx.x, blockIdx.y, blockIdx.z) represents the thread block index corresponding to the first thread block to which the first thread belongs, and (threadIdx.x, threadIdx.y, threadIdx.z) represents the thread index of the first thread within its first thread block. The three-dimensional coordinates (idx.x, idx.y, idx.z) of the first thread in the computing task are expressed as: idx.x = PEIdx.x * PEDim.x * blockDim.x + blockIdx.x * blockDim.x + threadIdx.x; idx.y = PEIdx.y * PEDim.y * blockDim.y + blockIdx.y * blockDim.y + threadIdx.y. idx.z=PEIdx.z*PEDim.z*blockDim.z+blockIdx.z*blockDim.z+threadIdx.z, Where (PEDim.x, PEDim.y, PEDim.z) represents the number of thread blocks contained in the x / y / z direction within the processing unit, and (blockDim.x, blockDim.y, blockDim.z) represents the number of threads contained in the x / y / z direction within the thread block.

7. The method according to claim 6, further comprising: The total number of threads contained in the computation task in the x / y / z direction is provided to the plurality of processing units, denoted as (dim_threads_of_grid_x, dim_threads_of_grid_y, dim_threads_of_grid_z).

8. An electronic device comprising a scheduler and a plurality of processing units for performing parallel computing, wherein, The scheduler is configured to: for a computational task performed in parallel by the plurality of processing units, divide the threads included in the computational task according to the plurality of processing units, and provide thread information to the plurality of processing units; and The plurality of processing units are configured to process the threads of the computing task based on the provided thread information.

9. An electronic device comprising: Processing device; Storage device, configured to store one or more programs, When the one or more programs are executed by the processing device, the processing device performs the method as described in any one of claims 1-7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, wherein, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-7.

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