Preparation method for inverted stacked transistor, transistor, device and apparatus

Abstract

Provided in the present disclosure are a preparation method for an inverted stacked transistor, a transistor, a device and an apparatus. The method comprises: forming on a substrate a first semiconductor structure and a second semiconductor structure which are sequentially stacked; etching the first semiconductor structure and the second semiconductor structure in a source-drain region, and filling the first source-drain region corresponding to the first semiconductor structure with an insulating material to form a filling structure; by means of a front-end process, on the basis of the second semiconductor structure, forming a third semiconductor structure, wherein the third semiconductor structure comprises a first source-drain structure; performing wafer flipping and removing the substrate and the filling structure to expose the first semiconductor structure, and on the basis of the first semiconductor structure, forming a fourth semiconductor structure, wherein the fourth semiconductor structure comprises at least a second source-drain structure; and on the basis of the third semiconductor structure and the fourth semiconductor structure, performing wafer flipping multiple times to form a first transistor and a second transistor respectively.

Description

Fabrication methods, transistors, devices, and equipment for flip-chip stacked transistors

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202411581005.8, filed on November 7, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of integrated semiconductors, and more particularly to a method for fabricating a flip-chip stacked transistor, the transistor, the device, and the apparatus. Background Technology

[0004] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, by integrating two or more layers of transistors in a vertical space, further increase transistor integration density and have become one of the important technologies for continuing the miniaturization of integrated circuits.

[0005] In related technologies, both monolithic and sequential methods for fabricating stacked transistors present significant challenges in terms of fabrication difficulty and complexity. Therefore, the fabrication process for stacked transistors still requires improvement in order to simplify the process and reduce fabrication difficulty. Summary of the Invention

[0006] This disclosure provides a method for fabricating a flip-chip stacked transistor, as well as the transistor, device, and apparatus.

[0007] This disclosure provides a method for fabricating a flip-chip stacked transistor. The method includes: forming a first semiconductor structure and a second semiconductor structure on a substrate, the first semiconductor structure being closer to the substrate than the second semiconductor structure; forming a first portion of the first transistor based on the second semiconductor structure, the first portion including a first source / drain structure; flipping the first portion to expose the first semiconductor structure; forming a second transistor based on the first semiconductor structure, the second transistor including at least a second source / drain structure and a gate structure; flipping the second transistor to expose the first source / drain structure; and forming a second portion of the first transistor based on the first source / drain structure, the second portion including at least a first source / drain metal.

[0008] A second aspect of this disclosure provides a flip-chip stacked transistor. The flip-chip stacked transistor is fabricated using the method provided in the first aspect above, comprising: a first transistor; and a second transistor, wherein a second semiconductor structure of the first transistor is self-aligned with the first semiconductor structure of the second transistor.

[0009] A third aspect of this disclosure provides a semiconductor device comprising: a flip-chip stacked transistor as provided in the second aspect.

[0010] The fourth aspect of this disclosure provides an electronic device, which includes: a circuit board and a semiconductor device provided in the third aspect, the semiconductor device being disposed on the circuit board.

[0011] In this disclosure, a first semiconductor structure and a second semiconductor structure are sequentially stacked on a substrate. The first and second semiconductor structures located in the source / drain regions are etched, and insulating material is filled into the first source / drain region corresponding to the first semiconductor structure to form a filling structure, which covers the source / drain region of the back-side transistor. Through front-end processing, a third semiconductor structure including the first source / drain structure is formed based on the second semiconductor structure. Then, the substrate and filling structure are flipped and removed to expose the first semiconductor structure. Based on the first semiconductor structure, a fourth semiconductor structure including at least the second source / drain structure is formed. Subsequently, a first transistor (front-side transistor) and a second transistor (back-side transistor) are formed based on the third and fourth semiconductor structures, respectively. The fabrication process of the flip-chip stacked transistor is decomposed into multiple stages, with each stage involving only partial heat treatment. This reduces the impact of a single heat treatment on the device, thereby improving the overall thermal budget. Furthermore, by changing the fabrication sequence of the flip-chip stacked transistor device, the impact of heat treatment on device performance can be reduced, thereby improving the thermal budget. In addition, since the filling structure is used to locate the source and drain regions where the back transistor is located, when fabricating the back transistor, it is not necessary to select the region through photolithography. The filling structure can be directly etched to open the source and drain regions corresponding to the back transistor, so that a back transistor that is completely self-aligned with the front transistor can be fabricated.

[0012] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of embodiments of this disclosure.

[0014] Figure 1 is a schematic diagram of an implementation process of a method for fabricating flip-chip stacked transistors according to an embodiment of this disclosure;

[0015] Figure 2 is a top view of the flip-chip stacked transistors in an embodiment of this disclosure;

[0016] Figures 3A to 3J are schematic diagrams of the structure of the flip-chip stacked transistor according to the embodiments of the present disclosure in the first fabrication process;

[0017] Figure 3K is a schematic diagram of a first structure of a flip-chip stacked transistor according to an embodiment of the present disclosure;

[0018] Figures 4A to 4G are schematic diagrams of the structure of the flip-chip stacked transistor in the second fabrication process according to the embodiments of this disclosure;

[0019] Figure 4H is a schematic diagram of a second structure of a flip-chip stacked transistor according to an embodiment of the present disclosure;

[0020] Figures 5A to 5I are schematic diagrams of the structure of the flip-chip stacked transistor according to the embodiments of the present disclosure in the third fabrication process;

[0021] Figure 5J is a schematic diagram of a third structure of flip-chip stacked transistors according to an embodiment of the present disclosure;

[0022] Figures 6A to 6H are schematic diagrams of the structure of the flip-chip stacked transistor in the fourth fabrication process according to the embodiments of this disclosure;

[0023] Figure 6I is a schematic diagram of a fourth structure of a flip-chip stacked transistor according to an embodiment of the present disclosure.

[0024] Explanation of reference numerals in the figures: Flip-chip stacked transistor 10; First transistor (front-side transistor) 11; First nanosheet structure 111; First source / drain structure 112; First interlayer dielectric layer 113; First gate structure 114; First gate dielectric layer 1141; First gate electrode layer 1142; First source / drain metal 115; First metal interconnect layer 116; Second transistor (back-side transistor) 12; Second nanosheet structure 121; Second source / drain structure 122; Second interlayer dielectric layer 123; Second gate structure 124; Second gate dielectric layer 1241; Second gate electrode layer 1242; Second source / drain metal 125; Second metal interconnect layer 126; First insulating layer 13; First carrier wafer 14; Second insulating layer 15; Second carrier wafer 16; Third insulating layer 17; Third carrier wafer 18; Substrate 20; First sacrificial layer 21; Bottom stacked layer 22; Second sacrificial layer 23; Top stacked layer 24; First semiconductor structure 251; Second semiconductor structure 252; Second intermediate sacrificial layer 253; First intermediate sacrificial layer 254; Isolation structure 26; Pseudo-gate structure 27; Sidewall 28; MDI layer 29; First inner sidewall 30; Fill structure 31; Source / drain isolation structure 32; Second inner sidewall 34; Second isolation layer 35; First isolation layer 36; Oxide layer 37; First pseudo-gate structure 38; Gate isolation structure 39; Second pseudo-gate structure 40; Second gate cutoff structure 41; First gate cutoff structure 42. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure.

[0026] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments disclosed herein. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0027] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. It is considered one of the important technologies for continuing the miniaturization of integrated circuits.

[0028] In one embodiment, there are two methods for fabricating stacked transistors: a monolithic method and a sequential method.

[0029] The first approach fabricates N-channel field-effect transistors (NFETs) and P-channel field-effect transistors (PFETs) on the same substrate without using substrate bonding. This dictates that transistors in the same layer must be of the same type, i.e., NFETs or PFETs. Furthermore, the upper and lower transistor layers must be strictly on the same plane, with no alignment deviations. The advantage of this approach is its higher integration density. The disadvantages of this approach include the following two points: (1) complex process, requiring extensive development and optimization of process technologies; (2) fixed polarity for each transistor layer, necessitating two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, resulting in poor design flexibility.

[0030] The second approach is based on substrate bonding and layer-by-layer fabrication. Specifically, the upper transistor is fabricated by bonding a substrate to the top of the already fabricated lower transistor, stacking the two transistors vertically. However, this approach requires strict temperature control during the thermal processing of the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this approach is that, thanks to substrate bonding, the device structure, channel crystal orientation, and even the channel material used in the upper and lower transistors can be optimized to obtain better and more matched device performance. This approach currently faces the following technical challenges: (1) fabrication of high-quality upper transistor active layers; (2) thinning and defect control of the upper bonding substrate; (3) alignment errors exist between the upper and lower transistors, requiring extremely high photolithography precision.

[0031] From a common perspective, the technical difficulties of the two schemes mentioned above are: (1) the thermal stability of the bottom transistors when fabricating the top transistor; (2) the performance of the top transistor under low thermal budget; and (3) the metal interconnection between transistors between layers.

[0032] To address the aforementioned technical problems, this disclosure provides a method for fabricating flip-chip stacked transistors. The active regions of the upper and lower homogeneous transistors are formed by etching, and flip-chip stacked transistors are fabricated on both the front and back sides of the wafer by flipping. This method can improve the thermal budget during the overall device fabrication process.

[0033] In the embodiments disclosed herein, the flip-chip stacked transistors described above can be applied to semiconductor devices such as memory and processors.

[0034] In one embodiment, the flip-chip stacked transistor may include at least two transistors. Taking a first transistor and a second transistor as an example, the first transistor and the second transistor are stacked. The second semiconductor structure of the first transistor is self-aligned with the first semiconductor structure of the second transistor. The first source-drain structure of the first transistor is self-aligned with the second source-drain structure of the second transistor in the vertical direction. Therefore, the first transistor and the second transistor are completely self-aligned.

[0035] In the embodiments disclosed herein, the first transistor and the second transistor in the flip-chip stacked transistor can be transistors of the same type, including but not limited to: fin field effect transistor (FinFET), gate-all-around field effect transistor (GAAFET), and planar transistor.

[0036] Figure 1 is a schematic diagram of an implementation process of a method for fabricating a flip-chip stacked transistor according to an embodiment of the present disclosure. As shown in Figure 1, the method for fabricating a flip-chip stacked transistor includes the following steps.

[0037] Step S110: Form a first semiconductor structure and a second semiconductor structure stacked sequentially on the substrate structure.

[0038] In some embodiments, the implementation process of step S110 can be divided into the following three steps: providing a substrate; sequentially forming a sacrificial layer and a first material layer on the substrate; etching the sacrificial layer and the first material layer to form a first semiconductor structure and a second semiconductor structure, wherein the etched first material layer close to the substrate serves as the first semiconductor structure, and the etched first material layer away from the substrate serves as the second semiconductor structure.

[0039] For example, the substrate can be any semiconductor substrate such as a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, silicon-on-insulator (SOI) substrate, etc.

[0040] After providing a substrate, semiconductor materials can be sequentially stacked on the substrate to form a sacrificial layer and a first material layer. A certain area of ​​the sacrificial layer and the first material layer is then etched to form several semiconductor structures erected on the substrate. These semiconductor structures are the etched first material layer. In one example, the material forming the sacrificial layer is different from the material forming the first material layer, so that the sacrificial layer can be removed subsequently by material selectivity. The function of the sacrificial layer will be explained later. The etching process can, for example, be at least one of dry etching, wet etching, or reactive ion etching.

[0041] In some embodiments, each semiconductor structure includes a first part (first semiconductor structure) and a second part (second semiconductor structure), wherein the first part is closer to the substrate than the second part. That is, the etched first material layer is divided into two parts, with the lower half closer to the substrate serving as the first semiconductor structure and the upper half farther from the substrate serving as the second semiconductor structure.

[0042] In some embodiments, the first material layer may include a first semiconductor material, or the first material layer may include at least a first semiconductor material and a second semiconductor material alternately stacked in sequence along the arrangement direction of the semiconductor structure. For example, the first semiconductor material may be silicon, and the second semiconductor material may be silicon-germanium.

[0043] Understandably, the first material layer can be a single layer formed by depositing one material, or it can be a stacked layer formed by alternating deposition of two different materials.

[0044] In one example, when the flip-chip stacked transistor is a FinFET, the substrate material can be silicon, the sacrificial layer material can be silicon-germanium, and the first material layer forming the semiconductor structure can be silicon. This semiconductor structure can also be referred to as an active structure. When the flip-chip stacked transistor is a GAAFET, the substrate material can be silicon, the sacrificial layer material can be silicon-germanium, and the first material layer forming the semiconductor structure can be formed by alternating deposition of silicon-germanium and silicon. Subsequently, the silicon-germanium material in the semiconductor structure can be removed to form the active structure. For example, the germanium content in the silicon-germanium material forming the sacrificial layer is different from the germanium content in the silicon-germanium material forming the semiconductor structure (i.e., SiGe 1 is used to prepare the sacrificial layer, and SiGe 2 is used to prepare the semiconductor structure).

[0045] In one example, when the flip-chip stacked transistor is a FinFET, the substrate material can be silicon-germanium, the sacrificial layer material can be silicon, and the first material layer forming the semiconductor structure can also be silicon-germanium. This semiconductor structure can also be referred to as an active structure. In the case of a GAAFET, the substrate material can also be silicon-germanium, the sacrificial layer material can be silicon, and the first material layer forming the semiconductor structure can be formed by alternating deposition of silicon-germanium and silicon. Subsequently, the silicon material in the semiconductor structure can be removed to form the active structure.

[0046] In one example, when the flip-chip stacked transistor is a FinFET, the substrate material can be germanium, the sacrificial layer material can be silicon, and the first material layer forming the semiconductor structure can be germanium. This semiconductor structure can also be referred to as an active structure. When the flip-chip stacked transistor is a GAAFET, the substrate material can be germanium, the sacrificial layer material can be silicon, and the first material layer forming the semiconductor structure can be formed by alternating deposition of germanium and silicon. Subsequently, the silicon material in the semiconductor structure can be removed to form the active structure.

[0047] In other embodiments, this disclosure can also fabricate an isolation structure between the front-side transistor and the back-side transistor in a flip-chip stacked transistor. In this case, the aforementioned sacrificial layer can be referred to as the first sacrificial layer.

[0048] When the first material layer includes a first semiconductor material, the first semiconductor material can be deposited on the first sacrificial layer to form a bottom layer, an isolation material can be deposited on the bottom layer to form a second sacrificial layer, and the first semiconductor material can be deposited again on the second sacrificial layer to form a top layer. When the first material layer includes alternatingly stacked first and second semiconductor materials, the first and second semiconductor materials can be alternately deposited on the first sacrificial layer to form a bottom stacked layer, an isolation material can be deposited on the bottom stacked layer to form a second sacrificial layer, and the first and second semiconductor materials can be alternately deposited again on the second sacrificial layer to form a top stacked layer. After etching to form the semiconductor structure, the etched second sacrificial layer (second intermediate sacrificial layer) is located between the first semiconductor structure and the first semiconductor structure. For example, the isolation material forming the second sacrificial layer can be the same as the material forming the first sacrificial layer.

[0049] In some embodiments, after forming the semiconductor structure, an isolation structure can be formed on the substrate to expose the first semiconductor structure and the second semiconductor structure; semiconductor material is deposited on the isolation structure to form a pseudo-gate structure surrounding the first semiconductor structure and the second semiconductor structure.

[0050] Understandably, after forming the semiconductor structure, an insulating material can be deposited on the substrate and thinned so that the upper surface of the formed isolation structure is flush with the upper surface of the sacrificial layer to expose the semiconductor structure.

[0051] In one example, the isolation structure can be shallow trench isolation (STI). For example, the insulating material forming the isolation structure can be any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon oxycarbide (SiCO), etc. The thinning process can be a process such as chemical-mechanical planarization (CMP).

[0052] After the semiconductor structure is formed, semiconductor materials can be deposited on the semiconductor structure to form a pseudo-gate structure.

[0053] To distinguish it from the first and second semiconductor materials mentioned above, the semiconductor material here is referred to as the third semiconductor material. Examples of third semiconductor materials include polycrystalline silicon (poly Si) and amorphous silicon.

[0054] Understandably, after forming the semiconductor structure and the isolation structure, the gate region can be opened by photolithography, and a third semiconductor material such as polysilicon can be deposited within the gate region as a dummy gate structure shared by the front and back transistors. That is, this disclosure defines the gate regions of the front and back transistors in a flip-chip stacked transistor through a dummy gate structure, thus enabling self-alignment of the upper and lower transistors in the gate region. In one example, the height of the dummy gate structure is greater than the height of the semiconductor structure.

[0055] The above describes a dummy gate structure shared by the front and back transistors. Embodiments of this disclosure may also allow for separate formation of dummy gate structures for the front and back transistors.

[0056] In some embodiments, during the formation of the semiconductor structure, an isolation structure may be formed on an isolation structure to expose the first semiconductor structure and the second semiconductor structure; semiconductor material may be deposited on the isolation structure to form a first dummy gate structure surrounding the first semiconductor structure; a gate isolation structure may be formed on the first dummy gate structure; and semiconductor material may be deposited on the gate isolation structure to form a second dummy gate structure surrounding the second semiconductor structure.

[0057] In some embodiments, after forming the isolation structure, a third semiconductor material such as polysilicon is first deposited as a pseudo-gate structure for the back transistor, and then an insulating material is deposited on the pseudo-gate structure of the back transistor to form a gate isolation structure. Then, a third semiconductor material such as polysilicon is deposited on the gate isolation structure as a pseudo-gate structure for the front transistor. The gate isolation structure serves as an isolation between the gate structure of the front transistor and the gate structure of the back transistor.

[0058] In some embodiments, before forming the dummy gate structures of the front and back transistors separately, an oxide material can be deposited on the substrate to form an oxide layer that covers the semiconductor structure. When depositing the oxide to form the oxide layer, a very thin film can be deposited on the surface of the substrate using atomic layer deposition (ALD).

[0059] After the oxide layer is formed, a first pseudo-gate structure, a gate isolation structure, and a second pseudo-gate structure can be formed sequentially on the oxide layer.

[0060] In some embodiments, after forming the dummy gate structure, sidewalls (spacers) can be formed on both sides of the dummy gate structure. Accordingly, the sidewalls also include first sidewalls located on both sides of the first dummy gate structure and second sidewalls located on both sides of the second dummy gate structure. For example, the sidewalls may have a single-layer structure and be made entirely of the same material, such as porous silicon carbide (SICOH).

[0061] Step S120: Etch the first semiconductor structure and the second semiconductor structure located in the source / drain region, and fill the first source / drain region corresponding to the first semiconductor structure with insulating material to form a filled structure.

[0062] Understandably, the semiconductor structure within the source / drain region can be etched away, removing both the first and second semiconductor structures within the region. Since an etched first sacrificial layer and isolation structures on either side of the first sacrificial layer exist below the semiconductor structure and above the substrate, these can also be removed to fully expose the entire source / drain region. The source / drain region can include a first source / drain region corresponding to the first semiconductor and a second source / drain region corresponding to the second semiconductor. After the source / drain region is exposed, insulating material can be filled into the first source / drain region corresponding to the first semiconductor to form a filling structure. This filling structure defines the source / drain region of the back-side transistor, enabling self-alignment of the upper and lower transistor layers in the source / drain region of a flip-chip stacked transistor.

[0063] For example, the insulating material can be silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), etc.

[0064] In addition, in some embodiments, before etching the semiconductor structure in the source / drain region, a second intermediate sacrificial layer located between the first semiconductor structure and the second semiconductor structure may be selectively removed to form a groove, and an insulating material may be filled in the groove to form an intermediate dielectric isolation (MDI) layer, which may serve as an isolation between the front transistor and the back transistor.

[0065] In some embodiments, when an MDI layer is present, the filling structure may cover a portion of the MDI layer when forming the filling structure.

[0066] In some embodiments, after forming the filling structure, a source-drain isolation structure may also be formed on the filling structure, the source-drain isolation structure being used to isolate the first source-drain structure of the first transistor from the second source-drain structure of the second transistor.

[0067] Understandably, after the filling structure is formed, insulating material can be deposited on the filling structure and the insulating material can be thinned so that the upper surface of the formed source-drain isolation structure is flush with the upper surface of the MDI layer.

[0068] Step S130: Form a third semiconductor structure based on the second semiconductor structure through the front-end process.

[0069] In some embodiments, the third semiconductor structure includes a first source-drain structure formed in the second source-drain region.

[0070] Understandably, after etching the semiconductor structure in the source / drain region, a source / drain groove will be formed. Therefore, source / drain epitaxial growth can be performed at the source / drain groove to form the first source / drain structure.

[0071] For example, strained materials such as silicon germanium or silicon carbide can be selectively epitaxially grown in the source-drain trench to fill the source-drain trench of the front-side transistor (first transistor), and then the first source-drain structure can be formed on the strained material by a heavy doping process.

[0072] In some embodiments, after forming the first source / drain structure, an interlayer dielectric can be deposited on the first source / drain structure and thinned to the upper surface of the first source / drain structure to form a first interlayer dielectric layer. In one embodiment, the interlayer dielectric may, for example, be SiO2. Thus, the third semiconductor structure includes the first source / drain structure and the first interlayer dielectric layer.

[0073] For ease of explanation, the first source / drain structure mentioned in the embodiments of this disclosure is an abbreviation, and the first source / drain structure actually refers to the first source structure and / or the first drain structure. In addition, the first source / drain metal, second source / drain structure, second source / drain metal, etc. mentioned later are similar to the first source / drain structure, and the term "source / drain" is an abbreviation for "source and / or drain".

[0074] Step S140: The third semiconductor structure is flipped and the substrate and filler structure are removed to expose the first semiconductor structure.

[0075] In this embodiment of the disclosure, after a portion of the front-side transistor (the third semiconductor structure) is fabricated, a flip-flop is performed to fabricate the back-side transistor.

[0076] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the first interlayer dielectric layer to form a first insulating layer, and the first insulating layer may be bonded to a first carrier wafer, then flipped to place the substrate on top, and the substrate may be removed.

[0077] After removing the substrate, the structure can be filled by selective etching of the material to expose the first source / drain region of the back transistor.

[0078] Understandably, since the filling structure covers the first source / drain region of the back transistor, the filling structure can be selectively etched during the fabrication of the back transistor to expose the first source / drain region. Because the filling structure is used to locate the source / drain region of the back transistor, subsequent fabrication of the back transistor does not require region selection via photolithography; the source / drain region can be directly opened through material selection to fabricate a back transistor that is completely self-aligned with the front transistor.

[0079] In some embodiments, after removing the substrate and before etching the filling structure, a semiconductor material may be filled in the gate region so that the upper surface of the formed dummy gate structure is flush with the upper surface of the sacrificial layer (first sacrificial layer).

[0080] Understandably, since the gate region of the back-side transistor also contains a first sacrificial layer and isolation structures on both sides of the first sacrificial layer, the isolation structures in the gate region can be removed after removing the substrate to expose the first sacrificial layer. Then, materials such as polysilicon can be filled into the etched gate region so that the formed pseudo-gate structure can completely define the gate region of the back-side transistor.

[0081] Step S150: Based on the first semiconductor structure, form a fourth semiconductor structure.

[0082] In some embodiments, the third semiconductor structure can be a complete back-side transistor (the second transistor) or a part of the back-side transistor. The schemes for forming the back-side transistor are described below first.

[0083] In some embodiments, step S150 can be implemented as follows: epitaxially growing a second source / drain structure on the first source / drain region; forming a gate structure of a fourth semiconductor structure based on the first semiconductor structure; depositing metal material on the second source / drain structure to form a second source / drain metal; and performing back-end interconnects on the second source / drain metal through back-end processes to form a second metal interconnect layer.

[0084] Understandably, after etching the filling structure in the first source / drain region, a source / drain groove will be formed. Therefore, source / drain epitaxial growth can be performed at this source / drain groove to form a second source / drain structure.

[0085] In some embodiments, after forming the second source / drain structure, an interlayer medium can be deposited on the second source / drain structure and thinned to the upper surface of the second source / drain structure to form a second interlayer medium layer.

[0086] In the case of forming a second interlayer dielectric layer, a portion of the second interlayer dielectric layer can be etched to expose the second source / drain structure, and then a metallic material can be deposited on the second source / drain structure to form the second source / drain metal.

[0087] In some embodiments, after the second source / drain metal is formed, a subsequent process can be performed to form a second metal interconnect layer.

[0088] Understandably, back-end processes can include interconnect dielectric deposition, metal line formation, and lead-out pad formation. Here, the interconnects and corresponding insulating media of the back-side transistors are made of high-temperature resistant materials, such as tungsten (W) metal, oxides, etc.

[0089] In this embodiment, the gate structure of the first transistor and the gate structure of the second transistor can be formed simultaneously on the back side, and this scheme is described below.

[0090] In the case where a pseudo-gate structure is formed that is shared by the front transistor and the back transistor, the pseudo-gate structure can be removed to form the first gate structure of the first transistor and the second gate structure of the second transistor, respectively.

[0091] Understandably, after forming the second interlayer dielectric layer and before forming the second source / drain metal, the aforementioned dummy gate structure can be removed by etching to obtain a gate trench, where a gate structure shared by the front and back sides is formed. The gate structure may include a gate dielectric layer formed by depositing insulating material at the gate trench, and a gate electrode layer formed by depositing metal material on the gate dielectric layer. The gate structure can then be etched back to the bottom of the back-side transistor, with the retained gate structure serving as the first gate structure of the front-side transistor, and a second gate structure formed in the exposed gate region of the back-side transistor. The first gate structure includes a first gate dielectric layer and a first gate electrode layer, and the second gate structure includes a second gate dielectric layer and a second gate electrode layer.

[0092] For example, the gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor.

[0093] For example, the gate electrode layer may be composed of multiple layers of electrode materials, each layer of which includes, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0094] In the case of a flip-chip stacked transistor as a GAAFET, the first material layer of the formed semiconductor structure is an alternating deposition of silicon and germanium. Therefore, when removing the dummy gate structure, the silicon and germanium material in the semiconductor structure can be removed simultaneously to form a nanosheet structure. This nanosheet structure includes a first nanosheet structure for the front-side transistor and a second nanosheet structure for the back-side transistor.

[0095] In this embodiment, a second gate structure can also be formed separately on the back side. In the case of forming the first pseudo-gate structure, the gate isolation structure and the second pseudo-gate structure as described above, the first pseudo-gate structure can be removed to form the second gate structure.

[0096] In addition, in some embodiments, a second isolation layer may be formed on the second gate structure and the second interlayer dielectric layer before the second source / drain metal is formed. The second isolation layer is used to isolate the second transistor from the second metal interconnect layer.

[0097] Understandably, an insulating material can be deposited on the second gate structure and the second interlayer dielectric layer to form a second isolation layer, which can also be called a pre-metal dielectric (PMD) layer. The PMD layer has the following two functions: (1) Electrical isolation: The PMD layer electrically isolates the transistor device from the metal interconnect layer, preventing current from flowing in unwanted paths and ensuring the normal operation of the circuit; (2) Physical protection: The PMD layer can block impurity sources such as mobile particles (e.g., sodium ions), preventing impurity sources from affecting the performance of the transistor device and protecting the device from the influence of the external environment. Insulating materials forming the PMD layer can be, for example, SiO2, SiN, etc.

[0098] The above describes a scheme where the back-side transistor is fabricated in a single step on the back side. This allows for the subsequent fabrication of the other part of the front-side transistor through a single flip-flop operation. In other words, embodiments of this disclosure can form flip-chip stacked transistors through two flip-flops. In this case, the fourth semiconductor structure includes a second source / drain structure, a second interlayer dielectric layer, a second gate structure, a second source / drain metal, and a second metal interconnect layer.

[0099] In some embodiments, step S150 can be implemented as follows: epitaxially growing a second source / drain structure in the first source / drain region; forming a second gate structure of a fourth semiconductor structure based on the first semiconductor structure.

[0100] In some embodiments, the process of forming a second gate structure based on a first semiconductor structure can be: removing the first pseudo-gate structure to form a second gate structure.

[0101] In the case of a flip-chip stacked transistor as a GAAFET, the first material layer of the formed semiconductor structure is an alternating deposition of silicon germanium and silicon. Therefore, when the first pseudo-gate structure is removed, the silicon germanium material in the first semiconductor structure can also be removed to form the second nanosheet structure.

[0102] In some embodiments, after forming the second source / drain structure and then the second gate structure, an interlayer dielectric can be deposited on the second source / drain structure to form a second interlayer dielectric layer.

[0103] After forming the second gate structure, an insulating material can be deposited on the second gate structure and the second interlayer dielectric layer to form a second isolation layer.

[0104] In this embodiment, a portion of the back-side transistor can be fabricated on the back side, followed by a flip-chip fabrication of the other portion of the front-side transistor, and then another flip-chip fabrication of the other portion of the back-side transistor. That is, this embodiment can also fabricate a flip-chip stacked transistor through three flip-chip fabrications. In this case, the fourth semiconductor structure includes a second source / drain structure, a second interlayer dielectric layer, and a second gate structure.

[0105] Step S160: Based on the third semiconductor structure and the fourth semiconductor structure, form the first transistor and the second transistor respectively.

[0106] In this embodiment of the disclosure, after the back-side transistor or a portion thereof has been fabricated, a flip-chip process is performed to fabricate another portion of the front-side transistor.

[0107] In some embodiments, when a complete back-side transistor is fabricated in step S150 above, the process of forming the first transistor based on the third semiconductor structure can be as follows: after forming the fourth semiconductor structure, the fourth semiconductor structure is flipped to expose the third semiconductor structure; metal material is deposited on the first source / drain structure in the third semiconductor structure to form the first source / drain metal; and back-end interconnects are performed on the first source / drain metal through back-end processes to form the first metal interconnect layer.

[0108] This embodiment of the disclosure decomposes the fabrication process of flip-chip stacked transistors into multiple stages by performing two flip-chip operations, with each stage involving only partial heat treatment. This reduces the impact of a single heat treatment on the device, thereby improving the overall thermal budget. Furthermore, the two flip-chip operations can alter the fabrication sequence of the flip-chip stacked transistor devices and subsequent interconnects, further reducing the impact of heat treatment on device performance and thus improving the thermal budget.

[0109] In some embodiments, after forming the fourth semiconductor structure, an insulating material can be deposited on the fourth semiconductor structure to form a second insulating layer, and the second insulating layer is bonded to a second carrier wafer, and then flipped.

[0110] In some embodiments, after wafer flipping, the first insulating layer and the first wafer layer may be removed to expose a portion of the fabricated front-side transistor (the third semiconductor structure).

[0111] Understandably, after exposing the third semiconductor structure, metal material can be deposited on the first source / drain structure to form the first source / drain metal; and through back-end processes, back-end interconnects can be performed on the first source / drain metal to form the first metal interconnect layer of the first transistor.

[0112] In some embodiments, in the presence of a first interlayer dielectric layer, a portion of the first interlayer dielectric layer may be etched to expose a first source / drain structure, and then a metallic material may be deposited on the first source / drain structure to form a first source / drain metal.

[0113] In addition, if only the second gate structure is formed on the back side as described above, the second dummy gate structure formed above can be removed to form the first gate structure.

[0114] In the case of a flip-chip stacked transistor as a GAAFET, the first material layer of the formed semiconductor structure is an alternating deposition of silicon germanium and silicon. Therefore, when removing the second pseudo-gate structure, the silicon germanium material in the second semiconductor structure can be removed at the same time to form the first nanosheet structure.

[0115] In addition, in some embodiments, a first isolation layer may be formed on the first gate structure and the first interlayer dielectric layer before the first source / drain metal is formed. The first isolation layer is used to isolate the first transistor from the first metal interconnect layer.

[0116] Understandably, insulating material can be deposited on the first gate structure and the first interlayer dielectric layer to form a first isolation layer, which can also be called a PMD layer.

[0117] In addition, if only a portion of the back-side transistor is fabricated in step S150 above, the process of forming the first transistor based on the third semiconductor structure can be as follows: after forming the fourth semiconductor structure, the fourth semiconductor structure is flipped to expose the third semiconductor structure; metal material is deposited on the first source / drain structure in the third semiconductor structure to form the first source / drain metal; and back-end interconnects are performed on the first source / drain metal to form the first metal interconnect layer.

[0118] In some embodiments, the process of forming the second transistor based on the fourth semiconductor structure can be as follows: after forming the first transistor, the first transistor is flipped to expose the fourth semiconductor structure; metal material is deposited on the second source / drain structure in the fourth semiconductor structure to form the second source / drain metal; and back-end interconnects are performed on the second source / drain metal through back-end processes to form the second metal interconnect layer.

[0119] Understandably, after forming the first metal interconnect layer, a third insulating layer can be formed on the first metal interconnect layer, and the third insulating layer can be bonded to the third carrier wafer. Then, the wafer is flipped over, and the second insulating layer and the second carrier wafer are removed to prepare another part of the back-side transistor.

[0120] The embodiments disclosed herein control the thermal budget through three flips, which can achieve better thermal control compared to two flips.

[0121] Furthermore, in embodiments of this disclosure, after forming the gate structure, gate cut-off structures can be formed on both sides of the gate structure. These gate cut-off structures are used to isolate the gate structure of the flip-chip stacked transistor from the gate structures of adjacent flip-chip stacked transistors. Accordingly, the gate cut-off structures include a first gate cut-off structure corresponding to the first gate structure and a second gate cut-off structure corresponding to the second gate structure.

[0122] In this embodiment, a first semiconductor structure and a second semiconductor structure are formed on a substrate. Based on the second semiconductor structure, a portion of a first transistor is first formed, then a flip-chip is performed to form a second transistor based on the first semiconductor structure. This flip-chip process is then repeated to form the other portion of the first transistor. Therefore, this embodiment decomposes the fabrication process of flip-chip stacked transistors into multiple stages through multiple flip-chip operations, with each stage involving only partial heat treatment. This reduces the impact of a single heat treatment on the device, thereby improving the overall thermal budget. Furthermore, multiple flip-chip operations can alter the fabrication sequence of the flip-chip stacked transistor device. By optimizing the fabrication sequence, the impact of heat treatment on device performance can be reduced, further improving the thermal budget.

[0123] In some embodiments, the solutions of this disclosure not only significantly improve transistor stacking density but also address issues such as consistency, defect density, and alignment of the active regions of the front and back transistors. They employ fewer high aspect ratio processes, enabling more compatible full self-aligned flip-chip stacking of various transistor types. The flip-chip stacking transistor solutions in this disclosure are compatible with existing mainstream device architectures, enabling front-to-back stacking of planar transistors, FinFETs, GAA Nanosheets, and even vertical transistors without requiring special process development for specific device architectures. This provides high flexibility and strong scalability from the perspective of semiconductor process node iteration. Flip-chip transistors are conceptually very advanced, possess significant industrial value, and have strong practicality and broad expansion prospects.

[0124] The following describes the fabrication method of the flip-chip stacked transistor provided in this disclosure, taking the active structure of the flip-chip stacked transistor as a nanosheet structure as an example. Figure 2 is a top view of the flip-chip stacked transistor in this disclosure embodiment. It should be noted that, for ease of understanding, only the nanosheet structure, gate structure, and source / drain structure are shown in the top view. Specifically, the AA' direction is the tangential direction of the flip-chip stacked transistor along the gate structure; the BB' direction is the tangential direction of the flip-chip stacked transistor along the source / drain structure; and the CC' direction is the tangential direction of the flip-chip stacked transistor along the nanosheet structure.

[0125] The first fabrication process is described below, in which the gate structures of the front-side transistor and the back-side transistor are formed in a single-sided process, and a flip-chip stacked transistor is formed by two flipping operations. Figures 3A to 3J are schematic diagrams of the flip-chip stacked transistor of the present disclosure in the first fabrication process, and Figure 3K is a schematic diagram of the first structure of the flip-chip stacked transistor of the present disclosure.

[0126] Step 1: A first sacrificial layer 21 is formed on the original substrate 20, a bottom stacked layer 22 is formed on the first sacrificial layer 21, a second sacrificial layer 23 is formed on the bottom stacked layer 22, and a top stacked layer 24 is formed on the second sacrificial layer 23 (see (a) in FIG3A).

[0127] For example, a Si layer 20 can be provided, on which SiGe1 material is deposited to form a first sacrificial layer 21; then, SiGe2 material and Si material are alternately deposited on the first sacrificial layer 21 to form a stack of predetermined thickness, which is the bottom stack layer 22; next, SiGe1 material is deposited on the bottom stack layer 22 to form a second sacrificial layer 23; finally, SiGe2 material and Si material are alternately deposited on the second sacrificial layer 23 to form a stack of predetermined thickness, which is the top stack layer 24. It should be noted that the SiGe1 and SiGe2 materials here are only illustrative examples, and other materials can actually be used.

[0128] Step 2: The top stacked layer 24, the second sacrificial layer 23, the bottom stacked layer 22, and the first sacrificial layer 21 are etched sequentially down to the substrate 20 to form a semiconductor structure (see (b) in Figure 3A).

[0129] Understandably, etching can form a first semiconductor structure 251 close to the substrate and a second semiconductor structure 252 away from the substrate, a second intermediate sacrificial layer 253, and a first intermediate sacrificial layer 254.

[0130] Step 3: Deposit oxide material on substrate 20 to form isolation structure 26, and etch and CMP to the upper surface of the first intermediate sacrificial layer 254 (see (c) in Figure 3A).

[0131] Step 4: The gate region is opened by photolithography, and polysilicon and other materials are deposited in the gate region to form a pseudo gate structure 27 shared by the front and back sides. Sidewalls (spacers) 28 are formed on both sides of the pseudo gate structure, the first semiconductor structure 251, the second semiconductor structure 252 and the second intermediate sacrificial layer 253 (see (a) in Figure 3B).

[0132] By defining the gate regions of the front and back transistors in a flip-chip stacked transistor using a pseudo-gate structure, self-alignment of the upper and lower transistors in the gate regions can be achieved.

[0133] Step 5: Etch sidewall 28 down to the second intermediate sacrificial layer 253 to expose the second semiconductor structure 252 of the front transistor (see (b) in Figure 3B).

[0134] Step 6: Etch the second semiconductor structure in the source and drain regions of the front transistor (see (c) in Figure 3B).

[0135] Step 7: Selectively etch the second intermediate sacrificial layer 253 between the semiconductor structures of the front and back transistors, and fill the etched grooves with insulating material to form the MDI layer 29 (see (a) in Figure 3C).

[0136] Step 8: Laterally etch a portion of the SiGe2 material of the front transistor, fill it with insulating material and etch it to form the first inner spacer 30 located on both sides of the SiGe2 of the front transistor (see (b) in Figure 3C).

[0137] In some embodiments, the eighth step of forming the first inner wall can also be performed simultaneously with the seventh step of forming the MDI layer.

[0138] Step 9: Anisotropic etching removes the sidewalls (spacers) and the first semiconductor structure of the back-side transistor in the source-drain region (see (c) in Figure 3C).

[0139] Step 10: Anisotropically etch the first intermediate sacrificial layer 254 and isolation structure 26 in the source and drain regions (see (a) in Figure 3D).

[0140] Step 11: Fill the source and drain regions with insulating material to form a filling structure 31 covering the source and drain regions of the back transistor (see (b) in Figure 3D).

[0141] Step 12: Form source-drain isolation structure 32 on the filling structure 31 (see (c) in Figure 3D).

[0142] This is a source / drain isolation structure formed on the fill structure. In this embodiment, the fill structure can also be etched after the first wafer flip, and then the source / drain isolation structure can be formed. Alternatively, after the first wafer flip, part of the fill structure can be etched, and the remaining fill structure can be used as the source / drain isolation structure.

[0143] Step 13: Form the first source-drain structure 112 of the front-side transistor (see (a) in Figure 3E).

[0144] Step 14: Deposit interlayer medium in the source / drain region to form the first interlayer medium layer 113 (see (b) in Figure 3E).

[0145] Step 15: Deposit insulating material on the first interlayer dielectric layer 113 to form the first insulating layer 13, and bond the first carrier wafer 14 to the first insulating layer 13 (see (c) in Figure 3E).

[0146] Step 16: First wafer rewind, thinning and CMP removal of substrate 20 (see (a) in Figure 3F).

[0147] Step 17: Selectively etch the isolation structure 26 of the gate region (see (b) in Figure 3F).

[0148] Step 18: Fill the etched area with materials such as polysilicon to supplement the pseudo-gate structure formed above (see (c) in Figure 3F).

[0149] Step 19: Remove the fill structure 31 (see (a) in Figure 3G).

[0150] Step 20: Laterally etch a portion of the SiGe2 material of the back transistor, fill with insulating material and etch to form the second inner sidewall 34 located on both sides of the SiGe2 of the back transistor (see (b) in Figure 3G).

[0151] Step 21: Form the second source-drain structure 122 and the second interlayer dielectric layer 123 of the back transistor (see (c) in Figure 3G).

[0152] Step 22: Remove pseudo-gate structure 27 (see (a) in Figure 3H).

[0153] Step 23: Remove the SiGe2 material and the first intermediate sacrificial layer from the first semiconductor structure and the second semiconductor structure to form the first nanosheet structure 111 and the second nanosheet structure 121, and form the first gate structure 114 based on the first nanosheet structure 111 and the second gate structure 124 based on the second nanosheet structure 121 (see (b) in Figure 3H).

[0154] Understandably, an insulating material can be deposited on the surface of the first nanosheet structure 111 to form a first gate dielectric layer 1141. A metal material can then be deposited on the first gate dielectric layer 1141 within the gate region to form a first gate electrode layer 1142. The first gate dielectric layer 1141 and the first gate electrode layer 1142 constitute the first gate structure 114. Similarly, an insulating material can be deposited on the surface of the second nanosheet structure 121 to form a second gate dielectric layer 1241. A metal material can then be deposited on the second gate dielectric layer 1241 within the gate region to form a second gate electrode layer 1242. The second gate dielectric layer 1241 and the second gate electrode layer 1242 constitute the second gate structure 124. Therefore, in this embodiment, the gate structure of the front-side transistor and the gate structure of the back-side transistor are formed in a single step on the back side.

[0155] Step 24: A second isolation layer 35 is formed on the second gate structure 124 and the second interlayer dielectric layer 123, and a second source / drain metal 125 is formed on the second source / drain structure 122 (see (c) in Figure 3H).

[0156] Step 25: Perform back-end interconnection to form the second metal interconnect layer 126 (see (a) in Figure 3I).

[0157] The back-end interconnects and corresponding insulating media of the transistors on the back side are made of high-temperature resistant materials, such as W, oxides, etc.

[0158] Step 26: Deposit insulating material on the second metal interconnect layer 126 to form the second insulating layer 15, bond the second carrier wafer 16 to the second insulating layer 15, and perform the second wafer flipping (see (b) in Figure 3I).

[0159] Step 27: Thinning and CMP removal of the first insulating layer 13 and the first carrier wafer 14 (see (a) in Figure 3J).

[0160] Step 28: A first isolation layer 36 is formed on the first gate structure 114 and the first interlayer dielectric layer 113, and a first source / drain metal 115 is formed on the first source / drain structure 112 (see (b) in Figure 3J).

[0161] Step 29: Perform back-end interconnection to form the first metal interconnect layer 116 (see Figure 3K).

[0162] It should be noted that, in this embodiment of the present disclosure, the MDI layer may not be formed. In the absence of an MDI layer, the aforementioned second intermediate sacrificial layer 253 may be made of Si material. Furthermore, in the aforementioned fifth step, the sidewalls 28 may be etched to the area above the second intermediate sacrificial layer 253, approximately to the bottom left or right of the second semiconductor structure 252. In this case, the sidewalls 28 may serve to restrict the growth of the source and drain structures of the first transistor.

[0163] The second fabrication process is described below, in which the gate structures of the front-side transistor and the back-side transistor are formed on both sides, and a flip-chip stacked transistor is formed by two flip-chip operations. Figures 4A to 4G are schematic diagrams of the flip-chip stacked transistor of the present disclosure in the second fabrication process, and Figure 4H is a schematic diagram of the second structure of the flip-chip stacked transistor of the present disclosure.

[0164] Step 1: A first sacrificial layer 21 is formed on the original substrate 20, a bottom stacked layer 22 is formed on the first sacrificial layer 21, a second sacrificial layer 23 is formed on the bottom stacked layer 22, and a top stacked layer 24 is formed on the second sacrificial layer 23 (see (a) in FIG4A).

[0165] For example, a Si layer 20 can be provided, on which SiGe1 material is deposited to form a first sacrificial layer 21; then, SiGe2 material and Si material are alternately deposited on the first sacrificial layer 21 to form a stack of predetermined thickness, which is the bottom stack layer 22; next, SiGe1 material is deposited on the bottom stack layer 22 to form a second sacrificial layer 23; finally, SiGe2 material and Si material are alternately deposited on the second sacrificial layer 23 to form a stack of predetermined thickness, which is the top stack layer 24. It should be noted that the SiGe1 material here is only an exemplary illustration, and other materials can actually be used.

[0166] Step 2: The top stacked layer 24, the second sacrificial layer 23, the bottom stacked layer 22, and the first sacrificial layer 21 are etched sequentially down to the substrate 20 to form a semiconductor structure (see (b) in Figure 4A).

[0167] Understandably, etching can form a first semiconductor structure 251 close to the substrate and a second semiconductor structure 252 away from the substrate, a second intermediate sacrificial layer 253, and a first intermediate sacrificial layer 254.

[0168] Step 3: Deposit oxide material on substrate 20 to form isolation structure 26, and etch and CMP to the upper surface of the first intermediate sacrificial layer 254 (see (c) in Figure 4A).

[0169] Step 4: Form oxide layer 37 on the substrate (see (a) in Figure 4B).

[0170] Understandably, oxide layer 37 is a thin film deposited on the surfaces of the first semiconductor structure 251, the second semiconductor structure 252, and the second intermediate sacrificial layer 253.

[0171] Step 5: Deposit polysilicon or other materials on oxide layer 37 and etch them back to the top of first semiconductor structure 251 to form first pseudo-gate structure 38 surrounding first semiconductor structure 251 (see (b) in Figure 4B).

[0172] Step 6: Deposit insulating material on the first pseudo-gate structure 38 and etch it back to the bottom of the second semiconductor structure to form the gate isolation structure 39 (see (c) in Figure 4B).

[0173] Step 7: Form a second pseudo-gate structure 40 surrounding the second semiconductor structure 252 on the gate isolation structure 39 (see (a) in Figure 4C).

[0174] Understandably, the height of the second pseudo-gate structure 40 is higher than the height of the second semiconductor structure 252.

[0175] Step 8: Photolithography is used to etch the pseudo-gate structure on the front and back sides and the gate isolation structure in the middle of the source and drain areas, and sidewalls 28 are deposited (see (b) in Figure 4C).

[0176] Step 9: Etch sidewall 28 down to the second intermediate sacrificial layer 253 to expose the second semiconductor structure 252 of the front transistor (see (c) in Figure 4C).

[0177] Step 10: Etch the second semiconductor structure in the source / drain region of the front-side transistor (see (a) in Figure 4D).

[0178] Step 11: Selectively etch the second intermediate sacrificial layer 253 between the semiconductor structures of the front and back transistors, and fill the etched grooves with insulating material to form the MDI layer 29 (see (b) in Figure 4D).

[0179] Step 12: Laterally etch a portion of the SiGe2 material of the front transistor, fill it with insulating material and etch it to form the first inner spacer 30 located on both sides of the SiGe2 of the front transistor (see (c) in Figure 4D).

[0180] Step 13: Anisotropic etching removes the sidewalls (spacers) and the first semiconductor structure of the back-side transistor in the source-drain region (see (a) in Figure 4E).

[0181] Step 14: Anisotropically etch the first intermediate sacrificial layer 254 and isolation structure 26 in the source / drain region (see (b) in Figure 4E).

[0182] Step 15: Fill the source and drain regions with insulating material to form a filling structure 31 covering the source and drain regions of the back transistor (see (c) in Figure 4E).

[0183] Step 16: Form source-drain isolation structure 32 on the filling structure 31 (see (a) in Figure 4F).

[0184] Step 17: Form the first source-drain structure 112 of the front-side transistor (see (b) in Figure 4F).

[0185] Step 18: Deposit interlayer medium in the source / drain region to form the first interlayer medium layer 113 (see (c) in Figure 4F).

[0186] Step 19: Deposit insulating material on the first interlayer dielectric layer 113 to form the first insulating layer 13, bond the first carrier wafer 14 to the first insulating layer 13, and perform the first wafer flipping (see (a) in Figure 4G).

[0187] Step 20: Form the back transistor and the second metal interconnect layer 126 according to the standard process flow (see (b) in Figure 4G).

[0188] Understandably, the substrate 20 can be removed first, and the isolation structure 26 of the gate region can be selectively etched. Polysilicon or other materials can be filled in the etched area to supplement the aforementioned pseudo-gate structure. The filling structure can be removed, and a portion of the SiGe2 material of the back transistor can be etched laterally. An insulating material can be filled and etched to form the second inner sidewall 34 on both sides of the SiGe2 of the back transistor, forming the second source / drain structure 122 and the second interlayer dielectric layer 123 of the back transistor. Then, the first pseudo-gate structure 38 can be removed, and the SiGe2 material in the first semiconductor structure can be removed to form the second nanosheet structure 121. The second gate structure 124 can be formed based on the second nanosheet structure 121. The second isolation layer 35 can be formed on the second gate structure 124 and the second interlayer dielectric layer 123, and the second source / drain metal 125 can be formed on the second source / drain structure 122. Back-end interconnection can be performed to form the second metal interconnect layer 126.

[0189] In addition, embodiments of this disclosure may also form a second gate cut-off structure 41 on both sides of the second gate structure 124.

[0190] Step 21: Deposit insulating material on the second metal interconnect layer 126 to form the second insulating layer 15, bond the second carrier wafer 16 to the second insulating layer 15, and perform the second wafer flipping (see (c) in Figure 4G).

[0191] Step 22: Form the front transistor and the first metal interconnect layer 116 according to the standard process flow (see Figure 4H).

[0192] Understandably, the process involves first thinning and CMP removal of the first insulating layer 13 and the first carrier wafer 14, then removing the second dummy gate structure 40, removing the SiGe2 material from the second semiconductor structure to form a first nanosheet structure 111, and forming a first gate structure 114 based on the first nanosheet structure 111. A first isolation layer 36 is formed on the first gate structure 114 and the first interlayer dielectric layer 113, and a first source / drain metal 115 is formed on the first source / drain structure 112. Back-end interconnects are then performed to form a first metal interconnect layer 116.

[0193] In addition, embodiments of this disclosure may also form a first gate cut-off structure 42 on both sides of the first gate structure 114.

[0194] The third fabrication process is described below, in which the gate structures of the front-side transistor and the back-side transistor are formed in a single-sided process, and a flip-chip stacked transistor is formed through three flip-chip operations. Figures 5A to 5I are schematic diagrams of the flip-chip stacked transistor of the present disclosure in the third fabrication process, and Figure 5J is a schematic diagram of the third structure of the flip-chip stacked transistor of the present disclosure.

[0195] Step 1: A first sacrificial layer 21 is formed on the original substrate 20, a bottom stacked layer 22 is formed on the first sacrificial layer 21, a second sacrificial layer 23 is formed on the bottom stacked layer 22, and a top stacked layer 24 is formed on the second sacrificial layer 23 (see (a) in FIG5A).

[0196] For example, a Si layer 20 can be provided, on which SiGe1 material is deposited to form a first sacrificial layer 21; then, SiGe2 material and Si material are alternately deposited on the first sacrificial layer 21 to form a stack of predetermined thickness, which is the bottom stack layer 22; next, SiGe1 material is deposited on the bottom stack layer 22 to form a second sacrificial layer 23; finally, SiGe2 material and Si material are alternately deposited on the second sacrificial layer 23 to form a stack of predetermined thickness, which is the top stack layer 24. It should be noted that the SiGe1 and SiGe2 materials here are only illustrative examples, and other materials can actually be used.

[0197] Step 2: The top stacked layer 24, the second sacrificial layer 23, the bottom stacked layer 22, and the first sacrificial layer 21 are etched sequentially down to the substrate 20 to form a semiconductor structure (see (b) in Figure 5A).

[0198] Understandably, etching can form a first semiconductor structure 251 close to the substrate and a second semiconductor structure 252 away from the substrate, a second intermediate sacrificial layer 253, and a first intermediate sacrificial layer 254.

[0199] Step 3: Deposit oxide material on substrate 20 to form isolation structure 26, and etch and CMP to the upper surface of the first intermediate sacrificial layer 254 (see (c) in Figure 5A).

[0200] Step 4: The gate region is opened by photolithography, and materials such as polysilicon are deposited in the gate region to form a pseudo gate structure 27 shared by the front and back sides. Sidewalls (spacers) 28 are formed on both sides of the pseudo gate structure, the first semiconductor structure 251, the second semiconductor structure 252 and the second intermediate sacrificial layer 253 (see (a) in Figure 5B).

[0201] By defining the gate regions of the front and back transistors in a flip-chip stacked transistor using a pseudo-gate structure, self-alignment of the upper and lower transistors in the gate regions can be achieved.

[0202] Step 5: Etch sidewall 28 down to the second intermediate sacrificial layer 253 to expose the second semiconductor structure 252 of the front transistor (see (b) in Figure 5B).

[0203] Step 6: Etch the second semiconductor structure in the source and drain regions of the front transistor (see (c) in Figure 5B).

[0204] Step 7: Selectively etch the second intermediate sacrificial layer 253 between the semiconductor structures of the front and back transistors, and fill the etched grooves with insulating material to form the MDI layer 29 (see (a) in Figure 5C).

[0205] Step 8: Laterally etch a portion of the SiGe2 material of the front transistor, fill it with insulating material and etch it to form the first inner spacer 30 located on both sides of the SiGe2 of the front transistor (see (b) in Figure 5C).

[0206] In some embodiments, the eighth step of forming the first inner wall can also be performed simultaneously with the seventh step of forming the MDI layer.

[0207] Step 9: Anisotropic etching removes the sidewalls (spacers) and the first semiconductor structure of the back-side transistor in the source-drain region (see (c) in Figure 5C).

[0208] Step 10: Anisotropically etch the first intermediate sacrificial layer 254 and isolation structure 26 in the source and drain regions (see (a) in Figure 5D).

[0209] Step 11: Fill the source and drain regions with insulating material to form a filling structure 31 covering the source and drain regions of the back transistor (see (b) in Figure 5D).

[0210] Step 12: Form source-drain isolation structure 32 on the filling structure 31 (see (c) in Figure 5D).

[0211] It should be noted that the source / drain isolation structure here is formed on the filling structure. In this embodiment, the filling structure can also be etched after the first wafer flip, and then the source / drain isolation structure can be formed. Alternatively, after the first wafer flip, part of the filling structure can be etched, and the remaining filling structure can be used as the source / drain isolation structure.

[0212] Step 13: Form the first source-drain structure 112 of the front-side transistor (see (a) in Figure 5E).

[0213] Step 14: Deposit interlayer medium in the source / drain region to form the first interlayer medium layer 113 (see (b) in Figure 5E).

[0214] Step 15: Deposit insulating material on the first interlayer dielectric layer 113 to form the first insulating layer 13, bond the first carrier wafer 14 to the first insulating layer 13, and perform the first wafer flipping (see (c) in Figure 5E).

[0215] Step 16: Thin and CMP remove substrate 20 (see (a) in Figure 5F).

[0216] Step 17: Selectively etch the isolation structure 26 of the gate region (see (b) in Figure 5F).

[0217] Step 18: Fill the etched area with materials such as polysilicon to supplement the pseudo-gate structure formed above (see (c) in Figure 5F).

[0218] Step 19: Remove the fill structure 31 (see (a) in Figure 5G).

[0219] Step 20: Laterally etch a portion of the SiGe2 material of the back transistor, fill with insulating material and etch to form the second inner sidewall 34 located on both sides of the SiGe2 of the back transistor (see (b) in Figure 5G).

[0220] Step 21: Form the second source-drain structure 122 and the second interlayer dielectric layer 123 of the back transistor (see (c) in Figure 5G).

[0221] Step 22: Remove pseudo-gate structure 27 (see (a) in Figure 5H).

[0222] Step 23: Remove the SiGe2 material and the first intermediate sacrificial layer from the first semiconductor structure and the second semiconductor structure to form the first nanosheet structure 111 and the second nanosheet structure 121, and form the first gate structure 114 based on the first nanosheet structure 111 and the second gate structure 124 based on the second nanosheet structure 121 (see (b) in Figure 5H).

[0223] Understandably, an insulating material can be deposited on the surface of the first nanosheet structure 111 to form a first gate dielectric layer 1141. A metal material can then be deposited on the first gate dielectric layer 1141 within the gate region to form a first gate electrode layer 1142. The first gate dielectric layer 1141 and the first gate electrode layer 1142 constitute the first gate structure 114. Similarly, an insulating material can be deposited on the surface of the second nanosheet structure 121 to form a second gate dielectric layer 1241. A metal material can then be deposited on the second gate dielectric layer 1241 within the gate region to form a second gate electrode layer 1242. The second gate dielectric layer 1241 and the second gate electrode layer 1242 constitute the second gate structure 124. Therefore, in this embodiment, the gate structure of the front-side transistor and the gate structure of the back-side transistor are formed in a single step on the back side.

[0224] Step 24: Deposit insulating material on the second gate structure 124 and the second interlayer dielectric layer 123 to form a second insulating layer 15. Bond the second carrier wafer 16 to the second insulating layer 15 and perform a second wafer flip (see (c) in Figure 5H).

[0225] Step 25: Remove the first insulating layer 13 and the first carrier wafer 14, and then form the first isolation layer 36, the first source / drain metal 115 and the first metal interconnect layer 116 according to the standard process flow (see (a) in Figure 5I).

[0226] Step 26: Deposit insulating material on the first metal interconnect layer 116 to form the third insulating layer 17, bond the third carrier wafer 18 to the third insulating layer 17, and perform the third wafer flip (see (b) in Figure 5I).

[0227] Step 27: Remove the second insulating layer 15 and the second carrier wafer 16, and then form the first isolation layer 36, the first source / drain metal 115 and the first metal interconnect layer 116 according to the standard process flow (see Figure 5J).

[0228] The fourth fabrication process is described below, in which the gate structures of the front-side transistor and the back-side transistor are formed on both sides, and a flip-chip stacked transistor is formed through three flip-chip operations. Figures 6A to 6H are schematic diagrams of the flip-chip stacked transistor in the fourth fabrication process according to an embodiment of the present disclosure, and Figure 6I is a schematic diagram of the fourth structure of the flip-chip stacked transistor according to an embodiment of the present disclosure.

[0229] Step 1: A first sacrificial layer 21 is formed on the original substrate 20, a bottom stacked layer 22 is formed on the first sacrificial layer 21, a second sacrificial layer 23 is formed on the bottom stacked layer 22, and a top stacked layer 24 is formed on the second sacrificial layer 23 (see (a) in FIG6A).

[0230] For example, a Si layer 20 can be provided, on which SiGe1 material is deposited to form a first sacrificial layer 21; then, SiGe2 material and Si material are alternately deposited on the first sacrificial layer 21 to form a stack of predetermined thickness, which is the bottom stack layer 22; next, SiGe1 material is deposited on the bottom stack layer 22 to form a second sacrificial layer 23; finally, SiGe2 material and Si material are alternately deposited on the second sacrificial layer 23 to form a stack of predetermined thickness, which is the top stack layer 24. It should be noted that the SiGe1 material here is only an exemplary illustration, and other materials can actually be used.

[0231] Step 2: Etch the top stacked layer 24, the second sacrificial layer 23, the bottom stacked layer 22, and the first sacrificial layer 21 sequentially up to the substrate 20 to form a semiconductor structure (see (b) in Figure 6A).

[0232] Understandably, etching can form a first semiconductor structure 251 close to the substrate and a second semiconductor structure 252 away from the substrate, a second intermediate sacrificial layer 253, and a first intermediate sacrificial layer 254.

[0233] Step 3: Deposit oxide material on substrate 20 to form isolation structure 26, and etch and CMP to the upper surface of the first intermediate sacrificial layer 254 (see (c) in Figure 6A).

[0234] Step 4: Form oxide layer 37 on the substrate (see (a) in Figure 6B).

[0235] Step 5: Deposit polysilicon or other materials on oxide layer 37 and etch them back to the top of first semiconductor structure 251 to form first pseudo-gate structure 38 surrounding first semiconductor structure 251 (see (b) in Figure 6B).

[0236] Step 6: Deposit insulating material on the first dummy gate structure 38 and etch it back to the bottom of the second semiconductor structure to form the gate isolation structure 39 (see (c) in Figure 6B).

[0237] Step 7: Form a second pseudo-gate structure 40 surrounding the second semiconductor structure 252 on the gate isolation structure 39 (see (a) in FIG6C).

[0238] Step 8: Photolithography is used to etch the pseudo-gate structure on the front and back sides and the gate isolation structure in the middle of the source and drain areas, and sidewalls 28 are deposited (see (b) in Figure 6C).

[0239] Step 9: Etch sidewall 28 down to the second intermediate sacrificial layer 253 to expose the second semiconductor structure 252 of the front transistor (see (c) in Figure 6C).

[0240] Step 10: Etch the second semiconductor structure in the source / drain region of the front-side transistor (see (a) in Figure 6D).

[0241] Step 11: Selectively etch the second intermediate sacrificial layer 253 between the semiconductor structures of the front and back transistors, and fill the etched grooves with insulating material to form the MDI layer 29 (see (b) in Figure 6D).

[0242] Step 12: Laterally etch a portion of the SiGe2 material of the front transistor, fill it with insulating material and etch it to form the first inner spacer 30 located on both sides of the SiGe2 of the front transistor (see (c) in Figure 6D).

[0243] Step 13: Anisotropic etching removes the sidewalls (spacers) and the first semiconductor structure of the back-side transistor in the source-drain region (see (a) in Figure 6E).

[0244] Step 14: Anisotropically etch the first intermediate sacrificial layer 254 and isolation structure 26 in the source / drain region (see (b) in Figure 6E).

[0245] Step 15: Fill the source and drain regions with insulating material to form a filling structure 31 covering the source and drain regions of the back transistor (see (c) in Figure 6E).

[0246] Step 16: Form source-drain isolation structure 32 on the filling structure 31 (see (a) in Figure 6F).

[0247] Step 17: Form the first source-drain structure 112 of the front-side transistor (see (b) in Figure 6F).

[0248] Step 18: Deposit interlayer medium in the source / drain region to form the first interlayer medium layer 113 (see (c) in Figure 6F).

[0249] Step 19: Deposit insulating material on the first interlayer dielectric layer 113 to form the first insulating layer 13, and bond the first carrier wafer 14 to the first insulating layer 13 to perform the first wafer flip (see (a) in Figure 6G).

[0250] Step 20: Form the gate structure and gate cut-off structure of the back transistor according to the standard process flow (see (b) in Figure 6G).

[0251] Understandably, the substrate 20 can be removed first, and the isolation structure 26 of the gate region can be selectively etched. Polysilicon or other materials can be filled in the etched area to supplement the aforementioned pseudo-gate structure. The filling structure can be removed, and a portion of the SiGe2 material of the back transistor can be etched laterally. An insulating material can be filled and etched to form the second inner sidewall 34 on both sides of the SiGe2 of the back transistor, forming the second source / drain structure 122 and the second interlayer dielectric layer 123 of the back transistor. Then, the first pseudo-gate structure 38 can be removed, and the SiGe2 material in the first semiconductor structure can be removed to form the second nanosheet structure 121, and the second gate structure 124 can be formed based on the second nanosheet structure 121. The second gate cut-off structure 41 can be formed on both sides of the second gate structure 124.

[0252] Step 21: Deposit insulating material on the gate structure and gate cut-off structure of the back transistor to form a second insulating layer 15, bond the second carrier wafer 16 to the second insulating layer 15, and perform a second wafer flip (see (c) in Figure 6G).

[0253] Step 22: Form the first gate structure 114, the first source / drain metal 115 and the first metal interconnect layer 116 of the front transistor according to the standard process flow (see (a) in Figure 6H).

[0254] Understandably, the process involves first thinning and CMP removal of the first insulating layer 13 and the first carrier wafer 14, then removing the second dummy gate structure 40 and the SiGe2 material in the second semiconductor structure to form a first nanosheet structure 111, and forming a first gate structure 114 based on the first nanosheet structure 111. A first gate cut-off structure 42 is formed on both sides of the first gate structure 114, a first isolation layer 36 is formed on the first gate structure 114 and the first interlayer dielectric layer 113, and a first source / drain metal 115 is formed on the first source / drain structure 112. Back-end interconnects are then performed to form a first metal interconnect layer 116.

[0255] Step 23: Deposit insulating material on the first metal interconnect layer 116 to form the third insulating layer 17, bond the third carrier wafer 18 to the third insulating layer 17, and perform the third wafer flip (see (b) in Figure 6H).

[0256] Step 24: Remove the second insulating layer 15 and the second carrier wafer 16, and then form the second isolation layer 35, the second source / drain metal 125 and the second metal interconnect layer 126 according to the standard process flow (see Figure 6I).

[0257] In this embodiment, the gate structure of the flip-chip stacked transistor can be formed in one step on the back side or separately on the front and back sides. An isolation structure (i.e., a gate isolation structure) may or may not be present between the gate structure of the front transistor and the gate structure of the back transistor. Gate cut-off structures may or may not be formed on both sides of the gate structure. If a gate cut-off structure is formed, it can be formed in one step on the back side, one step on the front side, or separately on the front and back sides. An isolation structure (i.e., a source-drain isolation structure) may or may not be present between the source-drain structure of the front transistor and the source-drain structure of the back transistor. If a source-drain isolation structure is present, it can be formed on the front side or the back side. The source-drain isolation structure can be formed by depositing an additional isolation material or by using the filling structure retained after etching as the source-drain isolation structure. In this embodiment, the method of forming the gate structure is completely independent of the method of forming the source-drain region; various methods of forming both can be combined, and this embodiment does not limit this. In addition, the embodiments of this disclosure may or may not form an MDI layer. In the case of not forming an MDI layer, in the first step of the above-mentioned preparation process, after forming the bottom stacked layer 22, the second sacrificial layer 23 is not formed, and the top stacked layer 24 can be formed directly on the bottom stacked layer 22.

[0258] In some embodiments, the flip-chip stacked transistors provided in this disclosure can be inspected using analytical instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, the structure of the flip-chip stacked transistors can be inspected by TEM slicing.

[0259] This disclosure provides a semiconductor device, including: a flip-chip stacked transistor as described in the above embodiments.

[0260] This disclosure provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device being disposed on the circuit board. The semiconductor device includes the flip-chip stacked transistors described above.

[0261] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0262] The above description is merely an exemplary embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a flip-chip stacked transistor, comprising: A first semiconductor structure and a second semiconductor structure are formed sequentially stacked on a substrate; The first semiconductor structure and the second semiconductor structure located in the source and drain regions are etched, and insulating material is filled in the first source and drain regions corresponding to the first semiconductor structure to form a filled structure; A third semiconductor structure is formed based on the second semiconductor structure through a front-end process. The third semiconductor structure includes a first source-drain structure formed in the second source-drain region, and the second source-drain region corresponds to the second semiconductor structure. The third semiconductor structure is flipped, and the substrate and the filling structure are removed to expose the first semiconductor structure, which includes the first source / drain region. Based on the first semiconductor structure, a fourth semiconductor structure is formed, the fourth semiconductor structure including at least a second source-drain structure formed in the first source-drain region; Based on the third semiconductor structure and the fourth semiconductor structure, a first transistor and a second transistor are formed, respectively.

2. The method according to claim 1, wherein, The formation of a fourth semiconductor structure based on the first semiconductor structure includes: The second source / drain structure is epitaxially grown at the first source / drain region; The process of forming the first transistor based on the third semiconductor structure includes: After forming the fourth semiconductor structure, the fourth semiconductor structure is flipped to expose the third semiconductor structure; Metal material is deposited on the first source / drain structure in the third semiconductor structure to form the first source / drain metal; A back-end interconnect is performed on the first source / drain metal using a back-end process to form a first metal interconnect layer.

3. The method according to claim 2, wherein, The process of forming a second transistor based on the fourth semiconductor structure includes: After the first transistor is formed, the first transistor is flipped to expose the fourth semiconductor structure; Metal material is deposited on the second source / drain structure in the fourth semiconductor structure to form the second source / drain metal; A second metal interconnect layer is formed by performing a back-end interconnect on the second source / drain metal using a back-end process.

4. The method according to claim 1, wherein, The formation of a fourth semiconductor structure based on the first semiconductor structure includes: The second source / drain structure is epitaxially grown at the first source / drain region; Based on the first semiconductor structure, the gate structure of the fourth semiconductor structure is formed; Metal is deposited on the second source / drain structure to form the second source / drain metal; A second metal interconnect layer is formed by performing a back-end interconnect on the second source / drain metal through a back-end process. The process of forming the first transistor based on the third semiconductor structure includes: After forming the fourth semiconductor structure, the fourth semiconductor structure is flipped to expose the third semiconductor structure; Metal material is deposited on the first source / drain structure in the third semiconductor structure to form the first source / drain metal; A back-end interconnect is performed on the first source / drain metal using a back-end process to form a first metal interconnect layer.

5. The method according to claim 1, wherein, Before etching the first and second semiconductor structures located in the source / drain regions, the method further includes: An isolation structure is formed on the substrate to expose the first semiconductor structure and the second semiconductor structure; Semiconductor material is deposited on the isolation structure to form a pseudo-gate structure surrounding the first semiconductor structure and the second semiconductor structure; The formation of a fourth semiconductor structure based on the first semiconductor structure includes: The second source / drain structure is epitaxially grown at the first source / drain region; The pseudo-gate structure is removed to form the first gate structure of the third semiconductor structure and the second gate structure of the fourth semiconductor structure, respectively.

6. The method according to claim 1, wherein, Before etching the first and second semiconductor structures located in the source / drain regions, the method further includes: An isolation structure is formed on the substrate to expose the first semiconductor structure and the second semiconductor structure; Semiconductor material is deposited on the isolation structure to form a first pseudo-gate structure surrounding the first semiconductor structure; A gate isolation structure is formed on the first pseudo-gate structure; Semiconductor material is deposited on the gate isolation structure to form a second pseudo-gate structure surrounding the second semiconductor structure; The formation of a fourth semiconductor structure based on the first semiconductor structure includes: The second source / drain structure is epitaxially grown at the first source / drain region; The first pseudo-gate structure is removed to form the second gate structure of the fourth semiconductor structure.

7. The method according to claim 6, wherein, The process of forming the first transistor based on the third semiconductor structure includes: After forming the fourth semiconductor structure, the fourth semiconductor structure is flipped to expose the third semiconductor structure; Remove the second pseudo-gate structure to form the first gate structure of the first transistor; Metal material is deposited on the first source / drain structure in the third semiconductor structure to form the first source / drain metal; A back-end interconnect is performed on the first source / drain metal using a back-end process to form a first metal interconnect layer.

8. A flip-chip stacked transistor, said flip-chip stacked transistor being fabricated using the method of any one of claims 1 to 7, said flip-chip stacked transistor comprising: First transistor; The second transistor is positioned opposite to the first transistor and the second transistor. The second semiconductor structure of the first transistor is self-aligned with the first semiconductor structure of the second transistor, and the first source-drain structure of the first transistor is self-aligned with the second source-drain structure of the second transistor in the vertical direction.

9. A semiconductor device, wherein, include: The flip-chip stacked transistor as described in claim 8.

10. An electronic device, wherein, include: The circuit board and the semiconductor device as described in claim 9, wherein the semiconductor device is disposed on the circuit board.

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