Interface circuit and chip, and electronic device

Abstract

The present application relates to the field of interface circuits, and provides an interface circuit and a chip, and an electronic device, which can enhance the ESD design window by means of circuit design. The interface circuit comprises a control circuit, a previous-stage driving circuit, and a subsequent-stage driving circuit. The control circuit is connected to the previous-stage driving circuit. The previous-stage driving circuit comprises a first output end, a second output end, a third output end, and a fourth output end. The subsequent-stage driving circuit comprises a second P-type transistor, a first P-type transistor, a first N-type transistor and a second N-type transistor which are connected between a high-level power supply line and a low-level power supply line in a complementary-symmetric manner, and gates of the four transistors are respectively connected to the first output end, the second output end, the third output end and the fourth output end. Under the control of a high pulse voltage on the high-level power supply line, the control circuit controls the second output end and the third output end of the previous-stage driving circuit to float, the first output end to output a high level, and the fourth output end to output a low level.

Description

Interface Circuit, Chip, and Electronic Device Technical Field

[0001] This application relates to the field of interface circuits, and particularly to an interface circuit, a chip, and an electronic device. Background Art

[0002] To protect a chip from being damaged by electrostatic discharge (ESD), the chip design process must strictly comply with the constraints of ESD design rules: 1) the size of the ESD protection device; 2) the robustness of the ESD discharge path; 3) the point-to-point (P2P) resistance on the ESD discharge path. In addition, designers engaged in interface / ESD design also need to ensure that the ESD protection device operates within a pre-designed ESD design window.

[0003] Referring to FIG. 1, the ESD design window defines the voltage and current ranges within which the ESD protection device can operate normally during an ESD event. It is jointly determined by the operating voltage (V DD ) of the protected circuit, the breakdown voltage (Vbd), the turn-on voltage (Vt1) of the ESD protection device, the snapback voltage (Vsp), the secondary breakdown voltage (Vt2), etc. The ESD protection device needs to be triggered and turned on at a voltage higher than the normal circuit operating voltage, and also needs to fail before reaching the breakdown voltage of the protected device. That is, we need to ensure that Vsp > V DD , Vt1 < Vt2 < Vbd, and leave sufficient margin.

[0004] However, as the process nodes become more and more advanced, the channel length and gate oxide thickness of the device continue to decrease, and the breakdown voltage (Vbd) continues to decrease, resulting in a narrower ESD design window, a smaller design margin, and poorer robustness. Summary of the Invention

[0005] This application provides an interface circuit, a chip, and an electronic device, which can improve the ESD design window of the chip through circuit design.

[0006] This application provides an interface circuit, comprising: a high-level power line, a low-level power line, and a control circuit, a pre-stage driving circuit, and a post-stage driving circuit connected to the high-level power line and the low-level power line. The control circuit is connected to the pre-stage driving circuit. The pre-stage driving circuit includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The post-stage driving circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor. The source of the second P-type transistor is connected to the high-level power line, the drain of the second P-type transistor is connected to the source of the first P-type transistor, and the gate of the second P-type transistor is connected to the first output terminal; the drain of the first P-type transistor is connected to a chip pad, and the gate of the first P-type transistor is connected to the second output terminal. The source of the second N-type transistor is connected to the low-level power line, the drain of the second N-type transistor is connected to the source of the first N-type transistor, and the gate of the second N-type transistor is connected to the fourth output terminal; the drain of the first N-type transistor is connected to a pad, and the gate of the first N-type transistor is connected to the third output terminal. Under the control of a high pulse voltage on the high-level power supply line, the control circuit controls the second and third output terminals of the pre-stage driver circuit to be left floating, the first output terminal to output a high level, and the fourth output terminal to output a low level.

[0007] Using the novel interface circuit of this application, when an ESD event occurs, the subsequent drive circuit is driven into ESD protection mode under the control of the control circuit and the front-end drive circuit. At this time, the gates of the first P-type transistor and the first N-type transistor are floating, and both the second P-type transistor and the second N-type transistor are cut off. Under these conditions, the connection pad can be coupled to an intermediate voltage level through the first P-type transistor and the first N-type transistor, thereby reducing the voltage level that the first P-type transistor and the first N-type transistor can withstand to about half (i.e., half of what it was before the connection pad was coupled). In other words, by changing the circuit design, the relative breakdown voltage that the circuit can withstand is significantly increased, improving the channel and gate oxide (GOX) withstand voltage of the device, and thus enhancing the ESD design window of the chip.

[0008] In some possible implementations, the subsequent driver circuit also includes a first diode and a second diode. The anode of the first diode is connected to the pad, and the cathode is connected to the high-level power supply line; the anode of the second diode is connected to the low-level power supply line, and the cathode of the first diode is connected to the pad. When an ESD event occurs, a large amount of charge accumulates on the pad, which is transferred through the first diode to the high-level power supply line, generating a momentary high-pulse voltage (i.e., an ESD pulse) on the high-level power supply line. This high-pulse voltage on the high-level power supply line can then be discharged through the low-level power supply line, the second diode, and back to the pad.

[0009] In some possible implementations, the pre-amplifier circuit also includes a first input terminal. Under the control of the power supply voltage on the high-level power line, the input signal from the first input terminal is output to the connector via the pre-amplifier circuit and the subsequent driver circuit. In other words, under the control of the control circuit and the pre-amplifier circuit, the subsequent driver circuit can simultaneously perform ESD protection and normal transmission functions.

[0010] In some possible implementations, the control circuit includes a first resistor, a first capacitor, a third P-type transistor, a third N-type transistor, a first inverter, a second inverter, a first node, a first control terminal, and a second control terminal. One end of the first resistor is connected to a high-level power supply line, and the other end is connected to the first node. One end of the first capacitor is connected to the first node, and the other end is connected to a low-level power supply line. The gates of both the third P-type and third N-type transistors are connected to the first node. The source of the third P-type transistor is connected to the high-level power supply line, and the source of the third N-type transistor is connected to the low-level power supply line. The drains of both the third P-type and third N-type transistors are connected to the input of the first inverter. The output of the first inverter is connected to the input of the second inverter, and the output of the first inverter is connected to the second control terminal; the output of the second inverter is connected to the first control terminal.

[0011] When an ESD event occurs, a high-level pulse voltage is generated on the high-level power supply line. Under the control of the RC clamp circuit formed by the first resistor and the first capacitor, the first node is at a low potential, the first control terminal is at a high potential, and the second control terminal is at a low potential. When no ESD event occurs, the high-level power supply line maintains a normal power supply voltage (i.e., high level). At this time, under the control of the RC clamp circuit, the first node is at a high potential, the first control terminal is at a low potential, and the second control terminal is at a high potential.

[0012] In some possible implementations, the pre-stage driver circuit includes a first transmission gate, a second transmission gate, a second resistor, and a third resistor. The control terminals of both the first and second transmission gates are connected to the second output terminal, and their inverting control terminals are connected to the first control terminal. One end of the second resistor is connected to a low-level power supply line, and the second end is connected to the input terminal of the first transmission gate. The output terminal of the first transmission gate is connected to the second output terminal. One end of the third resistor is connected to a high-level power supply line, and the second end is connected to the input terminal of the second transmission gate. The output terminal of the second transmission gate is connected to the third output terminal. In this case, when an ESD event occurs, the second and third output terminals are floating. The second output terminal outputs a low level, and the third output terminal outputs a high level.

[0013] In some possible implementations, the pre-stage driver circuit further includes a third transmission gate, a fourth transmission gate, a fourth P-type transistor, a fourth N-type transistor, a third inverter, and a fourth inverter. The control terminals of the third and fourth transmission gates are both connected to a second control terminal, and their inverting control terminals are both connected to a first control terminal. The input terminal of the third inverter is connected to a first input terminal, its output terminal is connected to the input terminal of the third transmission gate, and the output terminal of the third transmission gate is connected to a first output terminal. The gate of the fourth P-type transistor is connected to a second output terminal, its source is connected to a high-level power supply line, and its drain is connected to a first output terminal. The input terminal of the fourth inverter is connected to a first input terminal, its output terminal is connected to the input terminal of the fourth transmission gate, and the output terminal of the fourth transmission gate is connected to a fourth output terminal. The gate of the fourth N-type transistor is connected to a first control terminal, its source is connected to a low-level power supply line, and its drain is connected to a fourth output terminal. In this case, when an ESD event occurs, the first output terminal outputs a high level and the fourth output terminal outputs a low level; when no ESD event occurs, the first output terminal and the fourth output terminal output the inverted signal of the first input terminal.

[0014] In some possible implementations, the interface circuit also includes a fifth N-type transistor. The gate of the fifth N-type transistor is connected to the input of the first inverter, the source of the fifth N-type transistor is connected to the low-level power supply line, and the drain of the fifth N-type transistor is connected to the high-level power supply line. When an ESD event occurs, under the control of the input (high level) of the first inverter, the fifth N-type transistor turns on, and the high-pulse voltage on the high-level power supply line is discharged through the low-level power supply line.

[0015] This application also provides a chip including a connector pad and an interface circuit as provided in any of the aforementioned possible implementations, wherein the interface circuit is connected to the connector pad. Using this interface circuit, an ESD design window can be implemented without relying entirely on process improvements.

[0016] In some possible implementations, the first P-type transistor and the first N-type transistor are the core devices (i.e., low-voltage devices), thus meeting the needs of low-voltage application scenarios.

[0017] In some possible implementations, all transistors in the interface circuit are core components. In this case, high-voltage devices (input / output devices, I / O devices) are unnecessary, and thick gate oxide masks are not required during chip fabrication, thus saving on manufacturing costs.

[0018] This application also provides an electronic device that includes a chip and a circuit board as provided in any of the aforementioned possible implementations, wherein the chip and the circuit board are electrically connected. Attached Figure Description

[0019] Figure 1 is a schematic diagram of the ESD design window of a protection device provided in this application;

[0020] Figure 2 is a schematic diagram of an interface circuit provided in an embodiment of this application;

[0021] Figure 3 is a flowchart of an interface circuit provided in an embodiment of this application;

[0022] Figure 4 is a schematic diagram of an interface circuit provided in an embodiment of this application;

[0023] Figure 5 is a schematic diagram of a front-end drive circuit provided in an embodiment of this application;

[0024] Figure 6 is a schematic diagram of an interface circuit provided in an embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. "At least one" means one or more, and "more" means two or more. "Connected," "linked," etc., should be interpreted broadly, for example, as an electrical connection or a mechanical connection; a fixed connection or a detachable connection or an integral connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. "Upper," "lower," etc., are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0027] This application provides an electronic device that includes a chip. The chip employs a novel interface circuit. This interface circuit does not rely on advanced manufacturing processes but improves the withstand voltage of the circuit channel and gate oxide (GOX) by adopting a novel circuit design, thereby improving the chip's ESD design window.

[0028] This application does not limit the application scenarios of the aforementioned chips. For illustrative purposes, the chips of this application can be suitable for applications with high ESD requirements, such as automotive-grade chips, or for applications with 3D (dimensional) packaging, single power supply, low voltage, and high drive capability.

[0029] This application does not limit the form of the aforementioned electronic device. The electronic device can be any electronic product equipped with a storage device, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronic products, etc.

[0030] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronics products can include servers, storage devices, radar, base stations, and other communication equipment.

[0031] Of course, depending on actual needs, the above-mentioned electronic devices may also include other devices electrically connected to the chip, such as printed circuit boards (PCBs), input / output devices, etc., and this application does not impose any restrictions on this.

[0032] It should be understood that the interface circuit is the connection circuit between the chip and the external device, and can also be called the input / output interface circuit (or simply I / O interface). Through the interface circuit, functions such as high drive capability and ESD protection can be achieved.

[0033] The following describes in detail the novel interface circuit provided in the embodiments of this application, in conjunction with the chip.

[0034] As illustrated in FIG2, this application provides a novel interface circuit. The interface circuit includes a control circuit 100, a pre-stage driver circuit 200, a post-stage driver circuit 300, a high-level power supply line VDD, and a low-level power supply line VSS. The control circuit 100 is connected to the pre-stage driver circuit 200, the output of the pre-stage driver circuit 200 is connected to the input of the post-stage driver circuit 300, and the output of the post-stage driver circuit 300 is connected to the chip's pad. Furthermore, the control circuit 100, the pre-stage driver circuit 200, and the post-stage driver circuit 300 are all connected to the high-level power supply line VDD and the low-level power supply line VSS.

[0035] As illustrated in Figure 3, the workflow of this interface circuit can include: the control circuit 100 can monitor in real time whether an ESD event has occurred. When the control circuit 100 detects an ESD event, the front-end drive circuit 200 drives the rear-end drive circuit 300 to enter ESD protection mode. When the control circuit 100 does not detect an ESD event, the front-end drive circuit 200 drives the rear-end drive circuit 300 to enter normal operation mode.

[0036] When an ESD event occurs, the voltage on the pad will spike instantly. The voltage across the devices (field-effect transistors) connected to the pad in the subsequent drive circuit 300 will increase instantaneously, exceeding the device's breakdown voltage (Vbd), causing the circuit to fail.

[0037] Existing technologies mainly employ two methods: 1) Increasing the breakdown voltage (Vbd) by increasing the breakdown voltage per unit thickness of the dielectric, which is overly dependent on the process. 2) Increasing the channel breakdown voltage by stacking field-effect transistors (or simply transistors), which cannot improve designs limited by gate oxide (GOX) breakdown voltage.

[0038] In contrast, the novel interface circuit of this application, when an ESD event occurs, drives the subsequent drive circuit 300 into ESD protection mode under the control of the control circuit 100 and the front-end drive circuit 200. This can couple the pad to an intermediate level, thereby reducing the voltage across the device by about half. This is equivalent to increasing the relative breakdown voltage (Vbd) of the device, improving the withstand voltage of the device channel and gate oxide (GOX), and thus improving the ESD design window of the chip without relying entirely on process improvements.

[0039] The following describes the subsequent drive circuit 300 in detail, taking into account the control circuit 100 and the pre-stage drive circuit 200.

[0040] As illustrated in Figure 4, the control circuit 100 is connected to both the high-level power supply line VDD and the low-level power supply line VSS, and includes a first control terminal E and a second control terminal E_B. The control circuit 100 is connected to the pre-stage drive circuit 200 through the first control terminal E and the second control terminal E_B.

[0041] When an ESD event occurs, the control circuit 100, under the control of a high pulse voltage on the high-level power supply line VDD, outputs a first control signal (e.g., E=1, E_B=0) through the first control terminal E and the second control terminal E_B, to ensure that the preceding drive circuit 200 can control the following drive circuit 300 to enter ESD protection mode. When no ESD event occurs, the control circuit 100, under the control of the power supply voltage on the high-level power supply line VDD, outputs a second control signal (e.g., E=0, E_B=1) through the first control terminal E and the second control terminal E_B, to ensure that the preceding drive circuit 200 can control the following drive circuit 300 to enter normal operating mode.

[0042] Referring again to Figure 4, the pre-stage driver circuit 200 includes a first output terminal O1, a second output terminal O2, a third output terminal O3, a fourth output terminal O4, and a first input terminal Input. This pre-stage driver circuit 200 is connected to the subsequent driver circuit 300 through the first output terminal O1, the second output terminal O2, the third output terminal O3, and the fourth output terminal O4, and controls the subsequent driver circuit 300 through these same terminals.

[0043] When an ESD event occurs, the pre-stage driver circuit 200, under the control of the control circuit 100 (or the first control terminal E and the second control terminal E_B), controls the subsequent driver circuit 300 to enter ESD protection mode through the first output terminal O1, the second output terminal O2, the third output terminal O3, and the fourth output terminal O4. When no ESD event occurs, the pre-stage driver circuit 200, under the control of the control circuit 100 (or the first control terminal E and the second control terminal E_B), generates control signals through the first output terminal O1, the second output terminal O2, the third output terminal O3, and the fourth output terminal O4 to control the subsequent driver circuit 300. This allows the input signal at the first input terminal Input to be output to the connector (PAD) via the pre-stage driver circuit 200 and the subsequent driver circuit 300, entering normal operating mode.

[0044] Referring again to Figure 4, the subsequent drive circuit 300 may include a first P-type transistor PM1, a second P-type transistor PM2, a first N-type transistor NM1, and a second N-type transistor NM2. The source of the second P-type transistor PM2 is connected to the high-level power supply line VDD, the drain of the second P-type transistor PM2 is connected to the source of the first P-type transistor PM1, and the gate of the second P-type transistor is connected to the first output terminal O1 of the preceding drive circuit 200. The drain of the first P-type transistor PM1 is connected to the pad, and the gate of the first P-type transistor is connected to the second output terminal O2 of the preceding drive circuit 200. The source of the second N-type transistor NM2 is connected to the low-level power supply line VSS, the drain of the second N-type transistor NM2 is connected to the source of the first N-type transistor NM1, and the gate of the second N-type transistor NM2 is connected to the fourth output terminal O4 of the preceding drive circuit 200. The drain of the first N-type transistor NM1 is connected to the pad, and the gate of the first N-type transistor is connected to the third output terminal O3 of the pre-stage drive circuit 200.

[0045] In other words, the first output terminal O1, the second output terminal O2, the third output terminal O3, and the fourth output terminal O4 in the pre-stage drive circuit 200 are respectively connected to the gates of the second P-type transistor PM2, the first P-type transistor PM1, the first N-type transistor NM1, and the second N-type transistor NM2 in the post-stage drive circuit 300, thereby controlling the four transistors.

[0046] Additionally, referring to Figure 4, the subsequent drive circuit 300 may also include a first diode PD1 and a second diode ND1. The anode of the first diode PD1 is connected to the pad, and the cathode is connected to the high-level power supply line VDD. The anode of the second diode ND1 is connected to the low-level power supply line VSS, and the cathode of the first diode ND1 is connected to the pad. In this case, when an ESD event occurs, a large amount of charge will accumulate on the pad, which will be transferred to the high-level power supply line VDD via the first diode PD1, generating a momentary high-pulse voltage (i.e., an ESD pulse) on the high-level power supply line VDD. Furthermore, the low-level power supply line VSS is connected to the pad via the second diode ND1, forming a discharge path that can discharge the ESD pulse in the circuit, as detailed in Figure 6 and the corresponding explanation below.

[0047] It should be noted that the source and drain of the transistor involved in this application may not be clearly distinguished. That is, the two poles of the transistor other than the gate are the source and the drain. The embodiments in this application are only described as examples of one possible way.

[0048] The following is a schematic description of the control process of the control circuit 100, the front-end drive circuit 200, and the rear-end drive circuit 300 in the interface circuit under ESD protection mode and normal operation mode.

[0049] ESD protection mode

[0050] Referring to Figure 4, when an ESD event occurs, a high-pulse voltage is generated on the high-level power supply line VDD. Under the control of this high-pulse voltage on VDD, the control circuit 100 controls the pre-stage driver circuit 200 through the first control terminal E and the second control terminal E_B. This causes the second output terminal O2 and the third output terminal O3 of the pre-stage driver circuit 200 to float, the first output terminal O1 to output a high level, and the fourth output terminal O4 to output a low level. This results in the gates of the first P-type transistor PM1 and the first N-type transistor NM1 being floated, while the second P-type transistor PM2 and the second N-type transistor NM2 are both turned off, thus putting the interface circuit into ESD protection mode.

[0051] It should be understood that when the gates of the first P-type transistor PM1 and the first N-type transistor NM1 are floating, and the second P-type transistor PM2 and the second N-type transistor NM2 are both turned off, the connection pad (PAD) can be coupled to an intermediate level through the first P-type transistor PM1 and the first N-type transistor NM1, thereby reducing the level experienced by the first P-type transistor PM1 and the first N-type transistor NM1 to about half (that is, half of the level before the connection pad is coupled).

[0052] For example, when an ESD event occurs, assuming the high level on the pad is around 10V, in ESD protection mode, the first P-type transistor PM1 and the first N-type transistor NM1 can couple the pad to around 5V, which is equivalent to the voltage across the devices (PM1, NM1) dropping from 10V to around 5V.

[0053] Assuming the absolute breakdown voltage (Vbd) of devices (PM1, NM1) is 8V, the devices cannot directly withstand the high level (10V) on the pad and will break down. However, using the design method of this application, the voltage that devices (PM1, NM1) can withstand drops to 5V without breakdown. In other words, the absolute breakdown voltage (Vbd) of devices (PM1, NM1) remains unchanged, but by changing the circuit design, the relative breakdown voltage that the circuit can withstand is significantly increased, which improves the withstand voltage capability of the device channel and gate oxide (GOX), thereby improving the ESD design window of the chip.

[0054] Normal working mode

[0055] When no ESD event occurs, the high-level power supply line VDD maintains a normal power supply voltage (e.g., 1.8V). Under the control of the power supply voltage on the high-level power supply line VDD, the data signal input at the first input terminal Input is output to the connector disk (PAD) through the pre-stage driver circuit 200 and the post-stage driver circuit 300, ensuring normal transmission of the interface circuit.

[0056] In this normal operating mode, under the control of the pre-stage drive circuit 200, the first P-type transistor PM1 and the first N-type transistor NM1 remain on in the post-stage drive circuit 300, while the second P-type transistor PM2 and the second N-type transistor NM2 are either on or off, thus outputting the data signal input at the first input terminal Input to the pad. For example, when the data signal input at the first input terminal Input is a high level "1", the first output terminal O1 and the fourth output terminal O4 of the pre-stage drive circuit 200 output a low level, the second P-type transistor PM2 is on, and the second N-type transistor NM2 is off, outputting the high level "1" of the high-level power line VDD to the pad. When the data signal input at the first input terminal Input is a low level "0", the first output terminal O1 and the fourth output terminal O4 output a high level, the second P-type transistor PM2 is off, and the second N-type transistor NM2 is on, outputting the low level of the low-level power line VSS to the pad.

[0057] This application does not impose any restrictions on the specific circuit structure of the control circuit 100 and the pre-stage drive circuit 200, as long as they can satisfy the above-mentioned functional control of the post-stage drive circuit 300.

[0058] Schematic, referring to Figure 4, in some possible implementations, the control circuit 100 may include a first resistor R1, a first capacitor C1, a third P-type transistor PM3, a third N-type transistor NM3, a first inverter INV1, a second inverter INV2, a first node RC_NET, a first control terminal E, and a second control terminal E_B.

[0059] One end of the first resistor R1 is connected to the high-level power supply line VDD, and the other end of the first resistor R1 is connected to the first node RC_NET. One end of the first capacitor C1 is connected to the first node RC_NET, and the other end of the first capacitor C1 is connected to the low-level power supply line VSS. In this configuration, the first resistor R1 and the first capacitor C1 form an RC clamping circuit, thereby enabling potential control on the first node RC_NET. The third P-type transistor PM3 and the third N-type transistor NM3 are connected in a complementary and symmetrical manner to form a CMOS inverter. Specifically, the gate of the third P-type transistor PM3 is connected to the gate of the third N-type transistor NM3 and then to the first node RC_NET. The drain of the third P-type transistor PM3 is connected to the source of the third N-type transistor NM3 and then to the input of the first inverter NV1. The source of the third P-type transistor PM3 is connected to the high-level power supply line VDD, and the source of the third N-type transistor NM3 is connected to the low-level power supply line VSS. The output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, and the output terminal of the first inverter INV1 is connected to the second control terminal E_B, while the output terminal of the second inverter INV2 is connected to the first control terminal E.

[0060] When an ESD event occurs, a high pulse voltage is generated on the high-level power line VDD. At this time, under the control of the RC clamping circuit (R1+C1), the first node RC_NET is at a low potential, the first control terminal E is at a high potential, and the second control terminal E_B is at a low potential; that is, RC_NET=0, E=1, E_B=0.

[0061] When no ESD event occurs, the high-level power supply line VDD maintains a normal power supply voltage (i.e., high level). At this time, under the control of the RC clamping circuit (R1+C1), the first node RC_NET is at a high potential, the first control terminal E is at a low potential, and the second control terminal E_B is at a high potential; that is, RC_NET=1, E=0, E_B=1.

[0062] Schematic, referring to Figure 5, in some possible implementations, the pre-stage drive circuit 200 may include a first circuit section (A1, A2) and a second circuit section (B). The first circuit section (A1, A2) is used to control the second output terminal O2 and the third output terminal O3, and the second circuit section (B) is used to control the first output terminal O1 and the fourth output terminal O4.

[0063] Referring again to Figure 5, in some possible implementations, the first circuit section (A1, A2) may include a first transmission gate TG1, a second transmission gate TG2, a second resistor R2, and a third resistor R3. The control terminals (C) of both the first and second transmission gates TG1 and TG2 are connected to the second output terminal E_B, and the inverting control terminals (C') of both TG1 and TG2 are connected to the first control terminal E. One end of the second resistor R2 is connected to the low-level power supply line VSS, and the other end is connected to the input terminal of the first transmission gate TG1. The output terminal of the first transmission gate TG1 is connected to the second output terminal O2. One end of the third resistor R3 is connected to the high-level power supply line VDD, and the other end is connected to the input terminal of the second transmission gate TG2. The output terminal of the second transmission gate TG2 is connected to the third output terminal O3.

[0064] Of course, other circuit design structures can also be used for the first circuit section (A1, A2), as long as they can meet the functional requirements.

[0065] Referring again to Figure 5, in some possible implementations, the second circuit section (B) may include a third transmission gate TG3, a fourth transmission gate TG4, a fourth P-type transistor PM4, a fourth N-type transistor NM4, a third inverter INV3, and a fourth inverter INV4. The control terminals (C) of both the third and fourth transmission gates TG3 and TG4 are connected to the second control terminal E_B, and the inverting control terminals (C') of both TG3 and TG4 are connected to the first control terminal E. The input terminal of the third inverter INV3 is connected to the first input terminal Input, the output terminal of the third inverter INV3 is connected to the input terminal of the third transmission gate TG3, and the output terminal of the third transmission gate TG3 is connected to the first output terminal O1. The gate of the fourth P-type transistor PM4 is connected to the second control terminal E_B, the source of the fourth P-type transistor PM4 is connected to the high-level power supply line VDD, and the drain of the fourth P-type transistor PM4 is connected to the first output terminal O1. The input terminal of the fourth inverter INV4 is connected to the first input terminal Input. The output terminal of the fourth inverter INV4 is connected to the input terminal of the fourth transmission gate TG4. The output terminal of the fourth transmission gate TG4 is connected to the fourth output terminal O4. The gate of the fourth N-type transistor NM4 is connected to the first control terminal E. The source of the fourth N-type transistor NM4 is connected to the low-level power supply line VSS. The drain of the fourth N-type transistor NM4 is connected to the fourth output terminal O4.

[0066] Of course, the second circuit section (B) can also adopt other circuit design structures, as long as they can meet the functional requirements.

[0067] When an ESD event occurs, as shown in Figures 4 and 5, the first control terminal E is at a high potential, and the second control terminal E_B is at a low potential, i.e., E=1 and E_B=0. In this situation, the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are all turned off, and the second output terminal O2 and the third output terminal O3 are floating. The fourth P-type transistor PM4 is turned on, outputting the high level of the high-level power supply line VDD to the first output terminal O1. The fourth N-type transistor NM4 is turned on, outputting the low level of the low-level power supply line VSS to the fourth output terminal O4. Thus, under the control of the four output terminals (O1, O2, O3, O4), the gates of the first P-type transistor PM1 and the first N-type transistor NM1 are floating, while the second P-type transistor PM2 and the second N-type transistor NM2 are turned off, thereby entering ESD protection mode.

[0068] When no ESD event occurs, as shown in Figures 4 and 5, the first control terminal E is at a low potential, and the second control terminal E_B is at a high potential, i.e., E = 0 and E_B = 1. In this case, the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are all open. The high-level power supply line VDD is transmitted to the third output terminal O3 via the second transmission gate TG2, and the low-level power supply line VSS is transmitted to the second output terminal O2 via the first transmission gate TG1. The fourth P-type transistor PM4 and the fourth N-type transistor NM4 are both turned off. The data signal at the first input terminal Input is inverted by the third inverter INV3 and output to the first output terminal O1 via the third transmission gate TG3. Similarly, the data signal at the first input terminal Input is inverted by the fourth inverter INV4 and output to the fourth output terminal O4 via the fourth transmission gate TG4. In other words, the signals output by the first output terminal O1 and the fourth output terminal O4 are the inverted signals of the first input terminal Input, the third output terminal O3 outputs a high level, and the second output terminal O2 outputs a low level. Thus, under the control of the four output terminals (O1, O2, O3, O4), the second P-type transistor PM2 and the second N-type transistor NM2 are both turned on in the subsequent drive circuit 300. If the signals at the first output terminal O1 and the fourth output terminal O4 are low (i.e., the first input terminal Input is high), then the first N-type transistor NM1 is turned off, and the first P-type transistor PM1 is turned on, thereby allowing the high level of the high-level power supply line VDD to be transmitted to the connector pad (PAD) via the first P-type transistor PM1 and the second P-type transistor PM2. If the signals at the first output terminal O1 and the fourth output terminal O4 are high (that is, the first input terminal Input is low), then the first N-type transistor NM1 is turned on, the first P-type transistor PM1 is turned off, and the low level of the low-level power supply line VSS is transmitted to the connection pad (PAD) through the first N-type transistor NM1 and the second N-type transistor NM2. This indicates that the system has entered normal operating mode.

[0069] Additionally, in order to discharge the high-pulse voltage generated on the high-level power line VDD when an ESD event occurs, referring to Figure 6, in some possible implementations, a discharge circuit 400 can be set in the interface circuit. This discharge circuit 400 is connected to the input terminal of the first inverter INV1, the low-level power line VSS, and the high-level power line VDD. When an ESD event occurs, under the control of the input terminal of the first inverter INV1, the discharge circuit 400 can connect the high-level power line VDD to the low-level power line VSS. In this way, the high-level power line VDD can form a discharge path through the discharge circuit 400 to the low-level power line VSS until the high-level pulse voltage on the high-level power line VDD is completely discharged through the low-level power line VSS.

[0070] This application does not impose any restrictions on the specific structure of the discharge circuit 400, as long as it can meet the above functional requirements and discharge the high-pulse signal on the high-level power line VDD.

[0071] Schematic, referring to Figure 6, in some possible implementations, the discharge circuit 400 may include a fifth N-type transistor NM5. The gate of the fifth N-type transistor NM5 is connected to the input of the first inverter INV1, the source of the fifth N-type transistor NM5 is connected to the low-level power supply line VSS, and the drain of the fifth N-type transistor NM5 is connected to the high-level power supply line VDD. In this case, when an ESD event occurs, the first node RC_NET is low (i.e., RC_NET = 0), the input of the first inverter INV1 is high, and the fifth N-type transistor NM5 is turned on under the control of the input of the first inverter INV1. In this case, the high pulse voltage on the high-level power supply line VDD can be discharged through the low-level power supply line VSS, the second diode ND1, and the pad.

[0072] As described above, in ESD protection mode, the interface circuit provided in this application embodiment has its gates floating on the first P-type transistor PM1 and the first N-type transistor NM1, which couples the pad to an intermediate voltage level. This reduces the voltage across the devices by approximately half, meaning the voltage across the first P-type transistor PM1 and the first N-type transistor NM1 drops significantly. Therefore, the first P-type transistor PM1 and the first N-type transistor NM1 can be protected using low-voltage devices (i.e., core devices), thus meeting the requirements of low-voltage applications. For example, in automotive-grade and other applications with high ESD requirements, using low-voltage devices can meet the needs of overdrive applications.

[0073] As illustrated, in some chips that employ the aforementioned interface circuit, the first P-type transistor PM1 and the first N-type transistor NM1 are low-voltage devices (core devices).

[0074] As illustrated, in some chips employing the aforementioned interface circuitry, all transistors in the interface circuitry can be low-voltage devices (core devices), eliminating the need for high-voltage devices (input / output devices, I / O devices). In this case, thick gate oxide masks are unnecessary during chip fabrication, thus saving manufacturing costs.

[0075] Of course, the first P-type transistor PM1 and the first N-type transistor NM1 can also achieve ESD protection by using high-voltage devices (I / O devices). In practice, the design can be adjusted according to the requirements.

[0076] Additionally, it should be noted that the embodiments in this application are all illustrated using the example of a two-stage driving transistor (i.e., a 2-stack structure) in the subsequent driving circuit 300. However, this application is not limited to this. In some possible implementations, the subsequent driving circuit 300 may be configured with three or more stages of driving transistors. In practice, it can be configured as needed.

[0077] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An interface circuit, characterized in that, include: A high-level power supply line, a low-level power supply line, and a control circuit, a pre-stage drive circuit, and a post-stage drive circuit connected to the high-level power supply line and the low-level power supply line; The control circuit is connected to the front-end drive circuit; The pre-stage driver circuit includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal; The subsequent driving circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor; wherein, the source of the second P-type transistor is connected to the high-level power supply line, the drain of the second P-type transistor is connected to the source of the first P-type transistor, and the gate of the second P-type transistor is connected to the first output terminal; the drain of the first P-type transistor is connected to the chip's connection pad, and the gate of the first P-type transistor is connected to the second output terminal; the source of the second N-type transistor is connected to the low-level power supply line, the drain of the second N-type transistor is connected to the source of the first N-type transistor, and the gate of the second N-type transistor is connected to the fourth output terminal; the drain of the first N-type transistor is connected to the connection pad, and the gate of the first N-type transistor is connected to the third output terminal; Under the control of the high pulse voltage on the high-level power line, the control circuit controls the second and third output terminals of the pre-stage drive circuit to be floating, the first output terminal to output a high level, and the fourth output terminal to output a low level.

2. The interface circuit according to claim 1, characterized in that, The subsequent drive circuit also includes a first diode and a second diode; The anode of the first diode is connected to the connector, and the cathode of the first diode is connected to the high-level power supply line; the anode of the second diode is connected to the low-level power supply line, and the cathode of the first diode is connected to the connector.

3. The interface circuit according to claim 1 or 2, characterized in that, The pre-stage driver circuit also includes a first input terminal; The control circuit, under the control of the power supply voltage on the high-level power line, outputs the input signal from the first input terminal to the connecting disk via the pre-stage driving circuit and the post-stage driving circuit.

4. The interface circuit according to any one of claims 1-3, characterized in that, The control circuit includes a first resistor, a first capacitor, a third P-type transistor, a third N-type transistor, a first inverter, a second inverter, a first node, a first control terminal, and a second control terminal; One end of the first resistor is connected to the high-level power supply line, and the other end of the first resistor is connected to the first node; One end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the low-level power line; The gate of the third P-type transistor and the gate of the third N-type transistor are both connected to the first node. The source of the third P-type transistor is connected to the high-level power supply line, the source of the third N-type transistor is connected to the low-level power supply line, and the drains of both the third P-type transistor and the third N-type transistor are connected to the input terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the first inverter is connected to the second control terminal; the output terminal of the second inverter is connected to the first control terminal.

5. The interface circuit according to claim 3 or 4, characterized in that, The front-end drive circuit includes a first transmission gate, a second transmission gate, a second resistor, and a third resistor; The control terminals of the first transmission gate and the second transmission gate are both connected to the second output terminal, and the inverting control terminals of the first transmission gate and the second transmission gate are both connected to the first control terminal. One end of the second resistor is connected to the low-level power supply line, the second end of the second resistor is connected to the input terminal of the first transmission gate, and the output terminal of the first transmission gate is connected to the second output terminal. One end of the third resistor is connected to the high-level power supply line, the second end of the third resistor is connected to the input terminal of the second transmission gate, and the output terminal of the second transmission gate is connected to the third output terminal.

6. The interface circuit according to any one of claims 3-5, characterized in that, The front-end drive circuit also includes a third transmission gate, a fourth transmission gate, a fourth P-type transistor, a fourth N-type transistor, a third inverter, and a fourth inverter; The control terminals of the third transmission gate and the fourth transmission gate are both connected to the second control terminal, and the inverting control terminals of the third transmission gate and the fourth transmission gate are both connected to the first control terminal. The input terminal of the third inverter is connected to the first input terminal, the output terminal of the third inverter is connected to the input terminal of the third transmission gate, and the output terminal of the third transmission gate is connected to the first output terminal; the gate of the fourth P-type transistor is connected to the second output terminal, the source of the fourth P-type transistor is connected to the high-level power supply line, and the drain of the fourth P-type transistor is connected to the first output terminal. The input terminal of the fourth inverter is connected to the first input terminal, the output terminal of the fourth inverter is connected to the input terminal of the fourth transmission gate, and the output terminal of the fourth transmission gate is connected to the fourth output terminal; the gate of the fourth N-type transistor is connected to the first control terminal, the source of the fourth N-type transistor is connected to the low-level power supply line, and the drain of the fourth N-type transistor is connected to the fourth output terminal.

7. The interface circuit according to any one of claims 4-6, characterized in that, The interface circuit also includes a fifth N-type transistor; The gate of the fifth N-type transistor is connected to the input terminal of the first inverter, the source of the fifth N-type transistor is connected to the low-level power supply line, and the drain of the fifth N-type transistor is connected to the high-level power supply line.

8. A chip, characterized in that, It includes a connecting disk and an interface circuit as described in any one of claims 1-7, wherein the interface circuit is connected to the connecting disk.

9. The chip according to claim 8, characterized in that, The first P-type transistor and the first N-type transistor are the core components.

10. The chip according to claim 8, characterized in that, All transistors in the interface circuit are core components.

11. An electronic device, characterized in that, Includes the chip and circuit board as described in any one of claims 8-10, wherein the chip is electrically connected to the circuit board.

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