Method and apparatus for implementing AES encryption operation

Abstract

The present application discloses a method and apparatus for implementing an AES encryption operation. The present application supports an implementation in which, in a first mode, an AES hardware computing core is reused to accelerate an AES encryption operation. An AES hardware core can be effectively used in two modes, wherein the first mode is a Performance mode, and the second mode is a Lockstep mode. The present application not only ensures security and reliability, but also increases the encryption operation speed by means of parallel processing when needed.

Description

A method and apparatus for implementing AES encryption operations

[0001] This application claims priority to Chinese patent application filed on November 5, 2024, with application number 202411572496.X and entitled "A method and apparatus for implementing AES encryption operation", the contents of which should be understood to be incorporated herein by reference. Technical Field

[0002] This application relates to, but is not limited to, information security technology, and in particular to a method and apparatus for implementing AES encryption operations. Background Technology

[0003] The Advanced Encryption Standard (AES) CCM mode (Counter with CBC-MAC) (hereinafter referred to as AES CCM encryption operation) is an encryption mode that combines encryption and authentication functions. It uses Counter Mode (CTR) to encrypt data, while simultaneously using Cipher Block Chaining Message Authentication Code (CBC-MAC) to generate authentication tags to ensure data integrity and authenticity. AES, as a symmetric encryption algorithm, is responsible for encrypting and decrypting data, ensuring confidentiality. During encryption, CTR combines an incrementing counter with the key to generate a pseudo-random number stream, used to protect data blocks. CBC-MAC, on the other hand, is responsible for verifying the integrity and authenticity of the data, preventing tampering.

[0004] CCM mode combines CTR and CBC-MAC to provide not only encryption but also data authentication. Because CCM mode can achieve dual protection with limited computing resources, it is widely used, especially in resource-constrained environments such as wireless communication and IoT devices.

[0005] In functional safety scenarios, the lockstep mode introduces an additional layer of protection. By using two AES cores—the first AES core (AES core0) and the second AES core (AES core1)—the input data is computed through two independent paths, and the final results are compared to ensure the correctness of the calculation. This mode is particularly suitable for systems requiring high security. However, in practical applications, if such strict functional safety is not required, one of the AES cores, such as AES core1, will be idle and wasted.

[0006] Invention Overview

[0007] This application provides a method and apparatus for implementing AES encryption operations, which can at least solve any of the above-mentioned technical problems.

[0008] This application provides a method for implementing AES encryption operations, including:

[0009] In the first mode, different Advanced Encryption Standard (AES) cores participating in the AES CCM encryption operation process different tasks in parallel. These tasks include: Counter Mode CTR encryption / decryption, Cipher Block Chaining Message Authentication Code (CBC-MAC) calculation, and while the AES core processing CTR encryption / decryption is decrypting the current data block, the AES core processing CBC-MAC calculation is verifying the decrypted data block.

[0010] In one exemplary instance, it also includes:

[0011] Choose either the first mode for scenarios with non-functional safety requirements or the second mode for scenarios with functional safety requirements.

[0012] When the second mode is selected, the different AES cores participating in the AES CCM encryption operation simultaneously process the input data and compare the results to ensure the correctness of the calculation.

[0013] In one exemplary instance, the second mode further includes:

[0014] The different AES cores involved in the AES CCM encryption operation serially calculate the CTR and CBC MAC, and compare the results.

[0015] In one exemplary instance, the AES core for processing CTR encryption / decryption includes one or more.

[0016] In one exemplary instance, the different task is CTR encryption;

[0017] The AES core that processes CTR encryption / decryption is responsible for CTR encryption of the data; the AES core that processes CBC-MAC calculation processes the CBC-MAC calculation of the corresponding data blocks in parallel to generate authentication tags.

[0018] In one exemplary instance, the different task is CTR decryption;

[0019] The AES core that processes CTR encryption / decryption is responsible for decrypting the data to generate plaintext; the AES core that processes CBC-MAC calculation performs CBC-MAC verification based on the decryption result to ensure data integrity. At the same time as decryption, the AES core that processes CTR encryption / decryption and the AES core that processes CBC-MAC calculation process the next data block in parallel through a pipeline.

[0020] In one exemplary instance, the second mode and the first mode are selected by setting the configuration register.

[0021] In one exemplary instance, the first mode is a performance mode; the second mode is a lockstep mode.

[0022] This application also provides a method for implementing AES encryption operations, including:

[0023] In the first mode, different AES cores participating in the AES encryption operation process different plaintext / ciphertext data blocks in parallel; the data before and after AES encryption are independent.

[0024] In one exemplary instance, it also includes:

[0025] Choose either the first mode for scenarios with non-functional safety requirements or the second mode for scenarios with functional safety requirements.

[0026] When the second mode is selected, the different AES cores participating in the AES encryption operation simultaneously process the input data and compare the results to ensure the correctness of the calculation.

[0027] In one exemplary instance, the AES encryption that is independent of the preceding and following data includes: AES Electronic Codebook (ECB) encryption mode and AES Counter (CTR) mode.

[0028] In one exemplary instance, the different AES cores participating in the AES encryption operation process different plaintext / ciphertext data blocks in parallel, including:

[0029] The different AES cores participating in the AES encryption operation simultaneously input different plaintext or ciphertext data blocks to process the different data blocks in parallel.

[0030] This application provides another computer-readable storage medium storing computer-executable instructions for performing the method for implementing AES encryption operations as described in any of the above embodiments.

[0031] This application embodiment provides a computer device, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for performing the method for implementing AES encryption operations as described in any of the above claims.

[0032] This application also provides a method and apparatus for implementing AES encryption operations, including: a processing module, a mode selection module, a task scheduling module, and a result comparison module.

[0033] The processing module includes at least two AES cores. The at least two AES computing cores are divided into one or more core sets according to the task requirements, and are respectively configured to perform CTR encryption / decryption operations and CBC-MAC operations, or configured to perform the same encryption operation process in functional safety scenarios.

[0034] The mode selection module is configured to switch between Performance mode and Lockstep mode based on the security requirements of the upper-layer application.

[0035] The task scheduling module is configured to schedule the core collection in different modes as follows:

[0036] In Performance mode, the current data block to be processed is subjected to CTR encryption / decryption in one set of cores, and the input corresponding to the data block is subjected to CBC-MAC operation / verification in another set of cores to achieve parallel or pipelined processing of the two types of operation paths; in the decryption process, CTR decryption and CBC-MAC verification are interleaved according to the grouped data blocks to form a block-level pipeline.

[0037] In Lockstep mode, at least two AES cores are selected for each data block to be processed to form a lockstep core set, so that each AES core in the lockstep core set performs the same CTR encryption / decryption and CBC-MAC calculation process on the same input data.

[0038] The result comparison module is configured to perform consistency checks on the output results of the lockstep core set in Lockstep mode.

[0039] In one exemplary instance, the device is applied to the hardware security module (HSM) in a millimeter-wave radar chip.

[0040] The method for implementing AES encryption operation provided in this application embodiment supports the reuse of the AES hardware computing core to accelerate the implementation of AES encryption operation in a first mode applied to scenarios with non-functional safety requirements. The AES hardware core can be effectively utilized in both modes, which not only ensures security and reliability, but also improves the encryption operation speed through parallel processing when needed.

[0041] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings.

[0042] Overview of the attached figures

[0043] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0044] Figure 1 is a flowchart illustrating the method for implementing AES CCM encryption operations;

[0045] Figure 2 is a schematic diagram of an embodiment of the CCM encryption process in Performance mode in this application.

[0046] Figure 3 is a schematic diagram of an embodiment of the CCM decryption process in Performance mode in this application.

[0047] Figure 4 is a schematic diagram of the composition structure of a device for implementing AES encryption operation according to an embodiment of this application;

[0048] Figure 5 is a flowchart illustrating the method for implementing AES encryption in an embodiment of this application;

[0049] Figure 6 is a schematic diagram of an embodiment of the ECB encryption mode processing procedure in Performance mode in this application.

[0050] Figure 7 is a schematic diagram of an embodiment of the CTR processing procedure in Performance mode in this application.

[0051] Figure 8 is a schematic diagram of the composition structure of a device for implementing AES encryption operation according to an embodiment of this application;

[0052] Figure 9 is a schematic diagram of another component structure of the apparatus for implementing AES encryption operation according to an embodiment of this application.

[0053] Detailed Explanation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0055] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0057] Figure 1 is a flowchart illustrating the method for implementing AES encryption operations in an embodiment of this application. As shown in Figure 1, it may include:

[0058] Step 101: In the first mode, different AES cores participating in the AES CCM encryption operation process different tasks in parallel. The different tasks include: CTR encryption / decryption and CBC-MAC calculation. When the AES core processing CTR encryption / decryption decrypts the current data block, the AES core processing CBC-MAC calculation verifies the decrypted data block.

[0059] The AES core is the hardware computing unit that implements the AES algorithm. An AES core may include logic circuits for performing operations such as row shifting, byte substitution, column obfuscation, round key addition, reverse row shifting, reverse byte substitution, and reverse column obfuscation. Each AES core can perform encryption or decryption operations independently, or work collaboratively in pipelined or parallel modes.

[0060] In one exemplary instance, CTR encryption may include:

[0061] The AES core responsible for CTR encryption / decryption is responsible for CTR encryption of the data; the AES core responsible for CBC-MAC calculation processes the CBC-MAC calculation of the corresponding data blocks in parallel to generate authentication tags. In this embodiment, encryption is accelerated by having two AES cores work simultaneously.

[0062] In one exemplary instance, CTR decryption may include:

[0063] The AES core that handles CTR encryption / decryption first decrypts the CTR to generate plaintext; the AES core that handles CBC-MAC calculation performs CBC-MAC verification based on the decryption result to ensure data integrity. While decrypting, the two AES cores can pipeline and process the next data block in parallel.

[0064] In one exemplary instance, step 101 may further include:

[0065] In the case of selecting the second mode, the different AES cores participating in the AES CCM encryption operation serially calculate the CTR and CBC MAC, and compare the results.

[0066] In one embodiment, the AES core for processing CTR encryption / decryption may include one or more AES cores. By using multiple AES cores for parallel processing, the system's computational efficiency and throughput are significantly improved while ensuring the security of data encryption and the integrity of messages.

[0067] In one exemplary instance, the method for implementing AES encryption operations in this application embodiment further includes:

[0068] Step 100: Based on the application scenario requirements, select either the first mode for scenarios with non-functional safety requirements or the second mode for scenarios with functional safety requirements.

[0069] In one exemplary instance, switching between a first mode and a second mode can be achieved by setting the configuration register config_lockstepen. In one embodiment, for example, setting config_lockstepen = 0 indicates that the first mode is enabled, and setting the configuration register config_lockstepen = 1 indicates that the second mode is enabled.

[0070] In one exemplary instance, the first mode is suitable for scenarios that do not require functional safety, i.e., scenarios with non-functional safety requirements, and is used to improve computational efficiency through parallel processing. The first mode can also be called Performance Mode. The second mode is suitable for scenarios with functional safety requirements and is used to ensure the correctness of computation. The second mode can also be called Lockstep Mode.

[0071] In one exemplary instance, step 101 may further include:

[0072] In the second mode, different AES cores participating in the AES CCM encryption operation process the input data simultaneously and compare the results to ensure the correctness of the calculation. That is, different AES cores, such as AES core0 and AES core1, process the same data and perform the same encryption or decryption calculations. After the calculation is complete, the two sets of results are compared. If the results calculated by the two AES cores are consistent, the encryption / decryption process is considered correct; if they are inconsistent, it indicates that an error may have occurred during the calculation. This method provides higher computational security and reliability, and is particularly suitable for systems with very high security requirements.

[0073] The method for implementing AES encryption computation provided in this application embodiment addresses both functional safety and non-functional safety requirements in chip application scenarios. In scenarios with high functional safety requirements, a second mode is selected to ensure consistency in the encryption and authentication results of each data block. In scenarios where performance is prioritized, a first mode is selected to utilize parallel processing to improve processing speed. This enables flexible switching of AES CCM mode in different application scenarios, rationally utilizes AES computing resources, effectively utilizes chip resources, and improves encryption computation speed while ensuring security and reliability.

[0074] In one embodiment, taking a CCM using two sets of AES cores, namely AES core0 and AES core1, as an example, the implementation of Lockstep Mode and Performance Mode is as follows:

[0075] In Lockstep Mode: AES core0 and AES core1 serially calculate the CTR and CBC MAC, meaning AES core0 and AES core1 process the same data stream sequentially to ensure strict consistency in encryption and integrity verification. Specifically, AES core0 is responsible for CTR encryption / decryption (Counter mode) to generate ciphertext; then, AES core1 receives the encrypted data and performs CBC-MAC calculation to generate and verify the message integrity authentication code. In Lockstep Mode, although AES core0 and AES core1 do not process the same parts of the same data block simultaneously, their operations are strictly synchronized and performed sequentially to ensure the correctness and consistency of the calculation process, meeting functional safety requirements. Lockstep Mode is suitable for scenarios requiring high data security and integrity.

[0076] In Performance Mode, AES core0 and AES core1 process different tasks in parallel to accelerate the encryption and decryption process and improve computational efficiency. AES core0 is responsible for CTR encryption / decryption. Since CTR calculations are independent, AES core0 can process multiple data blocks consecutively, generating or decrypting ciphertext. AES core1 performs CBC-MAC calculations simultaneously. Although CBC-MAC calculations are data-dependent and cannot be fully parallelized, performance optimization can be achieved through pipelined design, i.e., division of labor. For example, while AES core0 decrypts the current block, AES core1 can verify already decrypted blocks, thus achieving parallel acceleration. In Performance Mode, when encrypting or decrypting large amounts of data, the processing speed is nearly twice that of a single core, significantly improving encryption speed.

[0077] In this embodiment, by setting different modes, switching to Performance Mode in application scenarios where functional safety is not required accelerates CCM computation using AES core1. After acceleration, the efficiency of encryption and decryption of a large number of payloads reaches nearly twice that of single-core computation. Performance Mode improves efficiency by rationally allocating computational tasks, which can greatly increase the encryption operation speed.

[0078] In an exemplary instance, taking CCM using two AES cores, AES core0 and AES core1, as an example, in Performance mode CCM encryption, the data processed by AES core0 and AES core1 are unrelated, thus allowing for parallel computation. The encryption process can be illustrated in Figure 2. AES core0 is responsible for CTR (Counter) encryption, generating ciphertext; AES core1 simultaneously performs CBC-MAC computation for message integrity authentication. Since these two computations are independent, CTR and CBC-MAC can be started simultaneously, allowing the entire encryption process to run in parallel, thus improving encryption efficiency. In Figure 2, B0 represents the first data block, A0-Ar represent associated data, P0-Pn represent the payload, and C0-Cn+1 represent the ciphertext. Figure 2 illustrates the first mode used in AES CCM encryption acceleration, namely Performance mode, which utilizes two cores, AES core0 and AES core1, to process encryption and authentication tasks in parallel. The process can be divided into the following parts:

[0079] The left side processes the initial data blocks, such as the first data block (B0), associated data (A0), and some other associated data (Ar). These data blocks are processed by AES core1, performing CBC-MAC calculations for data authentication.

[0080] The middle section illustrates the parallel processing of multiple payload blocks (P0 to Pn), specifically the accelerated CCM encryption (Eneryption) represented by the dashed box in Figure 2. AES core0 performs CTR encryption on each payload block (P0, P1, ..., Pn) using counter blocks Ctr1, Ctr2, ..., Ctrn+1, generating the corresponding ciphertext block (C0, C1, ..., Cn). Simultaneously, AES core1 performs CBC-MAC computation on the same payload blocks for integrity verification. Since CTR encryption and CBC-MAC computation are independent, they are performed in parallel to improve processing efficiency.

[0081] The right side shows the generation of the final authentication tag (T) at the end of the encryption process. This tag is generated based on the CBC-MAC calculation result and is used to verify the integrity of the data. The final counter block Ctr0 is also part of the encryption process, performing the final encryption operation.

[0082] As shown in Figure 2 of the embodiment of this application, in Performance mode, AES core0 is responsible for CTR encryption, while AES core1 is responsible for CBC-MAC calculation. The two AES cores adopt a parallel processing mode to handle different calculation tasks respectively. The efficiency of the entire CCM encryption can be close to the sum of the accelerations of the two cores. Especially when processing a large amount of load data, the encryption efficiency is significantly improved, thereby improving the overall throughput of encryption.

[0083] In an exemplary instance, taking CCM using two AES cores, AES core0 and AES core1, as an example, in Performance mode CCM decryption, the CBC-MAC verification of AES core1 depends on the CTR decryption result of AES core0. The decryption process can be illustrated in Figure 3. AES core0 first performs the CTR decryption operation on the current data block, providing its decryption result to AES core1. Then, AES core1 begins CBC-MAC verification of the data block; simultaneously, AES core0 can immediately begin processing the CTR decryption of the next data block. This achieves a certain degree of parallel processing. Although CBC-MAC verification depends on the decryption result of the previous step, the pipelined operation also improves the overall decryption efficiency. Figure 3 illustrates the first mode used in the AES CCM decryption acceleration process, namely Performance mode, which utilizes the collaborative work of two cores, AES core0 and AES core1. The process can be divided into the following parts:

[0084] The left side, similar to the encryption process shown in Figure 2, also involves processing the initial data blocks, such as the first data block (B0), associated data (A0), and other associated data (Ar). This data is processed by AES core1, performing CBC-MAC calculations to prepare for data authentication.

[0085] In the middle section, the ciphertext blocks (C0, C1, ..., Cn) are processed by AES core0 using CTR (counter) decryption. The decrypted results (P0, P1, ..., Pn) are then verified by AES core1 using CBC-MAC to ensure data integrity and correctness. A key point in the decryption process is that AES core1 needs to wait for the CTR decryption result from AES core0 before starting CBC-MAC verification. Therefore, AES core1 can only authenticate the data block after AES core0 has decrypted the plaintext of the first payload block. However, while AES core1 is authenticating the current data block, AES core0 can begin processing the decryption of the next ciphertext block. Through this pipelined operation, both work in parallel, thereby improving the overall decryption efficiency.

[0086] The right side shows that after decryption, AES core1 generates a final authentication tag (T) and compares it with the original authentication tag (Cr0). If the two tags match, the data integrity verification is successful and the decryption result is valid; otherwise, the decryption result is invalid.

[0087] Figure 3 illustrates the AES CCM decryption acceleration process. In this acceleration mode, although CBC-MAC verification relies on the results of CTR decryption, AES core0 and AES core1 can work simultaneously through appropriate pipeline design. In this way, AES core0 can continuously perform CTR decryption, while AES core1 progressively verifies the already decrypted blocks. AES core0 and AES core1 can still perform their respective tasks concurrently, albeit in a specific order, essentially equivalent to parallel processing of CTR decryption and CBC-MAC verification. This not only ensures data security but also significantly improves decryption efficiency.

[0088] Table 1 shows a performance comparison example between Lockstep mode and Performance mode.

[0089] Table 1

[0090] As shown in Table 1, the throughput (number of bits processed per cycle) of Lockstep mode is higher than that of Performance mode across all key lengths. While the number of bits processed per cycle decreases in both modes as the key length increases, Lockstep mode consistently outperforms Performance mode by approximately twice.

[0091] In the method for implementing AES encryption operation provided in this application embodiment, when the second mode, namely Lockstep, is disabled, the first mode, namely Performance mode, is used to apply the extra computing cores for CCM acceleration. This avoids the problem of one AES core, such as AES core1, being idle and wasted. It achieves encryption / decryption speed of twice that of a single core, making reasonable use of AES computing resources and improving the encryption operation speed while ensuring security and reliability.

[0092] The method for implementing AES encryption computation provided in this application supports reusing the AES hardware computing core to accelerate the implementation of AES CCM encryption computation in both Lockstep mode (high security) and Performance mode (high performance). In other words, the AES hardware core can be effectively utilized in both modes, ensuring not only security and reliability (in Lockstep mode) but also improving the encryption computation speed through parallel processing when needed (in Performance mode).

[0093] This application also provides a computer-readable storage medium storing computer-executable instructions for performing the method for implementing AES encryption operations as described in any of the above-described figures 1.

[0094] This application further provides a computer device, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for performing the method for implementing AES encryption operations as described in any of Figure 1 above.

[0095] Figure 4 is a schematic diagram of the structure of a device for implementing AES encryption operations according to an embodiment of this application. As shown in Figure 4, it includes at least: a first processing module; wherein,

[0096] The first processing module includes two or more AES cores, configured such that: when the first mode is selected, different AES cores participating in the AES CCM encryption operation process different tasks in parallel. The different tasks include: CTR encryption / decryption and CBC-MAC calculation. When the AES core processing CTR encryption / decryption decrypts the current data block, the AES core processing CBC-MAC calculation verifies the decrypted data block.

[0097] In one exemplary instance, it also includes:

[0098] The first selection module is configured to select either a first mode or a second mode based on the application scenario requirements; wherein, the first mode is applied to scenarios with non-functional safety requirements, and the second mode is applied to scenarios with functional safety requirements.

[0099] In one exemplary instance, the first processing module is configured as follows:

[0100] The AES core that handles CTR encryption / decryption is responsible for CTR encryption of the data; the AES core that handles CBC-MAC calculation processes the CBC-MAC calculation of the corresponding data blocks in parallel and generates authentication tags.

[0101] The AES core handling CTR encryption / decryption first decrypts the CTR to generate plaintext; the AES core handling CBC-MAC calculation waits for the decryption result and then performs CBC-MAC verification to ensure data integrity. Simultaneously with decryption, the AES cores handling CTR encryption / decryption and CBC-MAC calculation process the next data block in parallel through a pipeline.

[0102] In one exemplary instance, the first processing module includes two sets of AES cores, namely AES core0 and AES core1, and the first processing module can be configured as follows:

[0103] In Lockstep Mode, AES core0 and AES core1 calculate CTR and CBC MAC in sequence, meaning that AES core0 and AES core1 process the same data stream in order, ensuring that the same data stream is strictly consistent during encryption and integrity verification.

[0104] In Performance Mode, AES core0 and AES core1 process different tasks in parallel to accelerate the encryption and decryption process and improve computational efficiency. AES core0 is responsible for CTR encryption / decryption, while AES core1 performs CBC-MAC calculations simultaneously. When AES core0 decrypts the current block, AES core1 verifies the already decrypted block.

[0105] In one exemplary instance, the first processing module may also be configured as follows:

[0106] In the case of selecting the second mode, the different AES cores participating in the AES CCM encryption operation serially calculate the CTR and CBC MAC.

[0107] In one embodiment, the AES core involved in processing CTR encryption / decryption may include one or more AES cores.

[0108] In one exemplary instance, the first processing module may also be configured as follows:

[0109] When the second mode is selected, different AES cores participating in the AES CCM encryption operation simultaneously process the input data and compare the results to ensure the correctness of the calculation.

[0110] The apparatus for implementing AES encryption operations provided in this application embodiment, in the second mode, namely Lockstep disabled, uses the first mode, namely Performance mode, to apply redundant computing cores for CCM acceleration, avoiding the problem of one AES core, such as AES core1, being idle and wasted. It achieves encryption / decryption speed of twice that of a single core, making reasonable use of AES computing resources and improving encryption operation speed while ensuring security and reliability.

[0111] This application embodiment also provides a method for implementing AES encryption, as shown in Figure 5, including:

[0112] Step 501: For the case where the first mode is selected, different AES cores participating in the AES encryption operation process different plaintext data blocks / ciphertext data blocks in parallel; among them, the data before and after AES encryption are independent.

[0113] In one exemplary instance, it also includes:

[0114] Step 500: Select the second mode or the first mode according to the application scenario requirements; wherein, the second mode is applied to scenarios with functional safety requirements, and the first mode is applied to scenarios without functional safety requirements.

[0115] In one exemplary instance, step 501 may further include:

[0116] When the second mode is selected, the different AES cores participating in the AES encryption operation process the input data simultaneously and compare the results to ensure the correctness of the calculation.

[0117] In AES encryption mode, "preceding data" typically refers to the relationship between input data blocks during the encryption process. "Preceding data" refers to data blocks that have already been encrypted, while "subsequent data" refers to data blocks that have not yet been encrypted. The lack of dependency between preceding and subsequent data means that each data block's encryption does not depend on the encryption result of the previous data block. In other words, the encryption of a data block can be performed independently without waiting for the previous data block to complete encryption. In this case, for scenarios requiring non-functional safety, the AES encryption method provided in this application can be used. Switching to the first mode, Performance Mode, allows different AES cores participating in the AES encryption operation to process different plaintext / ciphertext data blocks in parallel, enabling parallel processing of different data blocks and significantly improving encryption efficiency.

[0118] In one exemplary instance, AES encryption that does not depend on preceding or following data may include, but is not limited to, AES Electronic Codebook (ECB) encryption mode, AES Counter (CTR) mode, etc.

[0119] In one embodiment, when AES encryption with no dependency between preceding and following data is performed in AES ECB encryption mode, different AES cores participating in the AES encryption operation process different plaintext / ciphertext data blocks in parallel, which may include:

[0120] Different AES cores participating in AES encryption operations simultaneously input different plaintext or ciphertext data blocks to process them in parallel. In scenarios where non-functional safety requirements are not a factor, this parallel processing method significantly improves processing efficiency and reduces processing time due to simultaneous encryption and decryption.

[0121] In one exemplary instance, as shown in Figure 6, the encryption process includes: a plaintext data block is divided into multiple fixed-length plaintext data blocks (e.g., P1, P2, ..., Pn), and each plaintext data block Pi (e.g., P1, P2) is encrypted using the same key K and AES encryption algorithm (CIPH_k). After encryption, corresponding ciphertext data blocks are generated, such as C1, C2, ..., Cn. The encryption of each plaintext data block is independent; that is, each Pi is encrypted solely using key K to obtain Ci, without depending on the content of other data blocks. Decryption is the inverse operation of encryption. The decryption process includes: each ciphertext data block Ci is decrypted using the same key K and AES decryption algorithm (CIPH_k^(-1)), and after decryption, the corresponding plaintext data block (P1, P2, ..., Pn) is recovered. In ECB encryption mode, there is no dependency between preceding and following data blocks; the encryption and decryption of each data block are performed independently. Therefore, encryption or decryption operations can be performed simultaneously between data blocks to achieve parallel processing. This allows the ECB encryption mode to utilize multiple computing cores to process different data blocks in parallel when high throughput is required.

[0122] Taking the ECB encryption mode using two AES cores, namely AES core0 and AES core1, as shown in the dashed box in Figure 6, two data blocks (Plaintext or Ciphertext) can be input simultaneously at a time. Because each data block is encrypted independently in ECB mode, without relying on the calculation results of other data blocks, AES core0 is responsible for processing the first data block (e.g., P1 / C1), and AES core1 is responsible for processing the second data block (e.g., P2 / C2). AES core0 and AES core1 perform encryption or decryption operations simultaneously. As shown in Figure 6, during the encryption process, two plaintext data blocks (e.g., P1 and P2) and the same key K are input. AES core0 encrypts the plaintext data block P1 to generate the corresponding ciphertext data block C1, and AES core1 encrypts the plaintext data block P2 to generate the corresponding ciphertext data block C2. In this embodiment, encryption of the two data blocks in parallel improves processing speed. During decryption, two ciphertext data blocks (e.g., C1 and C2) and the same key K are input. AES core 0 decrypts ciphertext data block C1 to recover the corresponding plaintext data block P1, and AES core 1 decrypts ciphertext data block C2 to recover the corresponding plaintext data block P2. Since the operations on each data block are independent during decryption, decryption can also be performed in parallel. The ECB acceleration scheme shown in Figure 6 of this embodiment utilizes the characteristic that the preceding and following data are independent. By using two AES cores in parallel to process two data blocks, the encryption / decryption speed is almost doubled, significantly improving the efficiency of encryption or decryption. Moreover, by using two AES cores simultaneously, previously idle computing cores (such as the cores used for comparison in Lockstep mode) are efficiently utilized for actual data processing, thereby improving overall performance.

[0123] In one embodiment, for AES encryption of AES data into AES CTR where there is no dependency between the preceding and following data, different AES cores participating in the AES encryption operation process different plaintext / ciphertext data blocks in parallel, which may include:

[0124] Different AES cores participating in AES encryption operations simultaneously input different plaintext or ciphertext data blocks to process these different data blocks in parallel. In scenarios where non-functional safety requirements are not a factor, this parallel processing method significantly improves processing efficiency and reduces processing time due to simultaneous encryption and decryption.

[0125] In one exemplary instance, as shown in Figure 7, the encryption process includes: using an initialization vector (IV) and a counter (Ctr1, Ctr2, ..., Ctrrn) to generate different counter values ​​(Ctr1, Ctr2, ..., Ctrrn), each counter value is encrypted using the AES encryption algorithm (CIPH_k) and key K to generate a keystream block, and the keystream block is XORed (⊕) with the corresponding plaintext data block (P1, P2, ..., Pn) to generate a ciphertext data block (C1, C2, ..., Cn). The decryption process is similar to the encryption process, including: using the same IV and counter sequence, AES encryption (CIPH_k) is performed on each counter value to generate a keystream block, and then XORing the keystream block with the corresponding ciphertext data block (C1, C2, ..., Cn) to recover the original plaintext data block (P1, P2, ..., Pn). In CTR, each counter value is unique and independent, so these encryption operations can be performed in parallel. AES core0 and AES core1 can process different counter values, thus accelerating the entire encryption process. Decryption is also independent, allowing for parallel processing. In other words, in CTR mode, the encryption / decryption operations of plaintext and ciphertext data blocks are independent of other blocks. Therefore, different data blocks can be encrypted or decrypted simultaneously, achieving efficient parallel processing. The counters (Ctr1, Ctr2, ..., Ctrn) ensure that the input value for each block is unique. Even if multiple data blocks are encrypted simultaneously, the generated keystream blocks are different, ensuring data security.

[0126] Taking a CTR using two AES cores, AES core0 and AES core1, as shown in the dashed box in Figure 7, two data blocks (Plaintext or Ciphertext) can be input simultaneously, meaning two data entries are input at once. Because each data block is encrypted independently in ECB mode, without relying on the calculation results of other data blocks, AES core0 handles the first data block (e.g., P1 / C1), and AES core1 handles the second data block (e.g., P2 / C2). AES core0 and AES core1 perform encryption or decryption operations simultaneously. As shown in Figure 7, during encryption, an initialization vector (IV) is first used. This vector is combined with a counter to generate a unique input value. Each data block corresponds to a counter value, such as Ctr1 and Ctr2. The value of each counter increments (+1) to ensure that a different keystream block is generated each time encryption is performed. AES core0 receives Ctr1 and key K, generates a keystream block using the AES encryption algorithm, and then XORs this keystream block with the plaintext data block P1 (⊕) to generate ciphertext data block C1. AES core1 receives Ctr2 and key K, generates a keystream block using the AES encryption algorithm, and then XORs this keystream block with the plaintext data block P2 to generate ciphertext data block C2. During encryption, the counter increments with each data block processed, Ctr3, Ctr4, ..., Ctrn, for encryption of subsequent data blocks. Since the keystream for each data block is generated independently, the encryption process can be performed in parallel. During decryption, the same initialization vector (IV) and counter sequence as during encryption are used to ensure that the keystream block is consistent with the keystream generated during encryption. AES core0 receives Ctr1 and key K, generates a keystream block, and then XORs the keystream block with the ciphertext data block C1 to recover the plaintext data block P1. AES core1 receives Ctr2 and key K in parallel, generates a keystream block, and then XORs the keystream block with the ciphertext data block C2 to recover the plaintext data block P2. During decryption, the counter value increments for the decryption of subsequent data blocks (Ctr3, Ctr4,...), and parallel processing continues. It should be noted that, as shown in Figure 7 of this embodiment, the CTR mode accelerates AES encryption / decryption through counters and parallel computation. The process within the dashed box indicates that multiple data blocks can be processed in parallel by multiple AES cores. Taking two cores as an example, the CTR mode uses an initialization vector and a counter to generate a unique keystream block, which is XORed with the data block to obtain the encryption or decryption result.The calculation of each counter value is independent. Therefore, two AES cores, such as AES core0 and AES core1, can process different data blocks separately. AES core0 and AES core1 process plaintext or ciphertext data blocks corresponding to different counter values ​​(such as Ctr1 and Ctr2), generating the corresponding ciphertext or recovering the plaintext. Each AES core works independently, and there is no dependency between data blocks, achieving parallel processing and acceleration, which greatly improves the speed of encryption and decryption.

[0127] The method for implementing AES encryption operations provided in this application supports reusing the AES hardware computing core to accelerate the implementation of AES CCM encryption operations in both Lockstep mode (high security) and Performance mode (high performance) for AES encryption modes where there is no dependency between preceding and following data. In other words, the AES hardware core can be effectively utilized in both modes, ensuring not only security and reliability (in Lockstep mode) but also improving the encryption operation speed through parallel processing when needed (in Performance mode).

[0128] This application also provides a computer-readable storage medium storing computer-executable instructions for performing the method for implementing AES encryption operations as described in any of Figure 5 above.

[0129] This application further provides a computer device, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for performing the method for implementing AES encryption operations as described in any of Figure 5 above.

[0130] Figure 8 is a schematic diagram of another structural composition of the apparatus for implementing AES encryption operation according to an embodiment of this application. As shown in Figure 8, it includes at least: a second processing module; wherein,

[0131] The second processing module is configured to allow different AES cores participating in the AES encryption operation to process different plaintext / ciphertext data blocks in parallel when the first mode is selected, wherein the data before and after AES encryption are independent.

[0132] In one exemplary instance, it may also include:

[0133] The second selection module is configured to select either the second mode or the first mode based on the application scenario requirements; wherein the second mode is applied to scenarios with functional safety requirements, and the first mode is applied to scenarios with non-functional safety requirements.

[0134] In one exemplary instance, the second processing module may also be configured as follows:

[0135] When the second mode is selected, the different AES cores participating in the AES encryption operation process the input data simultaneously and compare the results to ensure the correctness of the calculation.

[0136] In one exemplary instance, AES encryption that does not depend on preceding or following data may include, but is not limited to, AES Electronic Codebook (ECB) encryption mode, AES Counter (CTR) mode, etc.

[0137] In one exemplary instance, for cases where AES encryption is performed in AES ECB encryption mode or AES CTR mode, where there is no dependency between preceding and following data, the second processing module is configured as follows:

[0138] Different AES cores participating in AES encryption operations simultaneously input different plaintext or ciphertext data blocks to process these different data blocks in parallel.

[0139] The apparatus for implementing AES encryption operations provided in this application supports reusing the AES hardware computing core to accelerate the implementation of AES CCM encryption operations in both Lockstep mode (high security) and Performance mode (high performance) for AES encryption modes where there is no dependency between preceding and following data, such as AES ECB encryption mode and AES CTR. In other words, the AES hardware core can be effectively utilized in both modes, ensuring not only security and reliability (in Lockstep mode) but also improving the encryption operation speed through parallel processing when needed (in Performance mode).

[0140] Figure 9 is a schematic diagram of another possible structure of the apparatus for implementing AES encryption operations according to an embodiment of this application. As shown in Figure 9, it includes at least: a processing module, a mode selection module, a task scheduling module, and a result comparison module. Wherein:

[0141] The processing module includes at least two AES cores. The at least two AES computing cores are divided into one or more core sets according to the task requirements, and are respectively configured to perform CTR encryption / decryption operations and CBC-MAC operations, or configured to perform the same encryption operation process in functional safety scenarios.

[0142] The mode selection module is configured to switch between Performance mode and Lockstep mode based on the security requirements of the upper-layer application.

[0143] The task scheduling module is configured to schedule the core collection in different modes as follows:

[0144] In Performance mode, the current data block to be processed (including the plaintext block during encryption and the ciphertext block during decryption) is subjected to CTR encryption / decryption operations in one set of cores, and the input corresponding to the data block is subjected to CBC-MAC operations / verification in another set of cores to achieve parallel or pipelined processing of the two types of operation paths; in the decryption process, CTR decryption and CBC-MAC verification are interleaved according to the grouped data blocks to form a block-level pipeline;

[0145] In Lockstep mode, at least two AES cores are selected for each data block to be processed to form a lockstep core set, so that each AES core in the lockstep core set performs the same CTR encryption / decryption and CBC-MAC calculation process on the same input data.

[0146] The result comparison module is configured to perform consistency determination on the output results of the lockstep core set in Lockstep mode. In one embodiment, the consistency determination includes comparing the two results and / or voting by multiple parties, and outputting an error flag and / or triggering a fault-tolerant processing flow when there is inconsistency.

[0147] In one exemplary embodiment, the apparatus for implementing AES encryption operations in this application can be applied to the hardware security module (HSM) in a millimeter-wave radar chip. In another exemplary embodiment, the apparatus for implementing AES encryption operations in this application can also be integrated into the security processing unit in a UWB SoC for processing UWB data encryption and decryption.

[0148] In one embodiment, the device for implementing AES encryption is integrated into the hardware security module (HSM) in the millimeter-wave radar system-on-a-chip (SoC) for real-time encryption and authentication of communication messages between vehicle ECUs.

[0149] The processing module can include four AES cores, which can be divided into different core sets as needed. For example, in Performance mode, core set 0 and core set 1 are used to perform CTR operations, while core set 2 and core set 3 are used to perform CBC-MAC operations. In Lockstep mode, core set 0 and core set 1 form a lockstep set, and core set 2 and core set 3 form a lockstep set. Each core set performs a complete CTR+CBC-MAC operation on the same packet and compares the results within the set.

[0150] The mode selection module can be controlled by the software configuration register config_lockstepen. When the gateway is running in normal mode, the Performance mode is selected to improve throughput, and when it is running in security diagnostic mode, the Lockstep mode is selected to ensure computational reliability.

[0151] In Performance mode, the task scheduling module inputs each pending data block into the CTR path and the CBC-MAC path, which are executed in parallel. During the decryption process, the scheduling module can employ a block-level pipeline: when the i-th packet is decrypted on the CTR path, its result immediately enters the CBC-MAC verification, while the CTR path continues to process the (i+1)-th packet, thereby improving decryption throughput.

[0152] In Lockstep mode, the result comparison module reads the output results of the lockstep set and performs consistency judgment. When the outputs within the set are inconsistent, an internal security interrupt is triggered, an error is reported, and message output can be further blocked.

[0153] The device in this embodiment can be implemented in the HSM in the millimeter-wave radar SOC. In Performance mode, the AES-CCM throughput is increased by about 2 times. In Lockstep mode, hardware and software faults of a single AES core can be detected, thereby ensuring the reliability of vehicle safety-critical communication.

[0154] Although the embodiments disclosed in this application are as described above, the content described is merely for the purpose of understanding this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A method of implementing an AES encryption operation, characterized by, include: In the first mode, different Advanced Encryption Standard (AES) cores participating in the AES CCM encryption operation process different tasks in parallel. These tasks include: Counter Mode CTR encryption / decryption, Cipher Block Chaining Message Authentication Code (CBC-MAC) calculation, and while the AES core processing CTR encryption / decryption is decrypting the current data block, the AES core processing CBC-MAC calculation is verifying the decrypted data block.

2. The method according to claim 1, further comprising: Choose either the first mode for scenarios with non-functional safety requirements or the second mode for scenarios with functional safety requirements. When the second mode is selected, the different AES cores participating in the AES CCM encryption operation simultaneously process the input data and compare the results to ensure the correctness of the calculation.

3. The method according to claim 2, further comprising, in the second mode: The different AES cores involved in the AES CCM encryption operation serially calculate the CTR and CBC MAC, and compare the results.

4. The method of claim 3, wherein, The AES core for processing CTR encryption / decryption includes one or more.

5. The method according to claim 1 or 2, wherein, The different tasks are CTR encrypted; The AES core that processes CTR encryption / decryption is responsible for CTR encryption of the data; the AES core that processes CBC-MAC calculation processes the CBC-MAC calculation of the corresponding data blocks in parallel to generate authentication tags.

6. The method according to claim 1 or 2, wherein, The different tasks are for CTR decryption; The AES core that processes CTR encryption / decryption is responsible for generating plaintext through CTR decryption of data. The AES core that processes the CBC-MAC calculation performs CBC-MAC verification based on the decryption result to ensure data integrity. Simultaneously, the AES core that processes CTR encryption / decryption and the AES core that processes the CBC-MAC calculation process the next data block in parallel through a pipeline.

7. The method of claim 2, wherein, By setting the configuration register, the second mode and the first mode can be selected.

8. The method of claim 7, wherein, The first mode is the performance mode; the second mode is the lockstep mode.

9. A method of implementing an AES encryption operation, characterized by, include: In the first mode, different AES cores participating in the AES encryption operation process different plaintext / ciphertext data blocks in parallel; the data before and after AES encryption are independent.

10. The method of claim 9, further comprising: Choose either the first mode for scenarios with non-functional safety requirements or the second mode for scenarios with functional safety requirements. When the second mode is selected, the different AES cores participating in the AES encryption operation simultaneously process the input data and compare the results to ensure the correctness of the calculation.

11. The method of claim 9 or 10, wherein, The AES encryption that does not depend on the preceding and following data includes: AES Electronic Codebook (ECB) encryption mode and AES Counter (CTR) mode.

12. The method of claim 9 or 10, wherein, The different AES cores participating in the AES encryption operation process different plaintext / ciphertext data blocks in parallel, including: The different AES cores participating in the AES encryption operation simultaneously input different plaintext data blocks or ciphertext data blocks to process different data blocks in parallel.

13. A computer readable storage medium storing computer executable instructions for performing the method of any of claims 1-8, and / or 9-12 for implementing an AES encryption operation.

14. A computer device comprising a memory and a processor, wherein, The memory stores instructions executable by the processor for performing the steps of the method of any of claims 1-8, and / or 9-12 for implementing an AES encryption operation.

15. An apparatus for implementing an AES encryption operation, the apparatus comprising: The device comprises: The processing module, the mode selection module, the task scheduling module, and the result comparison module; wherein The processing module comprises at least two AES cores, and the at least two AES computing cores are divided into one or more core sets according to task requirements, and are respectively configured to perform CTR encryption / decryption operations and CBC-MAC operations, or to perform the same encryption operation process in a functional safety scenario; The mode selection module is configured to switch between the Performance mode and the Lockstep mode according to the security requirements of an upper layer application; The task scheduling module is configured to schedule the core sets as follows in different modes: In the Performance mode, the current data block to be processed is executed in a CTR encryption / decryption operation in one core set, and the input corresponding to the data block is executed in a CBC-MAC operation / verification in another core set, to realize parallel or pipelining processing of the two types of operation paths; wherein, in the decryption process, the CTR decryption and the CBC-MAC verification are staggered according to the grouped data blocks to form a block-level pipelining; In the Lockstep mode, at least two AES cores are selected for each data block to be processed to form a lockstep core set, and the AES cores in the lockstep core set perform the same CTR encryption / decryption and CBC-MAC calculation process on the same input data; The result comparison module is configured to determine the consistency of the output results of the lockstep core set in the Lockstep mode.

16. The apparatus of claim 15, wherein, The device is applied to a hardware security module (HSM) in a millimeter wave radar chip.

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