Switching element drive circuit and power conversion device

Abstract

The present invention addresses the problem of suppressing a decrease in the voltage of a first capacitor in a first bootstrap circuit. A switching element drive circuit (2) comprises a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a plurality of third bootstrap circuits (73), and a plurality of auxiliary diodes (D8). In each of the plurality of auxiliary diodes (D8), a cathode is connected to a high-potential end of a first capacitor (C1) in a first bootstrap circuit (71), corresponding to one inverter circuit (1) of a plurality of inverter circuits (1), among the plurality of first bootstrap circuits (71). In each of the plurality of auxiliary diodes (D8), an anode is connected to a high-potential end of a third capacitor (C3) in a third bootstrap circuit (73), corresponding to a different inverter circuit (1) than the one inverter circuit (1), among the plurality of third bootstrap circuits (73).

Description

Switching element drive circuit and power conversion device

[0001] This disclosure relates to a switching element drive circuit and a power conversion device, and more particularly to a switching element drive circuit comprising a bootstrap circuit, and a power conversion device comprising the switching element drive circuit.

[0002] Patent Document 1 discloses a three-phase multilevel power converter as a power conversion device, comprising three diode clamp type multilevel power conversion circuits (inverter circuits), three individual gate drive units, a shared power supply, and a signal output unit.

[0003] Each of the three diode clamp-type multilevel power conversion circuits has four switches connected in series. Each of the three individual gate drives consists of four gate drivers and four interface circuits, each connected to one of the four switches. Patent Document 1 states that a shared power supply can be shared by the three gate driver sections. Patent Document 1 also discloses an example in which each of the four interface circuits is implemented using a bootstrap circuit. The bootstrap circuit charges the high-voltage capacitor from the shared power supply or the low-voltage capacitor using a combination of diodes and capacitors.

[0004] In the power conversion device disclosed in Patent Document 1, a circuit (switching element drive circuit) comprising three individual gate drives, a shared power supply, and a signal output unit, there is a period during which the capacitor (first capacitor) of the high-voltage side bootstrap circuit (first bootstrap circuit) in each of the three individual gate drives cannot be charged, and the capacitor voltage may become too low.

[0005] Japanese Patent Publication No. 2009-177951

[0006] The object of this disclosure is to provide a switching element driving circuit and a power conversion device that can suppress the voltage drop of the first capacitor in each of a plurality of first bootstrap circuits.

[0007] A switching element drive circuit according to one aspect of the present disclosure drives a plurality of inverter circuits. The plurality of inverter circuits comprises a plurality of first switching elements, a plurality of second switching elements, a plurality of third switching elements, a plurality of fourth switching elements, a plurality of first clamp diodes, and a plurality of second clamp diodes. The plurality of first switching elements are connected to the positive terminal of a DC power supply unit having a positive terminal, a negative terminal, and an intermediate potential point. The plurality of second switching elements are each connected in series to the plurality of first switching elements. The plurality of third switching elements are each connected in series to the plurality of second switching elements. The plurality of fourth switching elements are each connected in series to the plurality of third switching elements. The plurality of fourth switching elements are connected to the negative terminal of the DC power supply unit. The plurality of first clamp diodes have their cathodes connected to a plurality of first connection points between the plurality of first switching elements and the plurality of second switching elements, and their anodes are connected to the intermediate potential point. The plurality of second clamp diodes have anodes connected to a plurality of second connection points between the plurality of third switching elements and the plurality of fourth switching elements, and cathodes connected to the intermediate potential points. The switching element driving circuit comprises a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of first bootstrap circuits, a plurality of second bootstrap circuits, a plurality of third bootstrap circuits, a DC voltage source, a control device, and a plurality of auxiliary diodes. The plurality of first gate drivers each drive the plurality of first switching elements. The plurality of second gate drivers each drive the plurality of second switching elements. The plurality of third gate drivers each drive the plurality of third switching elements. The plurality of fourth gate drivers each drive the plurality of fourth switching elements. The plurality of first bootstrap circuits correspond one-to-one with the plurality of first gate drivers.Each of the plurality of first bootstrap circuits includes a first capacitor connected in parallel to the corresponding first gate driver and a first diode connected to the high potential terminal of the first capacitor. The plurality of second bootstrap circuits correspond one-to-one with the plurality of second gate drivers. Each of the plurality of second bootstrap circuits includes a second capacitor connected in parallel to the corresponding second gate driver and a second diode connected to the high potential terminal of the second capacitor. The plurality of third bootstrap circuits correspond one-to-one with the plurality of third gate drivers. Each of the plurality of third bootstrap circuits includes a third capacitor connected in parallel to the corresponding third gate driver and a third diode connected to the high potential terminal of the third capacitor. The DC voltage source is connected to the plurality of fourth gate drivers. The control device outputs a plurality of first control signals, a plurality of second control signals, a plurality of third control signals, and a plurality of fourth control signals to be supplied to the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers, respectively. Each of the plurality of auxiliary diodes has its cathode connected to the high-potential terminal of the first capacitor of the first bootstrap circuit that corresponds to any one inverter circuit among the plurality of inverter circuits. Each of the plurality of auxiliary diodes has its anode connected to the high-potential terminal of the third capacitor of the third bootstrap circuit that corresponds to an inverter circuit different from any one inverter circuit among the plurality of third bootstrap circuits.

[0008] A switching element drive circuit according to one aspect of the present disclosure drives a plurality of inverter circuits. The plurality of inverter circuits comprises a plurality of first switching elements, a plurality of second switching elements, a plurality of third switching elements, a plurality of fourth switching elements, a plurality of first clamp diodes, and a plurality of second clamp diodes. The plurality of first switching elements are connected to the positive terminal of a DC power supply unit having a positive terminal, a negative terminal, and an intermediate potential point. The plurality of second switching elements are each connected in series to the plurality of first switching elements. The plurality of third switching elements are each connected in series to the plurality of second switching elements. The plurality of fourth switching elements are each connected in series to the plurality of third switching elements. The plurality of fourth switching elements are connected to the negative terminal of the DC power supply unit. The plurality of first clamp diodes have their cathodes connected to a plurality of first connection points between the plurality of first switching elements and the plurality of second switching elements, and their anodes are connected to the intermediate potential point. The plurality of second clamp diodes have their anodes connected to a plurality of second connection points between the plurality of third switching elements and the plurality of fourth switching elements, and their cathodes connected to the intermediate potential points. The switching element driving circuit comprises a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of first bootstrap circuits, a plurality of second bootstrap circuits, a plurality of third bootstrap circuits, a DC voltage source, a control device, and a plurality of auxiliary diodes. The plurality of first gate drivers each drive the plurality of first switching elements. The plurality of second gate drivers each drive the plurality of second switching elements. The plurality of third gate drivers each drive the plurality of third switching elements. The plurality of fourth gate drivers each drive the plurality of fourth switching elements. The plurality of first bootstrap circuits correspond one-to-one with the plurality of first gate drivers. Each of the plurality of first bootstrap circuits includes a first capacitor connected in parallel with the corresponding first gate driver.Each of the plurality of second bootstrap circuits corresponds one-to-one with each of the plurality of second gate drivers. Each of the plurality of second bootstrap circuits includes a second capacitor connected in parallel with the corresponding second gate driver and a first diode connected to the high potential terminal of the second capacitor. Each of the plurality of third bootstrap circuits corresponds one-to-one with each of the plurality of third gate drivers. Each of the plurality of third bootstrap circuits includes a third capacitor connected in parallel with the corresponding third gate driver and a second diode connected to the high potential terminal of the third capacitor. The DC voltage source is connected to each of the plurality of fourth gate drivers. The control device outputs a plurality of first control signals, a plurality of second control signals, a plurality of third control signals, and a plurality of fourth control signals to be supplied to each of the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers, respectively. Each of the plurality of auxiliary diodes has its cathode connected to the high potential terminal of the first capacitor of the first bootstrap circuit that corresponds to any one inverter circuit in the plurality of inverter circuits from among the plurality of first bootstrap circuits. Each of the plurality of auxiliary diodes has its anode connected to the high-potential terminal of the third capacitor of the third bootstrap circuit that corresponds to a third bootstrap circuit different from any one of the plurality of third bootstrap circuits.

[0009] A power conversion device according to one aspect of the present disclosure comprises a switching element drive circuit according to the above-described aspect and the plurality of inverter circuits.

[0010] Figure 1 is a circuit diagram of a power converter equipped with a switching element drive circuit according to Embodiment 1. Figure 2 is an explanatory diagram of the current path when the switching circuit is in the first switching state in the power converter. Figure 3 is an explanatory diagram of the power converter when the switching circuit is in the first switching state. Figure 4 is an explanatory diagram of the current path when the switching circuit is in the second switching state in the power converter. Figure 5 is an explanatory diagram of the charging path when the switching circuit is in the second switching state in the power converter. Figure 6 is an explanatory diagram of the current path when the switching circuit is in the third switching state in the power converter. Figure 7 is an explanatory diagram of the charging path when the switching circuit is in the third switching state in the power converter. Figure 8 is an explanatory diagram of the voltage command values ​​of each phase in the power converter. Figure 9 is an explanatory diagram of a group of voltage vectors relating to the power converter. Figure 10 is a more detailed explanatory diagram of a group of voltage vectors relating to the power converter. Figure 11 is a vector diagram for explaining the operation of the control device in the power converter. Figure 12 is a time chart of the switching state of each phase of the power converter described above. Figure 13 is a time chart of the on-off state of the first to fourth switching elements of the power converter described above. Figure 14 is an explanatory diagram of the operation of the power converter described above. Figure 15 is an operating waveform diagram of the power converter described above. Figure 16 is a circuit diagram of a power converter equipped with a switching element drive circuit according to Embodiment 2. Figure 17 is an explanatory diagram of the vector substitution control of the control device in the switching element drive circuit according to Embodiment 3. Figure 18 is a time chart of the switching state of each phase of the power converter described above. Figure 19 is a time chart of the on-off state of the first to fourth switching elements of the power converter described above. Figure 20 is a timing chart for explaining the switching pattern control of the control device in the switching element drive circuit according to Embodiment 4. Figure 21 is an explanatory diagram of the current path when the switching circuit is in the fourth switching state in the power converter described above. Figure 22 is an explanatory diagram when the switching circuit is in the fourth switching state in the power converter described above.Figure 23 is an explanatory diagram of the operation of the switching element drive circuit according to Embodiment 5. Figure 24 is a circuit diagram of a power conversion device equipped with a switching element drive circuit according to Embodiment 6. Figure 25 is a circuit diagram of a power conversion device equipped with a switching element drive circuit according to Embodiment 7.

[0011] (Embodiment 1) Below, a power conversion device 100 equipped with a switching element drive circuit 2 according to Embodiment 1 will be described with reference to Figures 1 to 15.

[0012] (1) Configuration of switching element drive circuit and power converter The switching element drive circuit 2 (see Figure 1) according to Embodiment 1 is a circuit that drives a plurality of inverter circuits 1 (three in the example of Figure 1). Each of the plurality of inverter circuits 1 is a diode clamp type 3-level inverter.

[0013] The multiple inverter circuits 1 (three in the example of Figure 1) comprise multiple (three in the example of Figure 1) first switching elements Q1, multiple (three in the example of Figure 1) second switching elements Q2, multiple (three in the example of Figure 1) third switching elements Q3, multiple (three in the example of Figure 1) fourth switching elements Q4, multiple (three in the example of Figure 1) first clamp diodes D5, and multiple (three in the example of Figure 1) second clamp diodes D6. The multiple first switching elements Q1 are connected to the positive electrode P1 of a DC power supply unit 3, which has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The "intermediate potential point M1" is the point where the potential is midway between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3. The multiple second switching elements Q2 are each connected in series to the multiple first switching elements Q1. The multiple third switching elements Q3 are each connected in series to the multiple second switching elements Q2. Multiple fourth switching elements Q4 are connected in series with multiple third switching elements Q3 and connected to the negative terminal N1 of the DC power supply unit 3. Multiple first clamp diodes D5 have their cathodes connected to multiple first connection points 11 between multiple first switching elements Q1 and multiple second switching elements Q2, and their anodes are connected to the intermediate potential point M1. Multiple second clamp diodes D6 have their anodes connected to multiple second connection points 12 between multiple third switching elements Q3 and multiple fourth switching elements Q4, and their cathodes are connected to the intermediate potential point M1.

[0014] The switching element driving circuit 2 comprises a plurality of (three in the example of Figure 1) first gate drivers 61, a plurality of (three in the example of Figure 1) second gate drivers 62, a plurality of (three in the example of Figure 1) third gate drivers 63, a plurality of (three in the example of Figure 1) fourth gate drivers 64, a plurality of (three in the example of Figure 1) first bootstrap circuits 71, a plurality of (three in the example of Figure 1) second bootstrap circuits 72, a plurality of (three in the example of Figure 1) third bootstrap circuits 73, a DC voltage source 6, a control device 4, and a plurality of (six in the example of Figure 1) auxiliary diodes D8.

[0015] A plurality of first gate drivers 61 drive the plurality of first switching elements Q1 respectively. A plurality of second gate drivers 62 drive the plurality of second switching elements Q2 respectively. A plurality of third gate drivers 63 drive the plurality of third switching elements Q3 respectively. A plurality of fourth gate drivers 64 drive the plurality of fourth switching elements Q4 respectively.

[0016] A plurality of first bootstrap circuits 71 correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first bootstrap circuits 71 includes a first capacitor C1 connected in parallel to the corresponding first gate driver 61. A plurality of second bootstrap circuits 72 correspond one-to-one to the plurality of second gate drivers 62. Each of the plurality of second bootstrap circuits 72 includes a second capacitor C2 connected in parallel to the corresponding second gate driver 62. A plurality of third bootstrap circuits 73 correspond one-to-one to the plurality of third gate drivers 63. Each of the plurality of third bootstrap circuits 73 includes a third capacitor C3 connected in parallel to the corresponding third gate driver 63.

[0017] A DC voltage source 6 is connected in parallel to the plurality of fourth gate drivers 64.

[0018] The control device 4 outputs a plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3, and a plurality of fourth control signals S4 to the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 respectively.

[0019] Each of the plurality of auxiliary diodes D8 has its cathode connected to the high-potential end of the first capacitor C1 of the first bootstrap circuit 71 corresponding to any one of the plurality of inverter circuits 1 in the plurality of first bootstrap circuits 71. Each of the plurality of auxiliary diodes D8 has its anode connected to the high-potential end of the third capacitor C3 of the third bootstrap circuit 73 corresponding to an inverter circuit 1 different from the above-mentioned any one inverter circuit 1 among the plurality of third bootstrap circuits 73.

[0020] The switching element drive circuit 2 according to Embodiment 1 can suppress a decrease in the voltage VC1 (see FIGS. 3 and 15) of the first capacitor C1 of each of the plurality of first bootstrap circuits 71.

[0021] The power conversion device 100 according to Embodiment 1 includes a switching element drive circuit 2 and a plurality (three in FIG. 1) of inverter circuits 1.

[0022] The power conversion device 100 according to Embodiment 1 can suppress a decrease in the voltage VC1 of the first capacitor C1 of each of the plurality of first bootstrap circuits 71.

[0023] (2) Details of the switching element drive circuit and the power conversion device The power conversion device 100 includes, for example, as shown in FIG. 1, a DC power supply unit 3, a plurality (three in the example of FIG. 1) of inverter circuits 1, and a switching element drive circuit 2. The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3.

[0024] The DC power supply unit 3 includes a fourth capacitor C31 and a fifth capacitor C32. In the DC power supply unit 3, the fourth capacitor C31 and the fifth capacitor C32 are connected in series. The DC power supply unit 3 further includes a first DC terminal 31 connected to the positive terminal P1 and a second DC terminal 32 connected to the negative terminal N1. In the DC power supply unit 3, the first end of the fourth capacitor C31 is connected to the first DC terminal 31, the second end of the fourth capacitor C31 is connected to the first end of the fifth capacitor C32, and the second end of the fifth capacitor C32 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection point between the fourth capacitor C31 and the fifth capacitor C32 is an intermediate potential point M1. An external power supply that outputs a DC output voltage is connected between the first DC terminal 31 and the second DC terminal 32, for example. In this case, the output voltage of the external power supply is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the fifth capacitor C32 is the same as the capacitance of the fourth capacitor C31. "The capacitance of the fifth capacitor C32 is the same as the capacitance of the fourth capacitor C31" does not mean that the capacitance of the fifth capacitor C32 is exactly the same as the capacitance of the fourth capacitor C31, but rather that the capacitance of the fifth capacitor C32 is within the range of 90% to 110% of the capacitance of the fourth capacitor C31.

[0025] The power converter 100 is a diode clamp type three-level three-phase inverter. In the power converter 100, each of the multiple inverter circuits 1 has an output terminal 8. In the power converter 100, multiple (three in the example of Figure 1) output terminals 8 are connected to an AC load (not shown).

[0026] The AC load is, for example, a three-phase servo motor. In the power converter 100, one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining one is an inverter circuit 1W that outputs a W-phase voltage. For the sake of explanation, below, the output terminal 8 included in inverter circuit 1U will be referred to as output terminal 8U, the output terminal 8 included in inverter circuit 1V will be referred to as output terminal 8V, and the output terminal 8 included in inverter circuit 1W will be referred to as output terminal 8W.

[0027] Each of the multiple inverter circuits 1 includes a switching circuit 10 (see Figure 2), a first clamp diode D5, and a second clamp diode D6. In the power conversion device 100, the potential of the intermediate potential point M1 is clamped by the first clamp diode D5 and the second clamp diode D6 of each inverter circuit 1.

[0028] Each switching circuit 10 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4. In each switching circuit 10, the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series from the positive electrode P1 side to the negative electrode N1 side of the DC power supply unit 3 in the order of first switching element Q1, second switching element Q2, third switching element Q3, and fourth switching element Q4.

[0029] Each switching circuit 10 further includes four diodes D1 to D4. Diode D1 is connected in antiparallel to the first switching element Q1. Diode D2 is connected in antiparallel to the second switching element Q2. Diode D3 is connected in antiparallel to the third switching element Q3. Diode D4 is connected in antiparallel to the fourth switching element Q4. The first clamp diode D5 is connected between the first connection point 11 between the first switching element Q1 and the second switching element Q2 and the intermediate potential point M1. The second clamp diode D6 is connected between the second connection point 12 between the third switching element Q3 and the fourth switching element Q4 and the intermediate potential point M1.

[0030] Each switching circuit 10 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4, each having a control terminal, a first main terminal, and a second main terminal. Each switching circuit 10 has, for example, an insulated-gate bipolar transistor (IGBT). Therefore, the control terminal, first main terminal, and second main terminal of each of the first switching element Q1, second switching element Q2, third switching element Q3, and fourth switching element Q4 in each switching circuit 10 are the gate terminal, collector terminal, and emitter terminal, respectively.

[0031] The control terminal of the first switching element Q1 of each switching circuit 10 is connected to the corresponding first gate driver 61 from among a plurality of first gate drivers 61. The control terminal of the second switching element Q2 of each switching circuit 10 is connected to the corresponding second gate driver 62 from among a plurality of second gate drivers 62. The control terminal of the third switching element Q3 of each switching circuit 10 is connected to the corresponding third gate driver 63 from among a plurality of third gate drivers 63. The control terminal of the fourth switching element Q4 of each switching circuit 10 is connected to the corresponding fourth gate driver 64 from among a plurality of fourth gate drivers 64.

[0032] In each switching circuit 10, the first main terminal of the first switching element Q1 is connected to the positive terminal P1 of the DC power supply unit 3, and the second main terminal of the first switching element Q1 is connected to the first main terminal of the second switching element Q2. In addition, in each switching circuit 10, the second main terminal of the second switching element Q2 is connected to the first main terminal of the third switching element Q3. In addition, in each switching circuit 10, the second main terminal of the third switching element Q3 is connected to the first main terminal of the fourth switching element Q4, and the second main terminal of the fourth switching element Q4 is connected to the negative terminal N1 of the DC power supply unit 3.

[0033] In inverter circuit 1U, the third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10 is connected to the output terminal 8U. In inverter circuit 1V, the third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10 is connected to the output terminal 8V. In inverter circuit 1W, the third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10 is connected to the output terminal 8W. The third connection point 13 of inverter circuit 1U is connected to, for example, the U-phase terminal of an AC load via the output terminal 8U. The third connection point 13 of inverter circuit 1V is connected to, for example, the V-phase terminal of an AC load via the output terminal 8V. The third connection point 13 of inverter circuit 1W is connected to, for example, the W-phase terminal of an AC load via the output terminal 8W.

[0034] In each switching circuit 10, the anode of diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1. In addition, in each switching circuit 10, the anode of diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2. In addition, in each switching circuit 10, the anode of diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3. Furthermore, in each switching circuit 10, the anode of diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.

[0035] In each switching circuit 10, diode D1 may be replaced with a parasitic diode of the IGBT constituting the first switching element Q1. Also, in each switching circuit 10, diode D2 may be replaced with a parasitic diode of the IGBT constituting the second switching element Q2. Also, in each switching circuit 10, diode D3 may be replaced with a parasitic diode of the IGBT constituting the third switching element Q3. Also, in each switching circuit 10, diode D4 may be replaced with a parasitic diode of the IGBT constituting the fourth switching element Q4.

[0036] In each inverter circuit 1, the cathode of the first clamp diode D5 is connected to the first connection point 11 between the first switching element Q1 and the second switching element Q2. The anode of the first clamp diode D5 is connected to the intermediate potential point M1 of the DC power supply unit 3. In Embodiment 1, since the intermediate potential point M1 is connected to ground, the potential of the intermediate potential point M1 is 0V. In this case, if the voltage across the DC power supply unit 3 is Vdc, the potential of the positive electrode P1 is Vdc / 2, and the potential of the negative electrode N1 is -Vdc / 2.

[0037] The cathode of the second clamp diode D6 is connected to the intermediate potential point M1. The anode of the second clamp diode D6 is connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4.

[0038] Multiple first gate drivers 61 correspond one-to-one with multiple first switching elements Q1. Each of the multiple first gate drivers 61 is connected to the control terminal of the corresponding first switching element Q1. Each of the multiple first gate drivers 61 drives the corresponding first switching element Q1. Multiple first gate drivers 61 are connected to a control device 4. The control device 4 outputs multiple first control signals S1 that correspond one-to-one with the multiple first gate drivers 61. Each of the multiple first gate drivers 61 controls the first switching element Q1 to be on or off based on the given first control signal S1.

[0039] Multiple second gate drivers 62 correspond one-to-one with multiple second switching elements Q2. Each of the multiple second gate drivers 62 is connected to the control terminal of the corresponding second switching element Q2. Each of the multiple second gate drivers 62 drives the corresponding second switching element Q2. Multiple second gate drivers 62 are connected to a control device 4. The control device 4 outputs multiple second control signals S2 that correspond one-to-one with the multiple second gate drivers 62. Each of the multiple second gate drivers 62 controls the second switching element Q2 to be on or off based on the given second control signal S2.

[0040] Multiple third gate drivers 63 correspond one-to-one with multiple third switching elements Q3. Each of the multiple third gate drivers 63 is connected to the control terminal of the corresponding third switching element Q3. Each of the multiple third gate drivers 63 drives the corresponding third switching element Q3. Multiple third gate drivers 63 are connected to a control device 4. The control device 4 outputs multiple third control signals S3 that correspond one-to-one with the multiple third gate drivers 63. Each of the multiple third gate drivers 63 controls the on / off state of the third switching element Q3 based on the given third control signal S3.

[0041] Multiple fourth gate drivers 64 correspond one-to-one with multiple fourth switching elements Q4. Each of the multiple fourth gate drivers 64 is connected to the control terminal of the corresponding fourth switching element Q4. Each of the multiple fourth gate drivers 64 drives the corresponding fourth switching element Q4. The multiple fourth gate drivers 64 are connected to a control device 4. The control device 4 outputs multiple fourth control signals S4 that correspond one-to-one with the multiple fourth gate drivers 64. Each of the multiple fourth gate drivers 64 controls the on / off state of the fourth switching element Q4 based on the given fourth control signal S4.

[0042] Each of the multiple first bootstrap circuits 71 supplies voltage to the corresponding first gate driver 61 among the multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 has a diode D11 (hereinafter also referred to as the first diode D11) in addition to the first capacitor C1. Each of the multiple second bootstrap circuits 72 supplies voltage to the corresponding second gate driver 62 among the multiple second gate drivers 62. Each of the multiple second bootstrap circuits 72 has a diode D12 (hereinafter also referred to as the second diode D12) in addition to the second capacitor C2. Each of the multiple third bootstrap circuits 73 supplies voltage to the corresponding third gate driver 63 among the multiple third gate drivers 63. Each of the multiple third bootstrap circuits 73 has a diode D13 (hereinafter also referred to as the third diode D13) in addition to the third capacitor C3.

[0043] In each first bootstrap circuit 71, the anode of the first diode D11 is connected to the positive terminal of the DC voltage source 6 via the second diode D12 and the third diode D13. In each first bootstrap circuit 71, the cathode of the first diode D11 is connected to the high-potential terminal (first terminal) of the first capacitor C1. The high-potential terminal of the first capacitor C1 is connected to the high-potential side power supply terminal 61H (see Figure 3) of the first gate driver 61. The low-potential terminal (second terminal) of the first capacitor C1 is connected to the low-potential side power supply terminal 61L (see Figure 3) of the first gate driver 61. The first bootstrap circuit 71 supplies the first gate driver 61 with the voltage necessary to turn on the first switching element Q1 (a voltage greater than the threshold voltage of the first switching element Q1).

[0044] Each of the multiple second bootstrap circuits 72 supplies voltage to the corresponding second gate driver 62 among the multiple second gate drivers 62. In each second bootstrap circuit 72, the anode of the second diode D12 is connected to the positive terminal of the DC voltage source 6 via the third diode D13. In each second bootstrap circuit 72, the cathode of the second diode D12 is connected to the high-potential terminal (first terminal) of the second capacitor C2. The high-potential terminal of the second capacitor C2 is connected to the high-potential side power supply terminal 62H (see Figure 3) of the second gate driver 62. The low-potential terminal (second terminal) of the second capacitor C2 is connected to the low-potential side power supply terminal 62L (see Figure 3) of the second gate driver 62. The second bootstrap circuit 72 supplies the second gate driver 62 with the voltage necessary to turn on the second switching element Q2 in the second gate driver 62 (a voltage greater than the threshold voltage of the second switching element Q2).

[0045] Each of the multiple third bootstrap circuits 73 supplies voltage to the corresponding third gate driver 63 among the multiple third gate drivers 63. In each third bootstrap circuit 73, the anode of the third diode D13 is connected to the positive terminal of the DC voltage source 6. In each third bootstrap circuit 73, the cathode of the third diode D13 is connected to the high-potential terminal (first terminal) of the third capacitor C3. The high-potential terminal of the third capacitor C3 is connected to the high-potential side power supply terminal 63H (see Figure 3) of the third gate driver 63. The low-potential terminal (second terminal) of the third capacitor C3 is connected to the low-potential side power supply terminal 63L (see Figure 3) of the third gate driver 63. The third bootstrap circuit 73 supplies the third gate driver 63 with the voltage necessary to turn on the third switching element Q3 (a voltage greater than the threshold voltage of the third switching element Q3).

[0046] The DC voltage source 6 is, for example, a DC power supply including an isolated DC-DC converter 60. In this embodiment, the positive terminal of the DC voltage source 6 is connected to the high-potential power supply terminal 64H (see Figure 3) of a plurality of fourth gate drivers 64. The positive terminal of the DC voltage source 6 is also connected to the high-potential terminal of the third capacitor C3 via the third diode D13 for each of the plurality of third bootstrap circuits 73. The positive terminal of the DC voltage source 6 is also connected to the high-potential terminal of the second capacitor C2 via the third diode D13 of the third bootstrap circuit 73 and the second diode D12 of the second bootstrap circuit 72 for each of the plurality of second bootstrap circuits 72. The positive terminal of the DC voltage source 6 is also connected to the high-potential terminal of the first capacitor C1 via the third diode D13 of the third bootstrap circuit 73, the second diode D12 of the second bootstrap circuit 72, and the first diode D11 of the first bootstrap circuit 71 for each of the plurality of first bootstrap circuits 71. The negative terminal of the DC voltage source 6 is connected to the low-potential power supply terminal 64L (see Figure 3) of the multiple fourth gate drivers 64. Furthermore, the negative terminal of the DC voltage source 6 is connected to the negative electrode N1 of the DC power supply unit 3.

[0047] The control device 4 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4 by controlling a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. The execution entity of the control device 4 includes a computer system. The computer system has one or more computers. The computer system mainly consists of a processor and memory as hardware. The function of the control device 4 as the execution entity in this disclosure is realized by the processor executing a program recorded in the memory of the computer system. The program may be pre-recorded in the memory of the computer system, may be provided via a telecommunications line, or may be recorded and provided on a non-temporary recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) that can be read by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The plurality of electronic circuits may be aggregated on a single chip or distributed across multiple chips. Multiple chips may be integrated into a single device, or they may be distributed across multiple devices.

[0048] The control device 4 outputs multiple (three) first control signals S1 to control multiple (three) first switching elements Q1. The control device 4 also outputs multiple (three) second control signals S2 to control multiple (three) second switching elements Q2. The control device 4 also outputs multiple (three) third control signals S3 to control multiple third switching elements Q3. The control device 4 also outputs multiple (three) fourth control signals S4 to control multiple (three) fourth switching elements Q4. Note that in Figure 2, only one of the three inverter circuits 1 (see Figure 1) is shown, and the remaining two inverter circuits 1 are not shown. Furthermore, in Figure 2, the three first gate drivers 61, three second gate drivers 62, three third gate drivers 63, three fourth gate drivers 64, three first bootstrap circuits 71, three second bootstrap circuits 72, three third bootstrap circuits 73, DC voltage source 6, and six auxiliary diodes D8 shown in Figure 1 are omitted. Also, in Figure 3, only one of the three inverter circuits 1 (see Figure 1) is shown, and the remaining two inverter circuits 1 are omitted. Furthermore, in Figure 3, the two first gate drivers 61, two second gate drivers 62, two third gate drivers 63, two fourth gate drivers 64, two first bootstrap circuits 71, two second bootstrap circuits 72, two third bootstrap circuits 73, and six auxiliary diodes D8 shown in Figure 1 are omitted.

[0049] As shown in Figure 1, the three first control signals S1 include a first control signal US1 that controls the first switching element Q1 of the inverter circuit 1U, a first control signal VS1 that controls the first switching element Q1 of the inverter circuit 1V, and a first control signal WS1 that controls the first switching element Q1 of the inverter circuit 1W.

[0050] The three second control signals S2 include a second control signal US2 for controlling the second switching element Q2 of the inverter circuit 1U, a second control signal VS2 for controlling the second switching element Q2 of the inverter circuit 1V, and a second control signal WS2 for controlling the second switching element Q2 of the inverter circuit 1W.

[0051] The three third control signals S3 include a third control signal US3 for controlling the third switching element Q3 of the inverter circuit 1U, a third control signal VS3 for controlling the third switching element Q3 of the inverter circuit 1V, and a third control signal WS3 for controlling the third switching element Q3 of the inverter circuit 1W.

[0052] The three fourth control signals S4 include a fourth control signal US4 for controlling the fourth switching element Q4 of the inverter circuit 1U, a fourth control signal VS4 for controlling the fourth switching element Q4 of the inverter circuit 1V, and a fourth control signal WS4 for controlling the fourth switching element Q4 of the inverter circuit 1W.

[0053] Each of the multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) which is at a higher potential than the first potential level.

[0054] The first potential level is, for example, 0V, and the second potential level is a potential level greater than the gate threshold voltage of the IGBT. In other words, for each of the multiple control signals (multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4), the first potential level is the potential level required to turn off the switching element corresponding to that control signal, and the second potential level is the potential level required to turn on the switching element corresponding to that control signal.

[0055] Each of the multiple first switching elements Q1 is turned on when the corresponding first control signal S1 is high level and turned off when it is low level. Each of the multiple second switching elements Q2 is turned on when the corresponding second control signal S2 is high level and turned off when it is low level. Each of the multiple third switching elements Q3 is turned on when the corresponding third control signal S3 is high level and turned off when it is low level. Each of the multiple fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is high level and turned off when it is low level.

[0056] Each of the six auxiliary diodes D8 is, for example, a rectifier diode or a Schottky barrier diode. The six auxiliary diodes D8 include auxiliary diodes D8vu, D8wu, D8uv, D8wv, D8uw, and D8vw, as shown in Figure 1.

[0057] The auxiliary diode D8vu has its cathode connected to the high-potential terminal of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the inverter circuit 1U, and its anode connected to the high-potential terminal of the third capacitor C3 of the third bootstrap circuit 73 corresponding to the inverter circuit 1V.

[0058] The auxiliary diode D8wu has its cathode connected to the high-potential terminal of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the inverter circuit 1U, and its anode connected to the high-potential terminal of the third capacitor C3 of the third bootstrap circuit 73 corresponding to the inverter circuit 1W.

[0059] The auxiliary diode D8uv has its cathode connected to the high-potential terminal of the first capacitor C1 of the first bootstrap circuit 71 corresponding to inverter circuit 1V, and its anode connected to the high-potential terminal of the third capacitor C3 of the third bootstrap circuit 73 corresponding to inverter circuit 1U.

[0060] The auxiliary diode D8wv has its cathode connected to the high-potential terminal of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the inverter circuit 1V, and its anode connected to the high-potential terminal of the third capacitor C3 of the third bootstrap circuit 73 corresponding to the inverter circuit 1W.

[0061] The auxiliary diode D8uw has its cathode connected to the high-potential terminal of the first capacitor C1 of the first bootstrap circuit 71 corresponding to inverter circuit 1W, and its anode connected to the high-potential terminal of the third capacitor C3 of the third bootstrap circuit 73 corresponding to inverter circuit 1U.

[0062] The auxiliary diode D8vw has its cathode connected to the high-potential terminal of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the inverter circuit 1W, and its anode connected to the high-potential terminal of the third capacitor C3 of the third bootstrap circuit 73 corresponding to the inverter circuit 1V.

[0063] (3) Operation of the power converter In the power converter 100, each of the multiple inverter circuits 1 is controlled to be in a first switching state, a second switching state, or a third switching state. In other words, in each of the three inverter circuits 1U, 1V, and 1W of the power converter 100, the switching state of the switching circuit 10 is controlled to be in one of three states: a first switching state, a second switching state, or a third switching state. The first switching state, the second switching state, and the third switching state differ in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state are different from each other. In other words, in each of the multiple inverter circuits 1, the potential level of the output voltage changes in three levels depending on the state of the first to fourth switching elements Q1 to Q4. Furthermore, regarding the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with respect to each other.

[0064] The first switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are ON, and both the third switching element Q3 and the fourth switching element Q4 are OFF. Each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3 when controlled to the first switching state. In the first switching state, the potential of the third connection point 13 of each of the multiple inverter circuits 1 is at the potential level of the positive electrode P1 of the DC power supply unit 3 (for example, Vdc / 2).

[0065] The second switching state is a combination in which both the first switching element Q1 and the fourth switching element Q4 are in the off state, and both the second switching element Q2 and the third switching element Q3 are in the on state. Each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3 when controlled to the second switching state. In the second switching state, the potential of the third connection point 13 of each of the multiple inverter circuits 1 is at the potential level of the intermediate potential point M1 (for example, 0V).

[0066] The third switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the off state, and both the third switching element Q3 and the fourth switching element Q4 are in the on state. Each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3 when controlled to the third switching state. In the third switching state, the potential of the third connection point 13 of each of the multiple inverter circuits 1 is at the potential level of the negative electrode N1 of the DC power supply unit 3 (for example, -Vdc / 2).

[0067] When the switching circuit 10 of the inverter circuit 1 is in the first switching state, as shown in Figure 2, a current I1 flows through the path from the positive electrode P1 of the DC power supply unit 3 - the first switching element Q1 - the second switching element Q2 - the third connection point 13 - the output terminal 8, and the voltage value of the output voltage to the AC load becomes approximately Vdc / 2.

[0068] Furthermore, when the inverter circuit 1 is in the first switching state, the voltage necessary for the first gate driver 61 to turn on the first switching element Q1 is supplied from the first capacitor C1 of the first bootstrap circuit 71 (see Figures 1 and 3) to the first gate driver 61. Therefore, the charge of the first capacitor C1 of the first bootstrap circuit 71 is discharged through the discharge path Ru1 of the first capacitor C1 - the high-potential side power supply terminal 61H of the first gate driver 61 - the low-potential side power supply terminal 61L of the first gate driver 61 - the first capacitor C1, as shown in Figure 3. Consequently, in the first bootstrap circuit 71, the voltage VC1 between the high-potential end and the low-potential end of the first capacitor C1 decreases over time.

[0069] Furthermore, when the inverter circuit 1 is in the first switching state, the voltage necessary for the second gate driver 62 to turn on the second switching element Q2 is supplied from the second capacitor C2 of the second bootstrap circuit 72 to the second gate driver 62. Therefore, the charge of the second capacitor C2 of the second bootstrap circuit 72 is discharged through the discharge path Ru2 of the second capacitor C2 - the high-potential side power supply terminal 62H of the second gate driver 62 - the low-potential side power supply terminal 62L of the second gate driver 62 - the second capacitor C2. Consequently, in the second bootstrap circuit 72, the voltage VC2 between the high-potential end and the low-potential end of the second capacitor C2 decreases over time.

[0070] Furthermore, as shown in Figure 3, if the voltage between the anode and cathode of the first diode D11 is Vd1, and the voltage between the first main terminal and the second main terminal of the second switching element Q2 is Vf2, then when the switching circuit 10 of the inverter circuit 1 is in the first switching state, the first capacitor C1 is charged by the second capacitor C2 if the first condition is met. The first condition is VC2 > (VC1 + Vd1 + Vf2). The charging path Ru21 for charging the first capacitor C1 by the second capacitor C2 is the path of second capacitor C2 - first diode D11 - first capacitor C1 - first connection point 11 - second switching element Q2 - second capacitor C2.

[0071] Furthermore, when inverter circuit 1 is in the second switching state, for example, as shown in Figure 4, current I1 flows through the path from the intermediate potential point M1 of the DC power supply unit 3 - the first clamp diode D5 - the second switching element Q2 - the third connection point 13 - the output terminal 8 (the path shown by the thick solid arrow), and the voltage value of the output voltage to the AC load becomes approximately 0V. More specifically, when inverter circuit 1U (see Figure 1), inverter circuit 1V (see Figure 1), and inverter circuit 1W (see Figure 1) are in the second switching state, the third switching state, and the third switching state, respectively, current I1 flows through the path from the intermediate potential point M1 of the DC power supply unit 3 - the first clamp diode D5 - the second switching element Q2 of inverter circuit 1U - the third connection point 13 - the output terminal 8.

[0072] Furthermore, when inverter circuit 1 is in the second switching state, for example, as shown in Figure 4, current I1 flows through the path from output terminal 8 - third connection point 13 - third switching element Q3 - second connection point 12 - second clamp diode D6 (the path indicated by the thick dashed arrow), and the output voltage value to the AC load may be approximately 0V. More specifically, when inverter circuits 1U, 1V, and 1W are in the second switching state, second switching state, and first switching state, respectively, current flows through the path from output terminal 8 of inverter circuit 1U - third connection point 13 - third switching element Q3 - second connection point 12 - second clamp diode D6 (the path indicated by the thick dashed arrow), and the output voltage value to the AC load is approximately 0V.

[0073] Furthermore, when the inverter circuit 1 is in the second switching state, the voltage necessary for the second gate driver 62 to turn on the second switching element Q2 is supplied from the second capacitor C2 of the second bootstrap circuit 72 (see Figures 1 and 5) to the second gate driver 62. Therefore, the charge of the second capacitor C2 of the second bootstrap circuit 72 is discharged through the discharge path Ru2 of the second capacitor C2 - high-potential side power supply terminal 62H of the second gate driver 62 - low-potential side power supply terminal 62L of the second gate driver 62 - second capacitor C2, as shown in Figure 5. Also, when the inverter circuit 1 is in the second switching state, the voltage necessary for the third gate driver 63 to turn on the third switching element Q3 is supplied from the third capacitor C3 of the third bootstrap circuit 73 to the third gate driver 63. Therefore, the charge in the third capacitor C3 of the third bootstrap circuit 73 is discharged through the discharge path Ru3 from the third capacitor C3 to the high-potential side power supply terminal 63H of the third gate driver 63 to the low-potential side power supply terminal 63L of the third gate driver 63 and then to the third capacitor C3.

[0074] Furthermore, as shown in Figure 5, if the voltage between the first and second main terminals of the second switching element Q2 is Vf2, the voltage between the first and second main terminals of the third switching element Q3 is Vf3, the voltage between the anode and cathode of the first diode D11 is Vd1, the voltage between the anode and cathode of the second diode D12 is Vd2, the voltage across the third capacitor C3 is VC3, the voltage across the second capacitor C2 is VC2, and the voltage across the first capacitor C1 is VC1, then when the inverter circuit 1 is in the second switching state, the second capacitor C2 is charged by the third capacitor C3 if the second condition is met, and the first capacitor C1 is charged by the second capacitor C2 if the third condition is met. The second condition is VC3 > (VC2 + Vd2 + Vf3). The third condition is VC2 > (VC1 + Vd1 + Vf2). The charging path Ru32 for charging the second capacitor C2 with the third capacitor C3 is the path from the third capacitor C3 - second diode D12 - second capacitor C2 - third connection point 13 - third switching element Q3 - third capacitor C3. The charging path Ru21 for charging the first capacitor C1 with the second capacitor C2 is the path from the second capacitor C2 - first diode D11 - first capacitor C1 - first connection point 11 - second switching element Q2 - second capacitor C2. The charging path Ru32 for charging the second capacitor C2 with the third capacitor C3 is the path from the third capacitor C3 - second diode D12 - second capacitor C2 - third connection point 13 - third switching element Q3 - third capacitor C3.

[0075] Furthermore, when the inverter circuit 1 is in the third switching state, as shown in Figure 6, current I1 flows through the path from output terminal 8 - third connection point 13 - third switching element Q3 - fourth switching element Q4 - negative terminal N1 of the DC power supply unit 3, and the voltage value of the output voltage to the AC load becomes -Vdc / 2. Also, when the inverter circuit 1 is in the third switching state, the first capacitor C1 of the first bootstrap circuit 71 (see Figures 1 and 7) is charged, so the voltage VC1 of the first capacitor C1 rises over time and the first capacitor C1 becomes fully charged. Also, when the inverter circuit 1 is in the third switching state, the second capacitor C2 of the second bootstrap circuit 72 is charged, so the voltage VC2 of the second capacitor C2 rises over time and the second capacitor C2 becomes fully charged. Furthermore, when the inverter circuit 1 is in the third switching state, the voltage necessary for the third gate driver 63 to turn on the third switching element Q3 is supplied from the third capacitor C3 of the third bootstrap circuit 73 to the third gate driver 63. Therefore, as shown in Figure 7, the charge of the third capacitor C3 of the third bootstrap circuit 73 is discharged through the discharge path Ru3 of the third capacitor C3 - the high-potential side power supply terminal 63H of the third gate driver 63 - the low-potential side power supply terminal 63L of the third gate driver 63 - the third capacitor C3. Furthermore, as shown in Figure 7, if the voltage between the positive and negative terminals of the DC voltage source 6 is V60, the voltage between the anode and cathode of the third diode D13 is Vd3, the voltage between the first and second main terminals of the third switching element Q3 is Vf3, and the voltage between the first and second main terminals of the fourth switching element Q4 is Vf4, then when the inverter circuit 1 is in the third switching state, the third capacitor C3 is charged by the DC voltage source 6 if the fourth condition is met, and the second capacitor C2 is charged by the third capacitor C3 if the fifth condition is met. The fourth condition is V60 > (VC3 + Vd3 + Vf4). The fifth condition is VC3 > (VC2 + Vd2 + Vf3).The charging path Ru63 for charging the third capacitor C3 with the DC voltage source 6 is the path from the positive terminal of the DC voltage source 6 - the third diode D13 - the third capacitor C3 - the second connection point 12 - the fourth switching element Q4 - the negative terminal of the DC voltage source 6. The charging path Ru32 for charging the second capacitor C2 with the third capacitor C3 is the path from the third capacitor C3 - the second diode D12 - the second capacitor C2 - the third connection point 13 - the third switching element Q3 - the third capacitor C3.

[0076] The control device 4 (see Figure 1) generates first to fourth control signals S1 to S4 (US1 to US4) for the first to fourth switching elements Q1 to Q4 of inverter circuit 1U, first to fourth control signals S1 to S4 (VS1 to VS4) for the first to fourth switching elements Q1 to Q4 of inverter circuit 1V, and first to fourth control signals S1 to S4 (WS1 to WS4) for the first to fourth switching elements Q1 to Q4 of inverter circuit 1W, based on voltage commands Vu, Vv, and Vw (see Figure 8) for the output voltages of inverter circuits 1U, 1V, and 1W, respectively.

[0077] As shown in Figure 8, the voltage commands Vu, Vv, and Vw are, for example, sinusoidal signals with a phase difference of 120° from each other, and their values ​​(voltage command values) change over time. The length of one period for voltage commands Vu, Vv, and Vw is the same. The control device 4 may perform PI (Proportional Integral) control of the voltage commands Vu, Vv, and Vw based on information output from the detection unit that detects the state of the AC load. When the AC load is a three-phase servo motor, the information output from the detection unit includes, for example, at least one of the following: information from the detection results of multiple current sensors that detect the output current flowing through the U-phase, V-phase, and W-phase of the AC load, and information from the detection results of an encoder that detects the rotation speed, rotation angle, etc., of the three-phase servo motor.

[0078] The output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W are out of phase with respect to each other.

[0079] In this embodiment, the control device 4 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing spatial vector modulation (hereinafter also referred to as voltage vector control).

[0080] The following provides a more detailed explanation of voltage vector control in the control device 4.

[0081] The control device 4 stores a group of voltage vectors in advance. Each of the voltage vectors in the group is determined by a combination of potential levels at the third connection point 13 (hereinafter also referred to as the output point 13) between the second switching element Q2 and the third switching element Q3 of the plurality of inverter circuits 1. In other words, the group of voltage vectors is determined by the switching state of the inverter circuit 1U corresponding to the U phase, the switching state of the inverter circuit 1V corresponding to the V phase, and the switching state of the inverter circuit 1W corresponding to the W phase. The number of voltage vectors included in the group of voltage vectors is 3 ３ = 27 items.

[0082] A group of voltage vectors includes three zero vectors V0p, V0z, and V0n, each with a magnitude of zero, as shown in the three-level spatial vector diagram (spatial vector modulation diagram) in Figure 9. Furthermore, a group of voltage vectors also includes three zero vectors, each with a magnitude of (2 / 3). １／２ It contains six voltage vectors V1, V2, V3, V4, V5, and V6, each with a voltage of 2Vdc and different directions. Furthermore, each group of voltage vectors has a magnitude of (2 / 3). １／２ It includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, where Vdc is. Also, each group of voltage vectors has a magnitude of (2 / 3). １／２ 3 １／２ - Includes six voltage vectors V13, V14, V15, V16, V17, and V18, which are Vdc and have different directions. In this embodiment, (2 / 3) １／２Vdc is used as the reference magnitude. In Figure 9, the angle between any two adjacent voltage vectors among the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Also, the angle between any two adjacent voltage vectors among the six voltage vectors V13, V14, V15, V16, V17, and V18 is 60 degrees. Note that Figure 9 is a three-level spatial vector diagram illustrating a group of voltage vectors on an orthogonal α-β coordinate system.

[0083] A group of voltage vectors can be represented as shown in Figure 10, a three-level spatial vector diagram (spatial vector modulation diagram), by expressing the first switching state, second switching state, and third switching state with the symbols "P", "0", and "N", respectively, and listing them in the order of U-phase, V-phase, and W-phase.

[0084] As shown in Figure 10, the three zero vectors V0p, V0z, and V0n can be expressed as V0p[PPP], V0z

[000] , and V0n[NNN], respectively. For example, V0p[PPP] represents that with respect to the zero vector V0p, the switching state of the U-phase inverter circuit 1U is "P", the switching state of the V-phase inverter circuit 1V is "P", and the switching state of the W-phase inverter circuit 1W is "P". Similarly, V0z

[000] represents that with respect to the zero vector V0z, the switching state of the U-phase inverter circuit 1U is "0", the switching state of the V-phase inverter circuit 1V is "0", and the switching state of the W-phase inverter circuit 1W is "0". Furthermore, V0n[NNN] represents that, with respect to the zero vector V0n, the switching state of the U-phase inverter circuit 1U is "N", the switching state of the V-phase inverter circuit 1V is "N", and the switching state of the W-phase inverter circuit 1W is "N". When the switching state of inverter circuit 1 is "P", the potential of the output point 13 in that inverter circuit 1 is the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of inverter circuit 1 is "N", the potential of the output point 13 in that inverter circuit 1 is the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of inverter circuit 1 is "0", the potential of the output point 13 in that inverter circuit 1 is the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0085] Furthermore, voltage vectors denoted with "p," such as V10p, include "P" but do not include "N." This applies to the following as well. Similarly, voltage vectors denoted with "n," such as V10n, include "N" but do not include "P." This also applies to the following as well.

[0086] The six voltage vectors V1, V2, V3, V4, V5, and V6 can be expressed as voltage vectors V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors like V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], which do not have "p", "n", or "o" after the number "V", include "P" and "N" as three-phase switching states. A group of voltage vectors includes the six voltage vectors V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], each with a magnitude twice that of the reference magnitude.

[0087] Furthermore, the twelve voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n can be expressed as the voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively. Therefore, a group of voltage vectors includes 12 voltage vectors, V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], each of which has a reference magnitude (reference vector).

[0088] Furthermore, the six voltage vectors V13, V14, V15, V16, V17, and V18 can be expressed as voltage vectors V13[P0N], V14[0PN], V15[NP0], V16[N0P], V17[0NP], and V18[PN0], respectively. A group of voltage vectors has a magnitude of 3 times the reference magnitude. １／２ As voltage vectors with double the magnitude, it includes six voltage vectors V13[P0N], V14[0PN], V15[NP0], V16[N0P], V17[0NP], and V18[PN0].

[0089] The control device 4 converts the instantaneous value of the command voltage for each output voltage of the multiple inverter circuits 1 into a command voltage vector Vref (see Figure 11). If Vα is the α-axis component of the command voltage vector Vref in the orthogonal α-β coordinate system, and Vβ is the β-axis component of the command voltage vector Vref in the orthogonal α-β coordinate system, then the command voltage vector Vref can be obtained using equation (1).

[0090]

[0091] The control device 4 selects voltage vectors Va, Vb, and Vc from a group of voltage vectors to be used within the control period Ts (see Figures 12 and 13) as voltage vectors corresponding to each vertex of the equilateral triangle surrounding the command voltage vector Vref, and determines the first allocation time T0 for voltage vector Va, the second allocation time T1 for voltage vector Vb, and the third allocation time T2 for voltage vector Vc so that the combined vector of voltage vectors Va, Vb, and Vc matches the command voltage vector Vref.

[0092] The control device 4 determines the first distribution time T0, second distribution time T1, and third distribution time T2 such that equations (2) and (3) are satisfied, where V is the magnitude of the command voltage vector Vref and θ is the angle between the command voltage vector Vref and the α-axis. In equation (2), "j" is the imaginary unit. The angle between the voltage vector Va closest to the command voltage vector Vref and the command voltage vector Vref is less than 30 degrees.

[0093]

[0094]

[0095] Furthermore, the control device 4 distributes a first distribution time T0 to each voltage vector Va based on the number of times the voltage vector Va is used within the control period Ts, a second distribution time T1 to each voltage vector Vb based on the number of times the voltage vector Vb is used within the control period Ts, and a third distribution time T2 based on the number of times the voltage vector Vc is used within the control period Ts.

[0096] In the example shown in Figure 11, the voltage vectors Va are voltage vector V8p [PP0] and voltage vector V8n [00N], voltage vector Vb is voltage vector V13 [P0N], and voltage vector Vc is voltage vector V7p [P00]. Figure 12 shows the switching states of the U-phase, V-phase, and W-phase when the control device 4 sequentially uses the eight voltage vectors within the control period Ts. Figure 13 shows the states of the first switching element Q1, second switching element Q2, third switching element Q3, and fourth switching element Q4 of the U-phase when the control device 4 sequentially uses the eight voltage vectors within the control period Ts. Figure 12 illustrates the case where, in the control period Ts, the allocation time for voltage vectors Va (voltage vectors V8p [PP0] and V8n [00N]) is T0, the allocation time for voltage vector Vb (voltage vector V13 [P0N]) is T1, and the allocation time for voltage vector Vc (voltage vector V7p [P00]) is T2. The control period Ts is one period of the carrier signal.

[0097] When the control device 4 changes the switching state of two adjacent voltage vectors among the eight voltage vectors arranged in time series within the control period Ts, it changes the switching state of only one of the U-phase, V-phase, and W-phase between "P" and "0" or between "0" and "N", and uses the same voltage vector twice. In Figure 12, the control device 4 uses the voltage vectors in the following order: voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N]. In the example shown in Figure 12, the control device 4 uses the voltage vector Va four times, so the allocation time for each of the voltage vectors Va used first (voltage vector V8n[00N]), fourth (voltage vector V8p[PP0]), fifth (voltage vector V8p[PP0]), and eighth (voltage vector V8n[00N]) within the control period Ts is set to T0 / 4. Also in the example shown in Figure 12, the control device 4 uses the voltage vector Vb twice, so the allocation time for each of the voltage vectors Vb used second (voltage vector V13[P0N]) and seventh (voltage vector V13[P0N]) within the control period Ts is set to T1 / 2. Furthermore, in the example shown in Figure 12, the control device 4 uses the voltage vector Vc twice, so the allocation time for the third voltage vector Vc (voltage vector V7p [P00]) and the sixth voltage vector Vc (voltage vector V7p [P00]) used within the control period Ts is set to T2 / 2. Note that even if the command voltage vector Vref is the same as in Figure 11, the order of the voltage vectors within the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts.

[0098] The control device 4 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 within a predetermined control period Ts (see Figure 12) so that the combined vector of the voltage vector Va (in the example shown in Figure 11, voltage vector V8p [PP0] and voltage vector V8n [00N]), voltage vector Vb (in the example shown in Figure 11, voltage vector V13 [P0N]), and voltage vector Vc (in the example shown in Figure 11, voltage vector V7p [P00]) matches the command voltage vector Vref.

[0099] In the power converter 100, for example, when the switching state of inverter circuit 1U and inverter circuit 1V is in the second switching state, the output voltages of inverter circuit 1U and inverter circuit 1V are 0V. In this embodiment, as shown in Figure 14, the first capacitor C1 (hereinafter also referred to as the first capacitor C1u) of the first bootstrap circuit 71 corresponding to inverter circuit 1U can be charged from the third capacitor C3 (hereinafter also referred to as the third capacitor C3v) of the third bootstrap circuit 73 corresponding to inverter circuit 1V via the charging path Ru31. The charging path Ru31 is the path from the high potential end of the third capacitor C3v - auxiliary diode D8vu - first capacitor C1u - second switching element Q2 of inverter circuit 1U - output terminal 8U - U-phase load 9U of AC load 9 - V-phase load 9V of AC load 9 - output terminal 8V - third switching element Q3 of inverter circuit 1V - low potential end of the third capacitor C3v. In Figure 14, the AC load 9 is shown as a U-phase load 9U, a V-phase load 9V, and a W-phase load 9W.

[0100] Figure 15 shows the waveforms of the output current iU of inverter circuit 1U, iV of inverter circuit 1V, the output current iW of inverter circuit 1W, the voltage VC1 of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the first switching element Q1 of inverter circuit 1U, the voltage VC2 of the second capacitor C2 of the second bootstrap circuit 72 corresponding to the second switching element Q2 of inverter circuit 1U, and the voltage VC3 of the third capacitor C3 of the third bootstrap circuit 73 corresponding to the third switching element Q3 of inverter circuit 1U.

[0101] The polarity of the output current iU of inverter circuit 1U is defined as positive when the output current iU flows from the third connection point 13 to the output terminal 8U (direction of the arrow in Figure 1), and negative when it flows from the output terminal 8U to the third connection point 13. Similarly, the polarity of the output current iV of inverter circuit 1V is defined as positive when the output current iV flows from the third connection point 13 to the output terminal 8V (direction of the arrow in Figure 1), and negative when it flows from the output terminal 8V to the third connection point 13. Similarly, the polarity of the output current iW of inverter circuit 1W is defined as positive when the output current iW flows from the third connection point 13 to the output terminal 8W (direction of the arrow in Figure 1), and negative when it flows from the output terminal 8W to the third connection point 13. The output currents iU of inverter circuit 1U, iV of inverter circuit 1V, and iW of inverter circuit 1W are each sinusoidal, as shown in Figure 15. Furthermore, the waveforms of the voltage VC1 of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the first switching element Q1 of the inverter circuit 1V, the voltage VC2 of the second capacitor C2 of the second bootstrap circuit 72 corresponding to the second switching element Q2 of the inverter circuit 1V, and the voltage VC3 of the third capacitor C3 of the third bootstrap circuit 73 corresponding to the third switching element Q3 of the inverter circuit 1V are the same as the waveforms of voltage VC1, voltage VC2, and voltage VC3 in Figure 15. Also, the waveforms of the voltage VC1 of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the first switching element Q1 of the inverter circuit 1W, the voltage VC2 of the second capacitor C2 of the second bootstrap circuit 72 corresponding to the second switching element Q2 of the inverter circuit 1W, and the voltage VC3 of the third capacitor C3 of the third bootstrap circuit 73 corresponding to the third switching element Q3 of the inverter circuit 1W are the same as the waveforms of voltage VC1, voltage VC2, and voltage VC3 in Figure 15.

[0102] In the switching element drive circuit 2 according to Embodiment 1, compared to the case where auxiliary diodes D8vu and D8wu are not provided, the decrease in the voltage VC1 of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the inverter circuit 1U is suppressed, and the voltage VC1 of the first capacitor C1 becomes higher than the voltage VC2 of the second capacitor C2 and the voltage VC3 of the third capacitor C3. Similarly, in the switching element drive circuit 2 according to Embodiment 1, compared to the case where auxiliary diodes D8uv and D8wv are not provided, the decrease in the voltage VC1 of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the inverter circuit 1V is suppressed. Similarly, in the switching element drive circuit 2 according to Embodiment 1, compared to the case where auxiliary diodes D8uw and D8vw are not provided, the decrease in the voltage VC1 of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the inverter circuit 1W is suppressed.

[0103] (4) Advantages The switching element driving circuit 2 according to Embodiment 1 comprises a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, a plurality of fourth gate drivers 64, a plurality of first bootstrap circuits 71, a plurality of second bootstrap circuits 72, a plurality of third bootstrap circuits 73, a DC voltage source 6, a control device 4, and a plurality of auxiliary diodes D8. Each of the plurality of auxiliary diodes D8 has its cathode connected to the high potential terminal of the first capacitor C1 of the first bootstrap circuit 71 that corresponds to any one inverter circuit 1 among the plurality of first bootstrap circuits 71. Each of the plurality of auxiliary diodes D8 has its anode connected to the high potential terminal of the third capacitor C3 of the third bootstrap circuit 73 that corresponds to an inverter circuit 1 different from the above-mentioned arbitrary one inverter circuit 1 among the plurality of third bootstrap circuits 73.

[0104] According to the above configuration, it is possible to suppress the decrease in the voltage VC1 of each of the first capacitors C1 of the multiple first bootstrap circuits 71.

[0105] Furthermore, in the switching element drive circuit 2 according to Embodiment 1, the control device 4 generates a plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3, and a plurality of fourth control signals S4 by spatial vector modulation.

[0106] With the above configuration, when performing spatial vector modulation in the control device 4, it becomes possible to suppress the decrease in the voltage VC1 of each of the first capacitors C1 of the multiple first bootstrap circuits 71 without performing any special control.

[0107] Furthermore, the power conversion device 100 according to Embodiment 1 includes a switching element drive circuit 2 and a plurality of inverter circuits 1.

[0108] According to the above configuration, it is possible to suppress the decrease in the voltage VC1 of each of the first capacitors C1 of the multiple first bootstrap circuits 71.

[0109] (Embodiment 2) The power converter 100A according to Embodiment 2 will be described with reference to Figure 16.

[0110] (1) The power converter 100A according to Embodiment 2 is substantially the same as the power converter 100 according to Embodiment 1 (see Figure 1), and differs from the power converter 100 according to Embodiment 1 in that it is equipped with a switching element drive circuit 2A instead of the switching element drive circuit 2 according to Embodiment 1 (see Figure 1). With respect to the power converter 100A according to Embodiment 2, the same reference numerals are used for components that are the same as those in the power converter 100 according to Embodiment 1, and their descriptions are omitted. Similarly, with respect to the switching element drive circuit 2A according to Embodiment 2, the same reference numerals are used for components that are the same as those in the switching element drive circuit 2 according to Embodiment 1, and their descriptions are omitted.

[0111] The switching element drive circuit 2A according to Embodiment 2 differs from the switching element drive circuit 2 according to Embodiment 1 in that it does not include the diode D11 (see Figure 1) in each of the plurality of first bootstrap circuits 71 of the switching element drive circuit 2 according to Embodiment 1. In this embodiment, the diode D12 in each of the plurality of second bootstrap circuits 72 is referred to as the first diode D12, and the diode D13 in each of the plurality of third bootstrap circuits 73 is referred to as the second diode D13.

[0112] In the switching element driving circuit 2A according to Embodiment 2, each of the multiple first bootstrap circuits 71 includes only a first capacitor C1 as a circuit element. Furthermore, in the switching element driving circuit 2A, each of the multiple first bootstrap circuits 71 is not connected to a second bootstrap circuit 72.

[0113] (2) Advantages The switching element driving circuit 2A according to Embodiment 2 drives a plurality of inverter circuits 1. The plurality of inverter circuits 1 include a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, a plurality of fourth switching elements Q4, a plurality of first clamp diodes D5, and a plurality of second clamp diodes D6. The plurality of first switching elements Q1 are connected to the positive electrode P1 of a DC power supply unit 3 having a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The plurality of second switching elements Q2 are each connected in series to the plurality of first switching elements Q1. The plurality of third switching elements Q3 are each connected in series to the plurality of second switching elements Q2. The plurality of fourth switching elements Q4 are each connected in series to the plurality of third switching elements Q3. The plurality of fourth switching elements Q4 are connected to the negative electrode N1 of the DC power supply unit 3. Multiple first clamp diodes D5 have their cathodes connected to multiple first connection points 11 between multiple first switching elements Q1 and multiple second switching elements Q2, and their anodes connected to an intermediate potential point M1. Multiple second clamp diodes D6 have their anodes connected to multiple second connection points 12 between multiple third switching elements Q3 and multiple fourth switching elements Q4, and their cathodes connected to an intermediate potential point M1. The switching element driving circuit 2A includes multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63, multiple fourth gate drivers 64, multiple first bootstrap circuits 71, multiple second bootstrap circuits 72, multiple third bootstrap circuits 73, a DC voltage source 6, a control device 4, and multiple auxiliary diodes D8. Multiple first gate drivers 61 each drive multiple first switching elements Q1. Multiple second gate drivers 62 each drive multiple second switching elements Q2. Multiple third gate drivers 63 each drive multiple third switching elements Q3. Multiple fourth gate drivers 64 each drive multiple fourth switching elements Q4. Multiple first bootstrap circuits 71 correspond one-to-one with multiple first gate drivers 61.Each of the multiple first bootstrap circuits 71 includes a first capacitor C1 connected in parallel to the corresponding first gate driver 61. The multiple second bootstrap circuits 72 correspond one-to-one to the multiple second gate drivers 62. Each of the multiple second bootstrap circuits 72 includes a second capacitor C2 connected in parallel to the corresponding second gate driver 62 and a first diode D12 connected to the high-potential terminal of the second capacitor C2. The multiple third bootstrap circuits 73 correspond one-to-one to the multiple third gate drivers 63. Each of the multiple third bootstrap circuits 73 includes a third capacitor C3 connected in parallel to the corresponding third gate driver 63 and a second diode D13 connected to the high-potential terminal of the third capacitor C3. The DC voltage source 6 is connected to the multiple fourth gate drivers 64. The control device 4 outputs multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4 to be given to each of the multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63, and multiple fourth gate drivers 64, respectively. Each of the multiple auxiliary diodes D8 has its cathode connected to the high-potential terminal of the first capacitor C1 of the first bootstrap circuit 71 that corresponds to any one inverter circuit 1 among the multiple first bootstrap circuits 71. Each of the multiple auxiliary diodes D8 has its anode connected to the high-potential terminal of the third capacitor C3 of the third bootstrap circuit 73 that corresponds to an inverter circuit 1 different from the one inverter circuit 1 among the multiple third bootstrap circuits 73.

[0114] According to the above configuration, it is possible to suppress the decrease in the voltage VC1 of each of the first capacitors C1 of the multiple first bootstrap circuits 71.

[0115] Furthermore, in the switching element drive circuit 2A according to Embodiment 2, each of the multiple first bootstrap circuits 71 includes only the first capacitor C1 and does not include the diode D11 (see Figure 1) in the first bootstrap circuit 71 of the switching element drive circuit 2 according to Embodiment 1. Therefore, compared to the switching element drive circuit 2 according to Embodiment 1, the number of components can be reduced, and miniaturization can be achieved.

[0116] Furthermore, the power conversion device 100A according to Embodiment 2 includes a switching element drive circuit 2A and a plurality of inverter circuits 1.

[0117] According to the above configuration, it is possible to suppress the decrease in the voltage VC1 of each of the first capacitors C1 of the multiple first bootstrap circuits 71.

[0118] (Embodiment 3) The switching element drive circuit 2 and power conversion device 100 according to Embodiment 3 will be described with reference to Figures 1 and 17 to 19.

[0119] (1) The circuit configuration of the switching element drive circuit 2 according to Embodiment 3 is the same as the circuit configuration of the switching element drive circuit 2 according to Embodiment 1 (see Figure 1). The circuit configuration of the power converter 100 according to Embodiment 3 is the same as the circuit configuration of the power converter 100 according to Embodiment 1 (see Figure 1).

[0120] (2) The switching element drive circuit 2 according to the third embodiment of the switching element drive circuit and power converter differs from the switching element drive circuit 2 according to the first embodiment in that the control device 4 performs vector substitution control instead of spatial vector modulation (voltage vector control).

[0121] In this embodiment, the control device 4, in vector substitution control, selects a group of voltage vectors (see Figures 9 and 10) determined by combinations of potentials of multiple output points 13 of multiple switching circuits 10 (see Figures 2 to 7), from among a group of voltage vectors adjacent to the command voltage vector Vref (see Figure 17). In vector substitution control, one of the two first voltage vectors VV1, which have a reference magnitude and are closest to the command voltage vector Vref, is replaced with a zero vector, which is a combination of the potential levels of the multiple output points 13 being at the potential of the negative electrode N1, and a second voltage vector VV2 (see Figure 17) which has the same direction as the first first voltage vector and is twice the magnitude of the first first voltage vector VV1. In vector substitution control, multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63, and multiple fourth gate drivers 64 are controlled within a predetermined control period Ts (see Figures 18 and 19) so that the combined vector of one or more voltage vectors other than two first voltage vectors VV1 from among multiple voltage vectors, the remaining first voltage vector VV1 from the two first voltage vectors VV1, the zero vector, and the second voltage vector VV2 matches the command voltage vector Vref.

[0122] The following explanation of vector substitution control is based on Figures 17 to 19, but explanations of operations similar to those of voltage vector control will be omitted as appropriate.

[0123] In this embodiment as well, the control device 4 stores the same group of voltage vectors as in Embodiment 1.

[0124] In vector substitution control, the control device 4 substitutes one of the two first voltage vectors VV1 (V8p [PP0] and V8n [00N] in the example of Figure 17) whose magnitude is the reference magnitude and is closest to the command voltage vector Vref, with the zero vector V0n [NNN] and the second voltage vector VV2 (V2 [PPN] in the example of Figure 17) which is in the same direction as the first voltage vector VV1 and has twice the magnitude of the first voltage vector VV1. The control device 4 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 within a predetermined control period Ts so that the combined vector of one or more voltage vectors other than the two first voltage vectors VV1 (in the example of Figure 17, voltage vector V13 [P0N] and voltage vector V7p [P00]), the remaining first voltage vector VV1 (in the example of Figure 17, voltage vector V8p [PP0]), the zero vector V0n [NNN], and the second voltage vector VV2 (in the example of Figure 17, voltage vector V2 [PPN]) matches the command voltage vector Vref.

[0125] In vector substitution control, the fourth voltage vector V8p[PP0] and the fifth voltage vector V8p[PP0] used among the eight voltage vectors in the example of voltage vector control in Figure 12 described in Embodiment 1 are replaced with the zero vector V0n[NNN] and the second voltage vector VV2 (voltage vector V2[PPN]), respectively. As shown in Figure 18, this makes it possible to generate a period in which the switching state of the U phase is "N". In the example of Figure 18, as shown in Figure 19, a third switching state can be generated in which both the first switching element Q1 and the second switching element Q2 of the switching circuit 10 of the inverter circuit 1U are in the off state, and both the third switching element Q3 and the fourth switching element Q4 are in the on state. Therefore, the switching element drive circuit 2 according to Embodiment 3 can suppress the voltage drop of the second capacitor C2 of the second bootstrap circuit 72. In the example shown in Figure 18, there are periods when the switching state of the V phase and the switching state of the W phase are both "N," so the second capacitor C2 of the second bootstrap circuit 72 corresponding to the switching circuit 10 of inverter circuit 1V and the switching circuit 10 of inverter circuit 1W are charged and maintain their voltage.

[0126] (3) Advantages Since the switching element drive circuit 2 according to Embodiment 3 has the same circuit configuration as the switching element drive circuit 2 according to Embodiment 1, it is possible to suppress the decrease in the voltage VC1 of the first capacitor C1 of the multiple first bootstrap circuits 71, just like the switching element drive circuit 2 according to Embodiment 1.

[0127] Furthermore, in the switching element drive circuit 2 according to Embodiment 3, the control device 4 performs vector substitution control. In vector substitution control, the control device 4 selects a group of voltage vectors adjacent to the command voltage vector Vref from a group of voltage vectors determined by the combination of potentials of the multiple output points 13 of the multiple inverter circuits 1. In vector substitution control, one of the two first voltage vectors VV1 whose magnitude is the reference magnitude and is closest to the command voltage vector Vref is replaced with a zero vector V0z [NNN] which is a combination in which the potential levels of the multiple output points 13 are all at the potential of the negative electrode N1, and a second voltage vector VV2 which is in the same direction as the one first voltage vector VV1 and has twice the magnitude of the one first voltage vector VV1. In vector substitution control, multiple first gate drivers 61, multiple second gate drivers 62, multiple third gate drivers 63, and multiple fourth gate drivers 64 are controlled within a predetermined control period Ts so that the composite vector of one or more voltage vectors other than two first voltage vectors VV1 from among multiple voltage vectors, the remaining first voltage vector VV1 from the two first voltage vectors VV1, the zero vector V0z[NNN], and the second voltage vector VV2 matches the command voltage vector Vref.

[0128] According to the above configuration, it is possible to suppress the decrease in the voltage VC2 of the second capacitor C2 of the multiple second bootstrap circuits 72.

[0129] (Embodiment 4) The switching element drive circuit 2 and power conversion device 100 according to Embodiment 4 will be described with reference to Figures 1 and 20 to 22.

[0130] (1) The circuit configuration of the switching element drive circuit 2 according to Embodiment 4 is the same as the circuit configuration of the switching element drive circuit 2 according to Embodiment 1 (see Figure 1). Also, the circuit configuration of the power converter 100 according to Embodiment 4 is the same as the circuit configuration of the power converter 100 according to Embodiment 1 (see Figure 1).

[0131] (2) The switching element driving circuit 2 according to the operating embodiment 4 of the switching element driving circuit and power converter differs from the switching element driving circuit 2 according to embodiment 1 in that the control device 4 performs switching pattern control instead of spatial vector modulation (voltage vector control).

[0132] The control device 4 of this embodiment includes a first control, a second control, a third control, and a fourth control in the switching pattern control. The first control controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 to on, on, off, and off, respectively. The second control controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 to off, on, on, and off, respectively. The third control controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 to off, on, off, and on, respectively. The fourth control controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 to off, off, on, and on, respectively. In switching pattern control, if the polarity of the output current is positive for each of the inverter circuits 1, the process proceeds from the third control to the second control and then to the first control.

[0133] The following provides a more detailed explanation of switching pattern control.

[0134] In the first control, the control device 4 controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 so that the switching circuit 10 (see Figure 2) of the inverter circuit 1 enters a first switching state.

[0135] In the second control, the control device 4 controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 so that the switching circuit 10 (see Figure 4) of the inverter circuit 1 enters the second switching state.

[0136] In the third control, the control device 4 controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 so that the switching circuit 10 (see Figure 22) enters the fourth switching state.

[0137] In the fourth control, the control device 4 controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 to off, off, on, and on, respectively. More specifically, in the fourth control, the control device 4 controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 so that the switching circuit 10 (see Figure 6) of the inverter circuit 1 is in the third switching state.

[0138] When the control device 4 performs the third control and the switching circuit 10 of the inverter circuit 1 is in the fourth switching state, as shown in Figure 21, a current I1 flows through the path from the intermediate potential point M1 of the DC power supply unit 3 - the first clamp diode D5 - the second switching element Q2 - the third connection point 13 - the output terminal 8, and the voltage value of the output voltage to the AC load becomes 0.

[0139] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the fourth switching state, the second capacitor C2 of the second bootstrap circuit 72 supplies the voltage necessary for the second gate driver 62 to turn on the second switching element Q2. Therefore, the charge of the second capacitor C2 of the second bootstrap circuit 72 is discharged through the discharge path Ru2 of the second capacitor C2 - high-potential side power supply terminal 62H of the second gate driver 62 - low-potential side power supply terminal 62L of the second gate driver 62 - second capacitor C2, as shown in Figure 22. Also, when the switching circuit 10 of the inverter circuit 1 is in the fourth switching state, the DC voltage source 6 supplies the voltage necessary for the fourth gate driver 64 to turn on the fourth switching element Q4. Also, when the switching circuit 10 of the inverter circuit 1 is in the fourth switching state, the DC voltage source 6 charges the third capacitor C3. As shown in Figure 22, the charging path Ru93 for charging the third capacitor C3 by the DC voltage source 6 is the path from the positive terminal of the DC voltage source 6 - the third diode D13 - the third capacitor C3 - the second connection point 12 - the fourth switching element Q4 - the negative terminal of the DC voltage source 6.

[0140] When the polarity of the output current of the inverter circuit 1 is positive, the control device 4 alternately repeats the first control and the second control. Here, as shown in Figure 20, when the control device 4 transitions from the first control, which controls the switching circuit 10 to the first switching state, to the second control, which controls the switching circuit 10 to the second switching state, it performs a third control between the first and second controls to control the switching circuit 10 to the fourth switching state. Therefore, immediately after the third control, the control device 4 transitions to the first control after going through the second control. In Figure 20, the potential levels of the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 are denoted as "L" for low levels and "H" for high levels.

[0141] Furthermore, the control device 4 sets a dead time period Td between the period when the potential level of the fourth control signal S4 is high and the period when the potential level of the third control signal S3 is high, so that the ON period of the fourth switching element Q4 and the ON period of the third switching element Q3 do not overlap. Furthermore, the control device 4 sets a dead time period Td between the period when the potential level of the first control signal S1 is high and the period when the potential level of the fourth control signal S4 is high, so that the ON period of the first switching element Q1 and the ON period of the fourth switching element Q4 do not overlap. Furthermore, the control device 4 sets a dead time period Td between the period when the potential level of the third control signal S3 is high and the period when the potential level of the first control signal S1 is high, so that the ON period of the third switching element Q3 and the ON period of the first switching element Q1 do not overlap. Note that the length of the dead time period Td may be 0.

[0142] In the switching element drive circuit 2 according to Embodiment 4, the third capacitor C3 of the third bootstrap circuit 73 corresponding to the inverter circuit 1 is charged each time the control device 4 performs the third control for each of the plurality of inverter circuits 1, thereby suppressing a decrease in the voltage VC3 of the third capacitor C3 of the third bootstrap circuit 73.

[0143] In the switching element drive circuit 2 according to Embodiment 4, the control device 4 performs voltage vector control for each of the plurality of inverter circuits 1 when the polarity of the output current is negative. However, it is not limited to voltage vector control, and in switching pattern control, the second control and the fourth control may be repeated alternately.

[0144] In this embodiment, the second capacitor C2 and the third capacitor C3 are charged during periods when the output current of the inverter circuit 1U is positive, so the decrease in the voltage VC2 of the second capacitor C2 and the voltage VC3 of the third capacitor C3 is suppressed. Similarly, during periods when the output current of the inverter circuit 1V is positive and during periods when the output current of the inverter circuit 1W is positive, the second capacitor C2 and the third capacitor C3 are charged, so the decrease in the voltage VC2 of the second capacitor C2 and the voltage VC3 of the third capacitor C3 is suppressed.

[0145] (3) Advantages Since the switching element drive circuit 2 according to Embodiment 4 has the same circuit configuration as the switching element drive circuit 2 according to Embodiment 1, it is possible to suppress the decrease in the voltage VC1 of each of the first capacitors C1 of the multiple first bootstrap circuits 71, just like the switching element drive circuit 2 according to Embodiment 1.

[0146] Furthermore, in the switching element drive circuit 2 according to Embodiment 4, the control device 4 performs switching pattern control for each of the plurality of inverter circuits 1. The control device 4 includes a first control, a second control, and a third control in the switching pattern control. The first control controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 to on, on, off, and off, respectively. The second control controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 to off, on, on, and off, respectively. The third control controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 to off, on, off, and on, respectively. In the switching pattern control, immediately after the third control, the control proceeds to the first control via the second control.

[0147] With the above configuration, compared to the switching element driving circuit 2 of Embodiment 1 and the switching element driving circuit 2A of Embodiment 2, it is possible to suppress the decrease in the voltage VC3 of each of the third capacitors C3 of the multiple third bootstrap circuits 73.

[0148] Furthermore, the power conversion device 100 according to Embodiment 4 includes a switching element drive circuit 2 and a plurality of inverter circuits 1.

[0149] According to the above configuration, it is possible to suppress the decrease in the voltage VC1 of each of the first capacitors C1 of the multiple first bootstrap circuits 71.

[0150] (Embodiment 5) The switching element drive circuit 2 and power conversion device 100 according to Embodiment 5 will be described with reference to Figures 1 and 23.

[0151] (1) The circuit configuration of the switching element drive circuit 2 according to Embodiment 5 is the same as the circuit configuration of the switching element drive circuit 2 according to Embodiment 1 (see Figure 1). The circuit configuration of the power converter 100 according to Embodiment 5 is the same as the circuit configuration of the power converter 100 according to Embodiment 1 (see Figure 1).

[0152] (2) The switching element drive circuit 2 according to the operating embodiment 5 of the switching element drive circuit and power converter differs from the switching element drive circuit 2 according to embodiment 1 in that the control device 4 performs triangular wave PWM control instead of voltage vector control.

[0153] In this embodiment, the control device 4 generates a first control signal S1 consisting of a PWM signal by comparing the command value Vout of the output voltage at the output terminal 8 (see Figure 1) with the triangular wave first carrier wave CA1, as shown in Figure 23, for each of the multiple (three in the example of Figure 1) inverter circuits 1. The control device 4 also generates a third control signal S3 consisting of a PWM signal obtained by inverting the PWM signal that constitutes the first control signal S1. Therefore, in the inverter circuit 1, the first switching element Q1 and the third switching element Q3 operate complementaryly. Furthermore, as shown in Figure 23, the control device 4 generates a second control signal S2 consisting of a PWM signal by comparing the command value Vout of the output voltage at the output terminal 8 (see Figure 1) with the triangular wave second carrier wave CA2. Furthermore, the control device 4 generates a fourth control signal S4 consisting of a PWM signal obtained by inverting the PWM signal that constitutes the second control signal S2. Therefore, in the inverter circuit 1, the second switching element Q2 and the fourth switching element Q4 operate complementaryly. In Figure 23, the potential levels of the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 are indicated as "L" for low levels and "H" for high levels.

[0154] (3) Advantages Since the switching element drive circuit 2 according to Embodiment 5 has the same circuit configuration as the switching element drive circuit 2 according to Embodiment 1, it is possible to suppress the decrease in the voltage VC1 of each of the first capacitors C1 of the multiple first bootstrap circuits 71, just like the switching element drive circuit 2 according to Embodiment 1.

[0155] Furthermore, the power converter 100 according to Embodiment 5 includes a switching element drive circuit 2 and a plurality of inverter circuits 1, similar to the power converter 100 according to Embodiment 1.

[0156] According to the above configuration, it is possible to suppress the decrease in the voltage VC1 of each of the first capacitors C1 of the multiple first bootstrap circuits 71.

[0157] (Embodiment 6) The switching element drive circuit 2B and power converter 100B according to Embodiment 6 will be described with reference to Figure 24.

[0158] (1) The power converter 100B according to Embodiment 6 differs from the power converter 100 (see Figure 1) according to Embodiment 1 in that it has two inverter circuits 1. Also, the switching element drive circuit 2B according to Embodiment 6 differs from the switching element drive circuit 2 according to Embodiment 1 in that it has two first bootstrap circuits 71, two second bootstrap circuits 72, three third bootstrap circuits 73, first gate drivers 61, second gate drivers 62, third gate drivers 63, and fourth gate drivers 64. Also, the switching element drive circuit 2B according to Embodiment 6 differs from the switching element drive circuit 2 according to Embodiment 1 in that it has two auxiliary diodes D8. With regard to the power converter 100B according to Embodiment 6, components that are the same as those in the power converter 100 according to Embodiment 1 are denoted by the same reference numerals and their descriptions are omitted. Also, with regard to the switching element drive circuit 2B according to Embodiment 6, components that are the same as those in the switching element drive circuit 2 according to Embodiment 1 are denoted by the same reference numerals and their descriptions are omitted.

[0159] In one of the two auxiliary diodes D8, the cathode is connected to the high-potential terminal of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the inverter circuit 1U, and the anode is connected to the high-potential terminal of the third capacitor C3 of the third bootstrap circuit 73 corresponding to the inverter circuit 1V.

[0160] Furthermore, in the other of the two auxiliary diodes D8, the cathode of the remaining auxiliary diode D8 is connected to the high-potential terminal of the first capacitor C1 of the first bootstrap circuit 71 corresponding to the inverter circuit 1V, and the anode is connected to the high-potential terminal of the third capacitor C3 of the third bootstrap circuit 73 corresponding to the inverter circuit 1U.

[0161] (2) Advantages The switching element driving circuit 2B according to embodiment 6 is equipped with two auxiliary diodes D8, which makes it possible to suppress the decrease in the voltage VC1 of each of the first capacitors C1 of the two first bootstrap circuits 71.

[0162] Further, the power conversion device 100B according to Embodiment 6 includes a switching element drive circuit 2B and two inverter circuits 1.

[0163] According to the above configuration, it is possible to suppress a decrease in the voltage VC1 of each of the first capacitors C1 of the two first bootstrap circuits 71.

[0164] (Embodiment 7) The power conversion device 100C according to Embodiment 7 will be described with reference to FIG. 25.

[0165] (1) Configuration The power conversion device 100C according to Embodiment 7 is substantially the same as the power conversion device 100 (see FIG. 1) according to Embodiment 1, and is different from the power conversion device 100 according to Embodiment 1 in that it includes a switching element drive circuit 2C instead of the switching element drive circuit 2 (see FIG. 1) according to Embodiment 1. Regarding the power conversion device 100C according to Embodiment 7, the same reference numerals are assigned to the same components as those of the power conversion device 100 according to Embodiment 1, and the description thereof is omitted. Further, regarding the switching element drive circuit 2C according to Embodiment 7, the same reference numerals are assigned to the same components as those of the switching element drive circuit 2 according to Embodiment 1, and the description thereof is omitted. In FIG. 25, the illustration of the DC power supply unit 3 (see FIG. 1) is omitted.

[0166] The power conversion device 100C includes N (N is an integer of 4 or more) inverter circuits 1. The switching element drive circuit 2C includes N first bootstrap circuits 71, N second bootstrap circuits 72, N third bootstrap circuits 73, N first gate drivers 61, N second gate drivers 62, N third gate drivers 63, N fourth gate drivers 64, and a control device 4. The control device 4 outputs N first control signals S1, N second control signals S2, N third control signals S3, and N fourth control signals S4.

[0167] Hereinafter, the inverter circuit 1 corresponding to the first phase among the N inverter circuits 1 is referred to as inverter circuit 1 １ and the inverter circuit 1 corresponding to the second phase is referred to as inverter circuit 1 ２The inverter circuit 1 corresponding to the (N-1) phase is called the inverter circuit 1 Ｎ－１ This refers to the inverter circuit corresponding to the Nth phase, which is called inverter circuit 1. Ｎ It is sometimes referred to as such. Also, below, Inverter Circuit 1 １ The first bootstrap circuit 71, the first capacitor C1, the second bootstrap circuit 72, the second capacitor C2, the third bootstrap circuit 73, and the third capacitor C3 corresponding to the first bootstrap circuit 71 are each... １ , first capacitor C1 １ , second bootstrap circuit 72 １ , second capacitor C2 １ , third bootstrap circuit 73 １ and the third capacitor C3 １ It is also called [another name]. Furthermore, below, Inverter Circuit 1 ２ The first bootstrap circuit 71, the first capacitor C1, the second bootstrap circuit 72, the second capacitor C2, the third bootstrap circuit 73, and the third capacitor C3 corresponding to the first bootstrap circuit 71 are each... ２ , first capacitor C1 ２ , second bootstrap circuit 72 ２ , second capacitor C2 ２ , third bootstrap circuit 73 ２ and the third capacitor C3 ２ It is also called [another name]. Furthermore, below, Inverter Circuit 1 Ｎ－１ The first bootstrap circuit 71, the first capacitor C1, the second bootstrap circuit 72, the second capacitor C2, the third bootstrap circuit 73, and the third capacitor C3 corresponding to the first bootstrap circuit 71 are each... Ｎ－１ , first capacitor C1 Ｎ－１ , second bootstrap circuit 72 Ｎ－１ , second capacitor C2 Ｎ－１ , third bootstrap circuit 73 Ｎ－１ and the third capacitor C3 Ｎ－１ It is also called [another name]. Furthermore, below, Inverter Circuit 1 ＮThe first bootstrap circuit 71, the first capacitor C1, the second bootstrap circuit 72, the second capacitor C2, the third bootstrap circuit 73, and the third capacitor C3 corresponding to the first bootstrap circuit 71 are each... Ｎ , first capacitor C1 Ｎ , second bootstrap circuit 72 Ｎ , second capacitor C2 Ｎ , third bootstrap circuit 73 Ｎ and the third capacitor C3 Ｎ It is also called by this name.

[0168] In Figure 25, the control device 4 is connected to the inverter circuit 1. １ The first control signal S1 given to the first gate driver 61, the second control signal S2 given to the second gate driver 62, the third control signal S3 given to the third gate driver 63, and the fourth control signal S4 given to the fourth gate driver 64 are respectively given to the first control signal S1 １ , second control signal S2 １ , third control signal S3 １ and fourth control signal S4 １ It is written as follows. Similarly, in Figure 25, the control device 4 is connected to the inverter circuit 1. Ｎ The first control signal S1 given to the first gate driver 61, the second control signal S2 given to the second gate driver 62, the third control signal S3 given to the third gate driver 63, and the fourth control signal S4 given to the fourth gate driver 64 are respectively given to the first control signal S1 Ｎ , second control signal S2 Ｎ , third control signal S3 Ｎ and fourth control signal S4 Ｎ It is written as follows.

[0169] In this embodiment, the plurality of auxiliary diodes D8 include (N-1) × N auxiliary diodes D8. １２ And auxiliary diode 8 １Ｎ And auxiliary diode 8 Ｎ１ And auxiliary diode 8 ＮＮ－１ This includes,

[0170] (2) Advantages The switching element driving circuit 2C according to Embodiment 7 comprises N first gate drivers 61, N second gate drivers 62, N multiple third gate drivers 63, N fourth gate drivers 64, N first bootstrap circuits 71, N second bootstrap circuits 72, N third bootstrap circuits 73, a DC voltage source 6, a control device 4, and (N-1) × N auxiliary diodes D8. Each of the (N-1) × N auxiliary diodes D8 has its cathode connected to the high-potential terminal of the first capacitor C1 of the first bootstrap circuit 71 that corresponds to any one inverter circuit 1 among the N inverter circuits 1. Each of the (N-1) × N auxiliary diodes D8 has its anode connected to the high-potential terminal of the third capacitor C3 of the third bootstrap circuit 73 that corresponds to an inverter circuit 1 different from the one inverter circuit 1 among the N third bootstrap circuits 73.

[0171] With the above configuration, it is possible to suppress the decrease in the voltage VC1 of each of the N first bootstrap circuits 71 first capacitors C1.

[0172] Furthermore, the power conversion device 100C according to Embodiment 7 comprises a switching element drive circuit 2C and N inverter circuits 1.

[0173] With the above configuration, it is possible to suppress the decrease in the voltage VC1 of each of the N first bootstrap circuits 71 first capacitors C1.

[0174] (Modifications) Embodiments 1 to 7 described above are merely one of many embodiments of the present disclosure. Embodiments 1 to 7 described above can be modified in various ways depending on the design, etc., as long as the objectives of the present disclosure are achieved.

[0175] For example, in embodiments 1 to 4, 6, and 7, the control device 4 may be configured to perform triangular wave PWM control instead of voltage vector control.

[0176] Furthermore, in any one of embodiments 1 to 7, each of the multiple auxiliary diodes D8 is not limited to one auxiliary diode, but may be configured by connecting two diodes in parallel, for example. Also, each of the multiple first capacitors C1 is not limited to one capacitor, but may be configured by connecting two capacitors in parallel, for example.

[0177] Furthermore, each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 is not limited to IGBTs, but may also be a MOSFET. In this case, the control terminal, first main terminal, and second main terminal of each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 are the gate terminal, drain terminal, and source terminal, respectively. Each of the multiple first switching elements Q1, multiple second switching elements Q2, multiple third switching elements Q3, and multiple fourth switching elements Q4 may also be a gate injection transistor (GIT). The GIT is, for example, a GaN-based GIT.

[0178] Furthermore, each of the switching element drive circuits 2, 2A, 2B, and 2C may include a DC voltage source 6 that corresponds one-to-one with a plurality of fourth gate drivers 64, and a plurality of DC-DC converters 60.

[0179] (Aspects) The following aspects are disclosed herein.

[0180] The switching element driving circuit (2; 2B; 2C) according to the first embodiment drives a plurality of inverter circuits (1). The plurality of inverter circuits (1) include a plurality of first switching elements (Q1), a plurality of second switching elements (Q2), a plurality of third switching elements (Q3), a plurality of fourth switching elements (Q4), a plurality of first clamp diodes (D5), and a plurality of second clamp diodes (D6). The plurality of first switching elements (Q1) are connected to the positive electrode (P1) of a DC power supply unit (3) having a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1). The plurality of second switching elements (Q2) are each connected in series to the plurality of first switching elements (Q1). The plurality of third switching elements (Q3) are each connected in series to the plurality of second switching elements (Q2). The plurality of fourth switching elements (Q4) are each connected in series to the plurality of third switching elements (Q3). Multiple fourth switching elements (Q4) are connected to the negative terminal (N1) of the DC power supply unit (3). Multiple first clamp diodes (D5) have their cathodes connected to multiple first connection points (11) between multiple first switching elements (Q1) and multiple second switching elements (Q2), and their anodes are connected to the intermediate potential point (M1). Multiple second clamp diodes (D6) have their anodes connected to multiple second connection points (12) between multiple third switching elements (Q3) and multiple fourth switching elements (Q4), and their cathodes are connected to the intermediate potential point (M1). The switching element driving circuit (2; 2B; 2C) comprises a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a plurality of third bootstrap circuits (73), a DC voltage source (6), a control device (4), and a plurality of auxiliary diodes (D8). The plurality of first gate drivers (61) each drive a plurality of first switching elements (Q1). The plurality of second gate drivers (62) each drive a plurality of second switching elements (Q2).Multiple third gate drivers (63) each drive multiple third switching elements (Q3). Multiple fourth gate drivers (64) each drive multiple fourth switching elements (Q4). Multiple first bootstrap circuits (71) correspond one-to-one with multiple first gate drivers (61). Each of the multiple first bootstrap circuits (71) includes a first capacitor (C1) connected in parallel with the corresponding first gate driver (61) and a first diode (D11) connected to the high-potential terminal of the first capacitor (C1). Multiple second bootstrap circuits (72) correspond one-to-one with multiple second gate drivers (62). Each of the multiple second bootstrap circuits (72) includes a second capacitor (C2) connected in parallel with the corresponding second gate driver (62) and a second diode (D12) connected to the high-potential terminal of the second capacitor (C2). Multiple third bootstrap circuits (73) correspond one-to-one with multiple third gate drivers (63). Each of the multiple third bootstrap circuits (73) includes a third capacitor (C3) connected in parallel with the corresponding third gate driver (63) and a third diode (D13) connected to the high-potential terminal of the third capacitor (C3). A DC voltage source (6) is connected to multiple fourth gate drivers (64). The control device (4) outputs multiple first control signals (S1), multiple second control signals (S2), multiple third control signals (S3), and multiple fourth control signals (S4) to be given to each of the multiple first gate drivers (61), multiple second gate drivers (62), multiple third gate drivers (63), and multiple fourth gate drivers (64). Each of the multiple auxiliary diodes (D8) has its cathode connected to the high-potential terminal of the first capacitor (C1) of the first bootstrap circuit (71) that corresponds to any one inverter circuit (1) among the multiple inverter circuits (1) in the multiple first bootstrap circuits (71). Each of the multiple auxiliary diodes (D8) has its anode connected to the high-potential terminal of the third capacitor (C3) of the third bootstrap circuit (73) that corresponds to an inverter circuit (1) different from the one inverter circuit (1) mentioned above among the multiple third bootstrap circuits (73).

[0181] According to this embodiment, it is possible to suppress the decrease in the voltage (VC1) of each of the first capacitors (C1) of the multiple first bootstrap circuits (71).

[0182] The switching element driving circuit (2A) according to the second embodiment drives a plurality of inverter circuits (1). The plurality of inverter circuits (1) include a plurality of first switching elements (Q1), a plurality of second switching elements (Q2), a plurality of third switching elements (Q3), a plurality of fourth switching elements (Q4), a plurality of first clamp diodes (D5), and a plurality of second clamp diodes (D6). The plurality of first switching elements (Q1) are connected to the positive electrode (P1) of a DC power supply unit (3) having a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1). The plurality of second switching elements (Q2) are each connected in series to the plurality of first switching elements (Q1). The plurality of third switching elements (Q3) are each connected in series to the plurality of second switching elements (Q2). The plurality of fourth switching elements (Q4) are each connected in series to the plurality of third switching elements (Q3). Multiple fourth switching elements (Q4) are connected to the negative terminal (N1) of the DC power supply unit (3). Multiple first clamp diodes (D5) have their cathodes connected to multiple first connection points (11) between multiple first switching elements (Q1) and multiple second switching elements (Q2), and their anodes are connected to the intermediate potential point (M1). Multiple second clamp diodes (D6) have their anodes connected to multiple second connection points (12) between multiple third switching elements (Q3) and multiple fourth switching elements (Q4), and their cathodes are connected to the intermediate potential point (M1). The switching element driving circuit (2A) includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a plurality of third bootstrap circuits (73), a DC voltage source (6), a control device (4), and a plurality of auxiliary diodes (D8). The plurality of first gate drivers (61) each drive a plurality of first switching elements (Q1). The plurality of second gate drivers (62) each drive a plurality of second switching elements (Q2). The plurality of third gate drivers (63) each drive a plurality of third switching elements (Q3).Multiple fourth gate drivers (64) each drive multiple fourth switching elements (Q4). Multiple first bootstrap circuits (71) correspond one-to-one with multiple first gate drivers (61). Each of the multiple first bootstrap circuits (71) includes a first capacitor (C1) connected in parallel with the corresponding first gate driver (61). Multiple second bootstrap circuits (72) correspond one-to-one with multiple second gate drivers (62). Each of the multiple second bootstrap circuits (72) includes a second capacitor (C2) connected in parallel with the corresponding second gate driver (62) and a first diode (D12) connected to the high-potential terminal of the second capacitor (C2). Multiple third bootstrap circuits (73) correspond one-to-one with multiple third gate drivers (63). Each of the multiple third bootstrap circuits (73) includes a third capacitor (C3) connected in parallel to the corresponding third gate driver (63), and a second diode (D13) connected to the high-potential terminal of the third capacitor (C3). A DC voltage source (6) is connected to the multiple fourth gate drivers (64). The control device (4) outputs multiple first control signals (S1), multiple second control signals (S2), multiple third control signals (S3), and multiple fourth control signals (S4) to be given to the multiple first gate drivers (61), multiple second gate drivers (62), multiple third gate drivers (63), and multiple fourth gate drivers (64), respectively. Each of the multiple auxiliary diodes (D8) has its cathode connected to the high-potential terminal of the first capacitor (C1) of the first bootstrap circuit (71) corresponding to any one inverter circuit (1) among the multiple inverter circuits (1). Each of the multiple auxiliary diodes (D8) has its anode connected to the high-potential terminal of the third capacitor (C3) of the third bootstrap circuit (73) that corresponds to an inverter circuit (1) different from any one inverter circuit (1) among the multiple third bootstrap circuits (73).

[0183] According to this embodiment, it is possible to suppress the decrease in the voltage (VC1) of each of the first capacitors (C1) of the multiple first bootstrap circuits (71).

[0184] In the switching element driving circuit (2; 2A; 2B; 2C) according to the third embodiment, in the first or second embodiment, each of the plurality of auxiliary diodes (D8) is a rectifier diode or a Schottky barrier diode.

[0185] In the switching element drive circuit (2; 2A; 2B; 2C) according to the fourth embodiment, in any one of the first to third embodiments, the control device (4) generates a plurality of first control signals (S1), a plurality of second control signals (S2), a plurality of third control signals (S3), and a plurality of fourth control signals (S4) by spatial vector modulation.

[0186] In the switching element drive circuit (2; 2A; 2B; 2C) according to the fifth embodiment, in any one of the first to third embodiments, the control device (4) is configured to perform vector substitution control. The control device (4) selects a group of voltage vectors adjacent to the command voltage vector (Vref) from a group of voltage vectors determined by the combination of potentials of a plurality of output points (13) of a plurality of inverter circuits (1). The control device (4) substitutes one of the two first voltage vectors (VV1) among the plurality of voltage vectors whose magnitude is the reference magnitude and closest to the command voltage vector (Vref) with a zero vector (V0z [NNN]) for a combination in which the potential levels of the plurality of output points (13) are all at the potential of the negative electrode (N1), and a second voltage vector (VV2) which has the same direction as the one first voltage vector (VV1) and twice the magnitude of the one first voltage vector (VV1). The control device (4) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64) within a predetermined control period (Ts) so as to make the composite vector of one or more voltage vectors other than the two first voltage vectors (VV1) out of a plurality of voltage vectors, the remaining first voltage vector (VV1) out of the two first voltage vectors (VV1), the zero vector (V0z [NNN]), and the second voltage vector (VV2) match the command voltage vector (Vref).

[0187] According to this embodiment, it is possible to suppress the decrease in the voltage (VC2) of the second capacitor (C2) of the multiple second bootstrap circuits (72).

[0188] In the switching element drive circuit (2; 2A; 2B; 2C) according to the sixth embodiment, in any one of the first to third embodiments, the control device (4) performs switching pattern control for each of the plurality of inverter circuits (1). The control device (4) includes a first control, a second control, and a third control in the switching pattern control. The first control controls the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4) to on, on, off, and off, respectively. The second control controls the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4) to off, on, on, and off, respectively. The third control controls the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4) to off, on, off, and on, respectively. In switching pattern control, the process transitions from the third control to the second control, and then to the first control.

[0189] According to this embodiment, it is possible to suppress the decrease in the voltage (VC3) of each of the third capacitors (C3) of the multiple third bootstrap circuits (73).

[0190] In the seventh embodiment of the switching element drive circuit (2; 2A; 2B; 2C), in any one of the first to third embodiments, the control device (4) generates a plurality of first control signals (S1), a plurality of second control signals (S2), a plurality of third control signals (S3), and a plurality of fourth control signals (S4) by triangular wave PWM control.

[0191] In the eighth embodiment of the switching element drive circuit (2; 2A; 2B; 2C), in any one of the first to seventh embodiments, the DC voltage source (6) includes one DC-DC converter (60) connected in parallel to a plurality of fourth switching elements (Q4).

[0192] This embodiment makes it possible to achieve miniaturization.

[0193] The power converter according to the ninth embodiment (100; 100A; 100B; 100C) comprises one switching element drive circuit (2; 2A; 2B; 2C) from any of the first to eight embodiments, and a plurality of inverter circuits (1).

[0194] According to this embodiment, it is possible to suppress the decrease in the voltage (VC1) of each of the first capacitors (C1) of the multiple first bootstrap circuits (71).

[0195] In the power converter according to the tenth embodiment (100; 100A; 100B; 100C), in the ninth embodiment, each of the plurality of first switching elements (Q1), plurality of second switching elements (Q2), plurality of third switching elements (Q3), and plurality of fourth switching elements (Q4) is an insulated-gate bipolar transistor, a MOSFET, or a gate-injection transistor.

[0196] 1 Inverter circuit 2, 2A, 2B, 2C Switching element drive circuit 3 DC power supply unit 4 Control device 6 DC voltage source 60 DC-DC converter 61 First gate driver 62 Second gate driver 63 Third gate driver 64 Fourth gate driver 65 Fifth gate driver 11 First connection point 12 Second connection point 13 Third connection point (output point) 71 First bootstrap circuit 72 Second bootstrap circuit 73 Third bootstrap circuit 100, 100A, 100B, 100C Power converter C1 First capacitor C2 Second capacitor C3 Third capacitor D5 First clamp diode D6 Second clamp diode D8 Auxiliary diode D11 Diode (First diode) D12 Diode (Second diode, First diode) D13 Diode (Third diode, Second diode) P1 Positive electrode Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element M1 Intermediate potential point N1 Negative electrode

Claims

1. A switching element driving circuit for driving multiple inverter circuits, wherein the multiple inverter circuits include: a plurality of first switching elements connected to the positive terminal of a DC power supply unit having a positive terminal, a negative terminal, and an intermediate potential point; a plurality of second switching elements each connected in series to the plurality of first switching elements; a plurality of third switching elements each connected in series to the plurality of second switching elements; a plurality of fourth switching elements each connected in series to the plurality of third switching elements and connected to the negative terminal of the DC power supply unit; a plurality of first clamp diodes each having cathodes connected to a plurality of first connection points between the plurality of first switching elements and the plurality of second switching elements, and anodes connected to the intermediate potential point; a plurality of second clamp diodes each having anodes connected to a plurality of second connection points between the plurality of third switching elements and the plurality of fourth switching elements, and cathodes connected to the intermediate potential point; and the switching element driving circuit includes: a plurality of first gate drivers for driving the plurality of first switching elements; a plurality of second gate drivers for driving the plurality of second switching elements; A plurality of third gate drivers for each of the plurality of third switching elements; a plurality of fourth gate drivers for each of the plurality of fourth switching elements; a plurality of first bootstrap circuits, each corresponding one-to-one with the plurality of first gate drivers and including a first capacitor connected in parallel to the corresponding first gate driver and a first diode connected to the high potential terminal of the first capacitor; a plurality of second bootstrap circuits, each corresponding one-to-one with the plurality of second gate drivers and including a second capacitor connected in parallel to the corresponding second gate driver and a second diode connected to the high potential terminal of the second capacitor; a plurality of third bootstrap circuits, each corresponding one-to-one with the plurality of third gate drivers and including a third capacitor connected in parallel to the corresponding third gate driver and a third diode connected to the high potential terminal of the third capacitor;A switching element driving circuit comprising: a DC voltage source connected to the plurality of fourth gate drivers; a control device that outputs a plurality of first control signals, a plurality of second control signals, a plurality of third control signals, and a plurality of fourth control signals to each of the plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, and a plurality of fourth gate drivers; and a plurality of auxiliary diodes, wherein each of the plurality of auxiliary diodes has its cathode connected to the high potential terminal of the first capacitor of the first bootstrap circuit corresponding to any one inverter circuit among the plurality of inverter circuits, and its anode connected to the high potential terminal of the third capacitor of the third bootstrap circuit corresponding to an inverter circuit different from any one inverter circuit among the plurality of third bootstrap circuits.

2. A switching element driving circuit for driving multiple inverter circuits, wherein the multiple inverter circuits include: a plurality of first switching elements connected to the positive terminal of a DC power supply unit having a positive terminal, a negative terminal, and an intermediate potential point; a plurality of second switching elements each connected in series to the plurality of first switching elements; a plurality of third switching elements each connected in series to the plurality of second switching elements; a plurality of fourth switching elements each connected in series to the plurality of third switching elements and connected to the negative terminal of the DC power supply unit; a plurality of first clamp diodes each having cathodes connected to a plurality of first connection points between the plurality of first switching elements and the plurality of second switching elements, and anodes connected to the intermediate potential point; a plurality of second clamp diodes each having anodes connected to a plurality of second connection points between the plurality of third switching elements and the plurality of fourth switching elements, and cathodes connected to the intermediate potential point; and the switching element driving circuit includes: a plurality of first gate drivers each driving the plurality of first switching elements; a plurality of second gate drivers each driving the plurality of second switching elements; A plurality of third gate drivers for each of the plurality of third switching elements; a plurality of fourth gate drivers for each of the plurality of fourth switching elements; a plurality of first bootstrap circuits, each corresponding one-to-one with the plurality of first gate drivers and including a first capacitor connected in parallel to the corresponding first gate driver; a plurality of second bootstrap circuits, each corresponding one-to-one with the plurality of second gate drivers and including a second capacitor connected in parallel to the corresponding second gate driver and a first diode connected to the high potential terminal of the second capacitor; a plurality of third bootstrap circuits, each corresponding one-to-one with the plurality of third gate drivers and including a third capacitor connected in parallel to the corresponding third gate driver and a second diode connected to the high potential terminal of the third capacitor; a DC voltage source connected to the plurality of fourth gate drivers;A switching element driving circuit comprising: a control device that outputs a plurality of first control signals, a plurality of second control signals, a plurality of third control signals, and a plurality of fourth control signals to each of the plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, and a plurality of fourth gate drivers; and a plurality of auxiliary diodes, wherein each of the plurality of auxiliary diodes has its cathode connected to the high potential terminal of the first capacitor of the first bootstrap circuit corresponding to any one inverter circuit among the plurality of inverter circuits, and its anode connected to the high potential terminal of the third capacitor of the third bootstrap circuit corresponding to an inverter circuit different from any one inverter circuit among the plurality of third bootstrap circuits.

3. The switching element driving circuit according to claim 1 or 2, wherein each of the plurality of auxiliary diodes is a rectifier diode or a Schottky barrier diode.

4. The control device generates the plurality of first control signals, the plurality of second control signals, the plurality of third control signals, and the plurality of fourth control signals by spatial vector modulation, the switching element driving circuit according to any one of claims 1 to 3.

5. The control device is configured to perform vector substitution control, and selects a plurality of voltage vectors adjacent to the command voltage vector from a group of voltage vectors determined by a combination of potentials of a plurality of output points of the plurality of inverter circuits, and replaces one of the two first voltage vectors among the plurality of voltage vectors whose magnitude is a reference magnitude and is closest to the command voltage vector with a zero vector which is a combination in which the potential levels of the plurality of output points are all at the potential of the negative electrode, and a second voltage vector which is in the same direction as the one first voltage vector and has twice the magnitude of the one first voltage vector, and controls the plurality of first gate drivers, the plurality of second gate drivers, and the plurality of fourth gate drivers within a predetermined control period so as to make the composite vector of one or more voltage vectors other than the two first voltage vectors among the plurality of voltage vectors, the remaining first voltage vector among the two first voltage vectors, the zero vector, and the second voltage vector match the command voltage vector, the switching element driving circuit according to any one of claims 1 to 3.

6. The control device performs switching pattern control for each of the plurality of inverter circuits, and the control device includes, in the switching pattern control, a first control that controls the first switching element, the second switching element, the third switching element, and the fourth switching element to on, on, off, and off respectively; a second control that controls the first switching element, the second switching element, the third switching element, and the fourth switching element to off, on, on, and off respectively; and a third control that controls the first switching element, the second switching element, the third switching element, and the fourth switching element to off, on, off, and on respectively, and immediately after the third control, proceeds to the first control via the second control, the switching element drive circuit according to any one of claims 1 to 3.

7. The switching element driving circuit according to any one of claims 1 to 3, wherein the control device generates the plurality of first control signals, the plurality of second control signals, the plurality of third control signals, and the plurality of fourth control signals by triangular wave PWM control.

8. The switching element driving circuit according to any one of claims 1 to 7, wherein the DC voltage source includes a DC-DC converter connected in parallel to the plurality of fourth switching elements.

9. A power conversion device comprising a switching element drive circuit according to any one of claims 1 to 8, and the plurality of inverter circuits.

10. The power conversion device according to claim 9, wherein each of the plurality of first switching elements, the plurality of second switching elements, the plurality of third switching elements, and the plurality of fourth switching elements is an insulated-gate bipolar transistor, a MOSFET, or a gate-injection transistor.

Images